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o add missing files

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This commit is contained in:
David Voswinkel
2009-05-12 22:20:41 +02:00
parent 8e877d38d4
commit 09198f5099
149 changed files with 43548 additions and 0 deletions
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4
tools/bsnes/smp/core/bpp.sh Executable file
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@@ -0,0 +1,4 @@
clear
bpp opcode_functions.cpp opcode_functions.bpp
bpp opcode_headers.hpp opcode_headers.bpp

16
tools/bsnes/smp/core/core.cpp Executable file
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@@ -0,0 +1,16 @@
#include <../base.hpp>
#define SMPCORE_CPP
namespace SNES {
#include "opcode_algorithms.cpp"
#include "opcode_functions.cpp"
#include "opcode_table.cpp"
#include "disasm/disasm.cpp"
SMPcore::SMPcore() {
initialize_opcode_table();
}
};

36
tools/bsnes/smp/core/core.hpp Executable file
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@@ -0,0 +1,36 @@
class SMPcore {
public:
#include "registers.hpp"
#include "memory.hpp"
#include "opcode_headers.hpp"
#include "disasm/disasm.hpp"
regs_t regs;
uint16 dp, sp, rd, wr, bit, ya;
virtual void op_io() = 0;
virtual uint8_t op_read(uint16_t addr) = 0;
virtual void op_write(uint16_t addr, uint8_t data) = 0;
uint8 op_adc (uint8 x, uint8 y);
uint16 op_addw(uint16 x, uint16 y);
uint8 op_and (uint8 x, uint8 y);
uint8 op_cmp (uint8 x, uint8 y);
uint16 op_cmpw(uint16 x, uint16 y);
uint8 op_eor (uint8 x, uint8 y);
uint8 op_inc (uint8 x);
uint8 op_dec (uint8 x);
uint8 op_or (uint8 x, uint8 y);
uint8 op_sbc (uint8 x, uint8 y);
uint16 op_subw(uint16 x, uint16 y);
uint8 op_asl (uint8 x);
uint8 op_lsr (uint8 x);
uint8 op_rol (uint8 x);
uint8 op_ror (uint8 x);
void (SMPcore::*opcode_table[256])();
void initialize_opcode_table();
SMPcore();
};

305
tools/bsnes/smp/core/disasm/disasm.cpp Executable file
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@@ -0,0 +1,305 @@
#ifdef SMPCORE_CPP
uint16 SMPcore::__relb(int8 offset, int op_len) {
uint16 pc = regs.pc + op_len;
return pc + offset;
}
void SMPcore::disassemble_opcode(char *output) {
char *s, t[512];
uint8 op, op0, op1;
uint16 opw, opdp0, opdp1;
s = output;
sprintf(s, "..%.4x ", regs.pc);
//TODO: read from IPLROM when applicable
op = memory::apuram[(uint16_t)(regs.pc + 0)];
op0 = memory::apuram[(uint16_t)(regs.pc + 1)];
op1 = memory::apuram[(uint16_t)(regs.pc + 2)];
opw = (op0) | (op1 << 8);
opdp0 = ((unsigned)regs.p.p << 8) + op0;
opdp1 = ((unsigned)regs.p.p << 8) + op1;
strcpy(t, " ");
switch(op) {
case 0x00: sprintf(t, "nop"); break;
case 0x01: sprintf(t, "tcall 0"); break;
case 0x02: sprintf(t, "set0 $%.3x", opdp0); break;
case 0x03: sprintf(t, "bbs0 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x04: sprintf(t, "or a,$%.3x", opdp0); break;
case 0x05: sprintf(t, "or a,$%.4x", opw); break;
case 0x06: sprintf(t, "or a,(x)"); break;
case 0x07: sprintf(t, "or a,($%.3x+x)", opdp0); break;
case 0x08: sprintf(t, "or a,#$%.2x", op0); break;
case 0x09: sprintf(t, "or $%.3x,$%.3x", opdp1, opdp0); break;
case 0x0a: sprintf(t, "or1 c,$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0x0b: sprintf(t, "asl $%.3x", opdp0); break;
case 0x0c: sprintf(t, "asl $%.4x", opw); break;
case 0x0d: sprintf(t, "push p"); break;
case 0x0e: sprintf(t, "tset $%.4x,a", opw); break;
case 0x0f: sprintf(t, "brk"); break;
case 0x10: sprintf(t, "bpl $%.4x", __relb(op0, 2)); break;
case 0x11: sprintf(t, "tcall 1"); break;
case 0x12: sprintf(t, "clr0 $%.3x", opdp0); break;
case 0x13: sprintf(t, "bbc0 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x14: sprintf(t, "or a,$%.3x+x", opdp0); break;
case 0x15: sprintf(t, "or a,$%.4x+x", opw); break;
case 0x16: sprintf(t, "or a,$%.4x+y", opw); break;
case 0x17: sprintf(t, "or a,($%.3x)+y", opdp0); break;
case 0x18: sprintf(t, "or $%.3x,#$%.2x", opdp1, op0); break;
case 0x19: sprintf(t, "or (x),(y)"); break;
case 0x1a: sprintf(t, "decw $%.3x", opdp0); break;
case 0x1b: sprintf(t, "asl $%.3x+x", opdp0); break;
case 0x1c: sprintf(t, "asl a"); break;
case 0x1d: sprintf(t, "dec x"); break;
case 0x1e: sprintf(t, "cmp x,$%.4x", opw); break;
case 0x1f: sprintf(t, "jmp ($%.4x+x)", opw); break;
case 0x20: sprintf(t, "clrp"); break;
case 0x21: sprintf(t, "tcall 2"); break;
case 0x22: sprintf(t, "set1 $%.3x", opdp0); break;
case 0x23: sprintf(t, "bbs1 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x24: sprintf(t, "and a,$%.3x", opdp0); break;
case 0x25: sprintf(t, "and a,$%.4x", opw); break;
case 0x26: sprintf(t, "and a,(x)"); break;
case 0x27: sprintf(t, "and a,($%.3x+x)", opdp0); break;
case 0x28: sprintf(t, "and a,#$%.2x", op0); break;
case 0x29: sprintf(t, "and $%.3x,$%.3x", opdp1, opdp0); break;
case 0x2a: sprintf(t, "or1 c,!$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0x2b: sprintf(t, "rol $%.3x", opdp0); break;
case 0x2c: sprintf(t, "rol $%.4x", opw); break;
case 0x2d: sprintf(t, "push a"); break;
case 0x2e: sprintf(t, "cbne $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x2f: sprintf(t, "bra $%.4x", __relb(op0, 2)); break;
case 0x30: sprintf(t, "bmi $%.4x", __relb(op0, 2)); break;
case 0x31: sprintf(t, "tcall 3"); break;
case 0x32: sprintf(t, "clr1 $%.3x", opdp0); break;
case 0x33: sprintf(t, "bbc1 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x34: sprintf(t, "and a,$%.3x+x", opdp0); break;
case 0x35: sprintf(t, "and a,$%.4x+x", opw); break;
case 0x36: sprintf(t, "and a,$%.4x+y", opw); break;
case 0x37: sprintf(t, "and a,($%.3x)+y", opdp0); break;
case 0x38: sprintf(t, "and $%.3x,#$%.2x", opdp1, op0); break;
case 0x39: sprintf(t, "and (x),(y)"); break;
case 0x3a: sprintf(t, "incw $%.3x", opdp0); break;
case 0x3b: sprintf(t, "rol $%.3x+x", opdp0); break;
case 0x3c: sprintf(t, "rol a"); break;
case 0x3d: sprintf(t, "inc x"); break;
case 0x3e: sprintf(t, "cmp x,$%.3x", opdp0); break;
case 0x3f: sprintf(t, "call $%.4x", opw); break;
case 0x40: sprintf(t, "setp"); break;
case 0x41: sprintf(t, "tcall 4"); break;
case 0x42: sprintf(t, "set2 $%.3x", opdp0); break;
case 0x43: sprintf(t, "bbs2 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x44: sprintf(t, "eor a,$%.3x", opdp0); break;
case 0x45: sprintf(t, "eor a,$%.4x", opw); break;
case 0x46: sprintf(t, "eor a,(x)"); break;
case 0x47: sprintf(t, "eor a,($%.3x+x)", opdp0); break;
case 0x48: sprintf(t, "eor a,#$%.2x", op0); break;
case 0x49: sprintf(t, "eor $%.3x,$%.3x", opdp1, opdp0); break;
case 0x4a: sprintf(t, "and1 c,$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0x4b: sprintf(t, "lsr $%.3x", opdp0); break;
case 0x4c: sprintf(t, "lsr $%.4x", opw); break;
case 0x4d: sprintf(t, "push x"); break;
case 0x4e: sprintf(t, "tclr $%.4x,a", opw); break;
case 0x4f: sprintf(t, "pcall $ff%.2x", op0); break;
case 0x50: sprintf(t, "bvc $%.4x", __relb(op0, 2)); break;
case 0x51: sprintf(t, "tcall 5"); break;
case 0x52: sprintf(t, "clr2 $%.3x", opdp0); break;
case 0x53: sprintf(t, "bbc2 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x54: sprintf(t, "eor a,$%.3x+x", opdp0); break;
case 0x55: sprintf(t, "eor a,$%.4x+x", opw); break;
case 0x56: sprintf(t, "eor a,$%.4x+y", opw); break;
case 0x57: sprintf(t, "eor a,($%.3x)+y", opdp0); break;
case 0x58: sprintf(t, "eor $%.3x,#$%.2x", opdp1, op0); break;
case 0x59: sprintf(t, "eor (x),(y)"); break;
case 0x5a: sprintf(t, "cmpw ya,$%.3x", opdp0); break;
case 0x5b: sprintf(t, "lsr $%.3x+x", opdp0); break;
case 0x5c: sprintf(t, "lsr a"); break;
case 0x5d: sprintf(t, "mov x,a"); break;
case 0x5e: sprintf(t, "cmp y,$%.4x", opw); break;
case 0x5f: sprintf(t, "jmp $%.4x", opw); break;
case 0x60: sprintf(t, "clrc"); break;
case 0x61: sprintf(t, "tcall 6"); break;
case 0x62: sprintf(t, "set3 $%.3x", opdp0); break;
case 0x63: sprintf(t, "bbs3 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x64: sprintf(t, "cmp a,$%.3x", opdp0); break;
case 0x65: sprintf(t, "cmp a,$%.4x", opw); break;
case 0x66: sprintf(t, "cmp a,(x)"); break;
case 0x67: sprintf(t, "cmp a,($%.3x+x)", opdp0); break;
case 0x68: sprintf(t, "cmp a,#$%.2x", op0); break;
case 0x69: sprintf(t, "cmp $%.3x,$%.3x", opdp1, opdp0); break;
case 0x6a: sprintf(t, "and1 c,!$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0x6b: sprintf(t, "ror $%.3x", opdp0); break;
case 0x6c: sprintf(t, "ror $%.4x", opw); break;
case 0x6d: sprintf(t, "push y"); break;
case 0x6e: sprintf(t, "dbnz $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x6f: sprintf(t, "ret"); break;
case 0x70: sprintf(t, "bvs $%.4x", __relb(op0, 2)); break;
case 0x71: sprintf(t, "tcall 7"); break;
case 0x72: sprintf(t, "clr3 $%.3x", opdp0); break;
case 0x73: sprintf(t, "bbc3 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x74: sprintf(t, "cmp a,$%.3x+x", opdp0); break;
case 0x75: sprintf(t, "cmp a,$%.4x+x", opw); break;
case 0x76: sprintf(t, "cmp a,$%.4x+y", opw); break;
case 0x77: sprintf(t, "cmp a,($%.3x)+y", opdp0); break;
case 0x78: sprintf(t, "cmp $%.3x,#$%.2x", opdp1, op0); break;
case 0x79: sprintf(t, "cmp (x),(y)"); break;
case 0x7a: sprintf(t, "addw ya,$%.3x", opdp0); break;
case 0x7b: sprintf(t, "ror $%.3x+x", opdp0); break;
case 0x7c: sprintf(t, "ror a"); break;
case 0x7d: sprintf(t, "mov a,x"); break;
case 0x7e: sprintf(t, "cmp y,$%.3x", opdp0); break;
case 0x7f: sprintf(t, "reti"); break;
case 0x80: sprintf(t, "setc"); break;
case 0x81: sprintf(t, "tcall 8"); break;
case 0x82: sprintf(t, "set4 $%.3x", opdp0); break;
case 0x83: sprintf(t, "bbs4 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x84: sprintf(t, "adc a,$%.3x", opdp0); break;
case 0x85: sprintf(t, "adc a,$%.4x", opw); break;
case 0x86: sprintf(t, "adc a,(x)"); break;
case 0x87: sprintf(t, "adc a,($%.3x+x)", opdp0); break;
case 0x88: sprintf(t, "adc a,#$%.2x", op0); break;
case 0x89: sprintf(t, "adc $%.3x,$%.3x", opdp1, opdp0); break;
case 0x8a: sprintf(t, "eor1 c,$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0x8b: sprintf(t, "dec $%.3x", opdp0); break;
case 0x8c: sprintf(t, "dec $%.4x", opw); break;
case 0x8d: sprintf(t, "mov y,#$%.2x", op0); break;
case 0x8e: sprintf(t, "pop p"); break;
case 0x8f: sprintf(t, "mov $%.3x,#$%.2x", opdp1, op0); break;
case 0x90: sprintf(t, "bcc $%.4x", __relb(op0, 2)); break;
case 0x91: sprintf(t, "tcall 9"); break;
case 0x92: sprintf(t, "clr4 $%.3x", opdp0); break;
case 0x93: sprintf(t, "bbc4 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0x94: sprintf(t, "adc a,$%.3x+x", opdp0); break;
case 0x95: sprintf(t, "adc a,$%.4x+x", opw); break;
case 0x96: sprintf(t, "adc a,$%.4x+y", opw); break;
case 0x97: sprintf(t, "adc a,($%.3x)+y", opdp0); break;
case 0x98: sprintf(t, "adc $%.3x,#$%.2x", opdp1, op0); break;
case 0x99: sprintf(t, "adc (x),(y)"); break;
case 0x9a: sprintf(t, "subw ya,$%.3x", opdp0); break;
case 0x9b: sprintf(t, "dec $%.3x+x", opdp0); break;
case 0x9c: sprintf(t, "dec a"); break;
case 0x9d: sprintf(t, "mov x,sp"); break;
case 0x9e: sprintf(t, "div ya,x"); break;
case 0x9f: sprintf(t, "xcn a"); break;
case 0xa0: sprintf(t, "ei"); break;
case 0xa1: sprintf(t, "tcall 10"); break;
case 0xa2: sprintf(t, "set5 $%.3x", opdp0); break;
case 0xa3: sprintf(t, "bbs5 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xa4: sprintf(t, "sbc a,$%.3x", opdp0); break;
case 0xa5: sprintf(t, "sbc a,$%.4x", opw); break;
case 0xa6: sprintf(t, "sbc a,(x)"); break;
case 0xa7: sprintf(t, "sbc a,($%.3x+x)", opdp0); break;
case 0xa8: sprintf(t, "sbc a,#$%.2x", op0); break;
case 0xa9: sprintf(t, "sbc $%.3x,$%.3x", opdp1, opdp0); break;
case 0xaa: sprintf(t, "mov1 c,$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0xab: sprintf(t, "inc $%.3x", opdp0); break;
case 0xac: sprintf(t, "inc $%.4x", opw); break;
case 0xad: sprintf(t, "cmp y,#$%.2x", op0); break;
case 0xae: sprintf(t, "pop a"); break;
case 0xaf: sprintf(t, "mov (x)+,a"); break;
case 0xb0: sprintf(t, "bcs $%.4x", __relb(op0, 2)); break;
case 0xb1: sprintf(t, "tcall 11"); break;
case 0xb2: sprintf(t, "clr5 $%.3x", opdp0); break;
case 0xb3: sprintf(t, "bbc5 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xb4: sprintf(t, "sbc a,$%.3x+x", opdp0); break;
case 0xb5: sprintf(t, "sbc a,$%.4x+x", opw); break;
case 0xb6: sprintf(t, "sbc a,$%.4x+y", opw); break;
case 0xb7: sprintf(t, "sbc a,($%.3x)+y", opdp0); break;
case 0xb8: sprintf(t, "sbc $%.3x,#$%.2x", opdp1, op0); break;
case 0xb9: sprintf(t, "sbc (x),(y)"); break;
case 0xba: sprintf(t, "movw ya,$%.3x", opdp0); break;
case 0xbb: sprintf(t, "inc $%.3x+x", opdp0); break;
case 0xbc: sprintf(t, "inc a"); break;
case 0xbd: sprintf(t, "mov sp,x"); break;
case 0xbe: sprintf(t, "das a"); break;
case 0xbf: sprintf(t, "mov a,(x)+"); break;
case 0xc0: sprintf(t, "di"); break;
case 0xc1: sprintf(t, "tcall 12"); break;
case 0xc2: sprintf(t, "set6 $%.3x", opdp0); break;
case 0xc3: sprintf(t, "bbs6 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xc4: sprintf(t, "mov $%.3x,a", opdp0); break;
case 0xc5: sprintf(t, "mov $%.4x,a", opw); break;
case 0xc6: sprintf(t, "mov (x),a"); break;
case 0xc7: sprintf(t, "mov ($%.3x+x),a", opdp0); break;
case 0xc8: sprintf(t, "cmp x,#$%.2x", op0); break;
case 0xc9: sprintf(t, "mov $%.4x,x", opw); break;
case 0xca: sprintf(t, "mov1 $%.4x:%d,c", opw & 0x1fff, opw >> 13); break;
case 0xcb: sprintf(t, "mov $%.3x,y", opdp0); break;
case 0xcc: sprintf(t, "mov $%.4x,y", opw); break;
case 0xcd: sprintf(t, "mov x,#$%.2x", op0); break;
case 0xce: sprintf(t, "pop x"); break;
case 0xcf: sprintf(t, "mul ya"); break;
case 0xd0: sprintf(t, "bne $%.4x", __relb(op0, 2)); break;
case 0xd1: sprintf(t, "tcall 13"); break;
case 0xd2: sprintf(t, "clr6 $%.3x", opdp0); break;
case 0xd3: sprintf(t, "bbc6 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xd4: sprintf(t, "mov $%.3x+x,a", opdp0); break;
case 0xd5: sprintf(t, "mov $%.4x+x,a", opw); break;
case 0xd6: sprintf(t, "mov $%.4x+y,a", opw); break;
case 0xd7: sprintf(t, "mov ($%.3x)+y,a", opdp0); break;
case 0xd8: sprintf(t, "mov $%.3x,x", opdp0); break;
case 0xd9: sprintf(t, "mov $%.3x+y,x", opdp0); break;
case 0xda: sprintf(t, "movw $%.3x,ya", opdp0); break;
case 0xdb: sprintf(t, "mov $%.3x+x,y", opdp0); break;
case 0xdc: sprintf(t, "dec y"); break;
case 0xdd: sprintf(t, "mov a,y"); break;
case 0xde: sprintf(t, "cbne $%.3x+x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xdf: sprintf(t, "daa a"); break;
case 0xe0: sprintf(t, "clrv"); break;
case 0xe1: sprintf(t, "tcall 14"); break;
case 0xe2: sprintf(t, "set7 $%.3x", opdp0); break;
case 0xe3: sprintf(t, "bbs7 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xe4: sprintf(t, "mov a,$%.3x", opdp0); break;
case 0xe5: sprintf(t, "mov a,$%.4x", opw); break;
case 0xe6: sprintf(t, "mov a,(x)"); break;
case 0xe7: sprintf(t, "mov a,($%.3x+x)", opdp0); break;
case 0xe8: sprintf(t, "mov a,#$%.2x", op0); break;
case 0xe9: sprintf(t, "mov x,$%.4x", opw); break;
case 0xea: sprintf(t, "not1 c,$%.4x:%d", opw & 0x1fff, opw >> 13); break;
case 0xeb: sprintf(t, "mov y,$%.3x", opdp0); break;
case 0xec: sprintf(t, "mov y,$%.4x", opw); break;
case 0xed: sprintf(t, "notc"); break;
case 0xee: sprintf(t, "pop y"); break;
case 0xef: sprintf(t, "sleep"); break;
case 0xf0: sprintf(t, "beq $%.4x", __relb(op0, 2)); break;
case 0xf1: sprintf(t, "tcall 15"); break;
case 0xf2: sprintf(t, "clr7 $%.3x", opdp0); break;
case 0xf3: sprintf(t, "bbc7 $%.3x,$%.4x", opdp0, __relb(op1, 3)); break;
case 0xf4: sprintf(t, "mov a,$%.3x+x", opdp0); break;
case 0xf5: sprintf(t, "mov a,$%.4x+x", opw); break;
case 0xf6: sprintf(t, "mov a,$%.4x+y", opw); break;
case 0xf7: sprintf(t, "mov a,($%.3x)+y", opdp0); break;
case 0xf8: sprintf(t, "mov x,$%.3x", opdp0); break;
case 0xf9: sprintf(t, "mov x,$%.3x+y", opdp0); break;
case 0xfa: sprintf(t, "mov $%.3x,$%.3x", opdp1, opdp0); break;
case 0xfb: sprintf(t, "mov y,$%.3x+x", opdp0); break;
case 0xfc: sprintf(t, "inc y"); break;
case 0xfd: sprintf(t, "mov y,a"); break;
case 0xfe: sprintf(t, "dbnz y,$%.4x", __relb(op0, 2)); break;
case 0xff: sprintf(t, "stop"); break;
}
t[strlen(t)] = ' ';
strcat(s, t);
sprintf(t, "A:%.2x X:%.2x Y:%.2x SP:01%.2x YA:%.4x ",
regs.a, regs.x, regs.y, regs.sp, regs.ya);
strcat(s, t);
sprintf(t, "%c%c%c%c%c%c%c%c",
regs.p.n ? 'N' : 'n',
regs.p.v ? 'V' : 'v',
regs.p.p ? 'P' : 'p',
regs.p.b ? 'B' : 'b',
regs.p.h ? 'H' : 'h',
regs.p.i ? 'I' : 'i',
regs.p.z ? 'Z' : 'z',
regs.p.c ? 'C' : 'c');
strcat(s, t);
}
#endif

3
tools/bsnes/smp/core/disasm/disasm.hpp Executable file
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void disassemble_opcode(char *output);
inline uint16 __relb(int8 offset, int op_len);

28
tools/bsnes/smp/core/memory.hpp Executable file
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alwaysinline uint8_t op_readpc() {
return op_read(regs.pc++);
}
alwaysinline uint8_t op_readstack() {
return op_read(0x0100 | ++regs.sp);
}
alwaysinline void op_writestack(uint8_t data) {
op_write(0x0100 | regs.sp--, data);
}
alwaysinline uint8_t op_readaddr(uint16_t addr) {
return op_read(addr);
}
alwaysinline void op_writeaddr(uint16_t addr, uint8_t data) {
op_write(addr, data);
}
alwaysinline uint8_t op_readdp(uint8_t addr) {
return op_read(((unsigned)regs.p.p << 8) + addr);
}
alwaysinline void op_writedp(uint8_t addr, uint8_t data) {
op_write(((unsigned)regs.p.p << 8) + addr, data);
}

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tools/bsnes/smp/core/opcode_algorithms.cpp Executable file
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#ifdef SMPCORE_CPP
uint8 SMPcore::op_adc(uint8 x, uint8 y) {
int r = x + y + regs.p.c;
regs.p.n = r & 0x80;
regs.p.v = ~(x ^ y) & (x ^ r) & 0x80;
regs.p.h = (x ^ y ^ r) & 0x10;
regs.p.z = (uint8)r == 0;
regs.p.c = r > 0xff;
return r;
}
uint16 SMPcore::op_addw(uint16 x, uint16 y) {
uint16 r;
regs.p.c = 0;
r = op_adc(x, y);
r |= op_adc(x >> 8, y >> 8) << 8;
regs.p.z = r == 0;
return r;
}
uint8 SMPcore::op_and(uint8 x, uint8 y) {
x &= y;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_cmp(uint8 x, uint8 y) {
int r = x - y;
regs.p.n = r & 0x80;
regs.p.z = (uint8)r == 0;
regs.p.c = r >= 0;
return x;
}
uint16 SMPcore::op_cmpw(uint16 x, uint16 y) {
int r = x - y;
regs.p.n = r & 0x8000;
regs.p.z = (uint16)r == 0;
regs.p.c = r >= 0;
return x;
}
uint8 SMPcore::op_eor(uint8 x, uint8 y) {
x ^= y;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_or(uint8 x, uint8 y) {
x |= y;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_sbc(uint8 x, uint8 y) {
int r = x - y - !regs.p.c;
regs.p.n = r & 0x80;
regs.p.v = (x ^ y) & (x ^ r) & 0x80;
regs.p.h = !((x ^ y ^ r) & 0x10);
regs.p.z = (uint8)r == 0;
regs.p.c = r >= 0;
return r;
}
uint16 SMPcore::op_subw(uint16 x, uint16 y) {
uint16 r;
regs.p.c = 1;
r = op_sbc(x, y);
r |= op_sbc(x >> 8, y >> 8) << 8;
regs.p.z = r == 0;
return r;
}
uint8 SMPcore::op_inc(uint8 x) {
x++;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_dec(uint8 x) {
x--;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_asl(uint8 x) {
regs.p.c = x & 0x80;
x <<= 1;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_lsr(uint8 x) {
regs.p.c = x & 0x01;
x >>= 1;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_rol(uint8 x) {
unsigned carry = (unsigned)regs.p.c;
regs.p.c = x & 0x80;
x = (x << 1) | carry;
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
uint8 SMPcore::op_ror(uint8 x) {
unsigned carry = (unsigned)regs.p.c << 7;
regs.p.c = x & 0x01;
x = carry | (x >> 1);
regs.p.n = x & 0x80;
regs.p.z = x == 0;
return x;
}
#endif

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tools/bsnes/smp/core/opcode_functions.bpp Executable file
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//opcode_functions.cpp was generated via bpp -> opcode_functions.bpp
@global class SMPcore
@include "opcode_mov.bpp"
@include "opcode_pc.bpp"
@include "opcode_read.bpp"
@include "opcode_rmw.bpp"
@include "opcode_misc.bpp"
@include "opcode_list.bpp"

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tools/bsnes/smp/core/opcode_functions.cpp Executable file
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tools/bsnes/smp/core/opcode_headers.bpp Executable file
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//==============
//opcode_mov.bpp
//==============
@macro op_mov_reg(d, s)
void op_mov_{d}_{s}();
@endmacro
@macro op_mov_sp_x()
void op_mov_sp_x();
@endmacro
@macro op_mov_reg_const(r)
void op_mov_{r}_const();
@endmacro
@macro op_mov_a_ix()
void op_mov_a_ix();
@endmacro
@macro op_mov_a_ixinc()
void op_mov_a_ixinc();
@endmacro
@macro op_mov_reg_dp(r)
void op_mov_{r}_dp();
@endmacro
@macro op_mov_reg_dpi(r, i)
void op_mov_{r}_dp{i}();
@endmacro
@macro op_mov_reg_addr(r)
void op_mov_{r}_addr();
@endmacro
@macro op_mov_a_addri(i)
void op_mov_a_addr{i}();
@endmacro
@macro op_mov_a_idpx()
void op_mov_a_idpx();
@endmacro
@macro op_mov_a_idpy()
void op_mov_a_idpy();
@endmacro
@macro op_mov_dp_dp()
void op_mov_dp_dp();
@endmacro
@macro op_mov_dp_const()
void op_mov_dp_const();
@endmacro
@macro op_mov_ix_a()
void op_mov_ix_a();
@endmacro
@macro op_mov_ixinc_a()
void op_mov_ixinc_a();
@endmacro
@macro op_mov_dp_reg(r)
void op_mov_dp_{r}();
@endmacro
@macro op_mov_dpi_reg(r, i)
void op_mov_dp{i}_{r}();
@endmacro
@macro op_mov_addr_reg(r)
void op_mov_addr_{r}();
@endmacro
@macro op_mov_addri_a(i)
void op_mov_addr{i}_a();
@endmacro
@macro op_mov_idpx_a()
void op_mov_idpx_a();
@endmacro
@macro op_mov_idpy_a()
void op_mov_idpy_a();
@endmacro
@macro op_movw_ya_dp()
void op_movw_ya_dp();
@endmacro
@macro op_movw_dp_ya()
void op_movw_dp_ya();
@endmacro
@macro op_mov1_c_bit()
void op_mov1_c_bit();
@endmacro
@macro op_mov1_bit_c()
void op_mov1_bit_c();
@endmacro
//=============
//opcode_pc.bpp
//=============
@macro op_branch(name, condition)
void op_{name}();
@endmacro
@macro op_bitbranch(name, bit, condition)
void op_{name}();
@endmacro
@macro op_cbne_dp()
void op_cbne_dp();
@endmacro
@macro op_cbne_dpx()
void op_cbne_dpx();
@endmacro
@macro op_dbnz_dp()
void op_dbnz_dp();
@endmacro
@macro op_dbnz_y()
void op_dbnz_y();
@endmacro
@macro op_jmp_addr()
void op_jmp_addr();
@endmacro
@macro op_jmp_iaddrx()
void op_jmp_iaddrx();
@endmacro
@macro op_call()
void op_call();
@endmacro
@macro op_pcall()
void op_pcall();
@endmacro
@macro op_tcall(bit)
void op_tcall_{bit}();
@endmacro
@macro op_brk()
void op_brk();
@endmacro
@macro op_ret()
void op_ret();
@endmacro
@macro op_reti()
void op_reti();
@endmacro
//===============
//opcode_read.bpp
//===============
@macro op_read_reg_const(name, r)
void op_{name}_{r}_const();
@endmacro
@macro op_read_a_ix(name)
void op_{name}_a_ix();
@endmacro
@macro op_read_reg_dp(name, r)
void op_{name}_{r}_dp();
@endmacro
@macro op_read_a_dpx(name)
void op_{name}_a_dpx();
@endmacro
@macro op_read_reg_addr(name, r)
void op_{name}_{r}_addr();
@endmacro
@macro op_read_a_addri(name, i)
void op_{name}_a_addr{i}();
@endmacro
@macro op_read_a_idpx(name)
void op_{name}_a_idpx();
@endmacro
@macro op_read_a_idpy(name)
void op_{name}_a_idpy();
@endmacro
@macro op_read_ix_iy(name, write)
void op_{name}_ix_iy();
@endmacro
@macro op_read_dp_dp(name, write)
void op_{name}_dp_dp();
@endmacro
@macro op_read_dp_const(name, write)
void op_{name}_dp_const();
@endmacro
@macro op_read_ya_dp(name)
void op_{name}_ya_dp();
@endmacro
@macro op_cmpw_ya_dp()
void op_cmpw_ya_dp();
@endmacro
@macro op_and1(name, op)
void op_and1_{name}();
@endmacro
@macro op_eor1()
void op_eor1_bit();
@endmacro
@macro op_not1()
void op_not1_bit();
@endmacro
@macro op_or1(name, op)
void op_or1_{name}();
@endmacro
//==============
//opcode_rmw.bpp
//==============
@macro op_adjust_reg(name, r)
void op_{name}_{r}();
@endmacro
@macro op_adjust_dp(name)
void op_{name}_dp();
@endmacro
@macro op_adjust_dpx(name)
void op_{name}_dpx();
@endmacro
@macro op_adjust_addr(name)
void op_{name}_addr();
@endmacro
@macro op_tadjust_addr(name, op)
void op_{name}_addr_a();
@endmacro
@macro op_adjustw_dp(name, op)
void op_{name}_dp();
@endmacro
//===============
//opcode_misc.bpp
//===============
@macro op_nop()
void op_nop();
@endmacro
@macro op_wait(name)
void op_{name}();
@endmacro
@macro op_xcn()
void op_xcn();
@endmacro
@macro op_daa()
void op_daa();
@endmacro
@macro op_das()
void op_das();
@endmacro
@macro op_setbit(name, op)
void op_{name}();
@endmacro
@macro op_notc()
void op_notc();
@endmacro
@macro op_seti(name, bit)
void op_{name}();
@endmacro
@macro op_setbit_dp(name, op)
void op_{name}_dp();
@endmacro
@macro op_push(r)
void op_push_{r}();
@endmacro
@macro op_pop(r)
void op_pop_{r}();
@endmacro
@macro op_mul_ya()
void op_mul_ya();
@endmacro
@macro op_div_ya_x()
void op_div_ya_x();
@endmacro
//
@include "opcode_list.bpp"

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tools/bsnes/smp/core/opcode_headers.hpp Executable file
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//==============
//opcode_mov.bpp
//==============
//=============
//opcode_pc.bpp
//=============
//===============
//opcode_read.bpp
//===============
//==============
//opcode_rmw.bpp
//==============
//===============
//opcode_misc.bpp
//===============
//
//==============
//opcode_mov.bpp
//==============
void op_mov_a_x();
void op_mov_a_y();
void op_mov_x_a();
void op_mov_y_a();
void op_mov_x_sp();
void op_mov_sp_x();
void op_mov_a_const();
void op_mov_x_const();
void op_mov_y_const();
void op_mov_a_ix();
void op_mov_a_ixinc();
void op_mov_a_dp();
void op_mov_x_dp();
void op_mov_y_dp();
void op_mov_a_dpx();
void op_mov_x_dpy();
void op_mov_y_dpx();
void op_mov_a_addr();
void op_mov_x_addr();
void op_mov_y_addr();
void op_mov_a_addrx();
void op_mov_a_addry();
void op_mov_a_idpx();
void op_mov_a_idpy();
void op_mov_dp_dp();
void op_mov_dp_const();
void op_mov_ix_a();
void op_mov_ixinc_a();
void op_mov_dp_a();
void op_mov_dp_x();
void op_mov_dp_y();
void op_mov_dpx_a();
void op_mov_dpy_x();
void op_mov_dpx_y();
void op_mov_addr_a();
void op_mov_addr_x();
void op_mov_addr_y();
void op_mov_addrx_a();
void op_mov_addry_a();
void op_mov_idpx_a();
void op_mov_idpy_a();
void op_movw_ya_dp();
void op_movw_dp_ya();
void op_mov1_c_bit();
void op_mov1_bit_c();
//=============
//opcode_pc.bpp
//=============
void op_bra();
void op_beq();
void op_bne();
void op_bcs();
void op_bcc();
void op_bvs();
void op_bvc();
void op_bmi();
void op_bpl();
void op_bbs0();
void op_bbc0();
void op_bbs1();
void op_bbc1();
void op_bbs2();
void op_bbc2();
void op_bbs3();
void op_bbc3();
void op_bbs4();
void op_bbc4();
void op_bbs5();
void op_bbc5();
void op_bbs6();
void op_bbc6();
void op_bbs7();
void op_bbc7();
void op_cbne_dp();
void op_cbne_dpx();
void op_dbnz_dp();
void op_dbnz_y();
void op_jmp_addr();
void op_jmp_iaddrx();
void op_call();
void op_pcall();
void op_tcall_0();
void op_tcall_1();
void op_tcall_2();
void op_tcall_3();
void op_tcall_4();
void op_tcall_5();
void op_tcall_6();
void op_tcall_7();
void op_tcall_8();
void op_tcall_9();
void op_tcall_10();
void op_tcall_11();
void op_tcall_12();
void op_tcall_13();
void op_tcall_14();
void op_tcall_15();
void op_brk();
void op_ret();
void op_reti();
//===============
//opcode_read.bpp
//===============
void op_adc_a_const();
void op_and_a_const();
void op_cmp_a_const();
void op_cmp_x_const();
void op_cmp_y_const();
void op_eor_a_const();
void op_or_a_const();
void op_sbc_a_const();
void op_adc_a_ix();
void op_and_a_ix();
void op_cmp_a_ix();
void op_eor_a_ix();
void op_or_a_ix();
void op_sbc_a_ix();
void op_adc_a_dp();
void op_and_a_dp();
void op_cmp_a_dp();
void op_cmp_x_dp();
void op_cmp_y_dp();
void op_eor_a_dp();
void op_or_a_dp();
void op_sbc_a_dp();
void op_adc_a_dpx();
void op_and_a_dpx();
void op_cmp_a_dpx();
void op_eor_a_dpx();
void op_or_a_dpx();
void op_sbc_a_dpx();
void op_adc_a_addr();
void op_and_a_addr();
void op_cmp_a_addr();
void op_cmp_x_addr();
void op_cmp_y_addr();
void op_eor_a_addr();
void op_or_a_addr();
void op_sbc_a_addr();
void op_adc_a_addrx();
void op_adc_a_addry();
void op_and_a_addrx();
void op_and_a_addry();
void op_cmp_a_addrx();
void op_cmp_a_addry();
void op_eor_a_addrx();
void op_eor_a_addry();
void op_or_a_addrx();
void op_or_a_addry();
void op_sbc_a_addrx();
void op_sbc_a_addry();
void op_adc_a_idpx();
void op_and_a_idpx();
void op_cmp_a_idpx();
void op_eor_a_idpx();
void op_or_a_idpx();
void op_sbc_a_idpx();
void op_adc_a_idpy();
void op_and_a_idpy();
void op_cmp_a_idpy();
void op_eor_a_idpy();
void op_or_a_idpy();
void op_sbc_a_idpy();
void op_adc_ix_iy();
void op_and_ix_iy();
void op_cmp_ix_iy();
void op_eor_ix_iy();
void op_or_ix_iy();
void op_sbc_ix_iy();
void op_adc_dp_dp();
void op_and_dp_dp();
void op_cmp_dp_dp();
void op_eor_dp_dp();
void op_or_dp_dp();
void op_sbc_dp_dp();
void op_adc_dp_const();
void op_and_dp_const();
void op_cmp_dp_const();
void op_eor_dp_const();
void op_or_dp_const();
void op_sbc_dp_const();
void op_addw_ya_dp();
void op_subw_ya_dp();
void op_cmpw_ya_dp();
void op_and1_bit();
void op_and1_notbit();
void op_eor1_bit();
void op_not1_bit();
void op_or1_bit();
void op_or1_notbit();
//==============
//opcode_rmw.bpp
//==============
void op_inc_a();
void op_inc_x();
void op_inc_y();
void op_dec_a();
void op_dec_x();
void op_dec_y();
void op_asl_a();
void op_lsr_a();
void op_rol_a();
void op_ror_a();
void op_inc_dp();
void op_dec_dp();
void op_asl_dp();
void op_lsr_dp();
void op_rol_dp();
void op_ror_dp();
void op_inc_dpx();
void op_dec_dpx();
void op_asl_dpx();
void op_lsr_dpx();
void op_rol_dpx();
void op_ror_dpx();
void op_inc_addr();
void op_dec_addr();
void op_asl_addr();
void op_lsr_addr();
void op_rol_addr();
void op_ror_addr();
void op_tset_addr_a();
void op_tclr_addr_a();
void op_incw_dp();
void op_decw_dp();
//===============
//opcode_misc.bpp
//===============
void op_nop();
void op_sleep();
void op_stop();
void op_xcn();
void op_daa();
void op_das();
void op_clrc();
void op_clrp();
void op_setc();
void op_setp();
void op_clrv();
void op_notc();
void op_ei();
void op_di();
void op_set0_dp();
void op_clr0_dp();
void op_set1_dp();
void op_clr1_dp();
void op_set2_dp();
void op_clr2_dp();
void op_set3_dp();
void op_clr3_dp();
void op_set4_dp();
void op_clr4_dp();
void op_set5_dp();
void op_clr5_dp();
void op_set6_dp();
void op_clr6_dp();
void op_set7_dp();
void op_clr7_dp();
void op_push_a();
void op_push_x();
void op_push_y();
void op_push_p();
void op_pop_a();
void op_pop_x();
void op_pop_y();
void op_pop_p();
void op_mul_ya();
void op_div_ya_x();

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tools/bsnes/smp/core/opcode_list.bpp Executable file
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//==============
//opcode_mov.bpp
//==============
@op_mov_reg(a, x)
@op_mov_reg(a, y)
@op_mov_reg(x, a)
@op_mov_reg(y, a)
@op_mov_reg(x, sp)
@op_mov_sp_x()
@op_mov_reg_const(a)
@op_mov_reg_const(x)
@op_mov_reg_const(y)
@op_mov_a_ix()
@op_mov_a_ixinc()
@op_mov_reg_dp(a)
@op_mov_reg_dp(x)
@op_mov_reg_dp(y)
@op_mov_reg_dpi(a, x)
@op_mov_reg_dpi(x, y)
@op_mov_reg_dpi(y, x)
@op_mov_reg_addr(a)
@op_mov_reg_addr(x)
@op_mov_reg_addr(y)
@op_mov_a_addri(x)
@op_mov_a_addri(y)
@op_mov_a_idpx()
@op_mov_a_idpy()
@op_mov_dp_dp()
@op_mov_dp_const()
@op_mov_ix_a()
@op_mov_ixinc_a()
@op_mov_dp_reg(a)
@op_mov_dp_reg(x)
@op_mov_dp_reg(y)
@op_mov_dpi_reg(a, x)
@op_mov_dpi_reg(x, y)
@op_mov_dpi_reg(y, x)
@op_mov_addr_reg(a)
@op_mov_addr_reg(x)
@op_mov_addr_reg(y)
@op_mov_addri_a(x)
@op_mov_addri_a(y)
@op_mov_idpx_a()
@op_mov_idpy_a()
@op_movw_ya_dp()
@op_movw_dp_ya()
@op_mov1_c_bit()
@op_mov1_bit_c()
//=============
//opcode_pc.bpp
//=============
@op_branch(bra, 0)
@op_branch(beq, !regs.p.z)
@op_branch(bne, regs.p.z)
@op_branch(bcs, !regs.p.c)
@op_branch(bcc, regs.p.c)
@op_branch(bvs, !regs.p.v)
@op_branch(bvc, regs.p.v)
@op_branch(bmi, !regs.p.n)
@op_branch(bpl, regs.p.n)
@op_bitbranch(bbs0, 0x01, !=)
@op_bitbranch(bbc0, 0x01, ==)
@op_bitbranch(bbs1, 0x02, !=)
@op_bitbranch(bbc1, 0x02, ==)
@op_bitbranch(bbs2, 0x04, !=)
@op_bitbranch(bbc2, 0x04, ==)
@op_bitbranch(bbs3, 0x08, !=)
@op_bitbranch(bbc3, 0x08, ==)
@op_bitbranch(bbs4, 0x10, !=)
@op_bitbranch(bbc4, 0x10, ==)
@op_bitbranch(bbs5, 0x20, !=)
@op_bitbranch(bbc5, 0x20, ==)
@op_bitbranch(bbs6, 0x40, !=)
@op_bitbranch(bbc6, 0x40, ==)
@op_bitbranch(bbs7, 0x80, !=)
@op_bitbranch(bbc7, 0x80, ==)
@op_cbne_dp()
@op_cbne_dpx()
@op_dbnz_dp()
@op_dbnz_y()
@op_jmp_addr()
@op_jmp_iaddrx()
@op_call()
@op_pcall()
@op_tcall( 0)
@op_tcall( 1)
@op_tcall( 2)
@op_tcall( 3)
@op_tcall( 4)
@op_tcall( 5)
@op_tcall( 6)
@op_tcall( 7)
@op_tcall( 8)
@op_tcall( 9)
@op_tcall(10)
@op_tcall(11)
@op_tcall(12)
@op_tcall(13)
@op_tcall(14)
@op_tcall(15)
@op_brk()
@op_ret()
@op_reti()
//===============
//opcode_read.bpp
//===============
@op_read_reg_const(adc, a)
@op_read_reg_const(and, a)
@op_read_reg_const(cmp, a)
@op_read_reg_const(cmp, x)
@op_read_reg_const(cmp, y)
@op_read_reg_const(eor, a)
@op_read_reg_const(or, a)
@op_read_reg_const(sbc, a)
@op_read_a_ix(adc)
@op_read_a_ix(and)
@op_read_a_ix(cmp)
@op_read_a_ix(eor)
@op_read_a_ix(or)
@op_read_a_ix(sbc)
@op_read_reg_dp(adc, a)
@op_read_reg_dp(and, a)
@op_read_reg_dp(cmp, a)
@op_read_reg_dp(cmp, x)
@op_read_reg_dp(cmp, y)
@op_read_reg_dp(eor, a)
@op_read_reg_dp(or, a)
@op_read_reg_dp(sbc, a)
@op_read_a_dpx(adc)
@op_read_a_dpx(and)
@op_read_a_dpx(cmp)
@op_read_a_dpx(eor)
@op_read_a_dpx(or)
@op_read_a_dpx(sbc)
@op_read_reg_addr(adc, a)
@op_read_reg_addr(and, a)
@op_read_reg_addr(cmp, a)
@op_read_reg_addr(cmp, x)
@op_read_reg_addr(cmp, y)
@op_read_reg_addr(eor, a)
@op_read_reg_addr(or, a)
@op_read_reg_addr(sbc, a)
@op_read_a_addri(adc, x)
@op_read_a_addri(adc, y)
@op_read_a_addri(and, x)
@op_read_a_addri(and, y)
@op_read_a_addri(cmp, x)
@op_read_a_addri(cmp, y)
@op_read_a_addri(eor, x)
@op_read_a_addri(eor, y)
@op_read_a_addri(or, x)
@op_read_a_addri(or, y)
@op_read_a_addri(sbc, x)
@op_read_a_addri(sbc, y)
@op_read_a_idpx(adc)
@op_read_a_idpx(and)
@op_read_a_idpx(cmp)
@op_read_a_idpx(eor)
@op_read_a_idpx(or)
@op_read_a_idpx(sbc)
@op_read_a_idpy(adc)
@op_read_a_idpy(and)
@op_read_a_idpy(cmp)
@op_read_a_idpy(eor)
@op_read_a_idpy(or)
@op_read_a_idpy(sbc)
@op_read_ix_iy(adc, 1)
@op_read_ix_iy(and, 1)
@op_read_ix_iy(cmp, 0)
@op_read_ix_iy(eor, 1)
@op_read_ix_iy(or, 1)
@op_read_ix_iy(sbc, 1)
@op_read_dp_dp(adc, 1)
@op_read_dp_dp(and, 1)
@op_read_dp_dp(cmp, 0)
@op_read_dp_dp(eor, 1)
@op_read_dp_dp(or, 1)
@op_read_dp_dp(sbc, 1)
@op_read_dp_const(adc, 1)
@op_read_dp_const(and, 1)
@op_read_dp_const(cmp, 0)
@op_read_dp_const(eor, 1)
@op_read_dp_const(or, 1)
@op_read_dp_const(sbc, 1)
@op_read_ya_dp(addw)
@op_read_ya_dp(subw)
@op_cmpw_ya_dp()
@op_and1(bit, !!)
@op_and1(notbit, !)
@op_eor1()
@op_not1()
@op_or1(bit, !!)
@op_or1(notbit, !)
//==============
//opcode_rmw.bpp
//==============
@op_adjust_reg(inc, a)
@op_adjust_reg(inc, x)
@op_adjust_reg(inc, y)
@op_adjust_reg(dec, a)
@op_adjust_reg(dec, x)
@op_adjust_reg(dec, y)
@op_adjust_reg(asl, a)
@op_adjust_reg(lsr, a)
@op_adjust_reg(rol, a)
@op_adjust_reg(ror, a)
@op_adjust_dp(inc)
@op_adjust_dp(dec)
@op_adjust_dp(asl)
@op_adjust_dp(lsr)
@op_adjust_dp(rol)
@op_adjust_dp(ror)
@op_adjust_dpx(inc)
@op_adjust_dpx(dec)
@op_adjust_dpx(asl)
@op_adjust_dpx(lsr)
@op_adjust_dpx(rol)
@op_adjust_dpx(ror)
@op_adjust_addr(inc)
@op_adjust_addr(dec)
@op_adjust_addr(asl)
@op_adjust_addr(lsr)
@op_adjust_addr(rol)
@op_adjust_addr(ror)
@op_tadjust_addr(tset, |)
@op_tadjust_addr(tclr, &~)
@op_adjustw_dp(incw, ++)
@op_adjustw_dp(decw, --)
//===============
//opcode_misc.bpp
//===============
@op_nop()
@op_wait(sleep)
@op_wait(stop)
@op_xcn()
@op_daa()
@op_das()
@op_setbit(clrc, regs.p.c = 0)
@op_setbit(clrp, regs.p.p = 0)
@op_setbit(setc, regs.p.c = 1)
@op_setbit(setp, regs.p.p = 1)
@op_setbit(clrv, regs.p.v = regs.p.h = 0)
@op_notc()
@op_seti(ei, 1)
@op_seti(di, 0)
@op_setbit_dp(set0, |= 0x01)
@op_setbit_dp(clr0, &= ~0x01)
@op_setbit_dp(set1, |= 0x02)
@op_setbit_dp(clr1, &= ~0x02)
@op_setbit_dp(set2, |= 0x04)
@op_setbit_dp(clr2, &= ~0x04)
@op_setbit_dp(set3, |= 0x08)
@op_setbit_dp(clr3, &= ~0x08)
@op_setbit_dp(set4, |= 0x10)
@op_setbit_dp(clr4, &= ~0x10)
@op_setbit_dp(set5, |= 0x20)
@op_setbit_dp(clr5, &= ~0x20)
@op_setbit_dp(set6, |= 0x40)
@op_setbit_dp(clr6, &= ~0x40)
@op_setbit_dp(set7, |= 0x80)
@op_setbit_dp(clr7, &= ~0x80)
@op_push(a)
@op_push(x)
@op_push(y)
@op_push(p)
@op_pop(a)
@op_pop(x)
@op_pop(y)
@op_pop(p)
@op_mul_ya()
@op_div_ya_x()

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tools/bsnes/smp/core/opcode_misc.bpp Executable file
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@macro op_nop()
void {class}::op_nop() {
op_io();
}
@endmacro
@macro op_wait(name)
void {class}::op_{name}() {
while(true) {
op_io();
op_io();
}
}
@endmacro
@macro op_xcn()
void {class}::op_xcn() {
op_io();
op_io();
op_io();
op_io();
regs.a = (regs.a >> 4) | (regs.a << 4);
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_daa()
void {class}::op_daa() {
op_io();
op_io();
if(regs.p.c || (regs.a) > 0x99) {
regs.a += 0x60;
regs.p.c = 1;
}
if(regs.p.h || (regs.a & 15) > 0x09) {
regs.a += 0x06;
}
regs.p.n = !!(regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_das()
void {class}::op_das() {
op_io();
op_io();
if(!regs.p.c || (regs.a) > 0x99) {
regs.a -= 0x60;
regs.p.c = 0;
}
if(!regs.p.h || (regs.a & 15) > 0x09) {
regs.a -= 0x06;
}
regs.p.n = !!(regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_setbit(name, op)
void {class}::op_{name}() {
op_io();
{op};
}
@endmacro
@macro op_notc()
void {class}::op_notc() {
op_io();
op_io();
regs.p.c = !regs.p.c;
}
@endmacro
@macro op_seti(name, bit)
void {class}::op_{name}() {
op_io();
op_io();
regs.p.i = {bit};
}
@endmacro
@macro op_setbit_dp(name, op)
void {class}::op_{name}_dp() {
dp = op_readpc();
rd = op_readdp(dp);
rd {op};
op_writedp(dp, rd);
}
@endmacro
@macro op_push(r)
void {class}::op_push_{r}() {
op_io();
op_io();
op_writestack(regs.{r});
}
@endmacro
@macro op_pop(r)
void {class}::op_pop_{r}() {
op_io();
op_io();
regs.{r} = op_readstack();
}
@endmacro
@macro op_mul_ya()
void {class}::op_mul_ya() {
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
ya = regs.y * regs.a;
regs.a = ya;
regs.y = ya >> 8;
//result is set based on y (high-byte) only
regs.p.n = !!(regs.y & 0x80);
regs.p.z = (regs.y == 0);
}
@endmacro
@macro op_div_ya_x()
void {class}::op_div_ya_x() {
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
op_io();
ya = regs.ya;
//overflow set if quotient >= 256
regs.p.v = !!(regs.y >= regs.x);
regs.p.h = !!((regs.y & 15) >= (regs.x & 15));
if(regs.y < (regs.x << 1)) {
//if quotient is <= 511 (will fit into 9-bit result)
regs.a = ya / regs.x;
regs.y = ya % regs.x;
} else {
//otherwise, the quotient won't fit into regs.p.v + regs.a
//this emulates the odd behavior of the S-SMP in this case
regs.a = 255 - (ya - (regs.x << 9)) / (256 - regs.x);
regs.y = regs.x + (ya - (regs.x << 9)) % (256 - regs.x);
}
//result is set based on a (quotient) only
regs.p.n = !!(regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro

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tools/bsnes/smp/core/opcode_mov.bpp Executable file
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@macro op_mov_reg(d, s)
void {class}::op_mov_{d}_{s}() {
op_io();
regs.{d} = regs.{s};
regs.p.n = (regs.{d} & 0x80);
regs.p.z = (regs.{d} == 0);
}
@endmacro
@macro op_mov_sp_x()
void {class}::op_mov_sp_x() {
op_io();
regs.sp = regs.x;
}
@endmacro
@macro op_mov_reg_const(r)
void {class}::op_mov_{r}_const() {
regs.{r} = op_readpc();
regs.p.n = (regs.{r} & 0x80);
regs.p.z = (regs.{r} == 0);
}
@endmacro
@macro op_mov_a_ix()
void {class}::op_mov_a_ix() {
op_io();
regs.a = op_readdp(regs.x);
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_mov_a_ixinc()
void {class}::op_mov_a_ixinc() {
op_io();
regs.a = op_readdp(regs.x++);
op_io();
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_mov_reg_dp(r)
void {class}::op_mov_{r}_dp() {
sp = op_readpc();
regs.{r} = op_readdp(sp);
regs.p.n = (regs.{r} & 0x80);
regs.p.z = (regs.{r} == 0);
}
@endmacro
@macro op_mov_reg_dpi(r, i)
void {class}::op_mov_{r}_dp{i}() {
sp = op_readpc();
op_io();
regs.{r} = op_readdp(sp + regs.{i});
regs.p.n = (regs.{r} & 0x80);
regs.p.z = (regs.{r} == 0);
}
@endmacro
@macro op_mov_reg_addr(r)
void {class}::op_mov_{r}_addr() {
sp = op_readpc() << 0;
sp |= op_readpc() << 8;
regs.{r} = op_readaddr(sp);
regs.p.n = (regs.{r} & 0x80);
regs.p.z = (regs.{r} == 0);
}
@endmacro
@macro op_mov_a_addri(i)
void {class}::op_mov_a_addr{i}() {
sp = op_readpc() << 0;
sp |= op_readpc() << 8;
op_io();
regs.a = op_readaddr(sp + regs.{i});
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_mov_a_idpx()
void {class}::op_mov_a_idpx() {
dp = op_readpc() + regs.x;
op_io();
sp = op_readdp(dp + 0) << 0;
sp |= op_readdp(dp + 1) << 8;
regs.a = op_readaddr(sp);
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_mov_a_idpy()
void {class}::op_mov_a_idpy() {
dp = op_readpc();
op_io();
sp = op_readdp(dp + 0) << 0;
sp |= op_readdp(dp + 1) << 8;
regs.a = op_readaddr(sp + regs.y);
regs.p.n = (regs.a & 0x80);
regs.p.z = (regs.a == 0);
}
@endmacro
@macro op_mov_dp_dp()
void {class}::op_mov_dp_dp() {
sp = op_readpc();
rd = op_readdp(sp);
dp = op_readpc();
op_writedp(dp, rd);
}
@endmacro
@macro op_mov_dp_const()
void {class}::op_mov_dp_const() {
rd = op_readpc();
dp = op_readpc();
op_readdp(dp);
op_writedp(dp, rd);
}
@endmacro
@macro op_mov_ix_a()
void {class}::op_mov_ix_a() {
op_io();
op_readdp(regs.x);
op_writedp(regs.x, regs.a);
}
@endmacro
@macro op_mov_ixinc_a()
void {class}::op_mov_ixinc_a() {
op_io();
op_io();
op_writedp(regs.x++, regs.a);
}
@endmacro
@macro op_mov_dp_reg(r)
void {class}::op_mov_dp_{r}() {
dp = op_readpc();
op_readdp(dp);
op_writedp(dp, regs.{r});
}
@endmacro
@macro op_mov_dpi_reg(r, i)
void {class}::op_mov_dp{i}_{r}() {
dp = op_readpc();
op_io();
dp += regs.{i};
op_readdp(dp);
op_writedp(dp, regs.{r});
}
@endmacro
@macro op_mov_addr_reg(r)
void {class}::op_mov_addr_{r}() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
op_readaddr(dp);
op_writeaddr(dp, regs.{r});
}
@endmacro
@macro op_mov_addri_a(i)
void {class}::op_mov_addr{i}_a() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
op_io();
dp += regs.{i};
op_readaddr(dp);
op_writeaddr(dp, regs.a);
}
@endmacro
@macro op_mov_idpx_a()
void {class}::op_mov_idpx_a() {
sp = op_readpc();
op_io();
sp += regs.x;
dp = op_readdp(sp + 0) << 0;
dp |= op_readdp(sp + 1) << 8;
op_readaddr(dp);
op_writeaddr(dp, regs.a);
}
@endmacro
@macro op_mov_idpy_a()
void {class}::op_mov_idpy_a() {
sp = op_readpc();
dp = op_readdp(sp + 0) << 0;
dp |= op_readdp(sp + 1) << 8;
op_io();
dp += regs.y;
op_readaddr(dp);
op_writeaddr(dp, regs.a);
}
@endmacro
@macro op_movw_ya_dp()
void {class}::op_movw_ya_dp() {
sp = op_readpc();
regs.a = op_readdp(sp + 0);
op_io();
regs.y = op_readdp(sp + 1);
regs.p.n = (regs.ya & 0x8000);
regs.p.z = (regs.ya == 0);
}
@endmacro
@macro op_movw_dp_ya()
void {class}::op_movw_dp_ya() {
dp = op_readpc();
op_readdp(dp);
op_writedp(dp + 0, regs.a);
op_writedp(dp + 1, regs.y);
}
@endmacro
@macro op_mov1_c_bit()
void {class}::op_mov1_c_bit() {
sp = op_readpc() << 0;
sp |= op_readpc() << 8;
bit = sp >> 13;
sp &= 0x1fff;
rd = op_readaddr(sp);
regs.p.c = (rd & (1 << bit));
}
@endmacro
@macro op_mov1_bit_c()
void {class}::op_mov1_bit_c() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
bit = dp >> 13;
dp &= 0x1fff;
rd = op_readaddr(dp);
(regs.p.c) ? rd |= (1 << bit) : rd &= ~(1 << bit);
op_io();
op_writeaddr(dp, rd);
}
@endmacro

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tools/bsnes/smp/core/opcode_pc.bpp Executable file
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@macro op_branch(name, condition)
void {class}::op_{name}() {
rd = op_readpc();
if({condition}) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_bitbranch(name, bit, condition)
void {class}::op_{name}() {
dp = op_readpc();
sp = op_readdp(dp);
rd = op_readpc();
op_io();
if((sp & {bit}) {condition} {bit}) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_cbne_dp()
void {class}::op_cbne_dp() {
dp = op_readpc();
sp = op_readdp(dp);
rd = op_readpc();
op_io();
if(regs.a == sp) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_cbne_dpx()
void {class}::op_cbne_dpx() {
dp = op_readpc();
op_io();
sp = op_readdp(dp + regs.x);
rd = op_readpc();
op_io();
if(regs.a == sp) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_dbnz_dp()
void {class}::op_dbnz_dp() {
dp = op_readpc();
wr = op_readdp(dp);
op_writedp(dp, --wr);
rd = op_readpc();
if(wr == 0) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_dbnz_y()
void {class}::op_dbnz_y() {
rd = op_readpc();
op_io();
regs.y--;
op_io();
if(regs.y == 0) return;
op_io();
op_io();
regs.pc += (int8_t)rd;
}
@endmacro
@macro op_jmp_addr()
void {class}::op_jmp_addr() {
rd = op_readpc() << 0;
rd |= op_readpc() << 8;
regs.pc = rd;
}
@endmacro
@macro op_jmp_iaddrx()
void {class}::op_jmp_iaddrx() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
op_io();
dp += regs.x;
rd = op_readaddr(dp + 0) << 0;
rd |= op_readaddr(dp + 1) << 8;
regs.pc = rd;
}
@endmacro
@macro op_call()
void {class}::op_call() {
rd = op_readpc() << 0;
rd |= op_readpc() << 8;
op_io();
op_io();
op_io();
op_writestack(regs.pc >> 8);
op_writestack(regs.pc >> 0);
regs.pc = rd;
}
@endmacro
@macro op_pcall()
void {class}::op_pcall() {
rd = op_readpc();
op_io();
op_io();
op_writestack(regs.pc >> 8);
op_writestack(regs.pc >> 0);
regs.pc = 0xff00 | rd;
}
@endmacro
@macro op_tcall(bit)
void {class}::op_tcall_{bit}() {
dp = 0xffde - ({bit} << 1);
rd = op_readaddr(dp + 0) << 0;
rd |= op_readaddr(dp + 1) << 8;
op_io();
op_io();
op_io();
op_writestack(regs.pc >> 8);
op_writestack(regs.pc >> 0);
regs.pc = rd;
}
@endmacro
@macro op_brk()
void {class}::op_brk() {
rd = op_readaddr(0xffde) << 0;
rd |= op_readaddr(0xffdf) << 8;
op_io();
op_io();
op_writestack(regs.pc >> 8);
op_writestack(regs.pc >> 0);
op_writestack(regs.p);
regs.pc = rd;
regs.p.b = 1;
regs.p.i = 0;
}
@endmacro
@macro op_ret()
void {class}::op_ret() {
rd = op_readstack() << 0;
rd |= op_readstack() << 8;
op_io();
op_io();
regs.pc = rd;
}
@endmacro
@macro op_reti()
void {class}::op_reti() {
regs.p = op_readstack();
rd = op_readstack() << 0;
rd |= op_readstack() << 8;
op_io();
op_io();
regs.pc = rd;
}
@endmacro

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tools/bsnes/smp/core/opcode_read.bpp Executable file
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@macro op_read_reg_const(name, r)
void {class}::op_{name}_{r}_const() {
rd = op_readpc();
regs.{r} = op_{name}(regs.{r}, rd);
}
@endmacro
@macro op_read_a_ix(name)
void {class}::op_{name}_a_ix() {
op_io();
rd = op_readdp(regs.x);
regs.a = op_{name}(regs.a, rd);
}
@endmacro
@macro op_read_reg_dp(name, r)
void {class}::op_{name}_{r}_dp() {
dp = op_readpc();
rd = op_readdp(dp);
regs.{r} = op_{name}(regs.{r}, rd);
}
@endmacro
@macro op_read_a_dpx(name)
void {class}::op_{name}_a_dpx() {
dp = op_readpc();
op_io();
rd = op_readdp(dp + regs.x);
regs.a = op_{name}(regs.a, rd);
}
@endmacro
@macro op_read_reg_addr(name, r)
void {class}::op_{name}_{r}_addr() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
rd = op_readaddr(dp);
regs.{r} = op_{name}(regs.{r}, rd);
}
@endmacro
@macro op_read_a_addri(name, i)
void {class}::op_{name}_a_addr{i}() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
op_io();
rd = op_readaddr(dp + regs.{i});
regs.a = op_{name}(regs.a, rd);
}
@endmacro
@macro op_read_a_idpx(name)
void {class}::op_{name}_a_idpx() {
dp = op_readpc() + regs.x;
op_io();
sp = op_readdp(dp + 0) << 0;
sp |= op_readdp(dp + 1) << 8;
rd = op_readaddr(sp);
regs.a = op_{name}(regs.a, rd);
}
@endmacro
@macro op_read_a_idpy(name)
void {class}::op_{name}_a_idpy() {
dp = op_readpc();
op_io();
sp = op_readdp(dp + 0) << 0;
sp |= op_readdp(dp + 1) << 8;
rd = op_readaddr(sp + regs.y);
regs.a = op_{name}(regs.a, rd);
}
@endmacro
@macro op_read_ix_iy(name, write)
void {class}::op_{name}_ix_iy() {
op_io();
rd = op_readdp(regs.y);
wr = op_readdp(regs.x);
wr = op_{name}(wr, rd);
{write} ? op_writedp(regs.x, wr) : op_io();
}
@endmacro
@macro op_read_dp_dp(name, write)
void {class}::op_{name}_dp_dp() {
sp = op_readpc();
rd = op_readdp(sp);
dp = op_readpc();
wr = op_readdp(dp);
wr = op_{name}(wr, rd);
{write} ? op_writedp(dp, wr) : op_io();
}
@endmacro
@macro op_read_dp_const(name, write)
void {class}::op_{name}_dp_const() {
rd = op_readpc();
dp = op_readpc();
wr = op_readdp(dp);
wr = op_{name}(wr, rd);
{write} ? op_writedp(dp, wr) : op_io();
}
@endmacro
@macro op_read_ya_dp(name)
void {class}::op_{name}_ya_dp() {
dp = op_readpc();
rd = op_readdp(dp + 0) << 0;
op_io();
rd |= op_readdp(dp + 1) << 8;
regs.ya = op_{name}(regs.ya, rd);
}
@endmacro
@macro op_cmpw_ya_dp()
void {class}::op_cmpw_ya_dp() {
dp = op_readpc();
rd = op_readdp(dp + 0) << 0;
rd |= op_readdp(dp + 1) << 8;
op_cmpw(regs.ya, rd);
}
@endmacro
@macro op_and1(name, op)
void {class}::op_and1_{name}() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
bit = dp >> 13;
dp &= 0x1fff;
rd = op_readaddr(dp);
regs.p.c = regs.p.c & {op}(rd & (1 << bit));
}
@endmacro
@macro op_eor1()
void {class}::op_eor1_bit() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
bit = dp >> 13;
dp &= 0x1fff;
rd = op_readaddr(dp);
op_io();
regs.p.c = regs.p.c ^ !!(rd & (1 << bit));
}
@endmacro
@macro op_not1()
void {class}::op_not1_bit() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
bit = dp >> 13;
dp &= 0x1fff;
rd = op_readaddr(dp);
rd ^= 1 << bit;
op_writeaddr(dp, rd);
}
@endmacro
@macro op_or1(name, op)
void {class}::op_or1_{name}() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
bit = dp >> 13;
dp &= 0x1fff;
rd = op_readaddr(dp);
op_io();
regs.p.c = regs.p.c | {op}(rd & (1 << bit));
}
@endmacro

61
tools/bsnes/smp/core/opcode_rmw.bpp Executable file
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@macro op_adjust_reg(name, r)
void {class}::op_{name}_{r}() {
op_io();
regs.{r} = op_{name}(regs.{r});
}
@endmacro
@macro op_adjust_dp(name)
void {class}::op_{name}_dp() {
dp = op_readpc();
rd = op_readdp(dp);
rd = op_{name}(rd);
op_writedp(dp, rd);
}
@endmacro
@macro op_adjust_dpx(name)
void {class}::op_{name}_dpx() {
dp = op_readpc();
op_io();
rd = op_readdp(dp + regs.x);
rd = op_{name}(rd);
op_writedp(dp + regs.x, rd);
}
@endmacro
@macro op_adjust_addr(name)
void {class}::op_{name}_addr() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
rd = op_readaddr(dp);
rd = op_{name}(rd);
op_writeaddr(dp, rd);
}
@endmacro
@macro op_tadjust_addr(name, op)
void {class}::op_{name}_addr_a() {
dp = op_readpc() << 0;
dp |= op_readpc() << 8;
rd = op_readaddr(dp);
regs.p.n = ((regs.a - rd) & 0x80);
regs.p.z = ((regs.a - rd) == 0);
op_readaddr(dp);
op_writeaddr(dp, rd {op} regs.a);
}
@endmacro
@macro op_adjustw_dp(name, op)
void {class}::op_{name}_dp() {
dp = op_readpc();
rd = op_readdp(dp) << 0;
rd {op};
op_writedp(dp++, rd);
rd += op_readdp(dp) << 8;
op_writedp(dp, rd >> 8);
regs.p.n = (rd & 0x8000);
regs.p.z = (rd == 0);
}
@endmacro

75
tools/bsnes/smp/core/opcode_table.cpp Executable file
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#ifdef SMPCORE_CPP
void SMPcore::initialize_opcode_table() {
#define op(id, name) opcode_table[id] = &sSMP::op_ ## name;
op(0x00, nop) op(0x01, tcall_0) op(0x02, set0_dp) op(0x03, bbs0)
op(0x04, or_a_dp) op(0x05, or_a_addr) op(0x06, or_a_ix) op(0x07, or_a_idpx)
op(0x08, or_a_const) op(0x09, or_dp_dp) op(0x0a, or1_bit) op(0x0b, asl_dp)
op(0x0c, asl_addr) op(0x0d, push_p) op(0x0e, tset_addr_a) op(0x0f, brk)
op(0x10, bpl) op(0x11, tcall_1) op(0x12, clr0_dp) op(0x13, bbc0)
op(0x14, or_a_dpx) op(0x15, or_a_addrx) op(0x16, or_a_addry) op(0x17, or_a_idpy)
op(0x18, or_dp_const) op(0x19, or_ix_iy) op(0x1a, decw_dp) op(0x1b, asl_dpx)
op(0x1c, asl_a) op(0x1d, dec_x) op(0x1e, cmp_x_addr) op(0x1f, jmp_iaddrx)
op(0x20, clrp) op(0x21, tcall_2) op(0x22, set1_dp) op(0x23, bbs1)
op(0x24, and_a_dp) op(0x25, and_a_addr) op(0x26, and_a_ix) op(0x27, and_a_idpx)
op(0x28, and_a_const) op(0x29, and_dp_dp) op(0x2a, or1_notbit) op(0x2b, rol_dp)
op(0x2c, rol_addr) op(0x2d, push_a) op(0x2e, cbne_dp) op(0x2f, bra)
op(0x30, bmi) op(0x31, tcall_3) op(0x32, clr1_dp) op(0x33, bbc1)
op(0x34, and_a_dpx) op(0x35, and_a_addrx) op(0x36, and_a_addry) op(0x37, and_a_idpy)
op(0x38, and_dp_const) op(0x39, and_ix_iy) op(0x3a, incw_dp) op(0x3b, rol_dpx)
op(0x3c, rol_a) op(0x3d, inc_x) op(0x3e, cmp_x_dp) op(0x3f, call)
op(0x40, setp) op(0x41, tcall_4) op(0x42, set2_dp) op(0x43, bbs2)
op(0x44, eor_a_dp) op(0x45, eor_a_addr) op(0x46, eor_a_ix) op(0x47, eor_a_idpx)
op(0x48, eor_a_const) op(0x49, eor_dp_dp) op(0x4a, and1_bit) op(0x4b, lsr_dp)
op(0x4c, lsr_addr) op(0x4d, push_x) op(0x4e, tclr_addr_a) op(0x4f, pcall)
op(0x50, bvc) op(0x51, tcall_5) op(0x52, clr2_dp) op(0x53, bbc2)
op(0x54, eor_a_dpx) op(0x55, eor_a_addrx) op(0x56, eor_a_addry) op(0x57, eor_a_idpy)
op(0x58, eor_dp_const) op(0x59, eor_ix_iy) op(0x5a, cmpw_ya_dp) op(0x5b, lsr_dpx)
op(0x5c, lsr_a) op(0x5d, mov_x_a) op(0x5e, cmp_y_addr) op(0x5f, jmp_addr)
op(0x60, clrc) op(0x61, tcall_6) op(0x62, set3_dp) op(0x63, bbs3)
op(0x64, cmp_a_dp) op(0x65, cmp_a_addr) op(0x66, cmp_a_ix) op(0x67, cmp_a_idpx)
op(0x68, cmp_a_const) op(0x69, cmp_dp_dp) op(0x6a, and1_notbit) op(0x6b, ror_dp)
op(0x6c, ror_addr) op(0x6d, push_y) op(0x6e, dbnz_dp) op(0x6f, ret)
op(0x70, bvs) op(0x71, tcall_7) op(0x72, clr3_dp) op(0x73, bbc3)
op(0x74, cmp_a_dpx) op(0x75, cmp_a_addrx) op(0x76, cmp_a_addry) op(0x77, cmp_a_idpy)
op(0x78, cmp_dp_const) op(0x79, cmp_ix_iy) op(0x7a, addw_ya_dp) op(0x7b, ror_dpx)
op(0x7c, ror_a) op(0x7d, mov_a_x) op(0x7e, cmp_y_dp) op(0x7f, reti)
op(0x80, setc) op(0x81, tcall_8) op(0x82, set4_dp) op(0x83, bbs4)
op(0x84, adc_a_dp) op(0x85, adc_a_addr) op(0x86, adc_a_ix) op(0x87, adc_a_idpx)
op(0x88, adc_a_const) op(0x89, adc_dp_dp) op(0x8a, eor1_bit) op(0x8b, dec_dp)
op(0x8c, dec_addr) op(0x8d, mov_y_const) op(0x8e, pop_p) op(0x8f, mov_dp_const)
op(0x90, bcc) op(0x91, tcall_9) op(0x92, clr4_dp) op(0x93, bbc4)
op(0x94, adc_a_dpx) op(0x95, adc_a_addrx) op(0x96, adc_a_addry) op(0x97, adc_a_idpy)
op(0x98, adc_dp_const) op(0x99, adc_ix_iy) op(0x9a, subw_ya_dp) op(0x9b, dec_dpx)
op(0x9c, dec_a) op(0x9d, mov_x_sp) op(0x9e, div_ya_x) op(0x9f, xcn)
op(0xa0, ei) op(0xa1, tcall_10) op(0xa2, set5_dp) op(0xa3, bbs5)
op(0xa4, sbc_a_dp) op(0xa5, sbc_a_addr) op(0xa6, sbc_a_ix) op(0xa7, sbc_a_idpx)
op(0xa8, sbc_a_const) op(0xa9, sbc_dp_dp) op(0xaa, mov1_c_bit) op(0xab, inc_dp)
op(0xac, inc_addr) op(0xad, cmp_y_const) op(0xae, pop_a) op(0xaf, mov_ixinc_a)
op(0xb0, bcs) op(0xb1, tcall_11) op(0xb2, clr5_dp) op(0xb3, bbc5)
op(0xb4, sbc_a_dpx) op(0xb5, sbc_a_addrx) op(0xb6, sbc_a_addry) op(0xb7, sbc_a_idpy)
op(0xb8, sbc_dp_const) op(0xb9, sbc_ix_iy) op(0xba, movw_ya_dp) op(0xbb, inc_dpx)
op(0xbc, inc_a) op(0xbd, mov_sp_x) op(0xbe, das) op(0xbf, mov_a_ixinc)
op(0xc0, di) op(0xc1, tcall_12) op(0xc2, set6_dp) op(0xc3, bbs6)
op(0xc4, mov_dp_a) op(0xc5, mov_addr_a) op(0xc6, mov_ix_a) op(0xc7, mov_idpx_a)
op(0xc8, cmp_x_const) op(0xc9, mov_addr_x) op(0xca, mov1_bit_c) op(0xcb, mov_dp_y)
op(0xcc, mov_addr_y) op(0xcd, mov_x_const) op(0xce, pop_x) op(0xcf, mul_ya)
op(0xd0, bne) op(0xd1, tcall_13) op(0xd2, clr6_dp) op(0xd3, bbc6)
op(0xd4, mov_dpx_a) op(0xd5, mov_addrx_a) op(0xd6, mov_addry_a) op(0xd7, mov_idpy_a)
op(0xd8, mov_dp_x) op(0xd9, mov_dpy_x) op(0xda, movw_dp_ya) op(0xdb, mov_dpx_y)
op(0xdc, dec_y) op(0xdd, mov_a_y) op(0xde, cbne_dpx) op(0xdf, daa)
op(0xe0, clrv) op(0xe1, tcall_14) op(0xe2, set7_dp) op(0xe3, bbs7)
op(0xe4, mov_a_dp) op(0xe5, mov_a_addr) op(0xe6, mov_a_ix) op(0xe7, mov_a_idpx)
op(0xe8, mov_a_const) op(0xe9, mov_x_addr) op(0xea, not1_bit) op(0xeb, mov_y_dp)
op(0xec, mov_y_addr) op(0xed, notc) op(0xee, pop_y) op(0xef, sleep)
op(0xf0, beq) op(0xf1, tcall_15) op(0xf2, clr7_dp) op(0xf3, bbc7)
op(0xf4, mov_a_dpx) op(0xf5, mov_a_addrx) op(0xf6, mov_a_addry) op(0xf7, mov_a_idpy)
op(0xf8, mov_x_dp) op(0xf9, mov_x_dpy) op(0xfa, mov_dp_dp) op(0xfb, mov_y_dpx)
op(0xfc, inc_y) op(0xfd, mov_y_a) op(0xfe, dbnz_y) op(0xff, stop)
#undef op
}
#endif

31
tools/bsnes/smp/core/registers.hpp Executable file
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struct flag_t {
bool n, v, p, b, h, i, z, c;
inline operator unsigned() const {
return (n << 7) + (v << 6) + (p << 5) + (b << 4)
+ (h << 3) + (i << 2) + (z << 1) + (c << 0);
}
inline unsigned operator=(uint8_t data) {
n = data & 0x80; v = data & 0x40; p = data & 0x20; b = data & 0x10;
h = data & 0x08; i = data & 0x04; z = data & 0x02; c = data & 0x01;
return data;
}
inline unsigned operator|=(unsigned data) { return operator=(operator unsigned() | data); }
inline unsigned operator^=(unsigned data) { return operator=(operator unsigned() ^ data); }
inline unsigned operator&=(unsigned data) { return operator=(operator unsigned() & data); }
flag_t() : n(0), v(0), p(0), b(0), h(0), i(0), z(0), c(0) {}
};
struct regs_t {
uint16_t pc;
union {
uint16 ya;
struct { uint8 order_lsb2(a, y); };
};
uint8_t x, sp;
flag_t p;
regs_t() : pc(0), ya(0), x(0), sp(0) {}
};

12
tools/bsnes/smp/core/ssmpgen.cpp Executable file
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@@ -0,0 +1,12 @@
#define CLASS_NAME "sSMP"
#include <tool/opgen_switch.cpp>
int main() {
generate("op_mov.cpp", "op_mov.b");
generate("op_pc.cpp", "op_pc.b");
generate("op_read.cpp", "op_read.b");
generate("op_rmw.cpp", "op_rmw.b");
generate("op_misc.cpp", "op_misc.b");
return 0;
}