o cleanup
This commit is contained in:
optixx
8
tools/bsnes/chip/bsx/bsx.cpp
Executable file
8
tools/bsnes/chip/bsx/bsx.cpp
Executable file
@@ -0,0 +1,8 @@
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#include <../base.hpp>
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#include <../cart/cart.hpp>
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#define BSX_CPP
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#include "bsx.hpp"
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#include "bsx_base.cpp"
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#include "bsx_cart.cpp"
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#include "bsx_flash.cpp"
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77
tools/bsnes/chip/bsx/bsx.hpp
Executable file
77
tools/bsnes/chip/bsx/bsx.hpp
Executable file
@@ -0,0 +1,77 @@
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class BSXBase : public MMIO {
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public:
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void init();
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void enable();
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void power();
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void reset();
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uint8 mmio_read(unsigned addr);
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void mmio_write(unsigned addr, uint8 data);
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private:
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struct {
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uint8 r2188, r2189, r218a, r218b;
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uint8 r218c, r218d, r218e, r218f;
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uint8 r2190, r2191, r2192, r2193;
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uint8 r2194, r2195, r2196, r2197;
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uint8 r2198, r2199, r219a, r219b;
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uint8 r219c, r219d, r219e, r219f;
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uint8 r2192_counter;
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uint8 r2192_hour, r2192_minute, r2192_second;
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} regs;
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};
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class BSXCart : public MMIO {
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public:
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void init();
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void enable();
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void power();
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void reset();
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uint8 mmio_read(unsigned addr);
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void mmio_write(unsigned addr, uint8 data);
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MappedRAM sram;
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MappedRAM psram;
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BSXCart();
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~BSXCart();
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private:
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uint8 *sram_data; //256kbit SRAM
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uint8 *psram_data; // 4mbit PSRAM
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struct {
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uint8 r[16];
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} regs;
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void update_memory_map();
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};
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class BSXFlash : public Memory {
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public:
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void init();
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void enable();
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void power();
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void reset();
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unsigned size() const;
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uint8 read(unsigned addr);
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void write(unsigned addr, uint8 data);
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private:
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struct {
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unsigned command;
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uint8 write_old;
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uint8 write_new;
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bool flash_enable;
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bool read_enable;
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bool write_enable;
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} regs;
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};
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extern BSXBase bsxbase;
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extern BSXCart bsxcart;
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extern BSXFlash bsxflash;
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137
tools/bsnes/chip/bsx/bsx_base.cpp
Executable file
137
tools/bsnes/chip/bsx/bsx_base.cpp
Executable file
@@ -0,0 +1,137 @@
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#ifdef BSX_CPP
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void BSXBase::init() {
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}
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void BSXBase::enable() {
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for(uint16 i = 0x2188; i <= 0x219f; i++) memory::mmio.map(i, *this);
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}
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void BSXBase::power() {
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reset();
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}
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void BSXBase::reset() {
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memset(®s, 0x00, sizeof regs);
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}
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uint8 BSXBase::mmio_read(unsigned addr) {
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addr &= 0xffff;
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switch(addr) {
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case 0x2188: return regs.r2188;
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case 0x2189: return regs.r2189;
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case 0x218a: return regs.r218a;
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case 0x218c: return regs.r218c;
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case 0x218e: return regs.r218e;
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case 0x218f: return regs.r218f;
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case 0x2190: return regs.r2190;
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case 0x2192: {
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unsigned counter = regs.r2192_counter++;
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if(regs.r2192_counter >= 18) regs.r2192_counter = 0;
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if(counter == 0) {
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time_t rawtime;
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time(&rawtime);
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tm *t = localtime(&rawtime);
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regs.r2192_hour = t->tm_hour;
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regs.r2192_minute = t->tm_min;
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regs.r2192_second = t->tm_sec;
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}
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switch(counter) {
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case 0: return 0x00; //???
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case 1: return 0x00; //???
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case 2: return 0x00; //???
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case 3: return 0x00; //???
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case 4: return 0x00; //???
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case 5: return 0x01;
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case 6: return 0x01;
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case 7: return 0x00;
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case 8: return 0x00;
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case 9: return 0x00;
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case 10: return regs.r2192_second;
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case 11: return regs.r2192_minute;
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case 12: return regs.r2192_hour;
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case 13: return 0x00; //???
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case 14: return 0x00; //???
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case 15: return 0x00; //???
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case 16: return 0x00; //???
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case 17: return 0x00; //???
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}
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} break;
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case 0x2193: return regs.r2193 & ~0x0c;
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case 0x2194: return regs.r2194;
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case 0x2196: return regs.r2196;
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case 0x2197: return regs.r2197;
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case 0x2199: return regs.r2199;
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}
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return cpu.regs.mdr;
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}
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void BSXBase::mmio_write(unsigned addr, uint8 data) {
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addr &= 0xffff;
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switch(addr) {
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case 0x2188: {
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regs.r2188 = data;
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} break;
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case 0x2189: {
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regs.r2189 = data;
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} break;
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case 0x218a: {
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regs.r218a = data;
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} break;
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case 0x218b: {
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regs.r218b = data;
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} break;
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case 0x218c: {
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regs.r218c = data;
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} break;
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case 0x218e: {
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regs.r218e = data;
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} break;
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case 0x218f: {
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regs.r218e >>= 1;
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regs.r218e = regs.r218f - regs.r218e;
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regs.r218f >>= 1;
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} break;
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case 0x2191: {
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regs.r2191 = data;
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regs.r2192_counter = 0;
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} break;
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case 0x2192: {
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regs.r2190 = 0x80;
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} break;
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case 0x2193: {
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regs.r2193 = data;
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} break;
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case 0x2194: {
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regs.r2194 = data;
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} break;
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case 0x2197: {
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regs.r2197 = data;
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} break;
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case 0x2199: {
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regs.r2199 = data;
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} break;
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}
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}
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#endif
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101
tools/bsnes/chip/bsx/bsx_cart.cpp
Executable file
101
tools/bsnes/chip/bsx/bsx_cart.cpp
Executable file
@@ -0,0 +1,101 @@
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#ifdef BSX_CPP
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void BSXCart::init() {
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}
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void BSXCart::enable() {
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for(uint16 i = 0x5000; i <= 0x5fff; i++) memory::mmio.map(i, *this);
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}
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void BSXCart::power() {
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reset();
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}
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void BSXCart::reset() {
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for(unsigned i = 0; i < 16; i++) regs.r[i] = 0x00;
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regs.r[0x07] = 0x80;
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regs.r[0x08] = 0x80;
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update_memory_map();
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}
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void BSXCart::update_memory_map() {
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Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
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if((regs.r[0x02] & 0x80) == 0x00) {
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//LoROM mapping
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bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
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bus.map(Bus::MapLinear, 0x80, 0xff, 0x8000, 0xffff, cart);
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} else {
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//HiROM mapping
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bus.map(Bus::MapShadow, 0x00, 0x3f, 0x8000, 0xffff, cart);
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bus.map(Bus::MapLinear, 0x40, 0x7d, 0x0000, 0xffff, cart);
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bus.map(Bus::MapShadow, 0x80, 0xbf, 0x8000, 0xffff, cart);
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bus.map(Bus::MapLinear, 0xc0, 0xff, 0x0000, 0xffff, cart);
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}
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if(regs.r[0x03] & 0x80) {
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bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, psram);
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//bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
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}
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if((regs.r[0x05] & 0x80) == 0x00) {
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bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, psram);
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}
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if((regs.r[0x06] & 0x80) == 0x00) {
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bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, psram);
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}
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if(regs.r[0x07] & 0x80) {
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bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom);
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}
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if(regs.r[0x08] & 0x80) {
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bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom);
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}
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bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, psram);
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bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
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}
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uint8 BSXCart::mmio_read(unsigned addr) {
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if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
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uint8 n = (addr >> 16) & 15;
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return regs.r[n];
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}
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if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
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return sram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
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}
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return 0x00;
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}
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void BSXCart::mmio_write(unsigned addr, uint8 data) {
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if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
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uint8 n = (addr >> 16) & 15;
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regs.r[n] = data;
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if(n == 0x0e && data & 0x80) update_memory_map();
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return;
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}
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if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
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return sram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
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}
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}
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BSXCart::BSXCart() {
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sram_data = new uint8_t[ 32 * 1024];
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psram_data = new uint8_t[512 * 1024];
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sram.map (sram_data, 32 * 1024);
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psram.map(psram_data, 512 * 1024);
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}
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BSXCart::~BSXCart() {
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delete[] sram_data;
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delete[] psram_data;
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}
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#endif
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113
tools/bsnes/chip/bsx/bsx_flash.cpp
Executable file
113
tools/bsnes/chip/bsx/bsx_flash.cpp
Executable file
@@ -0,0 +1,113 @@
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#ifdef BSX_CPP
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void BSXFlash::init() {}
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void BSXFlash::enable() {}
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void BSXFlash::power() {
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reset();
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}
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void BSXFlash::reset() {
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regs.command = 0;
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regs.write_old = 0x00;
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regs.write_new = 0x00;
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regs.flash_enable = false;
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regs.read_enable = false;
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regs.write_enable = false;
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}
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unsigned BSXFlash::size() const {
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return memory::bscram.size();
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}
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uint8 BSXFlash::read(unsigned addr) {
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if(addr == 0x0002) {
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if(regs.flash_enable) return 0x80;
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}
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if(addr == 0x5555) {
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if(regs.flash_enable) return 0x80;
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}
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if(regs.read_enable && addr >= 0xff00 && addr <= 0xff13) {
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//read flash cartridge vendor information
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switch(addr - 0xff00) {
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case 0x00: return 0x4d;
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case 0x01: return 0x00;
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case 0x02: return 0x50;
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case 0x03: return 0x00;
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case 0x04: return 0x00;
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case 0x05: return 0x00;
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case 0x06: return 0x2a; //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
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case 0x07: return 0x00;
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default: return 0x00;
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}
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}
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return memory::bscram.read(addr);
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}
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void BSXFlash::write(unsigned addr, uint8 data) {
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//there exist both read-only and read-write BS-X flash cartridges ...
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//unfortunately, the vendor info is not stored inside memory dumps
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//of BS-X flashcarts, so it is impossible to determine whether a
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//given flashcart is writeable.
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//however, it has been observed that LoROM-mapped BS-X carts always
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//use read-write flashcarts, and HiROM-mapped BS-X carts always use
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//read-only flashcarts.
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//below is an unfortunately necessary workaround to this problem.
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if(cartridge.mapper() == Cartridge::BSCHiROM) return;
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if((addr & 0xff0000) == 0) {
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regs.write_old = regs.write_new;
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regs.write_new = data;
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if(regs.write_enable && regs.write_old == regs.write_new) {
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return memory::bscram.write(addr, data);
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}
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} else {
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if(regs.write_enable) {
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return memory::bscram.write(addr, data);
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}
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}
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if(addr == 0x0000) {
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regs.command <<= 8;
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regs.command |= data;
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if((regs.command & 0xffff) == 0x38d0) {
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regs.flash_enable = true;
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regs.read_enable = true;
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}
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}
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if(addr == 0x2aaa) {
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regs.command <<= 8;
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regs.command |= data;
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}
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if(addr == 0x5555) {
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regs.command <<= 8;
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regs.command |= data;
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if((regs.command & 0xffffff) == 0xaa5570) {
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regs.write_enable = false;
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}
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if((regs.command & 0xffffff) == 0xaa55a0) {
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regs.write_old = 0x00;
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regs.write_new = 0x00;
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regs.flash_enable = true;
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regs.write_enable = true;
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}
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if((regs.command & 0xffffff) == 0xaa55f0) {
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regs.flash_enable = false;
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regs.read_enable = false;
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regs.write_enable = false;
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}
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}
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}
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#endif
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