o cleanup

tools/bsnes/cpu/scpu/timing/event.cpp

@@ -0,0 +1,35 @@
+#ifdef SCPU_CPP
+
+void sCPU::queue_event(unsigned id) {
+  switch(id) {
+    //interrupts triggered during (H)DMA do not trigger immediately after
+    case EventIrqLockRelease: {
+      status.irq_lock = false;
+    } break;
+
+    //ALU multiplication / division results are not immediately calculated;
+    //the exact formula for the calculations are unknown, but this lock at least
+    //allows emulation to avoid returning to fully computed results too soon.
+    case EventAluLockRelease: {
+      status.alu_lock = false;
+    } break;
+
+    //S-CPU WRAM consists of two 64kbyte DRAM chips, which must be refreshed
+    //once per scanline to avoid memory decay.
+    case EventDramRefresh: {
+      add_clocks(40);
+    } break;
+
+    //HDMA init routine; occurs once per frame
+    case EventHdmaInit: {
+      cycle_edge_state |= EventFlagHdmaInit;
+    } break;
+
+    //HDMA run routine; occurs once per scanline
+    case EventHdmaRun: {
+      cycle_edge_state |= EventFlagHdmaRun;
+    } break;
+  }
+}
+
+#endif

tools/bsnes/cpu/scpu/timing/irq.cpp

@@ -0,0 +1,107 @@
+#ifdef SCPU_CPP
+
+//called once every four clock cycles;
+//as NMI steps by scanlines (divisible by 4) and IRQ by PPU 4-cycle dots.
+//
+//ppu.(vh)counter(n) returns the value of said counters n-clocks before current time;
+//it is used to emulate hardware communication delay between opcode and interrupt units.
+void sCPU::poll_interrupts() {
+  //NMI hold
+  if(status.nmi_hold) {
+    status.nmi_hold = false;
+    if(status.nmi_enabled) status.nmi_transition = true;
+  }
+
+  //NMI test
+  bool nmi_valid = (ppu.vcounter(2) >= (!ppu.overscan() ? 225 : 240));
+  if(!status.nmi_valid && nmi_valid) {
+    //0->1 edge sensitive transition
+    status.nmi_line = true;
+    status.nmi_hold = true;  //hold /NMI for four cycles
+  } else if(status.nmi_valid && !nmi_valid) {
+    //1->0 edge sensitive transition
+    status.nmi_line = false;
+  }
+  status.nmi_valid = nmi_valid;
+
+  //IRQ hold
+  status.irq_hold = false;
+  if(status.irq_line) {
+    if(status.virq_enabled || status.hirq_enabled) status.irq_transition = true;
+  }
+
+  //IRQ test
+  bool irq_valid = (status.virq_enabled || status.hirq_enabled);
+  if(irq_valid) {
+    if((status.virq_enabled && ppu.vcounter(10) != (status.virq_pos))
+    || (status.hirq_enabled && ppu.hcounter(10) != (status.hirq_pos + 1) * 4)
+    || (status.virq_pos && ppu.vcounter(6) == 0)  //IRQs cannot trigger on last dot of field
+    ) irq_valid = false;
+  }
+  if(!status.irq_valid && irq_valid) {
+    //0->1 edge sensitive transition
+    status.irq_line = true;
+    status.irq_hold = true;  //hold /IRQ for four cycles
+  }
+  status.irq_valid = irq_valid;
+}
+
+void sCPU::nmitimen_update(uint8 data) {
+  bool nmi_enabled  = status.nmi_enabled;
+  bool virq_enabled = status.virq_enabled;
+  bool hirq_enabled = status.hirq_enabled;
+  status.nmi_enabled  = data & 0x80;
+  status.virq_enabled = data & 0x20;
+  status.hirq_enabled = data & 0x10;
+
+  //0->1 edge sensitive transition
+  if(!nmi_enabled && status.nmi_enabled && status.nmi_line) {
+    status.nmi_transition = true;
+  }
+
+  //?->1 level sensitive transition
+  if(status.virq_enabled && !status.hirq_enabled && status.irq_line) {
+    status.irq_transition = true;
+  }
+
+  if(!status.virq_enabled && !status.hirq_enabled) {
+    status.irq_line = false;
+    status.irq_transition = false;
+  }
+
+  status.irq_lock = true;
+  event.enqueue(2, EventIrqLockRelease);
+}
+
+bool sCPU::rdnmi() {
+  bool result = status.nmi_line;
+  if(!status.nmi_hold) {
+    status.nmi_line = false;
+  }
+  return result;
+}
+
+bool sCPU::timeup() {
+  bool result = status.irq_line;
+  if(!status.irq_hold) {
+    status.irq_line = false;
+    status.irq_transition = false;
+  }
+  return result;
+}
+
+bool sCPU::nmi_test() {
+  if(!status.nmi_transition) return false;
+  status.nmi_transition = false;
+  status.wai_lock = false;
+  return true;
+}
+
+bool sCPU::irq_test() {
+  if(!status.irq_transition) return false;
+  status.irq_transition = false;
+  status.wai_lock = false;
+  return !regs.p.i;
+}
+
+#endif

tools/bsnes/cpu/scpu/timing/joypad.cpp

@@ -0,0 +1,28 @@
+#ifdef SCPU_CPP
+
+void sCPU::run_auto_joypad_poll() {
+  uint16 joy1 = 0, joy2 = 0, joy3 = 0, joy4 = 0;
+  for(unsigned i = 0; i < 16; i++) {
+    uint8 port0 = snes.input.port_read(0);
+    uint8 port1 = snes.input.port_read(1);
+
+    joy1 |= (port0 & 1) ? (0x8000 >> i) : 0;
+    joy2 |= (port1 & 1) ? (0x8000 >> i) : 0;
+    joy3 |= (port0 & 2) ? (0x8000 >> i) : 0;
+    joy4 |= (port1 & 2) ? (0x8000 >> i) : 0;
+  }
+
+  status.joy1l = joy1;
+  status.joy1h = joy1 >> 8;
+
+  status.joy2l = joy2;
+  status.joy2h = joy2 >> 8;
+
+  status.joy3l = joy3;
+  status.joy3h = joy3 >> 8;
+
+  status.joy4l = joy4;
+  status.joy4h = joy4 >> 8;
+}
+
+#endif

tools/bsnes/cpu/scpu/timing/timing.cpp

@@ -0,0 +1,166 @@
+#ifdef SCPU_CPP
+
+#include "event.cpp"
+#include "irq.cpp"
+#include "joypad.cpp"
+
+unsigned sCPU::dma_counter() {
+  return (status.dma_counter + ppu.hcounter()) & 7;
+}
+
+void sCPU::add_clocks(unsigned clocks) {
+  event.tick(clocks);
+  unsigned ticks = clocks >> 1;
+  while(ticks--) {
+    ppu.tick();
+    if((ppu.hcounter() & 2) == 0) {
+      snes.input.tick();
+    } else {
+      poll_interrupts();
+    }
+  }
+  scheduler.addclocks_cpu(clocks);
+}
+
+void sCPU::scanline() {
+  status.dma_counter = (status.dma_counter + status.line_clocks) & 7;
+  status.line_clocks = ppu.lineclocks();
+
+  if(ppu.vcounter() == 0) {
+    //hdma init triggers once every frame
+    event.enqueue(cpu_version == 1 ? 12 + 8 - dma_counter() : 12 + dma_counter(), EventHdmaInit);
+  }
+
+  //dram refresh occurs once every scanline
+  if(cpu_version == 2) status.dram_refresh_position = 530 + 8 - dma_counter();
+  event.enqueue(status.dram_refresh_position, EventDramRefresh);
+
+  //hdma triggers once every visible scanline
+  if(ppu.vcounter() <= (ppu.overscan() == false ? 224 : 239)) {
+    event.enqueue(1104, EventHdmaRun);
+  }
+
+  if(status.auto_joypad_poll == true && ppu.vcounter() == (ppu.overscan() == false ? 227 : 242)) {
+    snes.input.poll();
+    run_auto_joypad_poll();
+  }
+}
+
+//used for H/DMA bus synchronization
+void sCPU::precycle_edge() {
+  if(status.dma_state == DmaCpuSync) {
+    add_clocks(status.clock_count - (status.dma_clocks % status.clock_count));
+    status.dma_state = DmaInactive;
+  }
+}
+
+//used to test for H/DMA, which can trigger on the edge of every opcode cycle.
+void sCPU::cycle_edge() {
+  while(cycle_edge_state) {
+    switch(bit::lowest(cycle_edge_state)) {
+      case EventFlagHdmaInit: {
+        hdma_init_reset();
+        if(hdma_enabled_channels()) {
+          status.hdma_pending = true;
+          status.hdma_mode = 0;
+        }
+      } break;
+
+      case EventFlagHdmaRun: {
+        if(hdma_active_channels()) {
+          status.hdma_pending = true;
+          status.hdma_mode = 1;
+        }
+      } break;
+    }
+
+    cycle_edge_state = bit::clear_lowest(cycle_edge_state);
+  }
+
+  //H/DMA pending && DMA inactive?
+  //.. Run one full CPU cycle
+  //.. HDMA pending && HDMA enabled ? DMA sync + HDMA run
+  //.. DMA pending && DMA enabled ? DMA sync + DMA run
+  //.... HDMA during DMA && HDMA enabled ? DMA sync + HDMA run
+  //.. Run one bus CPU cycle
+  //.. CPU sync
+
+  if(status.dma_state == DmaRun) {
+    if(status.hdma_pending) {
+      status.hdma_pending = false;
+      if(hdma_enabled_channels()) {
+        dma_add_clocks(8 - dma_counter());  //DMA sync
+        status.hdma_mode == 0 ? hdma_init() : hdma_run();
+        if(!dma_enabled_channels()) status.dma_state = DmaCpuSync;
+      }
+    }
+
+    if(status.dma_pending) {
+      status.dma_pending = false;
+      if(dma_enabled_channels()) {
+        dma_add_clocks(8 - dma_counter());  //DMA sync
+        dma_run();
+        status.dma_state = DmaCpuSync;
+      }
+    }
+  }
+
+  if(status.dma_state == DmaInactive) {
+    if(status.dma_pending || status.hdma_pending) {
+      status.dma_clocks = 0;
+      status.dma_state = DmaRun;
+    }
+  }
+}
+
+//used to test for NMI/IRQ, which can trigger on the edge of every opcode.
+//test one cycle early to simulate two-stage pipeline of x816 CPU.
+//
+//status.irq_lock is used to simulate hardware delay before interrupts can
+//trigger during certain events (immediately after DMA, writes to $4200, etc)
+void sCPU::last_cycle() {
+  if(!status.irq_lock) {
+    status.nmi_pending |= nmi_test();
+    status.irq_pending |= irq_test();
+
+    status.interrupt_pending = (status.nmi_pending || status.irq_pending);
+  }
+}
+
+void sCPU::timing_power() {
+}
+
+void sCPU::timing_reset() {
+  event.reset();
+
+  status.clock_count = 0;
+  status.line_clocks = ppu.lineclocks();
+
+  status.irq_lock = false;
+  status.alu_lock = false;
+  status.dram_refresh_position = (cpu_version == 1 ? 530 : 538);
+  event.enqueue(status.dram_refresh_position, EventDramRefresh);
+
+  status.nmi_valid      = false;
+  status.nmi_line       = false;
+  status.nmi_transition = false;
+  status.nmi_pending    = false;
+  status.nmi_hold       = false;
+
+  status.irq_valid      = false;
+  status.irq_line       = false;
+  status.irq_transition = false;
+  status.irq_pending    = false;
+  status.irq_hold       = false;
+
+  status.dma_counter  = 0;
+  status.dma_clocks   = 0;
+  status.dma_pending  = false;
+  status.hdma_pending = false;
+  status.hdma_mode    = 0;
+  status.dma_state    = DmaInactive;
+
+  cycle_edge_state = 0;
+}
+
+#endif

tools/bsnes/cpu/scpu/timing/timing.hpp

@@ -0,0 +1,41 @@
+  enum {
+    EventNone,
+    EventIrqLockRelease,
+    EventAluLockRelease,
+    EventDramRefresh,
+    EventHdmaInit,
+    EventHdmaRun,
+
+    //cycle edge
+    EventFlagHdmaInit = 1 << 0,
+    EventFlagHdmaRun  = 1 << 1,
+  };
+  unsigned cycle_edge_state;
+
+  //timing.cpp
+  unsigned dma_counter();
+
+  void add_clocks(unsigned clocks);
+  void scanline();
+
+  alwaysinline void precycle_edge();
+  alwaysinline void cycle_edge();
+  void last_cycle();
+
+  void timing_power();
+  void timing_reset();
+
+  //irq.cpp
+  alwaysinline void poll_interrupts();
+  void nmitimen_update(uint8 data);
+  bool rdnmi();
+  bool timeup();
+
+  alwaysinline bool nmi_test();
+  alwaysinline bool irq_test();
+
+  //joypad.cpp
+  void run_auto_joypad_poll();
+
+  //event.cpp
+  void queue_event(unsigned);  //priorityqueue callback function