From 1c58ae3458ab9ef8709706ad4079fc11d352ee82 Mon Sep 17 00:00:00 2001
From: optixx <david@optixx.org>
Date: Mon, 12 Jan 2009 23:16:00 +0100
Subject: [PATCH] o cleanup

---
 poc/sram_m32/.main.c.swp | Bin 12288 -> 0 bytes
 poc/sram_m32/1           | 110 ---------------------------------------
 2 files changed, 110 deletions(-)
 delete mode 100644 poc/sram_m32/.main.c.swp
 delete mode 100644 poc/sram_m32/1

diff --git a/poc/sram_m32/.main.c.swp b/poc/sram_m32/.main.c.swp
deleted file mode 100644
index 6ab5e28f62c650ef4fc95e895e6a4a6637fea8f5..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/poc/sram_m32/1 b/poc/sram_m32/1
deleted file mode 100644
index 3c7d166..0000000
--- a/poc/sram_m32/1
+++ /dev/null
@@ -1,110 +0,0 @@
- 
-#include <avr/io.h>  
-#include <util/delay.h>
-#include <avr/eeprom.h> 
-
-#include <stdio.h>
-
-#include "uart.h"
-
-extern FILE uart_stdout;
-
-uint16_t ee_data01 __attribute__((section(".eeprom"))) = 0x01;
-uint16_t ee_data02 __attribute__((section(".eeprom"))) = 0x02;
-uint16_t ee_data03 __attribute__((section(".eeprom"))) = 0x03;
-uint16_t ee_data04 __attribute__((section(".eeprom"))) = 0x04;
-
-
-#define DATAPORT    PORTA
-#define ADDRPORTLO  PORTA
-#define ADDRPORTHI  PORTC
-#define CRTLPORT    PORTD
-
-
-#define LATCH_LE_PIN    2
-#define LATCH_OE_PIN    3
-#define SRAM_OE_PIN     4
-#define SRAM_CE_PIN     5
-#define SRAM_WE_PIN     6
-
-
-// LE high -> forward imput 
-// LE low  -> latch input
-#define LATCH_LEHI      CRTLPORT != _BV(LATCH_LE_PIN);     
-#define LATCH_LELO      CRTLPORT &=~_BV(LATCH_LE_PIN);
-// OE high -> normal logic level
-// OE low  -> high impendance
-#define LATCH_OEHI      CRTLPORT != _BV(LATCH_OE_PIN);
-#define LATCH_OELO      CRTLPORT &=~_BV(LATCH_OE_PIN);
-// OE high output disable
-// OE low output enable
-#define SRAM_OEHI       CRTLPORT != _BV(SRAM_OE_PIN);
-#define SRAM_OELO       CRTLPORT &=~_BV(SRAM_OE_PIN);
-// CE high chip disable
-// CE low chip enable
-#define SRAM_CEHI       CRTLPORT != _BV(SRAM_CE_PIN);
-#define SRAM_CELO       CRTLPORT &=~_BV(SRAM_CE_PIN);
-// WE high write disable
-// WE low write enable
-#define SRAM_WEHI       CRTLPORT != _BV(SRAM_WE_PIN);
-#define SRAM_WELO       CRTLPORT &=~_BV(SRAM_WE_PIN);
-
-
-
-
-int sram_write(uint16_t addr, uint8_t data)
-{
-
-    uint8_t addr_lo = addr &  8;
-    uint8_t addr_hi = addr >> 8;
-    
-    SRAM_OEHI;
-    SRAM_CELO;
-    SRAM_WELO;
-
-
-    DATAPORT = data;
-    
-    LATCH_LEHI
-    ADDRPORTLO = addr_lo;
-    ADDRPORTHI = addr_hi;
-    LATCH_LELO
-
-    SRAM_CEHI;
-
-    SRAM_CELO;
-
-
-}
-
-
-
-int main (void) {            // (2)
- 
-    DDRB  = 0xff;             // (3)
-    PORTB = 0xff;             // (4)
-    uint8_t i = 0; 
-    uint8_t j = 7; 
-    uint8_t * addr = 0x0000;  
-    uint16_t c = 0; 
-    uart_init();
-    stdout = &uart_stdout;
-    
-    while(1) {                // (5a)
-        PORTB  |=  (1<< j);
-        j++;
-        if ( j == 8 ) j = 0; 
-        PORTB  &= ~(1 << j );  // Toggle PB0 z.B. angeschlossene LED
-        /* 
-           Die maximale Zeit pro Funktionsaufruf ist begrenzt auf 
-           262.14 ms / F_CPU in MHz (im Beispiel: 
-           262.1 / 3.6864 = max. 71 ms) 
-           16 * 62.5ms (+ Zeit für Schleife) = ca. eine Sekunde warten
-        */
-        
-        for (i=1; i<=70; i++)         
-            _delay_ms(15);    
-    }
-    return 0;                 // (6)
-}
-