From ac8485aacaa3ef8330839c650ea91be50714217c Mon Sep 17 00:00:00 2001 From: optixx Date: Sun, 14 Feb 2016 21:14:15 +0100 Subject: [PATCH] Transfer files from assembla --- files/docs/SNES-Interrupts.txt | 69 ++++++++++++++ files/docs/SNES-Memorymap.txt | 161 +++++++++++++++++++++++++++++++++ files/docs/SNES-Memorymap2.txt | 99 ++++++++++++++++++++ 3 files changed, 329 insertions(+) create mode 100644 files/docs/SNES-Interrupts.txt create mode 100644 files/docs/SNES-Memorymap.txt create mode 100644 files/docs/SNES-Memorymap2.txt diff --git a/files/docs/SNES-Interrupts.txt b/files/docs/SNES-Interrupts.txt new file mode 100644 index 0000000..180b840 --- /dev/null +++ b/files/docs/SNES-Interrupts.txt @@ -0,0 +1,69 @@ +Interrupt Processing Sequence + + +The interrupt processing sequence is initiated as the direct result of hard- +vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs. +The interrupt sequence can also be initiated as a result of the Break or +Co-Processor instructions within the software. The following listings +describe the function of each cycle in the interrupt processing sequence: + + + +Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs + + + +Cycle No. + E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description + + + + 1 1 PC X 1 1 1 1 1 Internal Operation + 2 2 PC X 1 0 0 0 1 Internal Operation + 3 [1] S PB 0 0 1 0 1 Write PB to Stack, S-1�S + 4 3 S PCH [2] 0[3] 0 1 0 1 Write PCH to Stack, S-1�S + 5 4 S PCL 12] 0[3] 0 1 0 1 Write PCL to Stack, S-1�S + 6 5 S P [4] 0[3] 0 1 0 1 Write P to Stack, S-1�S + 7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte, + 0->PD, 1->P1, OO->PB + 8 7 VH (VH) 1 0 1 0 0 Read Vector High 8yte + + + +Software Interrupt - BRK, COP Instructions + + + +Cycle No. + E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description + 1 1 PC-2 X 1 1 1 1 1 Opcode + 2 2 PC-1 X 1 0 0 1 1 Signature + 3 111 S PB 0 0 1 0 1 Write PB to Stack, S-1�S + 4 3 S PCH 0 0 1 0 1 Write PCH to Stack, S-1 - S + 5 4 S PCL 0 0 1 0 1 Write PCL to Stack, S-1�S + 6 5 S P 0 0 1 0 1 Write P to Stack, S-1�S + 7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte, + 0�Po, 1�Pl, 00�PB + 8 7 VH (VH) 1 0 1 0 0 Read Vector High Byte + + + +Notes: + [1] Delete this cycle in Emulation mode. + [2] Abort writes address of aborted opcode. + [3] R/W remains in the high state during Reset. + [4] In Emulation mode, bit 4 written to stack is changed to 0. + + + +Table 3. Vector Locations + + Emulation Native Priority +Name Source (E = 1) (E = 0) Level + +ABORT Hardware 00FFF8,9 00FFE8,9 2 +BRK Software 00FFFE,F 00FFE6,7 N/A +COP Software 00FFF4,5 00FFE4,5 N/A +IRQ Hardware 00FFFE,F 00FFEE,F 4 +NMI Hardware 00FFFA,B 00FFEA,B 3 +RES Hardware 00FFFC.D 00FFFC,D 1 diff --git a/files/docs/SNES-Memorymap.txt b/files/docs/SNES-Memorymap.txt new file mode 100644 index 0000000..6276a86 --- /dev/null +++ b/files/docs/SNES-Memorymap.txt @@ -0,0 +1,161 @@ +SNES Memory Mapping +by +Duncanthrax of ShadowCraft + +Version: 1.0 +Date: August 28, 1997 + +Introduction: + +This is a little document I'm throwing together as I go. It probably has a few innacuracies, but it's certainly better than nothing. +I became frustrated with the lack of solid knowledge and documentation regarding memory in the SNES, all the other maps +were very incomplete. So, since I'm building an emulator at the moment, I figured I'd write all this down for posterity. + +If you find anything in here that is wrong, or if you have an additions or questions, or suggestions... or if you want to help +with the emulator, mail me at: + +odin@ccs.neu.edu + +Or check out ShadowCraft's web page at: + +http://shadowguild.home.ml.org + +Have fun, and I hope this is helpful. + +*---------------------------------------------------* + +SNES Memory Map in LoROM Mode (Mode 0x20): + +Bank: Address: Purpose: +----- -------- -------- +00-3F 0000-1FFF Shadow RAM + 2000-5FFF Hardware Registers + 6000-7FFF Expansion RAM + 8000-FFFF 32k ROM Chunk +40-7C 0000-7FFF 32k ROM Chunk + 8000-FFFF 32k ROM Chunk +7D 0000-FFFF SRAM +7E 0000-1FFF Shadow RAM + 2000-FFFF System RAM +7F 0000-FFFF System RAM + +80-BF 0000-1FFF Shadow RAM + 2000-5FFF Hardware Registers + 6000-7FFF Expansion RAM + 8000-FFFF 32k ROM Chunk +C0-FC 0000-7FFF 32k ROM Chunk + 8000-FFFF 32k ROM Chunk +FD 0000-FFFF SRAM +FE 0000-1FFF Shadow RAM + 2000-FFFF System RAM +FF 0000-FFxx System RAM + FFxx-FFFF Reset and NMI Vectors + +SNES Memory Map in HiROM Mode (Mode 0x21): + +Bank: Address: Purpose: +----- -------- -------- +00-3F 0000-1FFF Shadow RAM + 2000-5FFF Hardware Registers + 6000-7FFF SRAM + 8000-FFFF 32k ROM Chunk +40-7D 0000-FFFF 64k ROM Chunk +7E 0000-1FFF Shadow RAM + 2000-FFFF System RAM +7F 0000-FFFF System RAM + +80-BF 0000-1FFF Shadow RAM + 2000-5FFF Hardware Registers + 6000-7FFF SRAM + 8000-FFFF 32k ROM Chunk +C0-FE 0000-FFFF 64k ROM Chunk +FF 0000-FFxx 64k ROM Chunk + FFxx-FFFF Reset and NMI Vectors + +*--------------------------------------------* + +Now that I've given you the overview of the memory layout, perhaps a little explanation would be in order. +We'll start at 00.0000 and work our way up... in LoROM first, then HiROM - to avoid confusion. + +00-3F 0000-1FFF Shadow RAM + +What's going on here? Well, this is RAM that is the same in every bank up to and including 7E. It's the first +8k of System RAM. So, if you write 0x42 to 00.1001, you'll read a 0x42 from 7E.1001. Simple, huh? + +00-3F 2000-5FFF Hardware Registers + +This is where you do graphics hardware calls, BIOS calls, DMA calls, and all that stuff. There are lots and +lots of documents on this, all of them confusing. I may write one later on that clarifies a bunch of stuff, but +for now I won't go into greater detail, as this is pretty straightforward... read and write values that interact +with hardware. + +00-3F 6000-7FFF Expansion RAM + +This is one of those areas in which I draw a blank. I'm not certain where this RAM is supposed to map, +whether it is part of system RAM or what. Anybody who wants to clarify the purpose of this area of RAM +can feel free. I've seen at least two cartridges that access this area... + +00-3F 8000-FFFF 32k ROM Chunk +40-7C 0000-7FFF 32k ROM Chunk + 8000-FFFF 32k ROM Chunk + +This bears a little explanation. When the LoROM is loaded into memory, this is where it is mapped +(in a real SNES it isn't "loaded" at all - just mapped). The first 64 32k chunks are loaded into the upper half +of banks 00-3F. Then, you continue at 40, mapping two (2!) 32k chunks in each bank from 40-7C. This +should take care of an entire LoROM. I know that theoretically a LoROM could be slightly bigger than this, +but I've never seen one that is... + +7D 0000-FFFF SRAM + +OK, this is pretty obvious. This is where the battery-backed SRAM on cartridges is mapped. Very simple. +Most have 64kb. DOOM, I've heard, has 256kb. Copiers have 256kb. Simple. + +7E 0000-1FFF Shadow RAM + 2000-FFFF System RAM +7F 0000-FFFF System RAM + +Also very simple. This is the SNES's 128k of RAM. There, that was easy, right? + +80-FF 0000-FFFF MIRROR! + +The upper area of the SNES's addressing space is for "Fast ROM". Games will use this area instead of +the lower area (they're mapped exactly the same) when they want to run faster. The SNES gains 1Mhz +of speed this way. + +The only thing that is different about the upper area is that the vectors for reset and NMI get stored in +the FF.FFxx last 32 bytes... + +*-------------------------------------------* + +LoROM vs. HiROM! + +OK, this is the most interesting part of SNES mapping, and also the part where I'm most likely to get +something wrong. As always, if this is incorrect or confusing, let me know! + +00-3F 0000-5FFF Same as LoROM + +00-3F 6000-7FFF 8k SRAM Chunk + +00-3F 8000-FFFF 32k ROM Chunk +40-7D 0000-FFFF 64k ROM Chunk + +Ok, this is not too hard, with one caveat... the first 64 32k chunks of the HiROM cartridge get loaded +into 00-3F, and then it REPEATS FROM THE BEGINNING starting at 40.0000, this time going in 64k +chunks until the end of the file. Now, people are about to start yelling about how this doesn't leave +room for the last 2 64k chunks of a 32mb ROM. Yes, I know... keep reading. + +7E-7F 0000-FFFF Same as LoROM + +Note 7D is no longer the SRAM, which is now in the expansion ram area. + +80-FD 0000-FFFF Same as LoROM + +FE-FF 0000-FFFF 64k ROM Chunk + +Aha! Here it is... the last two chunks of a 32mb ROM (i.e. Chrono Trigger, etc.) get loaded here. +Remember as always that the last 16 bytes are for vectors, and you're all set! + +*--------------------------------------------* + +Ok kiddies! That was a quick tour through the SNES memory map. Tune in next time for +"Dr. Duncanthrax teaches CPU!" - same Bat Time, same Bat Channel! diff --git a/files/docs/SNES-Memorymap2.txt b/files/docs/SNES-Memorymap2.txt new file mode 100644 index 0000000..d005f33 --- /dev/null +++ b/files/docs/SNES-Memorymap2.txt @@ -0,0 +1,99 @@ + +=-=-=-=-=-=-=-=-=-=-=+ + | SNES Memory Mapping | + | By: ]SiMKiN[ | + | v1.0 | + +=-=-=-=-=-=-=-=-=-=-=+ + +� LoROM: Mode 20 +� HiROM: Mode 21 + + + +� FastROM's can execute at 3.58Mhz +� SlowROM's can only execute 2.68Mhz + + + + � The SNES lets you access ROM through bank $00 onwards and bank + $80 onwards such that locations $00:8000 and $80:8000 are congruent, + (they access the same locations.) + � When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, + when accessing bank $80 onwards the 65816 can run at 2.68Mhz or + 3.58Mhz depending on how you set bit 0 of $420D. + + + ++=========+=============+====================================+=========+ +| Bank | Offset | Definition | Shadow | ++=========+=============+====================================+=========+ +| $00-$2f | $0000-$1fff | LowRAM, each bank is shadowed | $00-$3f | +| | | From bank $7e | $7e | +| | $2000-$2fff | PPU1, APU | $00-$3f | +| | $3000-$3fff | SFX, DSP, etc. | $00-$3f | +| | $4000-$41ff | Controller | $00-$3f | +| | $4200-$5fff | PPU2, DMA, etc. | $00-$3f | +| | $6000-$7fff | Reserved? | $00-$3f | +| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- | ++---------+-------------+------------------------------------+---------+ +| $30-$3f | $0000-$1fff | LowRAM, each bank is shadowed | $00-$3f | +| | | From bank $7e | $7e | +| | $2000-$2fff | PPU1, APU | $00-$3f | +| | $3000-$3fff | SFX, DSP, etc. | $00-$3f | +| | $4000-$41ff | Controller | $00-$3f | +| | $4200-$5fff | PPU2, DMA, etc. | $00-$3f | +| | $6000-$7fff | (Mode 21 - SRAM) 256KBytes | ------- | +| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- | ++---------+-------------+------------------------------------+---------+ +| $40-$6f | $0000-$7fff | (Mode 21 - ROM) | ------- | +| | $8000-$ffff | (Mode 20, 21 - ROM) | ------- | ++---------+-------------+------------------------------------+---------+ +| $70-$77 | $0000-$ffff | (Mode 20, 21 - SRAM) 256KBytes | ------- | ++---------+-------------+------------------------------------+---------+ +| $78-$7d | $0000-$ffff | Never Used | ------- | ++---------+-------------+------------------------------------+---------+ +| $7e | $0000-$1fff | LowRAM | $00-$3f | +| | | Shadowed to banks $00-$3f | ------- | +| | $2000-$7fff | HighRAM | ------- | +| | $8000-$ffff | Expanded Ram | ------- | ++---------+-------------+------------------------------------+---------+ +| $7f | $0000-$ffff | More Expanded RAM | ------- | ++---------+-------------+------------------------------------+---------+ +| $80-$ef | $0000-$ffff | Mirror of $00-$6f | $00-$6f | ++---------+-------------+------------------------------------+---------+ +| $f0-$ff | $0000-$ffff | (Mode 21 - ROM) | ------- | ++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ + + + +� ROM: The SNES ROM Image +� RAM: The SNES Work Memory (WRAM) + LowRAM, HighRAM, & Expanded RAM + All together = 128 Kilo-Bytes +� SRAM: Save RAM (Extra RAM added by Cart) + The SNES only utilizes 256 Kilo-bits + However 256 Kilo-Bytes are provided. + + + +� APU: Audio Processing Unit + SPC700, Inside which has a DSP + +� PPU: Picture Processing Unit + PPU1: 5c77-01 + PPU2: 5c78-03 + + + +� SFX: Super FX Cart Chip, by Nintendo +� DSP: Digital Signal Processing Cart Chip + a.k.a. 'NEC mUPD77C25' + + + +� Shadow: "Congruent Bank". Same meaning as Mirror. + + + + _________________________________________________ + .o(_Thanx to: Y0SHi, zsKnight, MrGrim, and MintaBoo_)o. +