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add first sreg code

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This commit is contained in:
David Voswinkel
2009-06-23 23:56:02 +02:00
parent f3cc60e77b
commit c4631f2991
7 changed files with 384 additions and 500 deletions
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70
avr/usbload/main.c
View File

@@ -179,13 +179,64 @@ uint8_t usbFunctionRead(uint8_t * data, uint8_t len)
int main(void)
{
uint8_t i;
wdt_enable(WDTO_1S);
uint32_t addr;
wdt_enable(WDTO_8S);
uart_init();
stdout = &uart_stdout;
sram_init();
printf("SRAM Init\n");
spi_init();
printf("SPI Init\n");
system_init();
printf("Sytem Init\n");
avr_bus_active();
DDRB|= (1 << PB1);
PORTB|= (1 << PB1);
while(1)
wdt_reset();
#if 0
avr_bus_active();
printf("set sreg 0xff55aa\n");
sreg_set(0xff55aa);
counter_load();
sram_write(0xff55aa,0x55);
while(1)
wdt_reset();
addr = 0x3fffff;
sreg_set(0x00000);
counter_load();
wdt_reset();
while(addr--){
counter_up();
}
printf("done\n");
while(1){
wdt_reset();
i = 10;
while(i--)
_delay_ms(100);
//printf("counter up\n");
}
#endif
avr_bus_active();
#if 1
addr = 0x00;
i = 0;
while (addr++ <= 0xff){
sram_write(addr,i++);
}
#endif
addr = 0x00;
while (addr++ <= 0xff){
printf("read addr=0x%08lx %x\n",addr,sram_read(addr));
}
while(1);
usbInit();
printf("USB Init\n");
usbDeviceDisconnect(); /* enforce re-enumeration, do this while
@@ -195,8 +246,15 @@ int main(void)
i = 10;
while (--i) { /* fake USB disconnect for > 250 ms */
wdt_reset();
_delay_ms(10);
led_on();
_delay_ms(35);
led_off();
_delay_ms(65);
}
led_on();
usbDeviceConnect();
printf("USB connect\n");
sei();

217
avr/usbload/sram.c
View File

@@ -1,67 +1,110 @@
#include <stdlib.h>
#include <stdint.h>
#include <avr/io.h>
#include <avr/wdt.h>
#include <util/delay.h> /* for _delay_ms() */
#include "sram.h"
#include "uart.h"
#include "debug.h"
void spi_init(void)
{
/*
* Set MOSI and SCK output, all others input
*/
SPI_DIR |= ((1 << S_MOSI) | (1 << S_SCK) | (1 << S_LATCH));
SPI_DIR &= ~(1 << S_MISO);
SPI_PORT |= (1 << S_MISO);
/*
* Enable SPI, Master
*/
SPCR = ((1 << SPE) | (1 << MSTR));
}
void spi_master_transmit(unsigned char cData)
void system_init(void)
{
/*
* Start transmission
*/
SPDR = cData;
/*-------------------------------------------------*/
DDRA = 0x00;
PORTA = 0x00;
/*-------------------------------------------------*/
DDRC |= ( (1 << AVR_ADDR_LATCH_PIN)
| (1 << AVR_ADDR_SCK_PIN)
| (1 << AVR_ADDR_SER_PIN)
| (1 << AVR_ADDR_LOAD_PIN)
| (1 << AVR_ADDR_DOWN_PIN)
| (1 << AVR_ADDR_UP_PIN));
DDRC &= ~ (1 << SNES_WR_PIN);
PORTC &= ~((1 << AVR_ADDR_LATCH_PIN)
| (1 << AVR_ADDR_SCK_PIN));
PORTC |= ( (1 << AVR_ADDR_DOWN_PIN)
| (1 << AVR_ADDR_UP_PIN)
| (1 << AVR_ADDR_LOAD_PIN)
| (1 << SNES_WR_PIN));
/*-------------------------------------------------*/
DDRB |= ( (1 << AVR_RD_PIN)
| (1 << AVR_WR_PIN)
| (1 << AVR_CS_PIN)
| (1 << SNES_IRQ_PIN));
PORTB |= ( (1 << AVR_RD_PIN)
| (1 << AVR_WR_PIN)
| (1 << AVR_CS_PIN)
| (1 << SNES_IRQ_PIN));
/*-------------------------------------------------*/
DDRD |= ( (1 << AVR_SNES_SW_PIN)
| (1 << HI_LOROM_SW_PIN)
| (1 << SNES_WR_EN_PIN));
/*
* Wait for transmission complete
*/
while (!(SPSR & (1 << SPIF)));
PORTD |= (1 << HI_LOROM_SW_PIN);
PORTD &= ~((1 << AVR_SNES_SW_PIN)
| (1 << SNES_WR_EN_PIN));
/*-------------------------------------------------*/
}
void sreg_set(uint32_t addr)
{
uint8_t i = 24;
printf("sreg addr=0x%08lx ",addr);
while(i--) {
if ((addr & ( 1L << i))){
printf("1");
AVR_ADDR_SER_PORT |= ( 1 << AVR_ADDR_SER_PIN);
} else {
AVR_ADDR_SER_PORT &= ~( 1 << AVR_ADDR_SER_PIN);
printf("0");
}
AVR_ADDR_SCK_PORT |= (1 << AVR_ADDR_SCK_PIN);
AVR_ADDR_SCK_PORT &= ~(1 << AVR_ADDR_SCK_PIN);
}
printf("\n");
AVR_ADDR_LATCH_PORT |= (1 << AVR_ADDR_LATCH_PIN);
AVR_ADDR_LATCH_PORT &= ~(1 << AVR_ADDR_LATCH_PIN);
counter_load();
}
void sram_set_addr(uint32_t addr)
{
spi_master_transmit((uint8_t) (addr >> 16));
spi_master_transmit((uint8_t) (addr >> 8));
spi_master_transmit((uint8_t) (addr >> 0));
LATCH_PORT |= (1 << S_LATCH);
LATCH_PORT &= ~(1 << S_LATCH);
}
uint8_t sram_read(uint32_t addr)
{
uint8_t byte;
RAM_DIR = 0x00;
RAM_PORT = 0xff;
CTRL_PORT |= (1 << R_RD);
CTRL_PORT |= (1 << R_WR);
spi_master_transmit((uint8_t) (addr >> 16));
spi_master_transmit((uint8_t) (addr >> 8));
spi_master_transmit((uint8_t) (addr >> 0));
LATCH_PORT |= (1 << S_LATCH);
LATCH_PORT &= ~(1 << S_LATCH);
CTRL_PORT &= ~(1 << R_RD);
avr_data_in();
AVR_WR_PORT |= (1 << AVR_WR_PIN);
AVR_RD_PORT |= (1 << AVR_RD_PIN);
AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
_delay_ms(1);
sreg_set(addr);
AVR_RD_PORT &= ~(1 << AVR_RD_PIN);
asm volatile ("nop");
asm volatile ("nop");
asm volatile ("nop");
@@ -70,65 +113,39 @@ uint8_t sram_read(uint32_t addr)
asm volatile ("nop");
asm volatile ("nop");
asm volatile ("nop");
byte = RAM_REG;
CTRL_PORT |= (1 << R_RD);
RAM_DIR = 0x00;
RAM_PORT = 0x00;
byte = AVR_DATA_PIN;
#if 0
printf("read %x\n",byte);
while(1)
wdt_reset();
#endif
AVR_RD_PORT |= (1 << AVR_RD_PIN);
AVR_CS_PORT |= (1 << AVR_CS_PIN);
avr_data_in();
return byte;
}
void sram_write(uint32_t addr, uint8_t data)
{
RAM_DIR = 0xff;
CTRL_PORT |= (1 << R_RD);
CTRL_PORT |= (1 << R_WR);
spi_master_transmit((uint8_t) (addr >> 16));
spi_master_transmit((uint8_t) (addr >> 8));
spi_master_transmit((uint8_t) (addr >> 0));
LATCH_PORT |= (1 << S_LATCH);
LATCH_PORT &= ~(1 << S_LATCH);
CTRL_PORT &= ~(1 << R_WR);
RAM_PORT = data;
CTRL_PORT |= (1 << R_WR);
RAM_DIR = 0x00;
RAM_PORT = 0x00;
}
void sram_init(void)
{
RAM_DIR = 0x00;
RAM_PORT = 0x00;
CTRL_DIR |= ((1 << R_WR) | (1 << R_RD));
CTRL_PORT |= (1 << R_RD);
CTRL_PORT |= (1 << R_WR);
LED_PORT |= (1 << D_LED0);
}
void sram_snes_mode01(void)
{
CTRL_PORT |= (1 << R_WR);
CTRL_PORT &= ~(1 << R_RD);
}
void sram_snes_mode02(void)
{
CTRL_DIR |= (1 << R_WR);
CTRL_PORT |= (1 << R_WR);
// CTRL_PORT &= ~(1<<R_RD);
CTRL_DIR &= ~(1 << R_RD);
CTRL_PORT &= ~(1 << R_RD);
avr_data_out();
AVR_CS_PORT &= ~(1 << AVR_CS_PIN);
AVR_WR_PORT |= (1 << AVR_WR_PIN);
AVR_RD_PORT |= (1 << AVR_RD_PIN);
sreg_set(addr);
AVR_WR_PORT &= ~(1 << AVR_WR_PIN);
AVR_DATA_PORT = data;
AVR_WR_PORT |= (1 << AVR_WR_PIN);
AVR_CS_PORT |= (1 << AVR_CS_PIN);
avr_data_in();
}

152
avr/usbload/sram.h
View File

@@ -3,48 +3,132 @@
#include <avr/io.h>
//SREG defines
#define S_MOSI PB5
#define S_MISO PB6
#define S_SCK PB7
#define S_LATCH PB4
//DEBUG defines
#define D_LED0 PD6
//SRAM defines
#define R_WR PB1
#define R_RD PB0
#define RAM_PORT PORTA
#define RAM_DIR DDRA
#define RAM_REG PINA
#define CTRL_PORT PORTB
#define CTRL_DIR DDRB
#define LATCH_PORT PORTB
#define LATCH_DIR DDRB
#define SPI_PORT PORTB
#define SPI_DIR DDRB
#define LED_PORT PORTD
#define LED_DIR DDRD
#define ROMSIZE 4
#define BLOCKS (ROMSIZE << 8)
#define MEMSIZE 0x80000
void spi_init(void);
void spi_master_transmit(unsigned char cData);
void sram_set_addr(uint32_t addr);
#define LED_PORT PORTC
#define LED_DIR DDRC
#define LED_PIN PC7
#define led_on() ((LED_PORT &=~ (1 << LED_PIN)),\
(LED_DIR &=~ (1 << LED_PIN)))
#define led_off() ((LED_PORT &=~ (1 << LED_PIN)),\
(LED_DIR |= (1 << LED_PIN)))
/* Port C*/
#define AVR_ADDR_PORT PORTC
#define AVR_ADDR_DIR DDRC
#define AVR_ADDR_LATCH_PORT PORTC
#define AVR_ADDR_LATCH_DIR DDRC
#define AVR_ADDR_LATCH_PIN PC6
#define AVR_ADDR_SCK_PORT PORTC
#define AVR_ADDR_SCK_DIR DDRC
#define AVR_ADDR_SCK_PIN PC5
#define AVR_ADDR_SER_PORT PORTC
#define AVR_ADDR_SER_DIR DDRC
#define AVR_ADDR_SER_PIN PC4
#define AVR_ADDR_LOAD_PORT PORTC
#define AVR_ADDR_LOAD_DIR DDRC
#define AVR_ADDR_LOAD_PIN PC2
#define counter_load() ((AVR_ADDR_LOAD_PORT &= ~(1 << AVR_ADDR_LOAD_PIN)),\
(AVR_ADDR_LOAD_PORT |= (1 << AVR_ADDR_LOAD_PIN)))
#define AVR_ADDR_DOWN_PORT PORTC
#define AVR_ADDR_DOWN_DIR DDRC
#define AVR_ADDR_DOWN_PIN PC1
#define counter_down() ((AVR_ADDR_DOWN_PORT &= ~(1 << AVR_ADDR_DOWN_PIN)),\
(AVR_ADDR_DOWN_PORT |= (1 << AVR_ADDR_DOWN_PIN)))
#define AVR_ADDR_UP_PORT PORTC
#define AVR_ADDR_UP_DIR DDRC
#define AVR_ADDR_UP_PIN PC0
#define counter_up() ((AVR_ADDR_UP_PORT &= ~(1 << AVR_ADDR_UP_PIN)),\
(AVR_ADDR_UP_PORT |= (1 << AVR_ADDR_UP_PIN)))
#define SNES_WR_PORT PORTC
#define SNES_WR_DIR DDRC
#define SNES_WR_PIN PC3
/* Port B*/
#define AVR_PORT PORTB
#define AVR_DIR DDRB
#define AVR_RD_PORT PORTB
#define AVR_RD_DIR DDRB
#define AVR_RD_PIN PB2
#define AVR_WR_PORT PORTB
#define AVR_WR_DIR DDRB
#define AVR_WR_PIN PB1
#define AVR_CS_PORT PORTB
#define AVR_CS_DIR DDRB
#define AVR_CS_PIN PB0
#define SNES_IRQ_PORT PORTB
#define SNES_IRQ_DIR DDRB
#define SNES_IRQ_PIN PB3
#define snes_irq_off() (SNES_IRQ_PORT |= (1 << SNES_IRQ_PIN))
#define snes_irq_on() (SNES_IRQ_PORT &= ~(1 << SNES_IRQ_PIN))
/* Port A*/
#define AVR_DATA_PORT PORTA
#define AVR_DATA_DIR DDRA
#define AVR_DATA_PIN PINA
#define avr_data_in() ((AVR_DATA_DIR = 0x00),\
(AVR_DATA_PORT = 0x00))
#define avr_data_out() (AVR_DATA_DIR = 0xff)
/* Port D*/
#define AVR_SNES_PORT PORTD
#define AVR_SNES_DIR DDRD
#define AVR_SNES_SW_PORT PORTD
#define AVR_SNES_SW_DIR DDRD
#define AVR_SNES_SW_PIN PD5
#define avr_bus_active() ((AVR_SNES_SW_PORT &= ~(1 << AVR_SNES_SW_PIN)),\
(HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN)))
#define snes_bus_active() (AVR_SNES_SW_PORT |= (1 << AVR_SNES_SW_PIN))
#define HI_LOROM_SW_PORT PORTD
#define HI_LOROM_SW_DIR DDRD
#define HI_LOROM_SW_PIN PD6
#define snes_hirom() (HI_LOROM_SW_PORT &= ~(1 << HI_LOROM_SW_PIN))
#define snes_lorom() (HI_LOROM_SW_PORT |= (1 << HI_LOROM_SW_PIN))
#define SNES_WR_EN_PORT PORTD
#define SNES_WR_EN_DIR DDRD
#define SNES_WR_EN_PIN PD7
#define snes_wr_disable() (SNES_WR_EN_PORT &= ~(1 << SNES_WR_EN_PIN))
#define snes_wr_enable() (SNES_WR_EN_PORT |= (1 << SNES_WR_EN_PIN))
void system_init(void);
void sreg_set(uint32_t addr);
uint8_t sram_read(uint32_t addr);
void sram_write(uint32_t addr, uint8_t data);
void sram_init(void);
void sram_snes_mode01(void);
void sram_snes_mode02(void);
void sram_clear(uint32_t addr, uint32_t len);
void sram_copy(uint32_t addr,uint8_t *src, uint32_t len);
void sram_read_buffer(uint32_t addr,uint8_t *dst, uint32_t len);