o add ff lib
o add ff lib samples o add ff linux sample
This commit is contained in:
David Voswinkel
464
tools/ffsample/avr/cfc.c
Normal file
464
tools/ffsample/avr/cfc.c
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/*-----------------------------------------------------------------------*/
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/* CompactFlash control module (C)ChaN, 2007 */
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/*-----------------------------------------------------------------------*/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <string.h>
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#include "diskio.h"
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/* ATA command */
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#define CMD_RESET 0x08 /* DEVICE RESET */
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#define CMD_READ 0x20 /* READ SECTOR(S) */
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#define CMD_WRITE 0x30 /* WRITE SECTOR(S) */
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#define CMD_IDENTIFY 0xEC /* DEVICE IDENTIFY */
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#define CMD_SETFEATURES 0xEF /* SET FEATURES */
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/* ATA register bit definitions */
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#define LBA 0xE0
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#define BUSY 0x80
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#define DRDY 0x40
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#define DF 0x20
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#define DRQ 0x08
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#define ERR 0x01
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#define SRST 0x40
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#define nIEN 0x20
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/* Contorl Ports */
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#define CTRL_PORT PORTA
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#define CTRL_DDR DDRA
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#define SOCK_PORT PORTC
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#define SOCK_DDR DDRC
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#define SOCK_PIN PINC
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#define DAT0_PORT PORTD
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#define DAT0_DDR DDRD
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#define DAT0_PIN PIND
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#define SOCKINS 0x03
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#define SOCKPWR 0x04
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/* Bit definitions for Control Port */
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#define CTL_READ 0x20
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#define CTL_WRITE 0x40
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#define CTL_RESET 0x80
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#define REG_DATA 0xF0
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#define REG_ERROR 0xF1
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#define REG_FEATURES 0xF1
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#define REG_COUNT 0xF2
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#define REG_SECTOR 0xF3
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#define REG_CYLL 0xF4
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#define REG_CYLH 0xF5
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#define REG_DEV 0xF6
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#define REG_COMMAND 0xF7
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#define REG_STATUS 0xF7
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#define REG_DEVCTRL 0xEE
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#define REG_ALTSTAT 0xEE
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/*--------------------------------------------------------------------------
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Module Private Functions
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---------------------------------------------------------------------------*/
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static volatile
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DSTATUS Stat = STA_NOINIT; /* Disk status */
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static volatile
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BYTE Timer; /* 100Hz decrement timer */
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/*-----------------------------------------------------------------------*/
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/* Read an ATA register */
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/*-----------------------------------------------------------------------*/
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static
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BYTE read_ata (
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BYTE reg /* Register to be read */
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)
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{
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BYTE rd;
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CTRL_PORT = reg;
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CTRL_PORT &= ~CTL_READ;
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CTRL_PORT &= ~CTL_READ;
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CTRL_PORT &= ~CTL_READ;
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rd = DAT0_PIN;
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CTRL_PORT |= CTL_READ;
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return rd;
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}
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/*-----------------------------------------------------------------------*/
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/* Write a byte to an ATA register */
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/*-----------------------------------------------------------------------*/
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static
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void write_ata (
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BYTE reg, /* Register to be written */
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BYTE dat /* Data to be written */
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)
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{
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CTRL_PORT = reg;
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DAT0_PORT = dat;
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DAT0_DDR = 0xFF;
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CTRL_PORT &= ~CTL_WRITE;
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CTRL_PORT &= ~CTL_WRITE;
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CTRL_PORT |= CTL_WRITE;
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DAT0_PORT = 0xFF;
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DAT0_DDR = 0;
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}
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/*-----------------------------------------------------------------------*/
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/* Read a part of data block */
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/*-----------------------------------------------------------------------*/
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static
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void read_part (
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BYTE *buff, /* Data buffer to store read data */
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BYTE ofs, /* Offset of the part of data in unit of word */
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BYTE count /* Number of word to pick up */
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)
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{
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BYTE c = 0, dl, dh;
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CTRL_PORT = REG_DATA; /* Select Data register */
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do {
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CTRL_PORT &= ~CTL_READ; /* IORD = L */
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CTRL_PORT &= ~CTL_READ; /* delay */
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dl = DAT0_PIN; /* Read Even data */
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CTRL_PORT |= CTL_READ; /* IORD = H */
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CTRL_PORT &= ~CTL_READ; /* IORD = L */
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CTRL_PORT &= ~CTL_READ; /* delay */
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dh = DAT0_PIN; /* Read Odd data */
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CTRL_PORT |= CTL_READ; /* IORD = H */
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if (count && (c >= ofs)) { /* Pick up a part of block */
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*buff++ = dl;
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*buff++ = dh;
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count--;
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}
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} while (++c);
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read_ata(REG_ALTSTAT);
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read_ata(REG_STATUS);
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}
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/*-----------------------------------------------------------------------*/
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/* Wait for Data Ready */
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/*-----------------------------------------------------------------------*/
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static
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BOOL wait_data (void)
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{
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BYTE s;
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Timer = 100; /* Time out = 1 sec */
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do {
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if (!Timer) return FALSE; /* Abort when timeout occured */
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s = read_ata(REG_STATUS); /* Get status */
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} while ((s & (BUSY|DRQ)) != DRQ); /* Wait for BUSY goes low and DRQ goes high */
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read_ata(REG_ALTSTAT);
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return TRUE;
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}
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/*--------------------------------------------------------------------------
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Public Functions
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---------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------*/
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/* Initialize Disk Drive */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_initialize (
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BYTE drv /* Physical drive nmuber (0) */
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)
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{
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if (drv) return STA_NOINIT; /* Supports only single drive */
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Stat |= STA_NOINIT;
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SOCK_PORT = 0xFF; /* Power OFF */
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SOCK_DDR = SOCKPWR;
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DAT0_PORT = 0;
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CTRL_DDR = 0;
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for (Timer = 10; Timer; ); /* 100ms */
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if (Stat & STA_NODISK) return Stat; /* Exit when socket is empty */
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/* Initialize CFC control port */
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SOCK_PORT &= ~SOCKPWR; /* Power ON */
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for (Timer = 1; Timer; ); /* 10ms */
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CTRL_PORT = CTL_READ | CTL_WRITE; /* Enable control signals */
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CTRL_DDR = 0xFF;
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DAT0_PORT = 0xFF; /* Pull-up D0-D7 */
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for (Timer = 5; Timer; ); /* 50ms */
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CTRL_PORT |= CTL_RESET; /* RESET = H */
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for (Timer = 5; Timer; ); /* 50ms */
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write_ata(REG_DEV, LBA); /* Select Device 0 */
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Timer = 200;
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do { /* Wait for card goes ready */
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if (!Timer) return Stat;
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} while (read_ata(REG_STATUS) & BUSY);
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write_ata(REG_DEVCTRL, SRST | nIEN); /* Software reset */
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for (Timer = 2; Timer; ); /* 20ms */
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write_ata(REG_DEVCTRL, nIEN); /* Release software reset */
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for (Timer = 2; Timer; ); /* 20ms */
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Timer = 200;
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do { /* Wait for card goes ready */
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if (!Timer) return Stat;
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} while ((read_ata(REG_STATUS) & (DRDY|BUSY)) != DRDY);
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write_ata(REG_FEATURES, 0x01); /* Select 8-bit PIO transfer mode */
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write_ata(REG_COMMAND, CMD_SETFEATURES);
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Timer = 100;
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do {
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if (!Timer) return Stat;
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} while (read_ata(REG_STATUS) & BUSY);
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Stat &= ~STA_NOINIT; /* When device goes ready, clear STA_NOINIT */
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return Stat;
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}
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/*-----------------------------------------------------------------------*/
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/* Return Disk Status */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_status (
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BYTE drv /* Physical drive nmuber (0) */
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)
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{
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if (drv) return STA_NOINIT; /* Supports only single drive */
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return Stat;
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}
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/*-----------------------------------------------------------------------*/
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/* Read Sector(s) */
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/*-----------------------------------------------------------------------*/
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DRESULT disk_read (
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BYTE drv, /* Physical drive nmuber (0) */
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BYTE *buff, /* Data buffer to store read data */
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DWORD sector, /* Sector number (LBA) */
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BYTE count /* Sector count (1..255) */
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)
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{
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BYTE c, iord_l, iord_h;
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if (drv || !count) return RES_PARERR;
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if (Stat & STA_NOINIT) return RES_NOTRDY;
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/* Issue Read Setor(s) command */
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write_ata(REG_COUNT, count);
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write_ata(REG_SECTOR, (BYTE)sector);
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write_ata(REG_CYLL, (BYTE)(sector >> 8));
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write_ata(REG_CYLH, (BYTE)(sector >> 16));
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write_ata(REG_DEV, ((BYTE)(sector >> 24) & 0x0F) | LBA);
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write_ata(REG_COMMAND, CMD_READ);
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do {
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if (!wait_data()) return RES_ERROR; /* Wait data ready */
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CTRL_PORT = REG_DATA;
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iord_h = REG_DATA;
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iord_l = REG_DATA & ~CTL_READ;
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c = 0;
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do {
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CTRL_PORT = iord_l; /* IORD = L */
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CTRL_PORT = iord_l; /* delay */
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CTRL_PORT = iord_l; /* delay */
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*buff++ = DAT0_PIN; /* Get even data */
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CTRL_PORT = iord_h; /* IORD = H */
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CTRL_PORT = iord_l; /* IORD = L */
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CTRL_PORT = iord_l; /* delay */
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CTRL_PORT = iord_l; /* delay */
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*buff++ = DAT0_PIN; /* Get Odd data */
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CTRL_PORT = iord_h; /* IORD = H */
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} while (--c);
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} while (--count);
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read_ata(REG_ALTSTAT);
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read_ata(REG_STATUS);
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return RES_OK;
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}
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/*-----------------------------------------------------------------------*/
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/* Write Sector(s) */
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/*-----------------------------------------------------------------------*/
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#if _READONLY == 0
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DRESULT disk_write (
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BYTE drv, /* Physical drive nmuber (0) */
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const BYTE *buff, /* Data to be written */
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DWORD sector, /* Sector number (LBA) */
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BYTE count /* Sector count (1..255) */
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)
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{
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BYTE s, c, iowr_l, iowr_h;
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if (drv || !count) return RES_PARERR;
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if (Stat & STA_NOINIT) return RES_NOTRDY;
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/* Issue Write Setor(s) command */
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write_ata(REG_COUNT, count);
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write_ata(REG_SECTOR, (BYTE)sector);
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write_ata(REG_CYLL, (BYTE)(sector >> 8));
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write_ata(REG_CYLH, (BYTE)(sector >> 16));
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write_ata(REG_DEV, ((BYTE)(sector >> 24) & 0x0F) | LBA);
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write_ata(REG_COMMAND, CMD_WRITE);
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do {
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if (!wait_data()) return RES_ERROR;
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CTRL_PORT = REG_DATA;
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iowr_h = REG_DATA;
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iowr_l = REG_DATA & ~CTL_WRITE;
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DAT0_DDR = 0xFF; /* Set D0-D7 as output */
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c = 0;
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do {
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DAT0_PORT = *buff++; /* Set even data */
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CTRL_PORT = iowr_l; /* IOWR = L */
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CTRL_PORT = iowr_h; /* IOWR = H */
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DAT0_PORT = *buff++; /* Set odd data */
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CTRL_PORT = iowr_l; /* IOWR = L */
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CTRL_PORT = iowr_h; /* IOWR = H */
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} while (--c);
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DAT0_PORT = 0xFF; /* Set D0-D7 as input */
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DAT0_DDR = 0;
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} while (--count);
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Timer = 100;
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do {
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if (!Timer) return RES_ERROR;
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s = read_ata(REG_STATUS);
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} while (s & BUSY);
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if (s & ERR) return RES_ERROR;
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read_ata(REG_ALTSTAT);
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read_ata(REG_STATUS);
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return RES_OK;
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}
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#endif /* _READONLY */
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/*-----------------------------------------------------------------------*/
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/* Miscellaneous Functions */
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/*-----------------------------------------------------------------------*/
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#if _USE_IOCTL != 0
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DRESULT disk_ioctl (
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BYTE drv, /* Physical drive nmuber (0) */
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BYTE ctrl, /* Control code */
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void *buff /* Buffer to send/receive data block */
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)
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{
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BYTE n, w, ofs, dl, dh, *ptr = buff;
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if (drv) return RES_PARERR;
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if (Stat & STA_NOINIT) return RES_NOTRDY;
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switch (ctrl) {
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case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
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ofs = 60; w = 2; n = 0;
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break;
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case GET_SECTOR_SIZE : /* Get sectors on the disk (WORD) */
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*(WORD*)buff = 512;
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return RES_OK;
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case GET_BLOCK_SIZE : /* Get erase block size in sectors (DWORD) */
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*(DWORD*)buff = 32;
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return RES_OK;
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case CTRL_SYNC : /* Nothing to do */
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return RES_OK;
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case ATA_GET_REV : /* Get firmware revision (8 chars) */
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ofs = 23; w = 4; n = 4;
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break;
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case ATA_GET_MODEL : /* Get model name (40 chars) */
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ofs = 27; w = 20; n = 20;
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break;
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case ATA_GET_SN : /* Get serial number (20 chars) */
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ofs = 10; w = 10; n = 10;
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break;
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default:
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return RES_PARERR;
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}
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write_ata(REG_COMMAND, CMD_IDENTIFY);
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if (!wait_data()) return RES_ERROR;
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read_part(ptr, ofs, w);
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while (n--) {
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dl = *ptr; dh = *(ptr+1);
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*ptr++ = dh; *ptr++ = dl;
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}
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return RES_OK;
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}
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#endif /* _USE_IOCTL != 0 */
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/*-----------------------------------------------------------------------*/
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/* Device timer interrupt procedure */
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/*-----------------------------------------------------------------------*/
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/* This function must be called in period of 10ms */
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void disk_timerproc (void)
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{
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static BYTE pv;
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BYTE n;
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n = Timer; /* 100Hz decrement timer */
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if (n) Timer = --n;
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n = pv;
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pv = SOCK_PIN & SOCKINS; /* Sapmle socket switch */
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if (n == pv) { /* Have contacts stabled? */
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if (pv & SOCKINS) { /* CD1 or CD2 is high (Socket empty) */
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Stat |= (STA_NODISK | STA_NOINIT);
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DAT0_DDR = 0; DAT0_PORT = 0; /* Float D0-D7 */
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CTRL_DDR = CTL_RESET; CTRL_PORT = 0; /* Assert RESET# */
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SOCK_PORT |= SOCKPWR; /* Power OFF */
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} else { /* CD1 and CD2 are low (Card inserted) */
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Stat &= ~STA_NODISK;
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}
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}
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}
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