116 lines
4.0 KiB
C
116 lines
4.0 KiB
C
/*
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Initialisation functions for exception handlers, PLL and MAM
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Partially copied from Jim Lynch's tutorial
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*/
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/**********************************************************
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Header files
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**********************************************************/
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#include "startup.h"
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#define MAMCR *(volatile unsigned int *)0xE01FC000
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#define MAMTIM *(volatile unsigned int *)0xE01FC004
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#define PLLCON *(volatile unsigned int *)0xE01FC080
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#define PLLCFG *(volatile unsigned int *)0xE01FC084
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#define PLLSTAT *(volatile unsigned int *)0xE01FC088
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#define PLLFEED *(volatile unsigned int *)0xE01FC08C
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#define VPBDIV *(volatile unsigned int *)0xE01FC100
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void IRQ_Routine(void) __attribute__ ((interrupt("IRQ")));
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void FIQ_Routine(void) __attribute__ ((interrupt("FIQ")));
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void SWI_Routine(void) __attribute__ ((interrupt("SWI")));
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void UNDEF_Routine(void) __attribute__ ((interrupt("UNDEF")));
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/* Stubs for various interrupts (may be replaced later) */
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/* ---------------------------------------------------- */
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void IRQ_Routine(void)
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{
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while (1);
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}
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void FIQ_Routine(void)
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{
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while (1);
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}
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void SWI_Routine(void)
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{
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while (1);
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}
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void UNDEF_Routine(void)
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{
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while (1);
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}
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/**********************************************************
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Initialize
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**********************************************************/
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#define PLOCK 0x400
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static void feed(void)
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{
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PLLFEED = 0xAA;
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PLLFEED = 0x55;
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} void Initialize(void)
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{
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// Setting the Phased Lock Loop (PLL)
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// ----------------------------------
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//
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// Olimex LPC-P2148 has a 12.0000 mhz crystal
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//
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// We'd like the LPC2148 to run at 60 mhz (has to be an even multiple of crystal)
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//
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// According to the Philips LPC2148 manual: M = cclk / Fosc where: M = PLL multiplier (bits 0-4 of PLLCFG)
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// cclk = 60000000 hz
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// Fosc = 12000000 hz
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//
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// Solving: M = 60000000 / 12000000 = 5
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//
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// Note: M - 1 must be entered into bits 0-4 of PLLCFG (assign 4 to these bits)
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//
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//
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// The Current Controlled Oscilator (CCO) must operate in the range 156 mhz to 320 mhz
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//
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// According to the Philips LPC2148 manual: Fcco = cclk * 2 * P where: Fcco = CCO frequency
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// cclk = 60000000 hz
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// P = PLL divisor (bits 5-6 of PLLCFG)
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//
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// Solving: Fcco = 60000000 * 2 * P
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// P = 2 (trial value)
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// Fcco = 60000000 * 2 * 2
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// Fcc0 = 240000000 hz (good choice for P since it's within the 156 mhz to 320 mhz range)
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//
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// From Table 22 (page 34) of Philips LPC2148 manual P = 2, PLLCFG bits 5-6 = 1 (assign 1 to these bits)
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//
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// Finally: PLLCFG = 0 01 00100 = 0x24
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//
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// Final note: to load PLLCFG register, we must use the 0xAA followed 0x55 write sequence to the PLLFEED register
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// this is done in the short function feed() below
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//
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// Setting Multiplier and Divider values
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PLLCFG = 0x24;
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feed();
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// Enabling the PLL */
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PLLCON = 0x1;
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feed();
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// Wait for the PLL to lock to set frequency
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while (!(PLLSTAT & PLOCK));
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// Connect the PLL as the clock source
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PLLCON = 0x3;
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feed();
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// Enabling MAM and setting number of clocks used for Flash memory fetch
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MAMTIM = 0x3;
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MAMCR = 0x2;
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// Setting peripheral Clock (pclk) to System Clock (cclk)
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VPBDIV = 0x1;
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}
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