127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/*
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* =====================================================================================
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*
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* ________ .__ __ ________ ____ ________
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* \_____ \ __ __|__| ____ | | __\______ \ _______ _/_ |/ _____/
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* / / \ \| | \ |/ ___\| |/ / | | \_/ __ \ \/ /| / __ \
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* / \_/. \ | / \ \___| < | ` \ ___/\ / | \ |__\ \
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* \_____\ \_/____/|__|\___ >__|_ \/_______ /\___ >\_/ |___|\_____ /
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* \__> \/ \/ \/ \/ \/
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* ___.
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* __ __ _____\_ |__
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* | | \/ ___/| __ \
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* | | /\___ \ | \_\ \
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* |____//____ >|___ /
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* \/ \/
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*
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* www.optixx.org
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*
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*
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* Version: 1.0
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* Created: 07/21/2009 03:32:16 PM
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* Author: david@optixx.org
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*
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* =====================================================================================
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include "crc.h"
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#include "uart.h"
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#include "config.h"
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#include "sram.h"
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#include "debug.h"
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extern FILE uart_stdout;
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uint16_t crc_xmodem_update(uint16_t crc, uint8_t data)
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{
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int i;
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crc = crc ^ ((uint16_t) data << 8);
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for (i = 0; i < 8; i++) {
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if (crc & 0x8000)
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crc = (crc << 1) ^ 0x1021;
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else
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crc <<= 1;
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}
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return crc;
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}
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uint16_t do_crc(uint8_t * data, uint16_t size)
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{
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uint16_t crc = 0;
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uint16_t i;
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for (i = 0; i < size; i++) {
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crc = crc_xmodem_update(crc, data[i]);
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}
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return crc;
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}
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uint16_t do_crc_update(uint16_t crc, uint8_t * data, uint16_t size)
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{
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uint16_t i;
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for (i = 0; i < size; i++)
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crc = crc_xmodem_update(crc, data[i]);
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return crc;
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}
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uint16_t crc_check_bulk_memory(uint32_t bottom_addr, uint32_t top_addr, uint32_t bank_size)
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{
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uint16_t crc = 0;
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uint32_t addr = 0;
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uint8_t req_bank = 0;
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sram_bulk_read_start(bottom_addr);
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for (addr = bottom_addr; addr < top_addr; addr++) {
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if (addr && addr % bank_size == 0) {
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debug(DEBUG_CRC,"crc_check_bulk_memory: bank=0x%02x addr=0x%08lx crc=0x%04x\n",
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req_bank,addr,crc);
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req_bank++;
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crc = 0;
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}
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crc = crc_xmodem_update(crc, sram_bulk_read());
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sram_bulk_read_next();
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}
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if (addr % 0x8000 == 0)
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debug(DEBUG_CRC,"crc_check_bulk_memory: bank=0x%02x addr=0x%08lx crc=0x%04x\n",
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req_bank,addr,crc);
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sram_bulk_read_end();
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return crc;
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}
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void crc_check_memory(uint32_t bottom_addr,uint32_t top_addr,uint32_t bank_size,uint8_t *buffer)
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{
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uint16_t crc = 0;
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uint32_t addr;
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uint8_t req_bank = 0;
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for (addr = bottom_addr; addr < top_addr; addr += TRANSFER_BUFFER_SIZE) {
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if (addr && addr % bank_size == 0) {
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debug(DEBUG_CRC,"crc_check_memory: bank=0x%02x addr=0x%08lx crc=0x%04x\n",
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req_bank,addr,crc);
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req_bank++;
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crc = 0;
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}
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sram_read_buffer(addr, buffer, TRANSFER_BUFFER_SIZE);
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crc = do_crc_update(crc, buffer, TRANSFER_BUFFER_SIZE);
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}
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}
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uint16_t crc_check_memory_range(uint32_t start_addr, uint32_t size,uint8_t *buffer)
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{
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uint16_t crc = 0;
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uint32_t addr;
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for (addr = start_addr; addr < start_addr + size; addr += TRANSFER_BUFFER_SIZE) {
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sram_read_buffer(addr, buffer, TRANSFER_BUFFER_SIZE);
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crc = do_crc_update(crc, buffer, TRANSFER_BUFFER_SIZE);
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}
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return crc;
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}
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