53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/* System Config */
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/*
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PLL
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- Main clock F_OSC=12,0MHz @ Keil MCB2130) [limits: 10 MHz to 25 MHz]
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- System should run at max. Frequency (60MHz) [limit: max 60 MHz]
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- Choose multiplier M=5
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so cclk = M * F_OSC= 5 * 12000000 = 60000000 Hz
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- MSEL-Bit in PLLCFG (bits 0-4) MSEL = M-1
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- F_CCO must be inbetween the limits 156 MHz to 320 MHz
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datasheet: F_CCO = F_OSC * M * 2 * P
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- choose devider P=2 => F_CCO = 12000000Hz * 5 * 2 * 2
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= 240 MHz
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- PSEL0 (Bit5 in PLLCFG) = 1, PSEL1 (Bit6) = 0 (0b01)
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*/
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#define FOSC 12000000
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#define PLL_M 5
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#define MSEL (PLL_M-1)
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#define PSEL0 5
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#define PSEL1 6
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#define PLLE 0
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#define PLLC 1
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#define PLOCK 10
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#define PLL_FEED1 0xAA
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#define PLL_FEED2 0x55
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/*
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MAM(Memory Accelerator Module)
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- choosen: MAM fully enabled = MAM-Mode 2
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- System-Clock cclk=60MHz -> 3 CCLKs are proposed as fetch timing
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*/
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#define MAM_MODE 2
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#define MAM_FETCH 3
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/*
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VPB (V... Pheriphal Bus)
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- choosen: VPB should run at full speed -> devider VPBDIV=1
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=> pclk = cclk = 60MHz
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*/
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#define VPBDIV_VAL 1
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/*
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SCB
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*/
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#define MEMMAP_BOOT_LOADER_MODE 0 // Interrupt vectors are re-mapped to Boot Block.
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#define MEMMAP_USER_FLASH_MODE (1<<0) // Interrupt vectors are not re-mapped and reside in Flash.
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#define MEMMAP_USER_RAM_MODE (1<<1) // Interrupt vectors are re-mapped to Static RAM.
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