quickdev16/tools/bsnes/cpu/core/opcode_rmw.bpp
2009-05-12 22:20:41 +02:00

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Executable File

@macro op_adjust(name, r, op)
void {class}::op_{name}_imm_b() {
{lc}op_io_irq();
regs.{r}.l {op};
regs.p.n = (regs.{r}.l & 0x80);
regs.p.z = (regs.{r}.l == 0);
}
void {class}::op_{name}_imm_w() {
{lc}op_io_irq();
regs.{r}.w {op};
regs.p.n = (regs.{r}.w & 0x8000);
regs.p.z = (regs.{r}.w == 0);
}
@endmacro
@macro op_asl()
void {class}::op_asl_imm_b() {
{lc}op_io_irq();
regs.p.c = (regs.a.l & 0x80);
regs.a.l <<= 1;
regs.p.n = (regs.a.l & 0x80);
regs.p.z = (regs.a.l == 0);
}
void {class}::op_asl_imm_w() {
{lc}op_io_irq();
regs.p.c = (regs.a.w & 0x8000);
regs.a.w <<= 1;
regs.p.n = (regs.a.w & 0x8000);
regs.p.z = (regs.a.w == 0);
}
@endmacro
@macro op_lsr()
void {class}::op_lsr_imm_b() {
{lc}op_io_irq();
regs.p.c = (regs.a.l & 0x01);
regs.a.l >>= 1;
regs.p.n = (regs.a.l & 0x80);
regs.p.z = (regs.a.l == 0);
}
void {class}::op_lsr_imm_w() {
{lc}op_io_irq();
regs.p.c = (regs.a.w & 0x0001);
regs.a.w >>= 1;
regs.p.n = (regs.a.w & 0x8000);
regs.p.z = (regs.a.w == 0);
}
@endmacro
@macro op_rol()
void {class}::op_rol_imm_b() {
{lc}op_io_irq();
bool carry = regs.p.c;
regs.p.c = (regs.a.l & 0x80);
regs.a.l = (regs.a.l << 1) | carry;
regs.p.n = (regs.a.l & 0x80);
regs.p.z = (regs.a.l == 0);
}
void {class}::op_rol_imm_w() {
{lc}op_io_irq();
bool carry = regs.p.c;
regs.p.c = (regs.a.w & 0x8000);
regs.a.w = (regs.a.w << 1) | carry;
regs.p.n = (regs.a.w & 0x8000);
regs.p.z = (regs.a.w == 0);
}
@endmacro
@macro op_ror()
void {class}::op_ror_imm_b() {
{lc}op_io_irq();
bool carry = regs.p.c;
regs.p.c = (regs.a.l & 0x01);
regs.a.l = (carry << 7) | (regs.a.l >> 1);
regs.p.n = (regs.a.l & 0x80);
regs.p.z = (regs.a.l == 0);
}
void {class}::op_ror_imm_w() {
{lc}op_io_irq();
bool carry = regs.p.c;
regs.p.c = (regs.a.w & 0x0001);
regs.a.w = (carry << 15) | (regs.a.w >> 1);
regs.p.n = (regs.a.w & 0x8000);
regs.p.z = (regs.a.w == 0);
}
@endmacro
@macro op_adjust_addr(name)
void {class}::op_{name}_addr_b() {
aa.l = op_readpc();
aa.h = op_readpc();
rd.l = op_readdbr(aa.w);
op_io();
op_{name}_b();
{lc}op_writedbr(aa.w, rd.l);
}
void {class}::op_{name}_addr_w() {
aa.l = op_readpc();
aa.h = op_readpc();
rd.l = op_readdbr(aa.w + 0);
rd.h = op_readdbr(aa.w + 1);
op_io();
op_{name}_w();
op_writedbr(aa.w + 1, rd.h);
{lc}op_writedbr(aa.w + 0, rd.l);
}
@endmacro
@macro op_adjust_addrx(name)
void {class}::op_{name}_addrx_b() {
aa.l = op_readpc();
aa.h = op_readpc();
op_io();
rd.l = op_readdbr(aa.w + regs.x.w);
op_io();
op_{name}_b();
{lc}op_writedbr(aa.w + regs.x.w, rd.l);
}
void {class}::op_{name}_addrx_w() {
aa.l = op_readpc();
aa.h = op_readpc();
op_io();
rd.l = op_readdbr(aa.w + regs.x.w + 0);
rd.h = op_readdbr(aa.w + regs.x.w + 1);
op_io();
op_{name}_w();
op_writedbr(aa.w + regs.x.w + 1, rd.h);
{lc}op_writedbr(aa.w + regs.x.w + 0, rd.l);
}
@endmacro
@macro op_adjust_dp(name)
void {class}::op_{name}_dp_b() {
dp = op_readpc();
op_io_cond2();
rd.l = op_readdp(dp);
op_io();
op_{name}_b();
{lc}op_writedp(dp, rd.l);
}
void {class}::op_{name}_dp_w() {
dp = op_readpc();
op_io_cond2();
rd.l = op_readdp(dp + 0);
rd.h = op_readdp(dp + 1);
op_io();
op_{name}_w();
op_writedp(dp + 1, rd.h);
{lc}op_writedp(dp + 0, rd.l);
}
@endmacro
@macro op_adjust_dpx(name)
void {class}::op_{name}_dpx_b() {
dp = op_readpc();
op_io_cond2();
op_io();
rd.l = op_readdp(dp + regs.x.w);
op_io();
op_{name}_b();
{lc}op_writedp(dp + regs.x.w, rd.l);
}
void {class}::op_{name}_dpx_w() {
dp = op_readpc();
op_io_cond2();
op_io();
rd.l = op_readdp(dp + regs.x.w + 0);
rd.h = op_readdp(dp + regs.x.w + 1);
op_io();
op_{name}_w();
op_writedp(dp + regs.x.w + 1, rd.h);
{lc}op_writedp(dp + regs.x.w + 0, rd.l);
}
@endmacro