456 lines
19 KiB
Plaintext
456 lines
19 KiB
Plaintext
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Functional Description
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The G65SC802 offers the design engineer the opportunity to utilize both
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existing software programs and hardware configurations, while also
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achieving the added advantages of increased register lengths and faster
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execution times. The G65SC802's "ease of use" design and implementation
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features provide the designer with increased flexibility and reduced
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implementation costs In the Emulation mode, the G65SC802 not only offers
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software compatibility, but is also hardware (pin-to-pin) compatible with
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6502 designs plus it provides the advantages of 16-bit internal operation
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in 6502-compatible applications. The G65SC802 is an excellent direct
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replacement microprocessor for 6502 designs.
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The G65SC816 provides the design engineer with upward mobility and software
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compatibility in applications where a 16-bit system configuration is desired.
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The G65SC816's 16-bit hardware configuration, coupled with current software
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allows a wide selection of system applications. In the Emulation mode, the
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G65SC816 ofters many advantages, including full software compatibility with
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6502 coding. In addition, the G65SC816's powerful instruction set and
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addressing modes make it an excellent choice for new 16-bit designs.
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Internal organization of the G65SC802 and G65SC816 can be divided into two
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parts: 1) The Register Section, and 2) The Control Section Instructions
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(or opcodes) obtained from program memory are executed by implementing a
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series of data transfers within the Register Section.
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Signals that cause data transfers to be executed are generated within the
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Control Section. Both the G65SC802 and the G65SC816 have a 16-bit internal
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architecture with an 8-bit external data bus.
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Instructlon Register and Decode
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An opcode enters the processor on the Data Bus, and is latched into the
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Instruction Register during the instruction fetch cycle. This instruction is
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then decoded, along with timing and interrupt signals, to generate the
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various Instruction Register control signals.
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Timing Control Unit (TCU)
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The Timing Control Unit keeps track of each instruction cycle as it is
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executed. The TCU is set to zero each time an instruction fetch is executed,
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and is advanced at the beginning of each cycle for as many cycles as is
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required to complete the instruction Each data transfer between registers
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depends upon decoding the contents of both the Instruction Register and
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the Timing Control Unit.
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Arithmetic and Logic Unit (ALU)
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All arithmetic and logic operations take place within the 16-bit ALU. In
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addition to data operations, the ALU also calculates the effective address
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for relative and indexed addressing modes. The result of a data operation
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is stored in either memory or an internal register. Carry, Negative, Over-
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flow and Zero flags may be updated following the ALU data operation.
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Internal Registers (Refer to Figure 2, Programming Model)
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Accumulator (A)
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The Accumulator is a general purpose register which stores one of the
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operands, or the result of most arithmetic and logical operations. In the
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Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the
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Accumulator is established as 16 bits wide. When the Accumulator Select
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Bit (M) equals one, the Accumulator is 8 bits wide. In this case, the upper
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8 bits (AH) may be used for temporary storage in conjunction with the
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Exchange AH and AL instruction.
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Data Bank (DB)
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During the Native mode (E=0), the 8-bit Data Bank Register holds the default
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bank address for memory transfers. The 24-bit address is composed of the
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16-bit instruction effective address and the 8-bit Data Bank address. The
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register value is multiplexed with the data value and is present on the
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Data/Address lines during the first half of a data transfer memory cycle for
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the G65SC816. The Data Bank Register is initialized to zero during Reset.
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Direct (D)
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The 16-bit Direct Register provides an address offset for all instructions
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using direct addressing. The effective bank zero address is formed by adding
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the 8-bit instruction operand address to the Direct Register. The Direct
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Register is initialized to zero during Reset.
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Index (X and Y)
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There are two Index Registers (X and Y) which may be used as general purpose
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registers or to provide an index value for calculation of the effective
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address. When executing an instruction with indexed addressing, the
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microprocessor fetches the opcode and the base address, and then modifies the
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address by adding the Index Register contents to the address prior to
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performing the desired operation.
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Pre-indexing or postindexing of Indirect addresses may be selected. In the
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Native mode (E=0), both Index Registers are 16 bits wide (providing the Index
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Select Bit (X) equals zero). If the Index Select Bit (X) equals one, both
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registers will be 8 bits wide.
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Processor Status (P)
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The 8-bit Processor Status Register contains status flags and mode select bits.
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The Carry (C), Negative (N). Overflow (V), and Zero (Z) status flags serve to
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report the status ot most ALU operations. These status flags are tested by use
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of Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory,
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Accumuiator (M), and Index (X) bits are used as mode select flags. These flags
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are set by the program to change microprocessor operations.
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The Emulation (E) select and the Break (B) flags are accessible only through
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the Processor Status Register. The Emulation mode select flag is selected by
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the Exchange Carry and Emulation Bits (XCE) instruction.
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Table 2, G65SC802 and G65SC816 Mode Comparison, illustrates the features of
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the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal
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to one in the Emulation mode. When an interrupt occurs during the Emulation
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mode, the Break flag is written to stack memory as bit 4 of the Processor
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Status Register.
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Program Bank (PB)
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The 8-bit Program Bank Register holds the bank address for all instruction
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fetches. The 24-bit address consists of the 16-bit instruction effective
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address and the 8-bit Program Bank address. The register value is multiplexed
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with the data value and presented on the Data/Address lines during the first
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half of a program memory read cycle. The Program Bank Register is initialized
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to zero during Reset.
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Program Counter (PC)
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The 16-bit Program Counter Register provides the addresses which are used to
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step the microprocessor through sequential program instructions. The register
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is incremented each time an instruction or operand is fetched from program
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memory.
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Stack Pointer (S)
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The Stack Pointer is a 16-bit register which is used to indicate the next
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available location in the stack memory area. It serves as the effective address
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in stack addressing modes as well as subroutine and interrupt processing. The
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Stack Pointer allows simple implementation of nested subroutines and multiple-
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level interrupts. During the Emulation mode, the Stack Pointer high-order byte
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(SH) is always equal to 01. The Bank Address is 00 for all Stack operations.
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Signal Description
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The following Signal Description applies to both the G65SC802 and the
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SSC816 except as otherwise noted.
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Abort (/ABORT) -- G65SC816
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The Abort input prevents modification of any internal registers during
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execution of the current instruction. Upon completion of this instruction,
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an interrupt sequence is initiated. The location of the aborted opcode is
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stored as the return address in Stack memory. The Abort vector address is
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00FFF8, 9 (Emulation mode) or 00FFE8, 9 (Native mode). Abort is asserted
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whenever there is a low level on the Abort input. and the Phi2 clock is high.
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The Abort internal latch is cleared during the second cycle of the interrupt
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sequence. This signal may be used to handle out-of-bounds memory references
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in virtual memory systems.
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Address Bus (A0-A15)
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These sixteen output lines form the Address Bus for memory and I/O exchange on
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the Data Bus. When using the G65SC816, the address lines may be set to the
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high impedance state by the Bus Enable (BE) signal.
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Bus Enable (BE)
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The Bus Enable input signal allows external control of the Address and Data
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Buffers, as well as the R/W signal With Bus Enable high, the R/W and Address
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Buffers are active. The Data/Address Buffers are active during the first half
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of every cycle and the second half of a write cycle. When BE is low, these
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buffers are disabled. Bus Enable is an asynchronous signal.
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Data Bus (D0-D7) -- G65SC802
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The eight Data Bus lines provide an 8-bit bidirectional Data Bus for use
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during data exchanges between the microprocessor and external memory or
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peripherals. Two memory cycles are required for the transfer of 16-bit values.
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Data/Address Bus (D0/BA0-D7/BA7) -- G65SC816
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These eight lines multiplex bits BAO-BA7 with the data value. The Bank Address
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is present during the first half of a memory cycle, and the data value is read
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or written during the second half of the memory cycle.
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The Bank address external transparent latch should be latched when the Phi2
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clock is high or RDY is low. Two memory cycles are required to transfer 16-bit
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values. These lines may be set to the high impedance state by the Bus Enable
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(BE) signal.
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Emulation Status (E) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
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The Emulation Status output reflects the state of the Emulation (E) mode flag
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in the Processor Status (P) Register. This signal may be thought of an opcode
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extension and used for memory and system management.
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Interrupt Request (/IRQ)
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The Interrupt Request input signal is used to request that an interrupt
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sequence be initiated. When the IRQ Disable (I) flag is cleared, a low input
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logic level initiates an interrupt sequence after the current instruction is
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completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
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the interrupt will be recognized immediately. The Interrupt Request vector
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address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode). Since IRQ is a
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level-sensitive input, an interrupt will occur if the interrupt source was not
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cleared since the last interrupt.
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Also, no interrupt will occur if the interrupt source is cleared prior to
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interrupt recognition.
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Memory Lock (/ML) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
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The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
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instructions in a multiprocessor system. Memory Lock indicates the need to
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defer arbitration of the next bus cycle. Memory Lock is low during the last
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three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
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referencing instructions, depending the state of the M flag.
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Memory/Index Select Status (M/X) -- G65SC816
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This multiplexed output reflects the state ot the Accumulator (M) and index (X)
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select flags (bits 5 and 4 of the Processor Status (P) Register).
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Flag M is valid during the Phi2 clock positive transition. Instructions PLP,
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REP, RTI and SEP may change the state of these bits. Note that the M/X output
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may be invalid in the cycle following a change in the M or X bits. These bits
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may be thought of as opcode extensions and may be used for memory and system
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management.
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Non-Maskable Interrupt (/NMI)
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A high-to-low transition initiates an intenupt sequence after the current
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instruction is completed. The Wait for Interrupt (WAI) instruction may be
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executed to ensure that the interrupt will be recognized immediately. The
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Non-Maskable Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B
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(Native mode). Since NMI is an edge-sensitive Input, an interrupt will occur
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if there is a negative transition while servicing a previous interrupt. Also,
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no interrupt will occur if NMI remains low.
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Phase 1 Out (Phi1 (OUT)) -- G65SC802
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This inverted clock output signal provides timing for external read and write
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operations. Executing the Stop (STP) instruction holds this clock in the low
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state.
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Phase 2 In (Phi2 (IN))
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This is the system clock input to the microprocessor internal clock generator
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(equivalent to Phi0 (IN) on the 6502). During the low power Standby Mode, Phi2
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(IN) should be held in the high state to preserve the contents of internal
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registers.
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Phase 2 Out (Phi2 (OUT)) -- G65SC802
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This clock output signal provides timing for external read and write
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operations. Addresses are valid (after the Address Setup Time (TADS))
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following the negative transition of Phase 2 Out. Executing the Stop (STP)
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instruction holds Phase 2 Out in the High state.
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Read/Write (R/W)
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When the R/W output signal is in the high state, the microprocessor is reading
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data from memory or I/O. When in the low state, the Data Bus contains valid
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data from the microprocessor which is to be stored at the addressed memory
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location. When using the G65SC816, the R/W signal may be set to the high
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impedance state by Bus Enable (BE).
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Ready (RDY)
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This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction
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has been executed allowing the user to halt operation of the microprocessor.
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A low input logic level will halt the microprocessor in its current state (note
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that when in the Emulation mode, the G65SC802 stops only during a read cycle).
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Returning RDY to the active high state allows the microprocessor to continue
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following the next Phase 2 In Clock negative transition. The RDY signal is
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internally pulled low following the execution of a Wait for Interrupt (WAI)
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instruction, and then returned to the high state when a /RES, /ABORT, /NMI, or
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/IRQ external interrupt is provided. This feature may be used to eliminate
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interrupt latency by placing the WAI instruction at the beginning of the IRQ
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servicing routine. If the IRQ Disable flag has been set, the next instruction
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will be executed when the IRQ occurs. The processor will not stop after a WAI
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instruction if RDY has been forced to a high state. The Stop (STP) instruction
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has no effect on RDY.
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Reset (/RES)
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The Reset input is used to initialize the microprocessor and start program
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execution. The Reset input buffer has hysteresis such that a simple R-C timing
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circuit may be used with the internal pullup device. The /RES signal must be
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held low for at least two clock cycles after VDD reaches operating voltage.
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Ready (RDY) has no effect while RES is being held low. During this Reset
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conditioning period, the following processor initialization takes place:
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Registers
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D = 0000 SH = 01
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DB = 00 XH = 00
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PB = 00 YH = 00
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N V M X D I Z C/E
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P = * * 1 1 0 1 * */1
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* = Not Initialized
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STP and WAI instructions are cleared.
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Signals
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E = 1 VDA = 0
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M/X = 1 /VP = 1
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R/W = 1 VPA = 0
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SYNC = 0
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When Reset is brought high, an interrupt sequence is initiated:
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* R/W remains in the high state during the stack address cycles.
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* The Reset vector address is 00FFFC,D.
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Set Overtlow (/SO) -- G65SC802
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A negative transition on this input sets the Overflow (V) flag, bit 6 of the
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Processor Status (P) Register.
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Synchronlze (SYNC) -- G65SC802
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The SYNC output is provided to identify those cycles during which the
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microprocessor is fetching an opcode. The SYNC signal is high during an opcode
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fetch cycle, and when combined with Ready (RDY), can be used for single
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instruction execution.
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Valid Data Address (VDA) and
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Valid Program Address (VPA) -- G65SC816
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These two output signals indicate the type of memory being accessed by
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the address bus. The following coding applies:
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VDA VPA
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0 0 Internal Operation -- Address and Data Bus available. Address
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outputs may be invalid due to low byte additions only.
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0 1 Valid program address -- may be used for program cache control.
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1 0 Valid data address -- may be used for data cache control.
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1 1 Opcode fetch -- may be used for program cache control
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and single step control.
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VDD and Vss
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VDD Vss the positive supply voltage and Vss is system ground. When
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using only one ground on the G65SC802 DIP package, pin 21 preferred.
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Vector Pull (VP) -- G65SC816 (Also Applies to G65SC802 44-Pin Version)
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The Vector Pull output indicates that a vector location is being addressed
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during an interrupt sequence. /VP is low during the last two interrupt sequence
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cycles, during which time the processor reads the interrupt vector. The /VP
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signal may be used to select and prioritize interrupts from several sources by
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modifying the vector addresses.
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--------------------------------------------------------------------------
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8 bits 8 bits 8 bits
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DB DB Data Bank Register
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XH XL Index Register (X)
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YH YL Index Register (Y)
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00 SH SL Stack Pointer (S)
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AH AL Accumulator (A)
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PB PCH PCL Program Counter (PC)
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Program Bank Register (PB)
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00 DH DL Direct Register (D)
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L = Low, H = High
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Processor Status Register (P)
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____________________________
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| 1 B E |
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|__________________________|
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| N V M X D I Z C |
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|__________________________|
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1 Always 1 if E=1
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B Break 0 on Stack after interupt if E=1
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E Emulation Bit 0= Native mode, 1= 6502 emulation
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N Negative 1= Negative
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V Overflow 1= True
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M Memory/Acc. Select 1= 8 bit, 0= 16 bit
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X Index Register Select 1= 8 bit, 0= 16 bit
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D Decimal mode 1= Decimal Mode
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I IRQ Disable 1= Disable
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Z Zero 1= Result Zero
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C Carry 1= True
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Figure 2. Programming model
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--------------------------------------------------------------------------
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Table 1. G65SC802 and G65SC816 Compability
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Function G65SC802/816 G65SC02 NMOS 6502
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Emulation
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Decimal Mode:
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* After Interrupts 0 -> D 0 -> D Not initialized
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* N, Z Flags Valid Valid Undefined
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* ADC, SBC No added cycle Add 1 cycle No added cycle
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Read-Modify-Write:
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* Absolute Indexed, No Page Crossing
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7 cycles 6 cycles 7 cycles
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* Write Last 2 cycles Last cycle Last 2 cycles
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* Memory Lock Last 3 cycles Last 2 cycles Not available
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Jump Indirect:
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* Cycles 5 cycles 6 cycles 5 cycles
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* Jump Address, operand = xxFF Correct Correct Invalid
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Branch or Index Across Page Boundary
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Read last Read last Read invalid
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program byte program byte address
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0 -> RDY During Write G65SC802: Ignored Processor Ignored until
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until read stops read
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G65SC816: Processor
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stops
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Write During Reset No Yes No
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Unused Opcodes No operation No operation Undefined
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Phi1 (OUT), Phi2 (OUT), /SO, SYNC Signals
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Available with Available Available
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G65SC802 only
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RDY Signal Bidirectional Input Input
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--------------------------------------------------------------------------
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Table 2. G65SC802 and G65SC816 Mode Comparison
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Function Emulation (E = 1) Native (E = 0)
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Stack Pointer (S) 8 bits in page 1 16 bits
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Direct Index Address Wrap within page Crosses page boundary
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Processor Status (P):
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* Bit 4 Always one, except zero X flag (8/16-bit Index)
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in stack after hardware
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interrupt
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* Bit 5 Always one M flag (8/16-bit Accumulator)
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Branch Across Page Boundary
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4 cycles 3 cycles
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Vector Locations:
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ABORT 00FFF8,9 00FFF8,9
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BRK 00FFFE,F 00FFF6,7
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COP 00FFF4,5 00FFF4,5
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IRQ 00FFFE,F 00FFFE,F
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NMI 00FFFA,B 00FFFA,B
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RES 00FFFC,D 00FFFC,D (1 -> E)
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Program Bank (PB) During Interrupt, RTI
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Not pushed, pulled Pushed and pulled
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0 -> RDY During Write
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G65SC802: Ignored until read Processor stops
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G65SC816: Processor stops
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Write During Read-Modify-Write
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Last 2 cycles Last 1 or 2 cycles depending
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on M flag
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