70 lines
2.5 KiB
Plaintext
70 lines
2.5 KiB
Plaintext
Interrupt Processing Sequence
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The interrupt processing sequence is initiated as the direct result of hard-
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vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs.
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The interrupt sequence can also be initiated as a result of the Break or
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Co-Processor instructions within the software. The following listings
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describe the function of each cycle in the interrupt processing sequence:
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Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs
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Cycle No.
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E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description
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1 1 PC X 1 1 1 1 1 Internal Operation
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2 2 PC X 1 0 0 0 1 Internal Operation
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3 [1] S PB 0 0 1 0 1 Write PB to Stack, S-1<>S
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4 3 S PCH [2] 0[3] 0 1 0 1 Write PCH to Stack, S-1<>S
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5 4 S PCL 12] 0[3] 0 1 0 1 Write PCL to Stack, S-1<>S
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6 5 S P [4] 0[3] 0 1 0 1 Write P to Stack, S-1<>S
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7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte,
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0->PD, 1->P1, OO->PB
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8 7 VH (VH) 1 0 1 0 0 Read Vector High 8yte
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Software Interrupt - BRK, COP Instructions
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Cycle No.
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E = 0 E = 1 Address Data R/W SYNC VDA VPA VP Description
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1 1 PC-2 X 1 1 1 1 1 Opcode
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2 2 PC-1 X 1 0 0 1 1 Signature
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3 111 S PB 0 0 1 0 1 Write PB to Stack, S-1<>S
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4 3 S PCH 0 0 1 0 1 Write PCH to Stack, S-1 - S
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5 4 S PCL 0 0 1 0 1 Write PCL to Stack, S-1<>S
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6 5 S P 0 0 1 0 1 Write P to Stack, S-1<>S
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7 6 VL (VL) 1 0 1 0 0 Read Vector Low Byte,
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0<>Po, 1<>Pl, 00<30>PB
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8 7 VH (VH) 1 0 1 0 0 Read Vector High Byte
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Notes:
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[1] Delete this cycle in Emulation mode.
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[2] Abort writes address of aborted opcode.
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[3] R/W remains in the high state during Reset.
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[4] In Emulation mode, bit 4 written to stack is changed to 0.
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Table 3. Vector Locations
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Emulation Native Priority
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Name Source (E = 1) (E = 0) Level
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ABORT Hardware 00FFF8,9 00FFE8,9 2
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BRK Software 00FFFE,F 00FFE6,7 N/A
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COP Software 00FFF4,5 00FFE4,5 N/A
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IRQ Hardware 00FFFE,F 00FFEE,F 4
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NMI Hardware 00FFFA,B 00FFEA,B 3
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RES Hardware 00FFFC.D 00FFFC,D 1
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