110 lines
1.5 KiB
C
110 lines
1.5 KiB
C
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#include <avr/io.h>
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#include <util/delay.h>
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#include <stdlib.h>
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//SREG defines
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#define S_MOSI PB3
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#define S_MISO PB4
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#define S_SCK PB5
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#define S_LATCH PB2
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//DEBUG defines
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#define D_LED0 PC5
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//SRAM defines
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#define R_WR PB6
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#define R_RD PB7
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#define R_DATA PORTD
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#define R_DIR DDRD
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void SPI_MasterInit(void)
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{
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/* Set MOSI and SCK output, all others input */
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DDRB |= ((1<<S_MOSI) | (1<<S_SCK) | (1<<S_LATCH));
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DDRB &= ~(1<<S_MISO);
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PORTB |= (1<<S_MISO);
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/* Enable SPI, Master*/
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SPCR = ((1<<SPE) | (1<<MSTR));
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}
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void SPI_MasterTransmit(unsigned char cData)
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{
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/* Start transmission */
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SPDR = cData;
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/* Wait for transmission complete */
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while(!(SPSR & (1<<SPIF)));
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}
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uint8_t SRAM_Read(uint32_t addr)
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{
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uint8_t byte;
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DDRD=0x00;
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PORTD=0xff;
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PORTB |= (1<<R_RD);
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PORTB |= (1<<R_WR);
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SPI_MasterTransmit((uint8_t)(addr>>16));
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SPI_MasterTransmit((uint8_t)(addr>>8));
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SPI_MasterTransmit((uint8_t)(addr>>0));
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PORTB |= (1<<S_LATCH);
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PORTB &= ~(1<<S_LATCH);
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PORTB &= ~(1<<R_RD);
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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byte = PIND;
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PORTB |= (1<<R_RD);
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DDRD=0x00;
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PORTD=0x00;
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return byte;
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}
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void SRAM_Write(uint32_t addr, uint8_t data)
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{
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DDRD=0xff;
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PORTB |= (1<<R_RD);
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PORTB |= (1<<R_WR);
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SPI_MasterTransmit((uint8_t)(addr>>16));
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SPI_MasterTransmit((uint8_t)(addr>>8));
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SPI_MasterTransmit((uint8_t)(addr>>0));
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PORTB |= (1<<S_LATCH);
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PORTB &= ~(1<<S_LATCH);
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PORTB &= ~(1<<R_WR);
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PORTD=data;
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PORTB |= (1<<R_WR);
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DDRD=0x00;
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PORTD=0x00;
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}
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int main(void)
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{
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while(1);
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return(0);
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}
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