438 lines
8.5 KiB
C
438 lines
8.5 KiB
C
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#include <avr/io.h>
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#include <util/delay.h>
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#include <stdlib.h>
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#include "uart.h"
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#include "mmc.h"
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#include "fat.h"
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// Debug
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#define debug(x, fmt) printf("%s:%u: %s=" fmt, __FILE__, __LINE__, #x, x)
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extern FILE uart_stdout;
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//SREG defines
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#define S_MOSI PB5
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#define S_MISO PB6
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#define S_SCK PB7
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#define S_LATCH PB4
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//DEBUG defines
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#define D_LED0 PD6
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//SRAM defines
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#define R_WR PB1
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#define R_RD PB0
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#define RAM_PORT PORTA
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#define RAM_DIR DDRA
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#define RAM_REG PINA
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#define CTRL_PORT PORTB
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#define CTR_DIR DDRB
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#define LATCH_PORT PORTB
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#define LATCH_DIR DDRB
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#define SPI_PORT PORTB
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#define SPI_DIR DDRB
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#define LED_PORT PORTD
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#define LED_DIR DDRD
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//#define FILENAME "sprite.raw" //ok
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//#define FILENAME "ascii.smc" //ok
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//#define FILENAME "rom.smc" //ok
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//#define FILENAME "supert.smc"
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//#define FILENAME "vortex.smc"
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//#define FILENAME "mrdo.smc"
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//#define FILENAME "spacei.smc"
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//#define FILENAME "bank01.smc" //ok
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//#define FILENAME "bank02.smc" //ok
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//#define FILENAME "bank03.smc" //ok
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//#define FILENAME "bank04.smc" //ok
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//#define FILENAME "bank05.smc" //ok
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//#define FILENAME "bank06.smc" //ok
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//#define FILENAME "bank07.smc" //ok
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//#define FILENAME "banklo.smc" //ok
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//#define FILENAME "bankhi.smc" //ok
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//#define FILENAME "vram2.smc" //ok
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//#define FILENAME "super02.smc"
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#define FILENAME "crc.smc"
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#define ROMSIZE 2
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#define DUMPNAME "dump256.smc"
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#define BUFFER_SIZE 512
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#define BLOCKS (ROMSIZE << 8)
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#define MEMSIZE 0x80000
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uint8_t read_buffer[BUFFER_SIZE];
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uint16_t crc_xmodem_update (uint16_t crc, uint8_t data)
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{
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int i;
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crc = crc ^ ((uint16_t)data << 8);
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for (i=0; i<8; i++)
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{
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if (crc & 0x8000)
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crc = (crc << 1) ^ 0x1021;
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else
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crc <<= 1;
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}
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return crc;
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}
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uint16_t do_crc(uint8_t * data,uint16_t size)
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{
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uint16_t crc =0;
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uint16_t i;
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for (i=0; i<size; i++){
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crc = crc_xmodem_update(crc,data[i]);
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//printf("%x : %x\n",crc,data[i]);
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}
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return crc;
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}
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uint16_t do_crc_update(uint16_t crc,uint8_t * data,uint16_t size)
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{
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uint16_t i;
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for (i=0; i<size; i++)
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crc = crc_xmodem_update(crc,data[i]);
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return crc;
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}
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void dump_packet(uint32_t addr,uint32_t len,uint8_t *packet){
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uint16_t i,j;
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uint16_t sum = 0;
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uint8_t clear=0;
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for (i=0;i<len;i+=16) {
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sum = 0;
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for (j=0;j<16;j++) {
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sum +=packet[i+j];
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}
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if (!sum){
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clear=1;
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continue;
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}
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if (clear){
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printf("*\n");
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clear = 0;
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}
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printf("%08lx:", addr + i);
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for (j=0;j<16;j++) {
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printf(" %02x", packet[i+j]);
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}
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printf(" |");
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for (j=0;j<16;j++) {
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if (packet[i+j]>=33 && packet[i+j]<=126 )
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printf("%c", packet[i+j]);
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else
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printf(".");
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}
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printf("|\n");
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}
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}
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void spi_init(void)
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{
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/* Set MOSI and SCK output, all others input */
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SPI_DIR |= ((1<<S_MOSI) | (1<<S_SCK) | (1<<S_LATCH));
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SPI_DIR &= ~(1<<S_MISO);
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SPI_PORT |= (1<<S_MISO);
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/* Enable SPI, Master*/
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SPCR = ((1<<SPE) | (1<<MSTR));
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}
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void spi_master_transmit(unsigned char cData)
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{
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/* Start transmission */
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SPDR = cData;
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/* Wait for transmission complete */
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while(!(SPSR & (1<<SPIF)));
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}
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void sram_set_addr(uint32_t addr)
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{
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spi_master_transmit((uint8_t)(addr>>16));
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spi_master_transmit((uint8_t)(addr>>8));
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spi_master_transmit((uint8_t)(addr>>0));
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LATCH_PORT |= (1<<S_LATCH);
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LATCH_PORT &= ~(1<<S_LATCH);
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}
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uint8_t sram_read(uint32_t addr)
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{
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uint8_t byte;
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RAM_DIR = 0x00;
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RAM_PORT = 0xff;
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CTRL_PORT |= (1<<R_RD);
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CTRL_PORT |= (1<<R_WR);
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spi_master_transmit((uint8_t)(addr>>16));
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spi_master_transmit((uint8_t)(addr>>8));
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spi_master_transmit((uint8_t)(addr>>0));
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LATCH_PORT |= (1<<S_LATCH);
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LATCH_PORT &= ~(1<<S_LATCH);
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CTRL_PORT &= ~(1<<R_RD);
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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byte = RAM_REG;
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CTRL_PORT |= (1<<R_RD);
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RAM_DIR =0x00;
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RAM_PORT =0x00;
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return byte;
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}
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void sram_write(uint32_t addr, uint8_t data)
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{
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RAM_DIR = 0xff;
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CTRL_PORT |= (1<<R_RD);
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CTRL_PORT |= (1<<R_WR);
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spi_master_transmit((uint8_t)(addr>>16));
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spi_master_transmit((uint8_t)(addr>>8));
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spi_master_transmit((uint8_t)(addr>>0));
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LATCH_PORT |= (1<<S_LATCH);
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LATCH_PORT &= ~(1<<S_LATCH);
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CTRL_PORT &= ~(1<<R_WR);
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RAM_PORT = data;
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CTRL_PORT |= (1<<R_WR);
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RAM_DIR = 0x00;
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RAM_PORT = 0x00;
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}
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void sram_init(void){
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RAM_DIR = 0x00;
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RAM_PORT = 0x00;
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CTR_DIR |= ((1<<R_WR) | (1<<R_RD));
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CTRL_PORT |= (1<<R_RD);
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CTRL_PORT |= (1<<R_WR);
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LED_PORT |= (1<<D_LED0);
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}
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void sram_snes_mode(void){
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CTRL_PORT |= (1<<R_WR);
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CTRL_PORT &= ~(1<<R_RD);
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}
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void sram_clear(uint32_t addr, uint32_t len){
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uint32_t i;
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for (i=addr; i<(addr + len);i++ ){
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if (0==i%0xfff)
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printf("sram_clear %lx\n\r",i);
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sram_write(i, 0x00);
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}
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}
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void sram_copy(uint32_t addr,uint8_t *src, uint32_t len){
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uint32_t i;
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uint8_t *ptr = src;
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for (i=addr; i<(addr + len);i++ )
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sram_write(i, *ptr++);
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}
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void sram_read_buffer(uint32_t addr,uint8_t *dst, uint32_t len){
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uint32_t i;
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uint8_t *ptr = dst;
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for (i=addr; i<(addr + len);i++ ){
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*ptr = sram_read(i);
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ptr++;
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}
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}
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uint8_t sram_check(uint8_t *buffer, uint32_t len){
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for (uint16_t cnt=0; cnt<len; cnt++)
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if (buffer[cnt])
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return 1;
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return 0;
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}
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int main(void)
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{
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uint16_t fat_cluster = 0;
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uint8_t fat_attrib = 0;
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uint32_t fat_size = 0;
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uint32_t rom_addr = 0;
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uint8_t bank_cnt = 0;
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uint16_t crc = 0;
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uint16_t block_cnt;
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uart_init();
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stdout = &uart_stdout;
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sram_init();
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printf("SRAM Init\n");
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spi_init();
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printf("SPI Init\n");
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#if 0
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uint8_t t[] = "david";
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printf("Test CRC %x\n",do_crc(t,5));
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while(1);
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#endif
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#if 0
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sram_clear(0x000000, 0x80000);
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printf("sram_clear\n");
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#endif
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#if 0
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printf("read 0x0f0f\n");
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sram_read(0x0f0f);
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printf("write 0x0f0f\n");
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sram_write(0x0f0f,0xaa);
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#endif
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#if 0
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rom_addr = 0x4aaaa;
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printf("write %lx\n",rom_addr);
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sram_set_addr(rom_addr);
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while(1);
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#endif
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while ( mmc_init() !=0) {
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printf("No sdcard...\n");
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}
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printf("MMC Init done\n");
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fat_init(read_buffer);
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printf("FAT Init done.\n");
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rom_addr = 0x000000;
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printf("Look for %s\n",FILENAME);
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if (fat_search_file((uint8_t*)FILENAME,
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&fat_cluster,
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&fat_size,
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&fat_attrib,
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read_buffer) == 1) {
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for (block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
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fat_read_file (fat_cluster,read_buffer,block_cnt);
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if (block_cnt && block_cnt % 64 == 0){
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bank_cnt++;
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printf("Write Ram Bank: 0x%x Addr: 0x%lx Block: %x CRC: %x\n",bank_cnt,rom_addr,block_cnt,crc);
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crc = 0;
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}
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crc = do_crc_update(crc,read_buffer,512);
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sram_copy(rom_addr,read_buffer,512);
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rom_addr += 512;
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}
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printf("Write Ram Bank: 0x%x Addr: 0x%lx Block: %x CRC: %x\n",bank_cnt,rom_addr,block_cnt,crc);
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printf("Done\n");
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}
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printf("Dump Headern\r");
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rom_addr = 0x8000-512;
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sram_read_buffer(rom_addr,read_buffer,512);
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dump_packet(rom_addr,512,read_buffer);
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#if 0
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printf("Dump Memory\n\r");
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rom_addr = 0x000000;
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for (uint16_t block_cnt=0; block_cnt < 64; block_cnt++) {
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sram_read_buffer(rom_addr,read_buffer,512);
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dump_packet(rom_addr,512,read_buffer);
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rom_addr += 512;
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}
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printf("\nDone 0x%lx\n",rom_addr);
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#endif
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#if 1
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block_cnt = 0;
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crc = 0;
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rom_addr = 0x000000;
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for (block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
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sram_read_buffer(rom_addr,read_buffer,512);
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if (block_cnt && block_cnt % 64 == 0){
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bank_cnt++;
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printf("Read Ram Bank: 0x%x Addr: 0x%lx Block: %x CRC: %x\n",bank_cnt,rom_addr,block_cnt,crc);
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crc = 0;
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}
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crc = do_crc_update(crc,read_buffer,512);
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rom_addr += 512;
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}
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printf("Read Ram Bank: 0x%x Addr: 0x%lx Block: %x CRC: %x\n",bank_cnt,rom_addr,block_cnt,crc);
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#endif
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#if 0
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printf("Look for %s\n",DUMPNAME);
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fat_cluster = 0;
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fat_attrib = 0;
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fat_size = 0;
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if (fat_search_file((uint8_t*)DUMPNAME,
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&fat_cluster,
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&fat_size,
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&fat_attrib,
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read_buffer) == 1) {
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printf("Found %s\n",DUMPNAME);
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rom_addr = 0x000000;
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bank_cnt =0;
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for (uint16_t block_cnt=0; block_cnt<BLOCKS; block_cnt++) {
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printf("Write 1");
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sram_read_buffer(rom_addr,read_buffer,512);
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printf("Write 2");
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fat_write_file (fat_cluster,read_buffer,block_cnt);
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if (block_cnt % 64 == 0){
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bank_cnt++;
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}
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printf("Write File Bank: 0x%x Addr: 0x%lx Skipped: %li\n",bank_cnt,rom_addr,skip_block);
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rom_addr += 512;
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}
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printf("Done 0x%lx Skipped %li\n",rom_addr,skip_block);
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}
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#endif
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sram_snes_mode();
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printf("\nEnter Snes mode\n");
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while(1);
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return 0 ;
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}
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