516 lines
16 KiB
Plaintext
516 lines
16 KiB
Plaintext
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G65SC802 and G65SC816
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Microprocessor Addressing modes
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The G65SC816 is capable of directly addressing 16 MBytes of memory.
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This address space has special significance within certain addressing
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modes, as follows:
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Reset and Interrupt Vectors
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The Reset and Interrupt vectors use the majority of the fixed addresses
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between 00FFE0 and 00FFFF.
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Stack
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The Native mode Stack address will always be within the range 000000 to
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00FFFF. In the Emulation mode, the Stack address range is 000100 to 0001FF.
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The following opcodes and addressing modes can increment or decrement beyond
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this range when accessing two or three bytes:
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JSL; JSR (a,x); PEA; PEI; PER; PHD; PLD; RTL; d,s; (d,s),y.
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Direct
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The Direct addressing modes are often used to access memory registers and
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pointers. The contents of the Direct Register (D) is added to the offset
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contained in the instruction operand to produce an address in the range 000000
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to 00FFFF. Note that in the Emulation mode, [Direct] and [Direct],y addressing
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modes and the PEI instruction will increment from 0000FE or 0000FF into the
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Stack area, even if D=0.
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Program Address Space
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The Program Bank register is not affected by the Relative, Relative Long,
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Absolute, Absolute Indirect, and Absolute Indexed Indirect addressing modes
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or by incrementing the Program Counter from FFFF. The only instructions that
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affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute
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Long. Program code may exceed 64K bytes altough code segments may not span
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bank boundaries.
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Data Address Space
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The data address space is contiguous throughout the 16 MByte address space.
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Words, arrays, records, or any data structures may span 64K byte bank
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boundaries with no compromise in code efficiency. As a result, indexing from
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page FF in the G65SC802 may result in data accessed in page zero. The
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following addressing modes generate 24-bit effective addresses.
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* Direct Indexed Indirect (d,x)
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* Direct Indirect Indexed (d),y
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* Direct Indirect (d)
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* Direct Indirect Long [d]
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* Direct Indirect Indexed Long [d],y
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* Absolute
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* Absolute,x
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* Absolute,y
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* Absolute long
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* Absolute long indexed
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* Stack Relative Indirect Indexed (d,s),y
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The following addressing mode descriptions provide additional detail as
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to how effective addresses are calculated.
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Twenty-four addressing modes are available for use with the G65SC802
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and G65SC816 microprocessors. The "long" addressing modes may be
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used with the G65SC802; however, the high byte of the address is not
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available to the hardware. Detailed descriptions of the 24 addressing
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modes are as follows:
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1. Immediate Addressing -- #
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The operand is the second byte (second and third bytes when in the 16-bit
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mode) of the instruction.
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2. Absolute -- a
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With Absolute addressing the second and third bytes of the instruction form
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the low-order 16 bits of the effective address. The Data Bank Register
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contains the high-order 8 bits of the operand address.
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__________________________
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Instruction: | opcode | addrl | addrh |
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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Operand
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Address: | DB | addrh | addrl |
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3. Absolute Long -- al
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The second, third, and fourth byte of the instruction form the 24-bit
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effective address.
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__________________________________
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Instruction: | opcode | addrl | addrh | baddr |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Operand
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Address: | baddr | addrh | addrl |
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4. Direct -- d
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The second byte of the instruction is added to the Direct Register
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(D) to form the effective address. An additional cycle is required
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when the Direct Register is not page aligned (DL not equal 0). The
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Bank register is always 0.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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Operand
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Address: | 00 | effective address |
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5. Accumulator -- A
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This form of addressing always uses a single byte instruction. The
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operand is the Accumulator.
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6. Implied -- i
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Implied addressing uses a single byte instruction. The operand is implicitly
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defined by the instruction.
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7. Direct Indirect Indexed -- (d),y
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This address mode is often referred to as Indirect,Y. The second byte of the
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instruction is added to the Direct Register (D). The 16-bit contents of this
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memory location is then combined with the Data Bank register to form a 24-bit
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base address. The Y Index Register is added to the base address to form the
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effective address.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| 00 | direct address |
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then:
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| 00 | (direct address) |
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+ | DB |
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-------------------------------
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| base address |
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+ | | Y Reg |
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------------------------------
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Operand
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Address: | effective address |
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8. Direct Indirect Indexed Long -- [d],y
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With this addressing mode the 24-bit base address is pointed to by
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the sum of the second byte of the instruction and the Direct
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Register The effective address is this 24-bit base address plus the Y
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Index Register
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| 00 | direct address |
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then:
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| (direct address) |
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+ | | Y Reg |
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------------------------------
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Operand
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Address: | effective address |
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9. Direct Indexed Indirect -- (d,x)
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This address mode is often referred to as Indirect X The second
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byte of the Instruction is added to the sum of the Direct Register
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and the X Index Register. The result points to the low-order 16 bits
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of the effective address. The Data Bank Register contains the high-
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order 8 bits of the effective address.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| direct address |
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+ | | X Reg |
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---------------------
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| 00 | address |
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then:
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| 00 | (address) |
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+ | DB |
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-------------------------------
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Operand
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Address: | effective address |
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10. Direct Indexed With X -- d,x
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The second byte of the instruction is added to the sum of the Direct Register
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and the X Index Register to form the 16-bit effective address. The operand is
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always in Bank 0.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| direct address |
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+ | | X Reg |
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-------------------------------
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Operand
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Address: | 00 | effective address |
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11. Direct Indexed With Y -- d,y
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The second byte of the instruction is added to the sum of the Direct Register
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and the Y Index Register to form the 16-bit effective address. The operand is
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always in Bank 0.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| direct address |
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+ | | Y Reg |
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-------------------------------
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Operand
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Address: | 00 | effective address |
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12. Absolute Indexed With X -- a,x
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The second and third bytes of the instruction are added to the
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X Index Register to form the low-order 16 bits of the ef~ective ad-
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dress The Data Bank Register contains the high-order 8 bits of the
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effective address
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____________________________
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Instruction: | opcode | addrl | addrh |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| DB | addrrh | addrl |
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+ | | X Reg |
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-------------------------------
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Operand
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Address: | effective address |
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13. Absolute Indexed With Y -- a,y
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The second and third bytes of the instruction are added to the
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Y Index Register to form the low-order 16 bits of the eftective ad-
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dress The Data Bank Register contains the high-order 8 bits of tne
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effective address.
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____________________________
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Instruction: | opcode | addrl | addrh |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| DB | addrrh | addrl |
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+ | | Y Reg |
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-------------------------------
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Operand
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Address: | effective address |
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14. Absolute Long Indexed With X -- al,x
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The second third and fourth bytes ot the instruction form a 24-bit base
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address. The effective address is the sum of this 24-bit address and the
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X Index Register.
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____________________________________
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Instruction: | opcode | addrl | addrh | baddr |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| baddr | addrrh | addrl |
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+ | | X Reg |
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-------------------------------
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Operand
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Address: | effective address |
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15. Program Counter Relative -- r
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This address mode referred to as Relative Addressing is used only with the
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Branch instructions. If the conditlon being tested is met, the second byte
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of the instruction is added to the Program Counter, which has been updated
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to point to the opcode of the next instruction. The offset is a signed 8-bit
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quantity in the range from -128 to 127 The Program Bank Register is not
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affected.
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16. Program Counter Relative Long -- rl
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This address mode referred to as Relative Long Addressing is used only with
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the Unconditional Branch Long instruction (BRL) and the Push Effective
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Relative instruction (PER). The second and third 2 bytes of the instruction
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are added to the Program Counter which has been updated to point to the opcode
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of the next instruction. With the branch instruction the Program Counter is
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loaded with the result With the Push Effective Relative instruction the result
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is stored on the stack. The offset and result are both an unsigned 16-bit
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quantity in the range 0 to 65535.
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17. Absolute Indirect -- (a)
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The second and third bytes of the instruction form an address to a pointer
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in Bank 0. The Program Counter is loaded with the first and second bytes at
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this pointer With the Jump Long (JML) instruction the Program Bank Register
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is loaded with the third byte of the pointer
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____________________________
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Instruction: | opcode | addrl | addrh |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| baddr | addrrh | addrl |
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Indirect Address = | 00 | addrh | addrl |
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New PC = (indirect address)
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with JML:
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New PC = (indirect address)
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New PB = (indirect address +2)
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18. Direct Indirect -- (d)
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The second byte of the instruction is added to the Direct Register to form
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a pointer to the low-order 16 bits of the effective address. The Data Bank
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Register contains the high-order 8 bits of the effective address.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| 00 | direct address |
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then:
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| 00 | (direct address) |
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+ | DB |
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-------------------------------
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Operand
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Address: | effective address |
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19. Direct Indirect Long -- [d]
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The second byte of the instruction is added to the Direct Register to form
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a pointer to the 24-bit effective address.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Direct Register |
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+ | offset |
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---------------------
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| 00 | direct address |
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then:
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-------------------------------
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Operand
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Address: | (direct address) |
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20. Absolute Indexed Indirect -- (a,x)
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The second and third bytes of the instruction are added to the X Index
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Register to form a 16-bit pointer in Bank 0. The contents of this pointer
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are loaded in the Program Counter. The Program Bank Register is not changed.
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____________________________
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Instruction: | opcode | addrl | addrh |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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| addrrh | addrl |
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+ | | X Reg |
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-------------------------------
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| 00 | address |
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then:
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PC = (address)
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21. Stack -- s
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Stack addressing refers to all instructions that push or pull data from the
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stack such as Push, Pull, Jump to Subroutine, Return from Subroutine,
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Interrupts, and Return from Interrupt. The bank address is always 0.
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Interrupt Vectors are always fetched from Bank 0.
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22. Stack Relative -- d,s
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The low-order 16 bits of the effective address is formed from the sum of the
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second byte of the instruction and the Stack Pointer. The high-order 8 bits
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of the effective address is always zero. The relative offset is an unsigned
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8-bit quantity in the range of 0 to 255.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Stack Pointer |
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+ | offset |
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---------------------
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| 00 | effective address |
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23. Stack Relative Indirect Indexed -- (d,s),y
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The second byte of the instruction is added to the Stack Pointer to form
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a pointer to the low-order 16-bit base address in Bank 0. The Data Bank
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Register contains the high-order 8 bits of the base address. The effective
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address is the sum of the 24-bit base address and the Y Index Register.
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___________________
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Instruction: | opcode | offset |
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~~~~~~~~~~~~~~~~~~~
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| Stack Pointer |
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+ | offset |
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---------------------
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| 00 | S + offset |
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then:
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| S + offset |
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+ | DB |
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-------------------------------
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| base address |
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+ | | Y Reg |
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------------------------------
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Operand
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Address: | effective address |
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24. Block Source Bank, Destination Bank -- xyc
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This addressing mode is used by the Block Move instructions.
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The second byte of the instruction contains the high-order 8 bits of the
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destination address.
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The Y Index Register contains the low-order 16 bits of the destination
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address. The third byte of the instruction contains the high-order 8 bits
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of the source address.
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The X Index Register contains the low-order 16 bits of the source address.
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The Accumulator contains one less than the number of bytes to move.
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The second byte of the block move instructions is also loaded into the Data
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Bank Register.
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____________________________
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Instruction: | opcode | dstbnk | srcbnk |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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dstbnk -> DB
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Source Address: | scrbnk | X reg |
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Destination Address: | DB | Y reg |
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Increment (MVN) or decrement (MVP) X and Y.
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Decrement A (if greaterthan zero) then PC-3 -> PC.
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