92 lines
3.7 KiB
Plaintext
92 lines
3.7 KiB
Plaintext
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Notes on G65SC802/816 Instructions
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All Opcodes Function in All Modes of Operation
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It should be noted that all opcodes function in all modes of operation.
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However, some instructions and addressing modes are intended for G65SC816
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24-bit addressing and are therefore less useful for the G65SC802. The
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following is a list of Instructions and addressing modes which are primarily
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intended for G65SC816 use:
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JSL; RTL; [d]; [d],y; JMP al; JML; al; al,x
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The following instructions may be used with the G65SC802 even though a
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Bank Address is not multiplexed on the Data Bus:
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PHK; PHB; PLB
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The following instructions have "limited" use in the Emulation mode.
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* The REP and SEP instructions cannot modify the M and X bits when in the
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Emulation mode. In this mode the M and X bits will always be high (logic 1).
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* When in the Emulation mode, the MVP and MVN instructions only move data
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in page zero since X and Y Index Register high byte is zero.
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Indirect Jumps
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The JMP (a) and JML (a) instructions use the direct Bank for indirect
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addressing, while JMP (a,x) and JSR (a,x) use the Program Bank for indirect
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address tables.
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Switching Modes
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When switching from the Native mode to the Emulation mode, the X and M bits
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of the Status Register are set high (logic 1), the high byte of the Stack is
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set to 01, and the high bytes of the X and Y Index Registers are set to 00.
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To save previous values, these bytes must always be stored before changing
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modes. Note that the low byte of the S, X and Y Registers and the low and high
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byte of the Accumulator AL and AH are not affected by a mode change.
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WAI Instruction
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The WAI instruction pulls RDY low and places the processor in the WAI
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"low power" mode. /NMI, /IRQ or /RESET will terminate the WAI condition and
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transfer control to the interrupt handler routine. Note that an /ABORT input
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will abort the WAI instruction, but will not restart the processor. When the
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Status Register I flag is set (IRQ disabled), the IRQ interrupt will cause the
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next instruction (following the WAI instruction) to be executed without going
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to the IRQ interrupt handler. This method results in the highest speed response
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to an IRQ input. When an interrupt is received after an ABORT which occurs
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during the WAI instruction, the processor will return to the WAI instruction.
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Other than RES (highest priority), ABORT is the next highest priority, followed
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by NMI or IRQ interrupts.
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STP Instruction
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The STP instruction disables the Phi2 clock to all circuitry. When disabled,
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the Phi2 clock is held in the high state. In this case, the Data Bus will
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remain in the data transfer state and the Bank address will not be multiplexed
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onto the Data Bus. Upon executing the STP instruction, the /RES signal is the
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only input which can restart the processor. The processor is restarted by
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enabling the Phi2 clock, which occurs on the falling edge of the /RES input.
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Note that the external oscillator must be stable and operating properly before
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RES goes high.
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Tranters trom 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers
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All transfers from one register to another will result in a full 16-bit output
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from the source register. The destination register size will determine the
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number of bits actually stored in the destination register and the values
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stored in the processor Status Register. The following are always 16-bit
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transfers, regardless of the accumulator size:
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TCS; TSC; TCD; TDC
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Stack Transfers
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When in the Emulation mode, a 01 is forced into SH. In this case, the B
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Accumulator will not be loaded into SH during a TCS instruction. When in the
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Native mode, the B Accumulator is transferred to SH. Note that in both the
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Emulation and Native modes, the full 16 bits of the Stack Register are
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transferred to the Accumulator, regardless of the state of the M bit in the
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Status Register.
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