36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
Here's the pinout to a 4Mbit/*Mbit mask Rom used in SNES carts as I've
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deduced from various specs and actual testing.
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1 A17 ------\__/------ +5v 32
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2 A18 | | *OE 31
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3 A15 A19 30
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4 A12 A14 29
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5 A7 A13 28
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6 A6 A8 27
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7 A5 A9 26
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8 A4 A11 25
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9 A3 A16 24
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10 A2 A10 23
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11 A1 *CE 22
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12 A0 D7 21
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13 D0 D6 20
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14 D1 D5 19
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15 D2 D4 18
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16 GND |---------------| D3 17
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The design approximates std EPROM/SRAM pinouts except for the upper address
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lines (A16-A19), and OE which sits where VPP or PRGM usually is for an EPROM.
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This pinout approximates Fujitsu's tentative mask ROM pinouts (a package
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called GAMEMEDC.ZIP seems to base itself on this and is consequently wrong).
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Nintendo uses Fujitsu chips in some carts, but from my testing and card-edge
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pinouts provided by other users, I conclude that Fujitsu must have modified
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the designs.
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NOTE!: Card-edge pin #40, address line 15 (A15) is not used by any cart I've
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seen. And ROM pin #3 (see above) that I've determined to be A15 is connected
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to card-edge pin#41, labeled on many pinouts schems as A16..not A15!!!
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Would some one please verify this inconsistency.
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PS: How many Megabits can the Snes address?
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