##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun Oct 30 20:22:20 2011
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:mult_gen:11.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc3s400
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Multiplier xilinx.com:ip:mult_gen:11.2
# END Select
# BEGIN Parameters
CSET ccmimp=Distributed_Memory
CSET clockenable=true
CSET component_name=cx4_mul
CSET constvalue=129
CSET internaluser=0
CSET multiplier_construction=Use_Mults
CSET multtype=Parallel_Multiplier
CSET optgoal=Speed
CSET outputwidthhigh=47
CSET outputwidthlow=0
CSET pipestages=2
CSET portatype=Signed
CSET portawidth=24
CSET portbtype=Signed
CSET portbwidth=24
CSET roundpoint=0
CSET sclrcepriority=SCLR_Overrides_CE
CSET syncclear=false
CSET use_custom_output_width=false
CSET userounding=false
CSET zerodetect=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:26:54.000Z
# END Extra information
GENERATE
# CRC:  4f144c3
