diff --git a/verilog/sd2snes/ipcore_dir/dac_buf.v b/verilog/sd2snes/ipcore_dir/dac_buf.v
index f84343f..1f5f74c 100644
--- a/verilog/sd2snes/ipcore_dir/dac_buf.v
+++ b/verilog/sd2snes/ipcore_dir/dac_buf.v
@@ -23,29 +23,29 @@
 *     appliances, devices, or systems. Use in such applications are            *
 *     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
 // You must compile the wrapper file dac_buf.v when simulating
 // the core, dac_buf. When compiling the wrapper file, be sure to
 // reference the XilinxCoreLib Verilog simulation library. For detailed
 // instructions, please refer to the "CORE Generator Help".
 
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
 `timescale 1ns/1ps
 
 module dac_buf(
-	clka,
-	wea,
-	addra,
-	dina,
-	clkb,
-	addrb,
-	doutb);
-
+  clka,
+  wea,
+  addra,
+  dina,
+  clkb,
+  addrb,
+  doutb
+);
 
 input clka;
 input [0 : 0] wea;
@@ -57,89 +57,126 @@ output [31 : 0] doutb;
 
 // synthesis translate_off
 
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(11),
-		.C_ADDRB_WIDTH(9),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(1),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan3"),
-		.C_HAS_ENA(0),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("no_coe_file_loaded"),
-		.C_LOAD_INIT_FILE(0),
-		.C_MEM_TYPE(1),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(2048),
-		.C_READ_DEPTH_B(512),
-		.C_READ_WIDTH_A(8),
-		.C_READ_WIDTH_B(32),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(2048),
-		.C_WRITE_DEPTH_B(512),
-		.C_WRITE_MODE_A("WRITE_FIRST"),
-		.C_WRITE_MODE_B("WRITE_FIRST"),
-		.C_WRITE_WIDTH_A(8),
-		.C_WRITE_WIDTH_B(32),
-		.C_XDEVICEFAMILY("spartan3"))
-	inst (
-		.CLKA(clka),
-		.WEA(wea),
-		.ADDRA(addra),
-		.DINA(dina),
-		.CLKB(clkb),
-		.ADDRB(addrb),
-		.DOUTB(doutb),
-		.RSTA(),
-		.ENA(),
-		.REGCEA(),
-		.DOUTA(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.DINB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
+  BLK_MEM_GEN_V6_1 #(
+    .C_ADDRA_WIDTH(11),
+    .C_ADDRB_WIDTH(9),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(1),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_FAMILY("spartan3"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(0),
+    .C_MEM_TYPE(1),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(2048),
+    .C_READ_DEPTH_B(512),
+    .C_READ_WIDTH_A(8),
+    .C_READ_WIDTH_B(32),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(2048),
+    .C_WRITE_DEPTH_B(512),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(8),
+    .C_WRITE_WIDTH_B(32),
+    .C_XDEVICEFAMILY("spartan3")
+  )
+  inst (
+    .CLKA(clka),
+    .WEA(wea),
+    .ADDRA(addra),
+    .DINA(dina),
+    .CLKB(clkb),
+    .ADDRB(addrb),
+    .DOUTB(doutb),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .DOUTA(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .DINB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
 
 // synthesis translate_on
 
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of dac_buf is "black_box"
-
 endmodule
-
diff --git a/verilog/sd2snes/ipcore_dir/dac_buf.xise b/verilog/sd2snes/ipcore_dir/dac_buf.xise
index 5f14e85..9e02186 100644
--- a/verilog/sd2snes/ipcore_dir/dac_buf.xise
+++ b/verilog/sd2snes/ipcore_dir/dac_buf.xise
@@ -9,29 +9,29 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="dac_buf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
     </file>
   </files>
 
@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="dac_buf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T01:00:57" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0C4CD66917CF19E8D82022B8EDE6CEB3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-02T02:40:57" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F04021A68581059F84CB48D6F91F3293" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
diff --git a/verilog/sd2snes/ipcore_dir/msu_databuf.v b/verilog/sd2snes/ipcore_dir/msu_databuf.v
index c2a0a23..13fd34d 100644
--- a/verilog/sd2snes/ipcore_dir/msu_databuf.v
+++ b/verilog/sd2snes/ipcore_dir/msu_databuf.v
@@ -23,29 +23,29 @@
 *     appliances, devices, or systems. Use in such applications are            *
 *     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
 // You must compile the wrapper file msu_databuf.v when simulating
 // the core, msu_databuf. When compiling the wrapper file, be sure to
 // reference the XilinxCoreLib Verilog simulation library. For detailed
 // instructions, please refer to the "CORE Generator Help".
 
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
 `timescale 1ns/1ps
 
 module msu_databuf(
-	clka,
-	wea,
-	addra,
-	dina,
-	clkb,
-	addrb,
-	doutb);
-
+  clka,
+  wea,
+  addra,
+  dina,
+  clkb,
+  addrb,
+  doutb
+);
 
 input clka;
 input [0 : 0] wea;
@@ -57,89 +57,126 @@ output [7 : 0] doutb;
 
 // synthesis translate_off
 
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(14),
-		.C_ADDRB_WIDTH(14),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(1),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan3"),
-		.C_HAS_ENA(0),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("no_coe_file_loaded"),
-		.C_LOAD_INIT_FILE(0),
-		.C_MEM_TYPE(1),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(16384),
-		.C_READ_DEPTH_B(16384),
-		.C_READ_WIDTH_A(8),
-		.C_READ_WIDTH_B(8),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(16384),
-		.C_WRITE_DEPTH_B(16384),
-		.C_WRITE_MODE_A("WRITE_FIRST"),
-		.C_WRITE_MODE_B("WRITE_FIRST"),
-		.C_WRITE_WIDTH_A(8),
-		.C_WRITE_WIDTH_B(8),
-		.C_XDEVICEFAMILY("spartan3"))
-	inst (
-		.CLKA(clka),
-		.WEA(wea),
-		.ADDRA(addra),
-		.DINA(dina),
-		.CLKB(clkb),
-		.ADDRB(addrb),
-		.DOUTB(doutb),
-		.RSTA(),
-		.ENA(),
-		.REGCEA(),
-		.DOUTA(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.DINB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
+  BLK_MEM_GEN_V6_1 #(
+    .C_ADDRA_WIDTH(14),
+    .C_ADDRB_WIDTH(14),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(1),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_FAMILY("spartan3"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(0),
+    .C_MEM_TYPE(1),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(16384),
+    .C_READ_DEPTH_B(16384),
+    .C_READ_WIDTH_A(8),
+    .C_READ_WIDTH_B(8),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(16384),
+    .C_WRITE_DEPTH_B(16384),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(8),
+    .C_WRITE_WIDTH_B(8),
+    .C_XDEVICEFAMILY("spartan3")
+  )
+  inst (
+    .CLKA(clka),
+    .WEA(wea),
+    .ADDRA(addra),
+    .DINA(dina),
+    .CLKB(clkb),
+    .ADDRB(addrb),
+    .DOUTB(doutb),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .DOUTA(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .DINB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
 
 // synthesis translate_on
 
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of msu_databuf is "black_box"
-
 endmodule
-
diff --git a/verilog/sd2snes/ipcore_dir/msu_databuf.xise b/verilog/sd2snes/ipcore_dir/msu_databuf.xise
index 39ae055..11ed195 100644
--- a/verilog/sd2snes/ipcore_dir/msu_databuf.xise
+++ b/verilog/sd2snes/ipcore_dir/msu_databuf.xise
@@ -9,29 +9,29 @@
     <!-- along with the project source files, is sufficient to open and    -->
     <!-- implement in ISE Project Navigator.                               -->
     <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="msu_databuf.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="msu_databuf.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
     </file>
   </files>
 
@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="msu_databuf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-12-12T23:27:26" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7C4C4A25F769831F8D602222C50CD9B3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-02T02:42:25" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5C4DFF8128BF7CCC1509FF9031261DA2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.v b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
index 360df18..42af65f 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
@@ -23,27 +23,27 @@
 *     appliances, devices, or systems. Use in such applications are            *
 *     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
 // You must compile the wrapper file upd77c25_datram.v when simulating
 // the core, upd77c25_datram. When compiling the wrapper file, be sure to
 // reference the XilinxCoreLib Verilog simulation library. For detailed
 // instructions, please refer to the "CORE Generator Help".
 
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
 `timescale 1ns/1ps
 
 module upd77c25_datram(
-	clka,
-	wea,
-	addra,
-	dina,
-	douta);
-
+  clka,
+  wea,
+  addra,
+  dina,
+  douta
+);
 
 input clka;
 input [0 : 0] wea;
@@ -53,89 +53,126 @@ output [15 : 0] douta;
 
 // synthesis translate_off
 
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(8),
-		.C_ADDRB_WIDTH(8),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(0),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan3"),
-		.C_HAS_ENA(0),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("no_coe_file_loaded"),
-		.C_LOAD_INIT_FILE(0),
-		.C_MEM_TYPE(0),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(256),
-		.C_READ_DEPTH_B(256),
-		.C_READ_WIDTH_A(16),
-		.C_READ_WIDTH_B(16),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(256),
-		.C_WRITE_DEPTH_B(256),
-		.C_WRITE_MODE_A("WRITE_FIRST"),
-		.C_WRITE_MODE_B("WRITE_FIRST"),
-		.C_WRITE_WIDTH_A(16),
-		.C_WRITE_WIDTH_B(16),
-		.C_XDEVICEFAMILY("spartan3"))
-	inst (
-		.CLKA(clka),
-		.WEA(wea),
-		.ADDRA(addra),
-		.DINA(dina),
-		.DOUTA(douta),
-		.RSTA(),
-		.ENA(),
-		.REGCEA(),
-		.CLKB(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.ADDRB(),
-		.DINB(),
-		.DOUTB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
+  BLK_MEM_GEN_V6_1 #(
+    .C_ADDRA_WIDTH(8),
+    .C_ADDRB_WIDTH(8),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(0),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_FAMILY("spartan3"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(0),
+    .C_MEM_TYPE(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(256),
+    .C_READ_DEPTH_B(256),
+    .C_READ_WIDTH_A(16),
+    .C_READ_WIDTH_B(16),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(256),
+    .C_WRITE_DEPTH_B(256),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(16),
+    .C_WRITE_WIDTH_B(16),
+    .C_XDEVICEFAMILY("spartan3")
+  )
+  inst (
+    .CLKA(clka),
+    .WEA(wea),
+    .ADDRA(addra),
+    .DINA(dina),
+    .DOUTA(douta),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .CLKB(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .ADDRB(),
+    .DINB(),
+    .DOUTB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
 
 // synthesis translate_on
 
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of upd77c25_datram is "black_box"
-
 endmodule
-
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
index 40d55fd..a2bc230 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
@@ -1,19 +1,46 @@
 ##############################################################
+#
+# Xilinx Core Generator version 13.1
+# Date: Thu Jun  2 00:43:50 2011
+#
 ##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
 ##############################################################
-SET designentry = Verilog
-SET BusFormat = BusFormatAngleBracketNotRipped
-SET devicefamily = spartan3
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Advanced
 SET device = xc3s400
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
 SET package = pq208
+SET removerpms = false
+SET simulationfiles = Behavioral
 SET speedgrade = -4
-SET FlowVendor = Foundation_ISE
-SET VerilogSim = True
-SET VHDLSim = True
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+# END Select
+# BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
 CSET algorithm=Minimum_Area
 CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
 CSET byte_size=9
 CSET coe_file=no_coe_file_loaded
 CSET collision_warnings=ALL
@@ -26,6 +53,7 @@ CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
 CSET load_init_file=false
 CSET memory_type=Single_Port_RAM
 CSET operating_mode_a=WRITE_FIRST
@@ -36,9 +64,9 @@ CSET pipeline_stages=0
 CSET port_a_clock=100
 CSET port_a_enable_rate=100
 CSET port_a_write_rate=50
-CSET port_b_clock=100
-CSET port_b_enable_rate=100
-CSET port_b_write_rate=50
+CSET port_b_clock=0
+CSET port_b_enable_rate=0
+CSET port_b_write_rate=0
 CSET primitive=8kx2
 CSET read_width_a=16
 CSET read_width_b=16
@@ -55,6 +83,7 @@ CSET reset_priority_a=CE
 CSET reset_priority_b=CE
 CSET reset_type=SYNC
 CSET softecc=false
+CSET use_axi_id=false
 CSET use_byte_write_enable=false
 CSET use_error_injection_pins=false
 CSET use_regcea_pin=false
@@ -64,3 +93,9 @@ CSET use_rstb_pin=false
 CSET write_depth_a=256
 CSET write_width_a=16
 CSET write_width_b=16
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+# END Extra information
+GENERATE
+# CRC: 47f41c0a
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v
index 54e57b7..96c7b56 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v
@@ -23,123 +23,152 @@
 *     appliances, devices, or systems. Use in such applications are            *
 *     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
 // You must compile the wrapper file upd77c25_datrom.v when simulating
 // the core, upd77c25_datrom. When compiling the wrapper file, be sure to
 // reference the XilinxCoreLib Verilog simulation library. For detailed
 // instructions, please refer to the "CORE Generator Help".
 
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
 `timescale 1ns/1ps
 
 module upd77c25_datrom(
-	clka,
-	wea,
-	addra,
-	dina,
-	clkb,
-	addrb,
-	doutb);
-
+  clka,
+  addra,
+  douta
+);
 
 input clka;
-input [0 : 0] wea;
 input [9 : 0] addra;
-input [15 : 0] dina;
-input clkb;
-input [9 : 0] addrb;
-output [15 : 0] doutb;
+output [15 : 0] douta;
 
 // synthesis translate_off
 
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(10),
-		.C_ADDRB_WIDTH(10),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(1),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan3"),
-		.C_HAS_ENA(0),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("upd77c25_datrom.mif"),
-		.C_LOAD_INIT_FILE(1),
-		.C_MEM_TYPE(1),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(1024),
-		.C_READ_DEPTH_B(1024),
-		.C_READ_WIDTH_A(16),
-		.C_READ_WIDTH_B(16),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(1024),
-		.C_WRITE_DEPTH_B(1024),
-		.C_WRITE_MODE_A("WRITE_FIRST"),
-		.C_WRITE_MODE_B("WRITE_FIRST"),
-		.C_WRITE_WIDTH_A(16),
-		.C_WRITE_WIDTH_B(16),
-		.C_XDEVICEFAMILY("spartan3"))
-	inst (
-		.CLKA(clka),
-		.WEA(wea),
-		.ADDRA(addra),
-		.DINA(dina),
-		.CLKB(clkb),
-		.ADDRB(addrb),
-		.DOUTB(doutb),
-		.RSTA(),
-		.ENA(),
-		.REGCEA(),
-		.DOUTA(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.DINB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
+  BLK_MEM_GEN_V6_1 #(
+    .C_ADDRA_WIDTH(10),
+    .C_ADDRB_WIDTH(10),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(0),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_FAMILY("spartan3"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME("upd77c25_datrom.mif"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(1),
+    .C_MEM_TYPE(3),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(1024),
+    .C_READ_DEPTH_B(1024),
+    .C_READ_WIDTH_A(16),
+    .C_READ_WIDTH_B(16),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(1024),
+    .C_WRITE_DEPTH_B(1024),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(16),
+    .C_WRITE_WIDTH_B(16),
+    .C_XDEVICEFAMILY("spartan3")
+  )
+  inst (
+    .CLKA(clka),
+    .ADDRA(addra),
+    .DOUTA(douta),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .WEA(),
+    .DINA(),
+    .CLKB(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .ADDRB(),
+    .DINB(),
+    .DOUTB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
 
 // synthesis translate_on
 
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of upd77c25_datrom is "black_box"
-
 endmodule
-
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco
index 0456fb0..5c48fdb 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 12.3
-# Date: Mon May 30 11:59:50 2011
+# Xilinx Core Generator version 13.1
+# Date: Thu Jun  2 00:42:40 2011
 #
 ##############################################################
 #
@@ -17,10 +17,10 @@ SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Verilog
+SET designentry = Advanced
 SET device = xc3s400
 SET devicefamily = spartan3
-SET flowvendor = Foundation_ISE
+SET flowvendor = Other
 SET formalverification = false
 SET foundationsym = false
 SET implementationfiletype = Ngc
@@ -32,12 +32,15 @@ SET verilogsim = true
 SET vhdlsim = true
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
 CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=true
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
 CSET byte_size=9
 CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_datrom.coe
 CSET collision_warnings=ALL
@@ -50,8 +53,9 @@ CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
 CSET load_init_file=true
-CSET memory_type=Simple_Dual_Port_RAM
+CSET memory_type=Single_Port_ROM
 CSET operating_mode_a=WRITE_FIRST
 CSET operating_mode_b=WRITE_FIRST
 CSET output_reset_value_a=0
@@ -59,9 +63,9 @@ CSET output_reset_value_b=0
 CSET pipeline_stages=0
 CSET port_a_clock=100
 CSET port_a_enable_rate=100
-CSET port_a_write_rate=50
-CSET port_b_clock=100
-CSET port_b_enable_rate=100
+CSET port_a_write_rate=0
+CSET port_b_clock=0
+CSET port_b_enable_rate=0
 CSET port_b_write_rate=0
 CSET primitive=8kx2
 CSET read_width_a=16
@@ -79,6 +83,7 @@ CSET reset_priority_a=CE
 CSET reset_priority_b=CE
 CSET reset_type=SYNC
 CSET softecc=false
+CSET use_axi_id=false
 CSET use_byte_write_enable=false
 CSET use_error_injection_pins=false
 CSET use_regcea_pin=false
@@ -89,5 +94,8 @@ CSET write_depth_a=1024
 CSET write_width_a=16
 CSET write_width_b=16
 # END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+# END Extra information
 GENERATE
-# CRC: 2baeb226
+# CRC: d64159b2
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v
index eeef4b6..483030c 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v
@@ -23,29 +23,29 @@
 *     appliances, devices, or systems. Use in such applications are            *
 *     expressly prohibited.                                                    *
 *                                                                              *
-*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
-// The synthesis directives "translate_off/translate_on" specified below are
-// supported by Xilinx, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
 // You must compile the wrapper file upd77c25_pgmrom.v when simulating
 // the core, upd77c25_pgmrom. When compiling the wrapper file, be sure to
 // reference the XilinxCoreLib Verilog simulation library. For detailed
 // instructions, please refer to the "CORE Generator Help".
 
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
 `timescale 1ns/1ps
 
 module upd77c25_pgmrom(
-	clka,
-	wea,
-	addra,
-	dina,
-	clkb,
-	addrb,
-	doutb);
-
+  clka,
+  wea,
+  addra,
+  dina,
+  clkb,
+  addrb,
+  doutb
+);
 
 input clka;
 input [0 : 0] wea;
@@ -57,89 +57,126 @@ output [23 : 0] doutb;
 
 // synthesis translate_off
 
-      BLK_MEM_GEN_V4_3 #(
-		.C_ADDRA_WIDTH(11),
-		.C_ADDRB_WIDTH(11),
-		.C_ALGORITHM(1),
-		.C_BYTE_SIZE(9),
-		.C_COMMON_CLK(1),
-		.C_DEFAULT_DATA("0"),
-		.C_DISABLE_WARN_BHV_COLL(0),
-		.C_DISABLE_WARN_BHV_RANGE(0),
-		.C_FAMILY("spartan3"),
-		.C_HAS_ENA(0),
-		.C_HAS_ENB(0),
-		.C_HAS_INJECTERR(0),
-		.C_HAS_MEM_OUTPUT_REGS_A(0),
-		.C_HAS_MEM_OUTPUT_REGS_B(0),
-		.C_HAS_MUX_OUTPUT_REGS_A(0),
-		.C_HAS_MUX_OUTPUT_REGS_B(0),
-		.C_HAS_REGCEA(0),
-		.C_HAS_REGCEB(0),
-		.C_HAS_RSTA(0),
-		.C_HAS_RSTB(0),
-		.C_HAS_SOFTECC_INPUT_REGS_A(0),
-		.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-		.C_INITA_VAL("0"),
-		.C_INITB_VAL("0"),
-		.C_INIT_FILE_NAME("upd77c25_pgmrom.mif"),
-		.C_LOAD_INIT_FILE(1),
-		.C_MEM_TYPE(1),
-		.C_MUX_PIPELINE_STAGES(0),
-		.C_PRIM_TYPE(1),
-		.C_READ_DEPTH_A(2048),
-		.C_READ_DEPTH_B(2048),
-		.C_READ_WIDTH_A(24),
-		.C_READ_WIDTH_B(24),
-		.C_RSTRAM_A(0),
-		.C_RSTRAM_B(0),
-		.C_RST_PRIORITY_A("CE"),
-		.C_RST_PRIORITY_B("CE"),
-		.C_RST_TYPE("SYNC"),
-		.C_SIM_COLLISION_CHECK("ALL"),
-		.C_USE_BYTE_WEA(0),
-		.C_USE_BYTE_WEB(0),
-		.C_USE_DEFAULT_DATA(0),
-		.C_USE_ECC(0),
-		.C_USE_SOFTECC(0),
-		.C_WEA_WIDTH(1),
-		.C_WEB_WIDTH(1),
-		.C_WRITE_DEPTH_A(2048),
-		.C_WRITE_DEPTH_B(2048),
-		.C_WRITE_MODE_A("NO_CHANGE"),
-		.C_WRITE_MODE_B("NO_CHANGE"),
-		.C_WRITE_WIDTH_A(24),
-		.C_WRITE_WIDTH_B(24),
-		.C_XDEVICEFAMILY("spartan3"))
-	inst (
-		.CLKA(clka),
-		.WEA(wea),
-		.ADDRA(addra),
-		.DINA(dina),
-		.CLKB(clkb),
-		.ADDRB(addrb),
-		.DOUTB(doutb),
-		.RSTA(),
-		.ENA(),
-		.REGCEA(),
-		.DOUTA(),
-		.RSTB(),
-		.ENB(),
-		.REGCEB(),
-		.WEB(),
-		.DINB(),
-		.INJECTSBITERR(),
-		.INJECTDBITERR(),
-		.SBITERR(),
-		.DBITERR(),
-		.RDADDRECC());
-
+  BLK_MEM_GEN_V6_1 #(
+    .C_ADDRA_WIDTH(11),
+    .C_ADDRB_WIDTH(11),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(1),
+    .C_DEFAULT_DATA("0"),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_FAMILY("spartan3"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(0),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME("upd77c25_pgmrom.mif"),
+    .C_INITA_VAL("0"),
+    .C_INITB_VAL("0"),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(1),
+    .C_MEM_TYPE(1),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(2048),
+    .C_READ_DEPTH_B(2048),
+    .C_READ_WIDTH_A(24),
+    .C_READ_WIDTH_B(24),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(2048),
+    .C_WRITE_DEPTH_B(2048),
+    .C_WRITE_MODE_A("NO_CHANGE"),
+    .C_WRITE_MODE_B("NO_CHANGE"),
+    .C_WRITE_WIDTH_A(24),
+    .C_WRITE_WIDTH_B(24),
+    .C_XDEVICEFAMILY("spartan3")
+  )
+  inst (
+    .CLKA(clka),
+    .WEA(wea),
+    .ADDRA(addra),
+    .DINA(dina),
+    .CLKB(clkb),
+    .ADDRB(addrb),
+    .DOUTB(doutb),
+    .RSTA(),
+    .ENA(),
+    .REGCEA(),
+    .DOUTA(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .DINB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
 
 // synthesis translate_on
 
-// XST black box declaration
-// box_type "black_box"
-// synthesis attribute box_type of upd77c25_pgmrom is "black_box"
-
 endmodule
-
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco
index f1ff6ce..c0b1aa0 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco
@@ -1,19 +1,46 @@
 ##############################################################
+#
+# Xilinx Core Generator version 13.1
+# Date: Tue May 31 20:54:32 2011
+#
 ##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
 ##############################################################
-SET designentry = Verilog
-SET BusFormat = BusFormatAngleBracketNotRipped
-SET devicefamily = spartan3
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Advanced
 SET device = xc3s400
+SET devicefamily = spartan3
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
 SET package = pq208
+SET removerpms = false
+SET simulationfiles = Behavioral
 SET speedgrade = -4
-SET FlowVendor = Foundation_ISE
-SET VerilogSim = True
-SET VHDLSim = True
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+# END Select
+# BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
 CSET algorithm=Minimum_Area
 CSET assume_synchronous_clk=true
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
 CSET byte_size=9
 CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_pgmrom.coe
 CSET collision_warnings=ALL
@@ -26,6 +53,7 @@ CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
 CSET load_init_file=true
 CSET memory_type=Simple_Dual_Port_RAM
 CSET operating_mode_a=NO_CHANGE
@@ -55,6 +83,7 @@ CSET reset_priority_a=CE
 CSET reset_priority_b=CE
 CSET reset_type=SYNC
 CSET softecc=false
+CSET use_axi_id=false
 CSET use_byte_write_enable=false
 CSET use_error_injection_pins=false
 CSET use_regcea_pin=false
@@ -64,3 +93,9 @@ CSET use_rstb_pin=false
 CSET write_depth_a=2048
 CSET write_width_a=24
 CSET write_width_b=24
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+# END Extra information
+GENERATE
+# CRC: f1fd9704
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 1e4ec04..d5477be 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -1,5 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 23.95 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %;
 //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
 NET "SNES_CS" IOSTANDARD = LVCMOS33;
 NET "SNES_READ" IOSTANDARD = LVCMOS33;