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FPGA: adjust menu memory mapping to make more room for file database

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This commit is contained in:
Maximilian Rehkopf 2012-06-10 20:07:45 +02:00
parent 66f26c18b1
commit 034b39588c
4 changed files with 36 additions and 54 deletions
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2
verilog/sd2snes/address.v
View File

@ -183,7 +183,7 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000) ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK) & SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hE00000) + 24'hC00000)
) )
: 24'b0); : 24'b0);

74
verilog/sd2snes/sd2snes.xise
View File

@ -9,107 +9,91 @@
<!-- along with the project source files, is sufficient to open and --> <!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. --> <!-- implement in ISE Project Navigator. -->
<!-- --> <!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header> </header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<files> <files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="bsx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="rtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="srtc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="upd77c25.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="main_tf.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="updtest_tf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/upd77c25_datram.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/upd77c25_datrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN"> <file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="ipcore_dir/upd77c25_datram.xise" xil_pn:type="FILE_COREGENISE"> <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_datrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/upd77c25_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
</files> </files>
@ -377,8 +361,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@ -449,9 +433,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings> <bindings/>
<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
</bindings>
<libraries/> <libraries/>

2
verilog/sd2sneslite/address.v
View File

@ -50,7 +50,7 @@ assign SRAM_SNES_ADDR = (IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000) ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK) & SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hE00000) + 24'hC00000)
); );
assign ROM_ADDR = SRAM_SNES_ADDR; assign ROM_ADDR = SRAM_SNES_ADDR;

12
verilog/sd2sneslite/sd2sneslite.xise
View File

@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and --> <!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. --> <!-- implement in ISE Project Navigator. -->
<!-- --> <!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header> </header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
<files> <files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
@ -35,13 +35,13 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
</files> </files>
<properties> <properties>