godzil/sd2snes
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

FPGA/Cx4: optimize non-sector-aligned SD DMA reads

Browse Source
This commit is contained in:
ikari 2012-01-14 02:21:01 +01:00
parent 3243143c39
commit 059966f06a
2 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
verilog/sd2snes_cx4/main.v
View File

@ -125,7 +125,9 @@ sd_dma snes_sd_dma(
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
@ -215,6 +217,8 @@ mcu_cmd snes_mcu_cmd(
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),

14
verilog/sd2snes_cx4/sd_dma.v
View File

@ -29,7 +29,9 @@ module sd_dma(
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
input [10:0] SD_DMA_PARTIAL_END,
input SD_DMA_START_MID_BLOCK,
input SD_DMA_END_MID_BLOCK
);
reg [10:0] SD_DMA_STARTr;
@ -85,7 +87,9 @@ always @(posedge CLK) begin
end
always @(posedge CLK) begin
if(cyclecnt == 1042) SD_DMA_DONEr <= 1;
if(cyclecnt == 1042
|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
@ -100,8 +104,10 @@ always @(posedge CLK) begin
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1;
if(SD_DMA_EN_rising)
cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
else if(!SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write