diff --git a/src/config.h b/src/config.h
index df06479..29f8e53 100644
--- a/src/config.h
+++ b/src/config.h
@@ -62,10 +62,8 @@
 #    error Unknown chip!
 #  endif
 #  define SD_CHANGE_VECT        INT0_vect
-#  define SDCARD_WP  			(0)
-#  define SDCARD_WP_SETUP()     do { DDRB &= ~ _BV(PB1); PORTB |= _BV(PB1); } while(0)
-// #  define SDCARD_WP  			(PINB & _BV(PB1))
-// #  define SDCARD_WP_SETUP()     do { DDRB &= ~ _BV(PB1); PORTB |= _BV(PB1); } while(0)
+#  define SDCARD_WP  			(PINA & _BV(PA0))
+#  define SDCARD_WP_SETUP()     do { DDRA &= ~ _BV(PA0); PORTA |= _BV(PA0); } while(0)
 #  define SD_CHANGE_ICR         MCUCR
 #  define SD_SUPPLY_VOLTAGE     (1L<<21)
 #  define DEVICE_SELECT         (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3)))
diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v
index 7fbd89e..1df56ef 100644
--- a/verilog/sd2snes/dcm.v
+++ b/verilog/sd2snes/dcm.v
@@ -21,12 +21,9 @@
 module my_dcm (
          input CLKIN,
          output CLKFX,
-         output CLK2X,
          output LOCKED,
-         input CLKFB,
          input RST,
-         output[7:0] STATUS,
-         output CLK0
+         output[7:0] STATUS
     );
 
    // DCM: Digital Clock Manager Circuit
@@ -40,16 +37,16 @@ module my_dcm (
       .CLKFX_DIVIDE(1),   // Can be any integer from 1 to 32
       .CLKFX_MULTIPLY(7), // Can be any integer from 2 to 32
       .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
-      .CLKIN_PERIOD(47.000),  // Specify period of input clock
+      .CLKIN_PERIOD(81.380),  // Specify period of input clock
       .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("1X"),  // Specify clock feedback of NONE, 1X or 2X
+      .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
       .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             //   an integer from 0 to 15
       .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
       .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
       .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
       .FACTORY_JF(16'hFFFF),   // FACTORY JF values
-//      .LOC("X0Y0"),
+//      .LOC("DCM_X0Y0"),
       .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
       .STARTUP_WAIT("TRUE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
    ) DCM_inst (
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index f87e27a..5c032a8 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -180,55 +180,7 @@ NET "SRAM_DATA[7]" LOC = P116;
 NET "SRAM_DATA[8]" LOC = P96;
 NET "SRAM_DATA[9]" LOC = P98;
 NET "SRAM_OE" LOC = P93;
-TIMESPEC TS_test = FROM  FFS TO  FFS 10 ns;
-NET "SNES_ADDR<0>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<0>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<1>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<1>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<2>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<2>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<3>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<3>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<4>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<4>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<5>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<5>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<6>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<6>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<7>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<7>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<8>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<8>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<9>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<9>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<10>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<10>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<11>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<11>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<12>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<12>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<13>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<13>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<14>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<14>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<15>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<15>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<16>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<16>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<17>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<17>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<18>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<18>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<19>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<19>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<20>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<20>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<21>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<21>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<22>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<22>" MAXSKEW = 5 ns;
-NET "SNES_ADDR<23>" MAXDELAY = 10 ns;
-NET "SNES_ADDR<23>" MAXSKEW = 5 ns;
+
 NET "CLKIN" IOSTANDARD = LVCMOS33;
 NET "CLKIN" PULLUP;
 NET "SPI_SS" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 699132f..3138e0b 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -116,17 +116,16 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLKFX(CLK2),
                   .LOCKED(DCM_LOCKED),
                   .RST(DCM_RST),
-                  .STATUS(DCM_STATUS),
-                  .CLKFB(CLKFB),
-                  .CLK0(CLK0)
+                  .STATUS(DCM_STATUS)
                 );
+                
+assign DCM_RST=0;
 
+/*
 dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
                               .Q(DCM_RST)
                            );
-                           
-assign CLKFB = CLK0;
-
+*/
 //wire DCM_FX_STOPPED = DCM_STATUS[2];
 //always @(posedge CLKIN) begin
 //   if(DCM_FX_STOPPED)
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index ec3d7c8..86f2ad4 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -89,16 +89,18 @@
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main"/>
     <property xil_pn:name="Map Effort Level" xil_pn:value="High"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="High"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Balanced"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true"/>
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes"/>
     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="Package" xil_pn:value="tq144"/>
-    <property xil_pn:name="Perform Timing-Driven Packing" xil_pn:value="true"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
     <property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="Yes"/>
     <property xil_pn:name="Register Duplication" xil_pn:value="On"/>
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="5"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
@@ -110,6 +112,7 @@
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes/smartxplorer_results/run9/maptimingextraeffortct3.xds"/>
     <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
   </properties>