Firmware: add test suite
This commit is contained in:
ikari
528
src/tests/fpga_spi.c
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528
src/tests/fpga_spi.c
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/* sd2snes - SD card based universal cartridge for the SNES
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Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
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AVR firmware portion
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Inspired by and based on code from sd2iec, written by Ingo Korb et al.
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See sdcard.c|h, config.h.
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FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
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see ff.c|h.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License only.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
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*/
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/*
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SPI commands
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cmd param function
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=============================================
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0t bbhhll set address to 0xbbhhll
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t = target
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target: 0 = RAM
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1 = MSU Audio buffer
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2 = MSU Data buffer
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targets 1 & 2 only require 2 address bytes to
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be written.
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10 bbhhll set SNES input address mask to 0xbbhhll
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20 bbhhll set SRAM address mask to 0xbbhhll
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3m - set mapper to m
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0=HiROM, 1=LoROM, 2=ExHiROM, 6=SF96, 7=Menu
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4s - trigger SD DMA (512b from SD to memory)
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s: Bit 2 = partial, Bit 1:0 = target
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target: see above
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60 sssseeee set SD DMA partial transfer start+end
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ssss = start offset (msb first)
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eeee = end offset (msb first)
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8p - read (RAM only)
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p: 0 = no increment after read
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8 = increment after read
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9p {xx}* write xx
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p: i-tt
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tt = target (see above)
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i = increment (see above)
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E0 ssrr set MSU-1 status register (=FPGA status [7:0])
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ss = bits to set in status register (1=set)
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rr = bits to reset in status register (1=reset)
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E1 - pause DAC
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E2 - resume/play DAC
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E3 - reset DAC playback pointer (0)
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E4 hhll set MSU read pointer
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E5 tt{7} set RTC (SPC7110 format + 1000s of year,
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nibbles packed)
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eg 0x20111210094816 is 2011-12-10, 9:48:16
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E6 ssrr set/reset BS-X status register [7:0]
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E7 - reset SRTC state
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E8 - reset DSP program and data ROM write pointers
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E9 hhmmllxxxx write+incr. DSP program ROM (xxxx=dummy writes)
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EA hhllxxxx write+incr. DSP data ROM (xxxx=dummy writes)
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EB - put DSP into reset
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EC - release DSP from reset
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ED - set feature enable bits (see below)
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EE - select memory (0: ROM (PSRAM), 1: RAM (SRAM))
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F0 - receive test token (to see if FPGA is alive)
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F1 - receive status (16bit, MSB first), see below
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F2 - get MSU data address (32bit, MSB first)
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F3 - get MSU audio track no. (16bit, MSB first)
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F4 - get MSU volume (8bit)
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FE - get SNES master clock frequency (32bit, MSB first)
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measured 1x/sec
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FF {xx}* echo (returns the sent data in the next byte)
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FPGA status word:
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bit function
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==========================================================================
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15 SD DMA busy (0=idle, 1=busy)
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14 DAC read pointer MSB
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13 MSU read pointer MSB
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12 [TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0]
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11 reserved (0)
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10 reserved (0)
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9 reserved (0)
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8 reserved (0)
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7 reserved (0)
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6 reserved (0)
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5 MSU1 Audio request from SNES
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4 MSU1 Data request from SNES
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3 reserved (0)
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2 MSU1 Audio control status: 0=no repeat, 1=repeat
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1 MSU1 Audio control status: 0=pause, 1=play
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0 MSU1 Audio control request
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FPGA feature enable bits:
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bit function
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==========================================================================
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7 -
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6 -
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5 -
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4 -
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3 enable MSU1 registers
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2 enable SRTC registers
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1 enable ST0010 mapping
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0 enable DSPx mapping
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*/
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#include <arm/NXP/LPC17xx/LPC17xx.h>
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#include "bits.h"
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#include "fpga.h"
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#include "config.h"
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#include "uart.h"
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#include "spi.h"
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#include "fpga_spi.h"
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#include "timer.h"
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#include "sdnative.h"
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void fpga_spi_init(void) {
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spi_init(SPI_SPEED_FAST);
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BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
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}
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void set_msu_addr(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x02);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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FPGA_DESELECT();
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}
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void set_dac_addr(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x01);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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FPGA_DESELECT();
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}
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void set_mcu_addr(uint32_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x00);
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FPGA_TX_BYTE((address>>16)&0xff);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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FPGA_DESELECT();
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}
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void set_saveram_mask(uint32_t mask) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x20);
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FPGA_TX_BYTE((mask>>16)&0xff);
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FPGA_TX_BYTE((mask>>8)&0xff);
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FPGA_TX_BYTE((mask)&0xff);
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FPGA_DESELECT();
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}
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void set_rom_mask(uint32_t mask) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x10);
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FPGA_TX_BYTE((mask>>16)&0xff);
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FPGA_TX_BYTE((mask>>8)&0xff);
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FPGA_TX_BYTE((mask)&0xff);
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FPGA_DESELECT();
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}
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void set_mapper(uint8_t val) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x30 | (val & 0x0f));
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FPGA_DESELECT();
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}
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uint8_t fpga_test() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF0); /* TEST */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint8_t result = FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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}
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uint16_t fpga_status() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF1); /* STATUS */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint16_t result = (FPGA_RX_BYTE()) << 8;
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result |= FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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}
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void fpga_set_sddma_range(uint16_t start, uint16_t end) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x60); /* DMA_RANGE */
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FPGA_TX_BYTE(start>>8);
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FPGA_TX_BYTE(start&0xff);
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FPGA_TX_BYTE(end>>8);
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FPGA_TX_BYTE(end&0xff);
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//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
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FPGA_DESELECT();
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}
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void fpga_sddma(uint8_t tgt, uint8_t partial) {
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uint32_t test = 0;
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uint8_t status = 0;
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BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
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FPGA_SELECT();
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FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */
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FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
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//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
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FPGA_DESELECT();
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF1); /* STATUS */
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FPGA_TX_BYTE(0x00); /* dummy */
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DBG_SD printf("FPGA DMA request sent, wait for completion...");
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while((status=FPGA_RX_BYTE()) & 0x80) {
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FPGA_RX_BYTE(); /* eat the 2nd status byte */
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test++;
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}
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DBG_SD printf("...complete\n");
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FPGA_DESELECT();
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if(test<5)printf("loopy: %ld %02x\n", test, status);
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BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
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}
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void set_dac_vol(uint8_t volume) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x50);
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FPGA_TX_BYTE(volume);
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FPGA_TX_BYTE(0x00); /* latch rise */
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FPGA_TX_BYTE(0x00); /* latch fall */
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FPGA_DESELECT();
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}
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void dac_play() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe2);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void dac_pause() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe1);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void dac_reset() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe3);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void msu_reset(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe4);
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FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
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FPGA_TX_BYTE(address & 0xff); /* address lo */
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void set_msu_status(uint8_t set, uint8_t reset) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe0);
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FPGA_TX_BYTE(set);
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FPGA_TX_BYTE(reset);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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uint8_t get_msu_volume() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint8_t result = FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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}
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uint16_t get_msu_track() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint16_t result = (FPGA_RX_BYTE()) << 8;
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result |= FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_msu_offset() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_romselclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF7);
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_cpuclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF8);
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_readclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF9);
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_writeclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFA); /* GET_SYSCLK */
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_pardclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFB); /* GET_SYSCLK */
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_pawrclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFC); /* GET_SYSCLK */
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_refreshclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFD); /* GET_SYSCLK */
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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uint32_t get_snes_sysclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
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FPGA_TX_BYTE(0x00); /* dummy */
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FPGA_TX_BYTE(0x00); /* dummy */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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result |= (FPGA_RX_BYTE());
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FPGA_DESELECT();
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return result;
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}
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void set_bsx_regs(uint8_t set, uint8_t reset) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe6);
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FPGA_TX_BYTE(set);
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FPGA_TX_BYTE(reset);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void set_fpga_time(uint64_t time) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe5);
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FPGA_TX_BYTE((time >> 48) & 0xff);
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FPGA_TX_BYTE((time >> 40) & 0xff);
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FPGA_TX_BYTE((time >> 32) & 0xff);
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FPGA_TX_BYTE((time >> 24) & 0xff);
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FPGA_TX_BYTE((time >> 16) & 0xff);
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FPGA_TX_BYTE((time >> 8) & 0xff);
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FPGA_TX_BYTE(time & 0xff);
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FPGA_TX_BYTE(0x00);
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FPGA_DESELECT();
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}
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void fpga_reset_srtc_state() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe7);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_reset_dspx_addr() {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xe8);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_write_bram_data(uint8_t data) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xe9);
|
||||
FPGA_TX_BYTE(data);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_write_dspx_dat(uint16_t data) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xea);
|
||||
FPGA_TX_BYTE((data>>8)&0xff);
|
||||
FPGA_TX_BYTE((data)&0xff);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_dspx_reset(uint8_t reset) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(reset ? 0xeb : 0xec);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_set_features(uint8_t feat) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xed);
|
||||
FPGA_TX_BYTE(feat);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_select_mem(uint8_t unit) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xee);
|
||||
FPGA_TX_BYTE(unit);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
void fpga_set_bram_addr(uint16_t addr) {
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xe8);
|
||||
FPGA_TX_BYTE((addr>>8)&0xff);
|
||||
FPGA_TX_BYTE((addr)&0xff);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
}
|
||||
|
||||
uint8_t fpga_read_bram_data() {
|
||||
uint8_t data;
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0xf5);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
data = FPGA_RX_BYTE();
|
||||
FPGA_TX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
return data;
|
||||
}
|
||||
Reference in New Issue
Block a user