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clean up AVR code(deprecated), kicad libs, pcb WIP

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This commit is contained in:
ikari 2010-03-25 00:16:44 +01:00
parent 42082bd2ac
commit 0c87b69aa1
29 changed files with 6498 additions and 2560 deletions
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20
cic/snescic-key.asm
View File

@ -4,7 +4,8 @@ processor p12f629
; --------------------------------------------------------------------- ; ---------------------------------------------------------------------
; SNES CIC clone for PIC Microcontroller (key mode only) ; SNES CIC clone for PIC Microcontroller (key mode only)
; ;
; Copyright (C) 2010 by Maximilian Rehkopf <otakon@gmx.net> ; Copyright (C) 2010 by Maximilian Rehkopf (ikari_01) <otakon@gmx.net>
; This software is part of the sd2snes project.
; ;
; This program is free software; you can redistribute it and/or modify ; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by ; it under the terms of the GNU General Public License as published by
@ -25,18 +26,22 @@ processor p12f629
; ;
; ,---_---. ; ,---_---.
; +5V (27,58) [16] |1 8| GND (5,36) [8] ; +5V (27,58) [16] |1 8| GND (5,36) [8]
; CIC clk (56) [6] |2 7| CIC data i/o 0 (55) [1] ; CIC clk (56) [6] |2 7| CIC data i/o 0 (55) [2]
; status out |3 6| CIC data i/o 1 (24) [2] ; status out |3 6| CIC data i/o 1 (24) [1]
; nc |4 5| CIC slave reset (25) [7] ; nc |4 5| CIC slave reset (25) [7]
; `-------' ; `-------'
; ;
; ;
; status out can be connected to a LED. It indicates: ; Status out can be connected to a LED. It indicates:
; ;
; state | output ; state | output
; -------------------------+-------------------- ; -------------------------+--------------------
; OK (normal operation) | high ; OK (normal operation) | high
; error (unlock failed) | alternating @~2.5Hz ; error (unlock failed) | alternating @~2.5Hz
; no CIC (modded SNES) | low
;
; In case lockout fails, the region is switched automatically and
; will be used after the next reset.
; ;
; memory usage: ; memory usage:
; ;
@ -87,10 +92,13 @@ init
banksel TRISIO banksel TRISIO
movlw 0x2d ; in out in in out in movlw 0x2d ; in out in in out in
movwf TRISIO movwf TRISIO
movlw 0x80 ; 0x00 for pullups movlw 0x24 ; pullups for reset+clk to avoid errors when no CIC in host
movwf WPU
movlw 0x00 ; 0x80 for global pullup disable
movwf OPTION_REG movwf OPTION_REG
banksel GPIO banksel GPIO
bsf GPIO, 4 ; LED on bcf GPIO, 4 ; LED off
idle idle
goto idle ; wait for interrupt from lock goto idle ; wait for interrupt from lock

113
pcb/kicad/fpga.bak
View File

@ -1,5 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 02:04:56 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:32:19 PM CET
LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,10 +34,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:sd2snes-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A3 16535 11700
Sheet 3 5 Sheet 4 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -48,107 +51,13 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Connection ~ 11050 2500
Wire Wire Line
10800 2500 11050 2500
Connection ~ 11050 2700
Wire Wire Line
10800 2700 11050 2700
Connection ~ 11050 2900
Wire Wire Line
10800 2900 11050 2900
Connection ~ 11050 3100
Wire Wire Line
10800 3100 11050 3100
Connection ~ 11050 3300
Wire Wire Line
10800 3300 11050 3300
Connection ~ 11050 3500
Wire Wire Line
10800 3500 11050 3500
Connection ~ 11050 3700
Wire Wire Line
10800 3700 11050 3700
Connection ~ 11050 3900
Wire Wire Line
10800 3900 11050 3900
Connection ~ 11050 4100
Wire Wire Line
10800 4100 11050 4100
Connection ~ 11050 4300
Wire Wire Line
10800 4300 11050 4300
Connection ~ 11050 4500
Wire Wire Line
10800 4500 11050 4500
Connection ~ 11050 4700
Wire Wire Line
10800 4700 11050 4700
Connection ~ 11050 4900
Wire Wire Line
10800 4900 11050 4900
Connection ~ 11050 5100
Wire Wire Line
10800 5100 11050 5100
Wire Wire Line
10800 2400 11050 2400
Wire Wire Line
11050 2400 11050 5300
Wire Wire Line
11050 5000 10800 5000
Connection ~ 11050 5000
Wire Wire Line
11050 4800 10800 4800
Connection ~ 11050 4800
Wire Wire Line
11050 4600 10800 4600
Connection ~ 11050 4600
Wire Wire Line
11050 4400 10800 4400
Connection ~ 11050 4400
Wire Wire Line
11050 4200 10800 4200
Connection ~ 11050 4200
Wire Wire Line
11050 4000 10800 4000
Connection ~ 11050 4000
Wire Wire Line
11050 3800 10800 3800
Connection ~ 11050 3800
Wire Wire Line
11050 3600 10800 3600
Connection ~ 11050 3600
Wire Wire Line
11050 3400 10800 3400
Connection ~ 11050 3400
Wire Wire Line
11050 3200 10800 3200
Connection ~ 11050 3200
Wire Wire Line
11050 3000 10800 3000
Connection ~ 11050 3000
Wire Wire Line
11050 2800 10800 2800
Connection ~ 11050 2800
Wire Wire Line
11050 2600 10800 2600
Connection ~ 11050 2600
$Comp
L GND #PWR013
U 1 1 4B6ED488
P 11050 5300
F 0 "#PWR013" H 11050 5300 30 0001 C CNN
F 1 "GND" H 11050 5230 30 0001 C CNN
1 11050 5300
1 0 0 -1
$EndComp
$Comp $Comp
L XC3S400-PQ208 U4 L XC3S400-PQ208 U4
U 1 1 4B6E1931 U 1 1 4B6E1931
P 6000 3850 P 8350 5600
F 0 "U4" H 7650 8450 60 0000 L CNN F 0 "U4" H 10000 10200 60 0000 L CNN
F 1 "XC3S400-PQ208" H 7700 -800 60 0000 L CNN F 1 "XC3S400-PQ208" H 10050 950 60 0000 L CNN
1 6000 3850 1 8350 5600
0 -1 -1 0 0 -1 -1 0
$EndComp $EndComp
$EndSCHEMATC $EndSCHEMATC

113
pcb/kicad/fpga.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 11:25:34 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:33:24 PM CET
LIBS:sd2snes-cache LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
@ -35,11 +35,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:testsw LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:cs4344
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A3 16535 11700
Sheet 3 5 Sheet 4 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -49,107 +52,13 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Connection ~ 11050 2500
Wire Wire Line
10800 2500 11050 2500
Connection ~ 11050 2700
Wire Wire Line
10800 2700 11050 2700
Connection ~ 11050 2900
Wire Wire Line
10800 2900 11050 2900
Connection ~ 11050 3100
Wire Wire Line
10800 3100 11050 3100
Connection ~ 11050 3300
Wire Wire Line
10800 3300 11050 3300
Connection ~ 11050 3500
Wire Wire Line
10800 3500 11050 3500
Connection ~ 11050 3700
Wire Wire Line
10800 3700 11050 3700
Connection ~ 11050 3900
Wire Wire Line
10800 3900 11050 3900
Connection ~ 11050 4100
Wire Wire Line
10800 4100 11050 4100
Connection ~ 11050 4300
Wire Wire Line
10800 4300 11050 4300
Connection ~ 11050 4500
Wire Wire Line
10800 4500 11050 4500
Connection ~ 11050 4700
Wire Wire Line
10800 4700 11050 4700
Connection ~ 11050 4900
Wire Wire Line
10800 4900 11050 4900
Connection ~ 11050 5100
Wire Wire Line
10800 5100 11050 5100
Wire Wire Line
10800 2400 11050 2400
Wire Wire Line
11050 2400 11050 5300
Wire Wire Line
11050 5000 10800 5000
Connection ~ 11050 5000
Wire Wire Line
11050 4800 10800 4800
Connection ~ 11050 4800
Wire Wire Line
11050 4600 10800 4600
Connection ~ 11050 4600
Wire Wire Line
11050 4400 10800 4400
Connection ~ 11050 4400
Wire Wire Line
11050 4200 10800 4200
Connection ~ 11050 4200
Wire Wire Line
11050 4000 10800 4000
Connection ~ 11050 4000
Wire Wire Line
11050 3800 10800 3800
Connection ~ 11050 3800
Wire Wire Line
11050 3600 10800 3600
Connection ~ 11050 3600
Wire Wire Line
11050 3400 10800 3400
Connection ~ 11050 3400
Wire Wire Line
11050 3200 10800 3200
Connection ~ 11050 3200
Wire Wire Line
11050 3000 10800 3000
Connection ~ 11050 3000
Wire Wire Line
11050 2800 10800 2800
Connection ~ 11050 2800
Wire Wire Line
11050 2600 10800 2600
Connection ~ 11050 2600
$Comp
L GND #PWR013
U 1 1 4B6ED488
P 11050 5300
F 0 "#PWR013" H 11050 5300 30 0001 C CNN
F 1 "GND" H 11050 5230 30 0001 C CNN
1 11050 5300
1 0 0 -1
$EndComp
$Comp $Comp
L XC3S400-PQ208 U4 L XC3S400-PQ208 U4
U 1 1 4B6E1931 U 1 1 4B6E1931
P 6000 3850 P 8350 5600
F 0 "U4" H 7650 8450 60 0000 L CNN F 0 "U4" H 10000 10200 60 0000 L CNN
F 1 "XC3S400-PQ208" H 7700 -800 60 0000 L CNN F 1 "XC3S400-PQ208" H 10050 950 60 0000 L CNN
1 6000 3850 1 8350 5600
0 -1 -1 0 0 -1 -1 0
$EndComp $EndComp
$EndSCHEMATC $EndSCHEMATC

1018
pcb/kicad/libs/mypackages.bak
View File

File diff suppressed because it is too large Load Diff

2
pcb/kicad/libs/mypackages.mdc
View File

@ -1,4 +1,4 @@
PCBNEW-LibDoc----V1 Mon 08 Feb 2010 11:27:02 PM CET PCBNEW-LibDoc----V1 Wed 24 Mar 2010 11:35:30 PM CET
# #
$MODULE PQFP208_ALTPADS $MODULE PQFP208_ALTPADS
Li PQFP208_ALTPADS Li PQFP208_ALTPADS

1099
pcb/kicad/libs/mypackages.mod
View File

File diff suppressed because it is too large Load Diff

37
pcb/kicad/libs/sdcard.bak
View File

@ -1,39 +1,4 @@
PCBNEW-LibModule-V1 Tue 09 Feb 2010 09:51:59 PM CET PCBNEW-LibModule-V1 Wed 24 Mar 2010 10:52:25 PM CET
$INDEX $INDEX
JAE-SG5S009V1A
$EndINDEX $EndINDEX
$MODULE JAE-SG5S009V1A
Po 0 0 0 15 4B71CAE8 00000000 ~~
Li JAE-SG5S009V1A
Sc 00000000
AR
Op 0 0 0
T0 0 0 300 300 0 60 N V 21 N"JAE-SG5S009V1A"
T1 0 0 300 300 0 60 N V 21 N"VAL**"
DC 4764 5772 4945 5772 40 28
DC -4764 5772 -4583 5772 40 28
$PAD
Sh "H1" C 354 354 0 0 0
Dr 0 0 0
At STD N 00000000
Ne 0 ""
Po -4764 5772
$EndPAD
$PAD
Sh "H2" C 354 354 0 0 0
Dr 0 0 0
At STD N 00000000
Ne 0 ""
Po 4764 5772
$EndPAD
$PAD
Sh "Rest" R 354 748 0 0 0
Dr 0 0 0
At SMD N 00000000
Ne 0 ""
Po -157 2654
.SolderMask 59
.LocalClearance 59
$EndPAD
$EndMODULE JAE-SG5S009V1A
$EndLIBRARY $EndLIBRARY

2
pcb/kicad/libs/sdcard.mdc
View File

@ -1,3 +1,3 @@
PCBNEW-LibDoc----V1 Tue 09 Feb 2010 10:09:22 PM CET PCBNEW-LibDoc----V1 Wed 24 Mar 2010 10:52:54 PM CET
# #
$EndLIBDOC $EndLIBDOC

137
pcb/kicad/libs/sdcard.mod
View File

@ -1,41 +1,134 @@
PCBNEW-LibModule-V1 Tue 09 Feb 2010 10:09:22 PM CET PCBNEW-LibModule-V1 Wed 24 Mar 2010 10:52:54 PM CET
$INDEX $INDEX
JAE-SG5S009V1A SD-RSMT-2-MQ-WF
$EndINDEX $EndINDEX
$MODULE JAE-SG5S009V1A $MODULE SD-RSMT-2-MQ-WF
Po 0 0 0 15 4B71CEFE 00000000 ~~ Po 0 0 0 15 4B841847 00000000 ~~
Li JAE-SG5S009V1A Li SD-RSMT-2-MQ-WF
Sc 00000000 Sc 00000000
AR AR
Op 0 0 0 Op 0 0 0
T0 0 0 300 300 0 60 N V 21 N"JAE-SG5S009V1A" T0 0 4500 600 600 0 120 N V 21 N"SD-RSMT-2-MQ-WF"
T1 0 0 300 300 0 60 N V 21 N"VAL**" T1 0 6000 600 600 0 120 N V 21 N"VAL**"
DC 4764 5772 4945 5772 40 28 DS -4161 0 -4142 0 150 21
DC -4764 5772 -4583 5772 40 28 DS 5512 0 3976 0 150 21
DS 2992 0 3406 0 150 21
DS 2008 0 2421 0 150 21
DS 1024 0 1437 0 150 21
DS 39 0 453 0 150 21
DS -945 0 -531 0 150 21
DS -1929 0 -1516 0 150 21
DS -2913 0 -2500 0 150 21
DS -3583 0 -3484 0 150 21
DS -4626 0 -4606 0 150 21
DS -5512 0 -5079 0 150 21
DS 5512 12008 -5512 12008 150 21
DS -5512 12008 -5512 0 150 21
DS 5512 0 5512 12008 150 21
$PAD $PAD
Sh "H1" C 354 354 0 0 0 Sh "GND2" R 787 1181 0 0 0
Dr 0 0 0 Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 6110 10630
$EndPAD
$PAD
Sh "GND1" R 787 1181 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -6110 10630
$EndPAD
$PAD
Sh "" C 512 512 0 0 0
Dr 433 0 0
At STD N 00000000 At STD N 00000000
Ne 0 "" Ne 0 ""
Po -4764 5772 Po -4528 807
.SolderMask 1575
.LocalClearance 1575
$EndPAD $EndPAD
$PAD $PAD
Sh "H2" C 354 354 0 0 0 Sh "" C 748 748 0 0 0
Dr 0 0 0 Dr 630 0 0
At STD N 00000000 At STD N 00000000
Ne 0 "" Ne 0 ""
Po 4764 5772 Po 3740 807
$EndPAD $EndPAD
$PAD $PAD
Sh "Rest" R 354 748 0 0 0 Sh "3" R 394 787 0 0 0
Dr 0 0 0 Dr 0 0 0
At SMD N 00000000 At SMD N 00888000
Ne 0 "" Ne 0 ""
Po -157 2654 Po 740 -394
.SolderMask 59
.LocalClearance 59
$EndPAD $EndPAD
$EndMODULE JAE-SG5S009V1A $PAD
Sh "2" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1724 -394
$EndPAD
$PAD
Sh "1" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 2709 -394
$EndPAD
$PAD
Sh "9" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 3693 -394
$EndPAD
$PAD
Sh "DT" R 276 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -4378 -394
$EndPAD
$PAD
Sh "8" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -3866 -394
$EndPAD
$PAD
Sh "7" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -3197 -394
$EndPAD
$PAD
Sh "5" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1228 -394
$EndPAD
$PAD
Sh "6" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -2213 -394
$EndPAD
$PAD
Sh "4" R 394 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -244 -394
$EndPAD
$PAD
Sh "WP" R 276 787 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -4850 -394
$EndPAD
$EndMODULE SD-RSMT-2-MQ-WF
$EndLIBRARY $EndLIBRARY

611
pcb/kicad/libs/snescart.bak
View File

@ -1,75 +1,536 @@
EESchema-LIBRARY Version 2.3 Date: Sat 06 Feb 2010 04:49:32 PM CET PCBNEW-LibModule-V1 Sat 06 Feb 2010 05:04:41 PM CET
# $INDEX
# SNESCART_EXT SNESCART_EXT
# $EndINDEX
DEF SNESCART_EXT J 0 40 Y Y 1 F N $MODULE SNESCART_EXT
F0 "J" -450 1900 60 H V C CNN Po 0 0 0 15 4B6D92ED 00000000 ~~
F1 "SNESCART_EXT" 500 -2000 60 H V C CNN Li SNESCART_EXT
DRAW Sc 00000000
S -500 1800 500 -1900 0 1 0 N AR
X SYS_CLK 1 -800 -1600 300 R 50 50 1 1 O C Op 0 0 0
X EXPAND 2 800 -800 300 L 50 50 1 1 O .SolderMask 4
X PA6 3 800 0 300 L 50 50 1 1 O .SolderPaste -4
X /PARD 4 800 -300 300 L 50 50 1 1 O T0 -4134 2953 600 600 0 120 N V 21 N"J?"
X GND 5 -50 -2200 300 U 50 50 1 1 W T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT"
X A11 6 -800 400 300 R 50 50 1 1 O DA 17441 1693 17717 1693 900 40 28
X A10 7 -800 500 300 R 50 50 1 1 O DA 13071 1693 13071 1969 900 40 28
X A9 8 -800 600 300 R 50 50 1 1 O DA 11535 1693 11811 1693 900 40 28
X A8 9 -800 700 300 R 50 50 1 1 O DS 18110 -29331 5906 -29331 40 28
X A7 10 -800 800 300 R 50 50 1 1 O DS 5906 -29331 5906 -30709 40 28
X D1 20 800 1400 300 L 50 50 1 1 B DS 5906 -30709 -5709 -30709 40 28
X PA4 30 800 200 300 L 50 50 1 1 O DS -5709 -30709 -5709 -29331 40 28
X A15 40 -800 0 300 R 50 50 1 1 O DS -5709 -29331 -19488 -29331 40 28
X D4 50 800 1100 300 L 50 50 1 1 B DS -19488 -29331 -19488 -27756 40 28
X PA3 60 800 300 300 L 50 50 1 1 O DS -19488 -27756 -18504 -27756 40 28
X A6 11 -800 900 300 R 50 50 1 1 O DS -18504 -27756 -18504 -27087 40 28
X D2 21 800 1300 300 L 50 50 1 1 B DS -18504 -27087 -19488 -27087 40 28
X LINE_L 31 800 -1500 300 L 50 50 1 1 I DS -19488 -27087 -19488 -25118 40 28
X A16 41 -800 -100 300 R 50 50 1 1 O DS -19488 -25118 -20039 -25118 40 28
X D5 51 800 1000 300 L 50 50 1 1 B DS -20039 -25118 -20039 -4803 40 28
X PA5 61 800 100 300 L 50 50 1 1 O DS -20039 -4803 -18465 -4803 40 28
X A5 12 -800 1000 300 R 50 50 1 1 O DS -18465 -4803 -18465 -4016 40 28
X D3 22 800 1200 300 L 50 50 1 1 B DS -18465 -4016 -19449 -4016 40 28
X /WRAM 32 800 -600 300 L 50 50 1 1 O DS -19449 -4016 -19449 -2205 40 28
X A17 42 -800 -200 300 R 50 50 1 1 O DS -19449 -2205 -17717 -2205 40 28
X D6 52 800 900 300 L 50 50 1 1 B DS -17717 -2205 -17717 -2165 40 28
X LINE_R 62 800 -1600 300 L 50 50 1 1 I DS 19921 -25079 19291 -25079 40 28
X A4 13 -800 1100 300 R 50 50 1 1 O DS 19291 -25079 19291 -27087 40 28
X /RD 23 -800 -1000 300 R 50 50 1 1 O DS 19291 -27087 18307 -27087 40 28
X REFRESH 33 800 -700 300 L 50 50 1 1 O DS 18307 -27087 18307 -27756 40 28
X A18 43 -800 -300 300 R 50 50 1 1 O DS 18307 -27756 19291 -27756 40 28
X D7 53 800 800 300 L 50 50 1 1 B DS 19291 -27756 19291 -29331 40 28
X A3 14 -800 1200 300 R 50 50 1 1 O DS 19291 -29331 18110 -29331 40 28
X CIC_P1_DOUT 24 800 -1000 300 L 50 50 1 1 I DS 19921 -6890 19921 -25079 40 28
X PA7 34 800 -100 300 L 50 50 1 1 O DS 17717 1693 17717 -2165 40 28
X A19 44 -800 -400 300 R 50 50 1 1 O DS 17717 -2165 17717 -2205 40 28
X /WR 54 -800 -1100 300 R 50 50 1 1 O DS 17717 -2205 19921 -2205 40 28
X A2 15 -800 1300 300 R 50 50 1 1 O DS 19921 -2205 19921 -4094 40 28
X CIC_P7_RESET 25 800 -1300 300 L 50 50 1 1 O DS 19921 -4094 19291 -4094 40 28
X /PAWR 35 800 -400 300 L 50 50 1 1 O DS 19291 -4094 19291 -6102 40 28
X A20 45 -800 -500 300 R 50 50 1 1 O DS 19291 -6102 18307 -6102 40 28
X CIC_P2_DIN 55 800 -1100 300 L 50 50 1 1 O DS 18307 -6102 18307 -6890 40 28
X A1 16 -800 1400 300 R 50 50 1 1 O DS 18307 -6890 19921 -6890 40 28
X /RESET 26 -800 -1400 300 R 50 50 1 1 B DS 13071 1969 17441 1969 40 28
X GND 36 50 -2200 300 U 50 50 1 1 W DS 11811 1693 11811 -2480 40 28
X A21 46 -800 -600 300 R 50 50 1 1 O DS 11811 -2480 12795 -2480 40 28
X CIC_P6_CLK 56 800 -1200 300 L 50 50 1 1 O C DS 12795 -2480 12795 1693 40 28
X A0 17 -800 1500 300 R 50 50 1 1 O DA -11535 1693 -11535 1969 900 40 28
X VCC 27 -50 2100 300 D 50 50 1 1 W DA -13071 1693 -12795 1693 900 40 28
X A12 37 -800 300 300 R 50 50 1 1 O DA -17441 1693 -17441 1969 900 40 28
X A22 47 -800 -700 300 R 50 50 1 1 O DS -17717 1693 -17717 -2165 40 28
X CPU_CLK 57 -800 -1500 300 R 50 50 1 1 O DS -13071 1969 -17441 1969 40 28
X /IRQ 18 -800 -1200 300 R 50 50 1 1 B DS -11811 1693 -11811 -2480 40 28
X PA0 28 800 600 300 L 50 50 1 1 O DS -11811 -2480 -12795 -2480 40 28
X A13 38 -800 200 300 R 50 50 1 1 O DS -12795 -2480 -12795 1693 40 28
X A23 48 -800 -800 300 R 50 50 1 1 O DS -11535 1969 11535 1969 40 28
X VCC 58 50 2100 300 D 50 50 1 1 W $PAD
X D0 19 800 1500 300 L 50 50 1 1 B Sh "1" R 591 2756 0 0 0
X PA2 29 800 400 300 L 50 50 1 1 O Dr 0 0 0
X A14 39 -800 100 300 R 50 50 1 1 O At CONN N 00008000
X /ROMSEL 49 -800 -1300 300 R 50 50 1 1 O Ne 0 ""
X PA1 59 800 500 300 L 50 50 1 1 O Po -16732 197
ENDDRAW $EndPAD
ENDDEF $PAD
# Sh "2" R 591 2756 0 0 0
#End Library Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -15748 197
$EndPAD
$PAD
Sh "3" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -14764 197
$EndPAD
$PAD
Sh "4" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -13780 197
$EndPAD
$PAD
Sh "5" R 787 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -10925 197
$EndPAD
$PAD
Sh "6" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -9843 197
$EndPAD
$PAD
Sh "7" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -8858 197
$EndPAD
$PAD
Sh "8" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -7874 197
$EndPAD
$PAD
Sh "9" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -6890 197
$EndPAD
$PAD
Sh "10" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -5906 197
$EndPAD
$PAD
Sh "11" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -4921 197
$EndPAD
$PAD
Sh "12" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -3937 197
$EndPAD
$PAD
Sh "13" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -2953 197
$EndPAD
$PAD
Sh "14" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -1969 197
$EndPAD
$PAD
Sh "15" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po -984 197
$EndPAD
$PAD
Sh "16" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 0 197
$EndPAD
$PAD
Sh "17" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 984 197
$EndPAD
$PAD
Sh "18" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 1969 197
$EndPAD
$PAD
Sh "19" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 2953 197
$EndPAD
$PAD
Sh "20" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 3937 197
$EndPAD
$PAD
Sh "21" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 4921 197
$EndPAD
$PAD
Sh "22" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 5906 197
$EndPAD
$PAD
Sh "23" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 6890 197
$EndPAD
$PAD
Sh "24" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 7874 197
$EndPAD
$PAD
Sh "25" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 8858 197
$EndPAD
$PAD
Sh "26" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 9843 197
$EndPAD
$PAD
Sh "27" R 787 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 10925 197
$EndPAD
$PAD
Sh "28" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 13780 197
$EndPAD
$PAD
Sh "29" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 14764 197
$EndPAD
$PAD
Sh "30" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 15748 197
$EndPAD
$PAD
Sh "31" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00008000
Ne 0 ""
Po 16732 197
$EndPAD
$PAD
Sh "32" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -16732 197
$EndPAD
$PAD
Sh "33" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -15748 197
$EndPAD
$PAD
Sh "34" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -14764 197
$EndPAD
$PAD
Sh "35" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -13780 197
$EndPAD
$PAD
Sh "36" R 787 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -10925 197
$EndPAD
$PAD
Sh "37" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -9843 197
$EndPAD
$PAD
Sh "38" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -8858 197
$EndPAD
$PAD
Sh "39" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -7874 197
$EndPAD
$PAD
Sh "40" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -6890 197
$EndPAD
$PAD
Sh "41" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -5906 197
$EndPAD
$PAD
Sh "42" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -4921 197
$EndPAD
$PAD
Sh "43" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -3937 197
$EndPAD
$PAD
Sh "44" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -2953 197
$EndPAD
$PAD
Sh "45" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -1969 197
$EndPAD
$PAD
Sh "46" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po -984 197
$EndPAD
$PAD
Sh "47" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 0 197
$EndPAD
$PAD
Sh "48" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 984 197
$EndPAD
$PAD
Sh "49" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 1969 197
$EndPAD
$PAD
Sh "50" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 2953 197
$EndPAD
$PAD
Sh "51" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 3937 197
$EndPAD
$PAD
Sh "52" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 4921 197
$EndPAD
$PAD
Sh "53" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 5906 197
$EndPAD
$PAD
Sh "54" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 6890 197
$EndPAD
$PAD
Sh "55" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 7874 197
$EndPAD
$PAD
Sh "56" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 8858 197
$EndPAD
$PAD
Sh "57" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 9843 197
$EndPAD
$PAD
Sh "58" R 787 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 10925 197
$EndPAD
$PAD
Sh "59" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 13780 197
$EndPAD
$PAD
Sh "60" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 14764 197
$EndPAD
$PAD
Sh "61" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 15748 197
$EndPAD
$PAD
Sh "62" R 591 2756 0 0 0
Dr 0 0 0
At CONN N 00000001
Ne 0 ""
Po 16732 197
$EndPAD
$PAD
Sh "" R 4921 3150 0 0 0
Dr 0 0 0
At CONN N 00C00000
Ne 0 ""
Po -15256 394
$EndPAD
$PAD
Sh "" R 4921 3150 0 0 0
Dr 0 0 0
At CONN N 00C00000
Ne 0 ""
Po 15256 394
$EndPAD
$PAD
Sh "" R 23622 3150 0 0 0
Dr 0 0 0
At CONN N 00C00000
Ne 0 ""
Po 0 394
$EndPAD
$PAD
Sh "" R 2362 1969 0 0 0
Dr 0 0 0
At CONN N 00400000
Ne 0 ""
Po -10945 -3819
$EndPAD
$PAD
Sh "" R 2283 2362 0 0 0
Dr 0 0 0
At CONN N 00400000
Ne 0 ""
Po 14331 -3780
$EndPAD
$EndMODULE SNESCART_EXT
$EndLIBRARY

2
pcb/kicad/libs/snescart.mdc
View File

@ -1,3 +1,3 @@
PCBNEW-LibDoc----V1 Sat 06 Feb 2010 05:04:41 PM CET PCBNEW-LibDoc----V1 Wed 24 Mar 2010 11:07:41 PM CET
# #
$EndLIBDOC $EndLIBDOC

14
pcb/kicad/libs/snescart.mod
View File

@ -1,9 +1,9 @@
PCBNEW-LibModule-V1 Sat 06 Feb 2010 05:04:41 PM CET PCBNEW-LibModule-V1 Wed 24 Mar 2010 11:07:41 PM CET
$INDEX $INDEX
SNESCART_EXT SNESCART_EXT
$EndINDEX $EndINDEX
$MODULE SNESCART_EXT $MODULE SNESCART_EXT
Po 0 0 0 15 4B6D92ED 00000000 ~~ Po 0 0 0 15 4BAA8D25 00000000 ~~
Li SNESCART_EXT Li SNESCART_EXT
Sc 00000000 Sc 00000000
AR AR
@ -12,14 +12,16 @@ Op 0 0 0
.SolderPaste -4 .SolderPaste -4
T0 -4134 2953 600 600 0 120 N V 21 N"J?" T0 -4134 2953 600 600 0 120 N V 21 N"J?"
T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT" T1 0 2953 600 600 0 120 N V 21 N"SNESCART_EXT"
DS 6693 -29331 18110 -29331 40 28
DS 5906 -30709 6693 -30709 40 28
DS -6496 -30709 -5709 -30709 40 28
DS -19488 -29331 -6496 -29331 40 28
DA 17441 1693 17717 1693 900 40 28 DA 17441 1693 17717 1693 900 40 28
DA 13071 1693 13071 1969 900 40 28 DA 13071 1693 13071 1969 900 40 28
DA 11535 1693 11811 1693 900 40 28 DA 11535 1693 11811 1693 900 40 28
DS 18110 -29331 5906 -29331 40 28 DS 6693 -29331 6693 -30709 40 28
DS 5906 -29331 5906 -30709 40 28
DS 5906 -30709 -5709 -30709 40 28 DS 5906 -30709 -5709 -30709 40 28
DS -5709 -30709 -5709 -29331 40 28 DS -6496 -30709 -6496 -29331 40 28
DS -5709 -29331 -19488 -29331 40 28
DS -19488 -29331 -19488 -27756 40 28 DS -19488 -29331 -19488 -27756 40 28
DS -19488 -27756 -18504 -27756 40 28 DS -19488 -27756 -18504 -27756 40 28
DS -18504 -27756 -18504 -27087 40 28 DS -18504 -27756 -18504 -27087 40 28

26
pcb/kicad/mcu.bak
View File

@ -1,5 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 02:04:56 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:32:19 PM CET
LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,10 +34,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:sd2snes-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 2 5 Sheet 3 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -49,12 +52,21 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Comp $Comp
L SD_CARD J?
U 1 1 4BAA6A9C
P 8650 2500
F 0 "J?" H 8400 1950 60 0000 C CNN
F 1 "SD_CARD" H 8650 3000 60 0000 C CNN
1 8650 2500
1 0 0 -1
$EndComp
$Comp
L LPC1754 U11 L LPC1754 U11
U 1 1 4B6F321A U 1 1 4B6F321A
P 4650 3900 P 3900 3850
F 0 "U11" H 4650 3500 60 0000 C CNN F 0 "U11" H 3900 3450 60 0000 C CNN
F 1 "LPC1754" H 4650 3200 60 0000 C CNN F 1 "LPC1754" H 3900 3150 60 0000 C CNN
1 4650 3900 1 3900 3850
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$EndSCHEMATC $EndSCHEMATC

26
pcb/kicad/mcu.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 11:25:34 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:33:24 PM CET
LIBS:sd2snes-cache LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
@ -35,11 +35,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:testsw LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:cs4344
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 2 5 Sheet 3 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -50,12 +53,21 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Comp $Comp
L SD_CARD J?
U 1 1 4BAA6A9C
P 8650 2500
F 0 "J?" H 8400 1950 60 0000 C CNN
F 1 "SD_CARD" H 8650 3000 60 0000 C CNN
1 8650 2500
1 0 0 -1
$EndComp
$Comp
L LPC1754 U11 L LPC1754 U11
U 1 1 4B6F321A U 1 1 4B6F321A
P 4650 3900 P 3900 3850
F 0 "U11" H 4650 3500 60 0000 C CNN F 0 "U11" H 3900 3450 60 0000 C CNN
F 1 "LPC1754" H 4650 3200 60 0000 C CNN F 1 "LPC1754" H 3900 3150 60 0000 C CNN
1 4650 3900 1 3900 3850
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$EndSCHEMATC $EndSCHEMATC

18
pcb/kicad/pwr_misc.bak
View File

@ -1,5 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 02:04:56 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:32:19 PM CET
LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,10 +34,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:sd2snes-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 3 5 Sheet 3 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -49,6 +52,15 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Comp $Comp
L PIC12F629 U?
U 1 1 4BAA92DB
P 8450 2650
F 0 "U?" H 8400 2650 60 0000 C CNN
F 1 "PIC12F629" H 8450 3400 60 0000 C CNN
1 8450 2650
1 0 0 -1
$EndComp
$Comp
L GND #PWR01 L GND #PWR01
U 1 1 4B6ED41C U 1 1 4B6ED41C
P 2550 6950 P 2550 6950

27
pcb/kicad/pwr_misc.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 11:25:34 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:33:24 PM CET
LIBS:sd2snes-cache LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
@ -35,11 +35,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:testsw LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:cs4344
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 3 5 Sheet 3 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""
@ -50,6 +53,24 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Comp $Comp
L CS4344 U?
U 1 1 4BAA9331
P 6650 4850
F 0 "U?" H 6300 5250 60 0000 C CNN
F 1 "CS4344" H 6850 4450 60 0000 C CNN
1 6650 4850
1 0 0 -1
$EndComp
$Comp
L PIC12F629 U?
U 1 1 4BAA92DB
P 8450 2650
F 0 "U?" H 8400 2650 60 0000 C CNN
F 1 "PIC12F629" H 8450 3400 60 0000 C CNN
1 8450 2650
1 0 0 -1
$EndComp
$Comp
L GND #PWR01 L GND #PWR01
U 1 1 4B6ED41C U 1 1 4B6ED41C
P 2550 6950 P 2550 6950

158
pcb/kicad/sd2snes-cache.bak
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Tue 09 Feb 2010 02:04:56 PM CET EESchema-LIBRARY Version 2.3 Date: Wed 24 Mar 2010 11:32:19 PM CET
# #
# +1.2V # +1.2V
# #
@ -137,6 +137,51 @@ X VCCB 6 100 650 300 D 50 50 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# CY62148EV30-BVXI
#
DEF CY62148EV30-BVXI U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "CY62148EV30-BVXI" 50 0 60 H V C CNN
DRAW
S -550 1000 550 -1000 0 1 0 N
X A0 A1 -850 900 300 R 50 50 1 1 I
X DQ4 B1 850 500 300 L 50 50 1 1 B
X DQ5 C1 850 400 300 L 50 50 1 1 B
X Vss D1 100 -1300 300 U 50 50 1 1 W
X Vcc E1 100 1300 300 D 50 50 1 1 W
X DQ6 F1 850 300 300 L 50 50 1 1 B
X DQ7 G1 850 200 300 L 50 50 1 1 B
X A9 H1 -850 0 300 R 50 50 1 1 I
X A1 A2 -850 800 300 R 50 50 1 1 I
X A2 B2 -850 700 300 R 50 50 1 1 I
X /OE G2 850 -500 300 L 50 50 1 1 I
X A10 H2 -850 -100 300 R 50 50 1 1 I
X NC A3 850 -900 300 L 50 50 1 1 I
X /WE B3 850 -600 300 L 50 50 1 1 I
X A18 F3 -850 -900 300 R 50 50 1 1 I
X /CE G3 850 -400 300 L 50 50 1 1 I
X A11 H3 -850 -200 300 R 50 50 1 1 I
X A3 A4 -850 600 300 R 50 50 1 1 I
X A4 B4 -850 500 300 R 50 50 1 1 I
X A5 C4 -850 400 300 R 50 50 1 1 I
X A17 F4 -850 -800 300 R 50 50 1 1 I
X A16 G4 -850 -700 300 R 50 50 1 1 I
X A12 H4 -850 -300 300 R 50 50 1 1 I
X A6 A5 -850 300 300 R 50 50 1 1 I
X A7 B5 -850 200 300 R 50 50 1 1 I
X A15 G5 -850 -600 300 R 50 50 1 1 I
X A13 H5 -850 -400 300 R 50 50 1 1 I
X A8 A6 -850 100 300 R 50 50 1 1 I
X DQ0 B6 850 900 300 L 50 50 1 1 B
X DQ1 C6 850 800 300 L 50 50 1 1 B
X Vcc D6 -100 1300 300 D 50 50 1 1 W
X Vss E6 -100 -1300 300 U 50 50 1 1 W
X DQ2 F6 850 700 300 L 50 50 1 1 B
X DQ3 G6 850 600 300 L 50 50 1 1 B
X A14 H6 -850 -500 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# GND # GND
# #
DEF ~GND #PWR 0 0 Y Y 1 F P DEF ~GND #PWR 0 0 Y Y 1 F P
@ -266,6 +311,117 @@ X Vout 5 700 100 300 L 50 50 1 1 w
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# MT45W8MW16
#
DEF MT45W8MW16 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MT45W8MW16" 0 0 60 H V C CNN
DRAW
S -550 1400 550 -1400 0 1 0 N
X /LB A1 850 -600 300 L 50 50 1 1 I
X DQ8 B1 850 400 300 L 50 50 1 1 B
X DQ9 C1 850 300 300 L 50 50 1 1 B
X VssQ D1 100 -1700 300 U 50 50 1 1 W
X VccQ E1 100 1700 300 D 50 50 1 1 W
X DQ14 F1 850 -200 300 L 50 50 1 1 B
X DQ15 G1 850 -300 300 L 50 50 1 1 B
X A18 H1 -850 -500 300 R 50 50 1 1 I
X WAIT J1 850 -1100 300 L 50 50 1 1 O
X /OE A2 -850 -1200 300 R 50 50 1 1 I
X /UB B2 850 -700 300 L 50 50 1 1 I
X DQ10 C2 850 200 300 L 50 50 1 1 B
X DQ11 D2 850 100 300 L 50 50 1 1 B
X DQ12 E2 850 0 300 L 50 50 1 1 B
X DQ13 F2 850 -100 300 L 50 50 1 1 B
X A19 G2 -850 -600 300 R 50 50 1 1 I
X A8 H2 -850 500 300 R 50 50 1 1 I
X CLK J2 850 -1300 300 L 50 50 1 1 I C
X A0 A3 -850 1300 300 R 50 50 1 1 I
X A3 B3 -850 1000 300 R 50 50 1 1 I
X A5 C3 -850 800 300 R 50 50 1 1 I
X A17 D3 -850 -400 300 R 50 50 1 1 I
X A21 E3 -850 -800 300 R 50 50 1 1 I
X A14 F3 -850 -100 300 R 50 50 1 1 I
X A12 G3 -850 100 300 R 50 50 1 1 I
X A9 H3 -850 400 300 R 50 50 1 1 I
X /ADV J3 850 -1200 300 L 50 50 1 1 I
X A1 A4 -850 1200 300 R 50 50 1 1 I
X A4 B4 -850 900 300 R 50 50 1 1 I
X A6 C4 -850 700 300 R 50 50 1 1 I
X A7 D4 -850 600 300 R 50 50 1 1 I
X A16 E4 -850 -300 300 R 50 50 1 1 I
X A15 F4 -850 -200 300 R 50 50 1 1 I
X A13 G4 -850 0 300 R 50 50 1 1 I
X A10 H4 -850 300 300 R 50 50 1 1 I
X A22 J4 -850 -900 300 R 50 50 1 1 I
X A2 A5 -850 1100 300 R 50 50 1 1 I
X /CE B5 -850 -1100 300 R 50 50 1 1 I
X DQ1 C5 850 1200 300 L 50 50 1 1 B
X DQ3 D5 850 1000 300 L 50 50 1 1 B
X DQ4 E5 850 900 300 L 50 50 1 1 B
X DQ5 F5 850 800 300 L 50 50 1 1 B
X /WE G5 -850 -1300 300 R 50 50 1 1 I
X A11 H5 -850 200 300 R 50 50 1 1 I
X CRE A6 850 -900 300 L 50 50 1 1 I
X DQ0 B6 850 1300 300 L 50 50 1 1 B
X DQ2 C6 850 1100 300 L 50 50 1 1 B
X Vcc D6 -100 1700 300 D 50 50 1 1 W
X Vss E6 -100 -1700 300 U 50 50 1 1 W
X DQ6 F6 850 700 300 L 50 50 1 1 B
X DQ7 G6 850 600 300 L 50 50 1 1 B
X A20 H6 -850 -700 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# PIC12F629
#
DEF PIC12F629 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 H V C CNN
F1 "PIC12F629" 0 750 60 H V C CNN
DRAW
S 400 -600 -450 650 0 1 0 N
X VDD 1 -750 500 300 R 50 50 1 1 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 1 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 1 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 1 I
X GP2 5 700 -500 300 L 50 50 1 1 I
X GP1 6 700 -200 300 L 50 50 1 1 I
X GP0 7 700 200 300 L 50 50 1 1 I
X VSS 8 700 500 300 L 50 50 1 1 W
X VDD 1 -750 500 300 R 50 50 1 2 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 2 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 2 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 2 I
X GP2 5 700 -500 300 L 50 50 1 2 I
X GP1 6 700 -200 300 L 50 50 1 2 I
X GP0 7 700 200 300 L 50 50 1 2 I
X VSS 8 700 500 300 L 50 50 1 2 W
ENDDRAW
ENDDEF
#
# SD_CARD
#
DEF SD_CARD J 0 40 Y Y 1 F N
F0 "J" -250 -550 60 H V C CNN
F1 "SD_CARD" 0 500 60 H V C CNN
DRAW
P 7 0 1 0 -400 450 450 450 450 -500 -300 -500 -400 -400 -400 450 -400 450 N
X CS 1 -600 50 200 R 50 50 1 1 I
X DI 2 -600 150 200 R 50 50 1 1 I
X VSS 3 650 -50 200 L 50 50 1 1 W
X VDD 4 650 350 200 L 50 50 1 1 W
X SCLK 5 -600 350 200 R 50 50 1 1 I
X VSS2 6 650 -150 200 L 50 50 1 1 W
X DO 7 -600 250 200 R 50 50 1 1 O
X DAT1 8 650 150 200 L 50 50 1 1 I
X DAT2 9 650 50 200 L 50 50 1 1 I
X WPROT WP -600 -150 200 R 50 50 1 1 I
X DETECT DT -600 -250 200 R 50 50 1 1 O
X GND1 GND1 650 -250 200 L 50 50 1 1 W
X GND2 GND2 650 -350 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# SNESCART_EXT # SNESCART_EXT
# #
DEF SNESCART_EXT J 0 40 Y Y 1 F N DEF SNESCART_EXT J 0 40 Y Y 1 F N

178
pcb/kicad/sd2snes-cache.lib
View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Tue 09 Feb 2010 11:25:34 PM CET EESchema-LIBRARY Version 2.3 Date: Wed 24 Mar 2010 11:33:24 PM CET
# #
# +1.2V # +1.2V
# #
@ -137,6 +137,71 @@ X VCCB 6 100 650 300 D 50 50 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# CS4344
#
DEF CS4344 U 0 40 Y Y 1 F N
F0 "U" -350 400 60 H V C CNN
F1 "CS4344" 200 -400 60 H V C CNN
DRAW
S -400 350 400 -350 0 1 0 N
X SDIN 1 -700 200 300 R 50 50 1 1 I
X /DEM/SCLK 2 -700 0 300 R 50 50 1 1 I
X LRCK 3 -700 -100 300 R 50 50 1 1 I
X MCLK 4 -700 -200 300 R 50 50 1 1 I
X VQ 5 700 200 300 L 50 50 1 1 O
X FILT 6 700 100 300 L 50 50 1 1 O
X AOUTL 7 700 -100 300 L 50 50 1 1 O
X GND 8 0 -650 300 U 50 50 1 1 W
X VA 9 0 650 300 D 50 50 1 1 W
X AOUTR 10 700 -200 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# CY62148EV30-BVXI
#
DEF CY62148EV30-BVXI U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "CY62148EV30-BVXI" 50 0 60 H V C CNN
DRAW
S -550 1000 550 -1000 0 1 0 N
X A0 A1 -850 900 300 R 50 50 1 1 I
X DQ4 B1 850 500 300 L 50 50 1 1 B
X DQ5 C1 850 400 300 L 50 50 1 1 B
X Vss D1 100 -1300 300 U 50 50 1 1 W
X Vcc E1 100 1300 300 D 50 50 1 1 W
X DQ6 F1 850 300 300 L 50 50 1 1 B
X DQ7 G1 850 200 300 L 50 50 1 1 B
X A9 H1 -850 0 300 R 50 50 1 1 I
X A1 A2 -850 800 300 R 50 50 1 1 I
X A2 B2 -850 700 300 R 50 50 1 1 I
X /OE G2 850 -500 300 L 50 50 1 1 I
X A10 H2 -850 -100 300 R 50 50 1 1 I
X NC A3 850 -900 300 L 50 50 1 1 I
X /WE B3 850 -600 300 L 50 50 1 1 I
X A18 F3 -850 -900 300 R 50 50 1 1 I
X /CE G3 850 -400 300 L 50 50 1 1 I
X A11 H3 -850 -200 300 R 50 50 1 1 I
X A3 A4 -850 600 300 R 50 50 1 1 I
X A4 B4 -850 500 300 R 50 50 1 1 I
X A5 C4 -850 400 300 R 50 50 1 1 I
X A17 F4 -850 -800 300 R 50 50 1 1 I
X A16 G4 -850 -700 300 R 50 50 1 1 I
X A12 H4 -850 -300 300 R 50 50 1 1 I
X A6 A5 -850 300 300 R 50 50 1 1 I
X A7 B5 -850 200 300 R 50 50 1 1 I
X A15 G5 -850 -600 300 R 50 50 1 1 I
X A13 H5 -850 -400 300 R 50 50 1 1 I
X A8 A6 -850 100 300 R 50 50 1 1 I
X DQ0 B6 850 900 300 L 50 50 1 1 B
X DQ1 C6 850 800 300 L 50 50 1 1 B
X Vcc D6 -100 1300 300 D 50 50 1 1 W
X Vss E6 -100 -1300 300 U 50 50 1 1 W
X DQ2 F6 850 700 300 L 50 50 1 1 B
X DQ3 G6 850 600 300 L 50 50 1 1 B
X A14 H6 -850 -500 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# GND # GND
# #
DEF ~GND #PWR 0 0 Y Y 1 F P DEF ~GND #PWR 0 0 Y Y 1 F P
@ -266,6 +331,117 @@ X Vout 5 700 100 300 L 50 50 1 1 w
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# MT45W8MW16
#
DEF MT45W8MW16 U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "MT45W8MW16" 0 0 60 H V C CNN
DRAW
S -550 1400 550 -1400 0 1 0 N
X /LB A1 850 -600 300 L 50 50 1 1 I
X DQ8 B1 850 400 300 L 50 50 1 1 B
X DQ9 C1 850 300 300 L 50 50 1 1 B
X VssQ D1 100 -1700 300 U 50 50 1 1 W
X VccQ E1 100 1700 300 D 50 50 1 1 W
X DQ14 F1 850 -200 300 L 50 50 1 1 B
X DQ15 G1 850 -300 300 L 50 50 1 1 B
X A18 H1 -850 -500 300 R 50 50 1 1 I
X WAIT J1 850 -1100 300 L 50 50 1 1 O
X /OE A2 -850 -1200 300 R 50 50 1 1 I
X /UB B2 850 -700 300 L 50 50 1 1 I
X DQ10 C2 850 200 300 L 50 50 1 1 B
X DQ11 D2 850 100 300 L 50 50 1 1 B
X DQ12 E2 850 0 300 L 50 50 1 1 B
X DQ13 F2 850 -100 300 L 50 50 1 1 B
X A19 G2 -850 -600 300 R 50 50 1 1 I
X A8 H2 -850 500 300 R 50 50 1 1 I
X CLK J2 850 -1300 300 L 50 50 1 1 I C
X A0 A3 -850 1300 300 R 50 50 1 1 I
X A3 B3 -850 1000 300 R 50 50 1 1 I
X A5 C3 -850 800 300 R 50 50 1 1 I
X A17 D3 -850 -400 300 R 50 50 1 1 I
X A21 E3 -850 -800 300 R 50 50 1 1 I
X A14 F3 -850 -100 300 R 50 50 1 1 I
X A12 G3 -850 100 300 R 50 50 1 1 I
X A9 H3 -850 400 300 R 50 50 1 1 I
X /ADV J3 850 -1200 300 L 50 50 1 1 I
X A1 A4 -850 1200 300 R 50 50 1 1 I
X A4 B4 -850 900 300 R 50 50 1 1 I
X A6 C4 -850 700 300 R 50 50 1 1 I
X A7 D4 -850 600 300 R 50 50 1 1 I
X A16 E4 -850 -300 300 R 50 50 1 1 I
X A15 F4 -850 -200 300 R 50 50 1 1 I
X A13 G4 -850 0 300 R 50 50 1 1 I
X A10 H4 -850 300 300 R 50 50 1 1 I
X A22 J4 -850 -900 300 R 50 50 1 1 I
X A2 A5 -850 1100 300 R 50 50 1 1 I
X /CE B5 -850 -1100 300 R 50 50 1 1 I
X DQ1 C5 850 1200 300 L 50 50 1 1 B
X DQ3 D5 850 1000 300 L 50 50 1 1 B
X DQ4 E5 850 900 300 L 50 50 1 1 B
X DQ5 F5 850 800 300 L 50 50 1 1 B
X /WE G5 -850 -1300 300 R 50 50 1 1 I
X A11 H5 -850 200 300 R 50 50 1 1 I
X CRE A6 850 -900 300 L 50 50 1 1 I
X DQ0 B6 850 1300 300 L 50 50 1 1 B
X DQ2 C6 850 1100 300 L 50 50 1 1 B
X Vcc D6 -100 1700 300 D 50 50 1 1 W
X Vss E6 -100 -1700 300 U 50 50 1 1 W
X DQ6 F6 850 700 300 L 50 50 1 1 B
X DQ7 G6 850 600 300 L 50 50 1 1 B
X A20 H6 -850 -700 300 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# PIC12F629
#
DEF PIC12F629 U 0 40 Y Y 1 F N
F0 "U" -50 0 60 H V C CNN
F1 "PIC12F629" 0 750 60 H V C CNN
DRAW
S 400 -600 -450 650 0 1 0 N
X VDD 1 -750 500 300 R 50 50 1 1 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 1 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 1 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 1 I
X GP2 5 700 -500 300 L 50 50 1 1 I
X GP1 6 700 -200 300 L 50 50 1 1 I
X GP0 7 700 200 300 L 50 50 1 1 I
X VSS 8 700 500 300 L 50 50 1 1 W
X VDD 1 -750 500 300 R 50 50 1 2 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 2 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 2 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 2 I
X GP2 5 700 -500 300 L 50 50 1 2 I
X GP1 6 700 -200 300 L 50 50 1 2 I
X GP0 7 700 200 300 L 50 50 1 2 I
X VSS 8 700 500 300 L 50 50 1 2 W
ENDDRAW
ENDDEF
#
# SD_CARD
#
DEF SD_CARD J 0 40 Y Y 1 F N
F0 "J" -250 -550 60 H V C CNN
F1 "SD_CARD" 0 500 60 H V C CNN
DRAW
P 7 0 1 0 -400 450 450 450 450 -500 -300 -500 -400 -400 -400 450 -400 450 N
X CS 1 -600 50 200 R 50 50 1 1 I
X DI 2 -600 150 200 R 50 50 1 1 I
X VSS 3 650 -50 200 L 50 50 1 1 W
X VDD 4 650 350 200 L 50 50 1 1 W
X SCLK 5 -600 350 200 R 50 50 1 1 I
X VSS2 6 650 -150 200 L 50 50 1 1 W
X DO 7 -600 250 200 R 50 50 1 1 O
X DAT1 8 650 150 200 L 50 50 1 1 I
X DAT2 9 650 50 200 L 50 50 1 1 I
X WPROT WP -600 -150 200 R 50 50 1 1 I
X DETECT DT -600 -250 200 R 50 50 1 1 O
X GND1 GND1 650 -250 200 L 50 50 1 1 W
X GND2 GND2 650 -350 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# SNESCART_EXT # SNESCART_EXT
# #
DEF SNESCART_EXT J 0 40 Y Y 1 F N DEF SNESCART_EXT J 0 40 Y Y 1 F N

17
pcb/kicad/sd2snes.bak
View File

@ -1,5 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 02:04:56 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:32:19 PM CET
LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,10 +34,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:sd2snes-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 1 5 Sheet 1 6
Title "sd2snes Mark II" Title "sd2snes Mark II"
Date "9 feb 2010" Date "9 feb 2010"
Rev "A" Rev "A"
@ -48,6 +51,14 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Text Notes 750 7700 0 500 ~ 100
sd2snes Mark II
$Sheet
S 1250 3300 1600 1150
U 4BAA6ABD
F0 "Memory" 60
F1 "memory.sch" 60
$EndSheet
$Sheet $Sheet
S 8050 1250 1600 1250 S 8050 1250 1600 1250
U 4B6ED75B U 4B6ED75B

5029
pcb/kicad/sd2snes.brd
View File

File diff suppressed because it is too large Load Diff

52
pcb/kicad/sd2snes.cmp
View File

@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (20100205 SVN-R2303)-unstable date = Tue 09 Feb 2010 11:10:01 PM CET Cmp-Mod V01 Created by CvPCB (20100205 SVN-R2303)-unstable date = Wed 24 Mar 2010 11:36:00 PM CET
BeginCmp BeginCmp
TimeStamp = /4B6E16F2/4B6E1766; TimeStamp = /4B6E16F2/4B6E1766;
@ -8,24 +8,10 @@ IdModule = SNESCART_EXT;
EndCmp EndCmp
BeginCmp BeginCmp
TimeStamp = /4B6ED75B/4B716001; TimeStamp = /4B6ED75B/4BAA6A9C;
Reference = J2; Reference = J2;
ValeurCmp = SDCARD; ValeurCmp = SD_CARD;
IdModule = JAE-SG5S009V1A; IdModule = SD-RSMT-2-MQ-WF;
EndCmp
BeginCmp
TimeStamp = /4B6ED75B/4B71DB24;
Reference = sw1;
ValeurCmp = TESTSW;
IdModule = 8DIPCMS;
EndCmp
BeginCmp
TimeStamp = /4B6ED75B/4B71DCB8;
Reference = sw2;
ValeurCmp = TESTSW2;
IdModule = 8DIPCMS;
EndCmp EndCmp
BeginCmp BeginCmp
@ -53,7 +39,7 @@ BeginCmp
TimeStamp = /4B6E18FC/4B6E1931; TimeStamp = /4B6E18FC/4B6E1931;
Reference = U4; Reference = U4;
ValeurCmp = XC3S400-PQ208; ValeurCmp = XC3S400-PQ208;
IdModule = PQFP208_ALTPADS; IdModule = PQFP208;
EndCmp EndCmp
BeginCmp BeginCmp
@ -98,4 +84,32 @@ ValeurCmp = LPC1754;
IdModule = LQFP80-.5; IdModule = LQFP80-.5;
EndCmp EndCmp
BeginCmp
TimeStamp = /4BAA6ABD/4B868602;
Reference = U12;
ValeurCmp = MT45W8MW16;
IdModule = VFBGA54;
EndCmp
BeginCmp
TimeStamp = /4BAA6ABD/4B86E25C;
Reference = U13;
ValeurCmp = CY62148EV30-BVXI;
IdModule = VFBGA36;
EndCmp
BeginCmp
TimeStamp = /4B6EC9C3/4BAA9331;
Reference = U14;
ValeurCmp = CS4344;
IdModule = TSSOP10;
EndCmp
BeginCmp
TimeStamp = /4B6EC9C3/4BAA92DB;
Reference = U15;
ValeurCmp = PIC12F629;
IdModule = SO8N;
EndCmp
EndListe EndListe

193
pcb/kicad/sd2snes.net
View File

@ -1,4 +1,4 @@
# EESchema Netlist Version 1.1 created Tue 09 Feb 2010 11:10:01 PM CET # EESchema Netlist Version 1.1 created Wed 24 Mar 2010 11:36:00 PM CET
( (
( /4B6E16F2/4B6E1766 SNESCART_EXT J1 SNESCART_EXT ( /4B6E16F2/4B6E1766 SNESCART_EXT J1 SNESCART_EXT
( 1 ? ) ( 1 ? )
@ -64,20 +64,7 @@
( 61 ? ) ( 61 ? )
( 62 ? ) ( 62 ? )
) )
( /4B6ED75B/4B716001 JAE-SG5S009V1A J2 SDCARD ( /4B6ED75B/4BAA6A9C SD-RSMT-2-MQ-WF J2 SD_CARD
( ~ ? )
)
( /4B6ED75B/4B71DB24 8DIPCMS sw1 TESTSW
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 ? )
)
( /4B6ED75B/4B71DCB8 8DIPCMS sw2 TESTSW2
( 1 ? ) ( 1 ? )
( 2 ? ) ( 2 ? )
( 3 ? ) ( 3 ? )
@ -86,6 +73,11 @@
( 6 ? ) ( 6 ? )
( 7 ? ) ( 7 ? )
( 8 ? ) ( 8 ? )
( 9 ? )
( DT ? )
( GND1 ? )
( GND2 ? )
( WP ? )
) )
( /4B6E16F2/4B6E1740 TSSOP48 U1 74ALVC164245 ( /4B6E16F2/4B6E1740 TSSOP48 U1 74ALVC164245
( 1 ? ) ( 1 ? )
@ -237,21 +229,21 @@
( 47 ? ) ( 47 ? )
( 48 ? ) ( 48 ? )
) )
( /4B6E18FC/4B6E1931 PQFP208_ALTPADS U4 XC3S400-PQ208 ( /4B6E18FC/4B6E1931 PQFP208 U4 XC3S400-PQ208
( 1 GND ) ( 1 ? )
( 2 ? ) ( 2 ? )
( 3 ? ) ( 3 ? )
( 4 ? ) ( 4 ? )
( 5 ? ) ( 5 ? )
( 6 ? ) ( 6 ? )
( 7 ? ) ( 7 ? )
( 8 GND ) ( 8 ? )
( 9 ? ) ( 9 ? )
( 10 ? ) ( 10 ? )
( 11 ? ) ( 11 ? )
( 12 ? ) ( 12 ? )
( 13 ? ) ( 13 ? )
( 14 GND ) ( 14 ? )
( 15 ? ) ( 15 ? )
( 16 ? ) ( 16 ? )
( 17 ? ) ( 17 ? )
@ -262,12 +254,12 @@
( 22 ? ) ( 22 ? )
( 23 ? ) ( 23 ? )
( 24 ? ) ( 24 ? )
( 25 GND ) ( 25 ? )
( 26 ? ) ( 26 ? )
( 27 ? ) ( 27 ? )
( 28 ? ) ( 28 ? )
( 29 ? ) ( 29 ? )
( 30 GND ) ( 30 ? )
( 31 ? ) ( 31 ? )
( 32 ? ) ( 32 ? )
( 33 ? ) ( 33 ? )
@ -278,32 +270,32 @@
( 38 ? ) ( 38 ? )
( 39 ? ) ( 39 ? )
( 40 ? ) ( 40 ? )
( 41 GND ) ( 41 ? )
( 42 ? ) ( 42 ? )
( 43 ? ) ( 43 ? )
( 44 ? ) ( 44 ? )
( 45 ? ) ( 45 ? )
( 46 ? ) ( 46 ? )
( 47 GND ) ( 47 ? )
( 48 ? ) ( 48 ? )
( 49 ? ) ( 49 ? )
( 50 ? ) ( 50 ? )
( 51 ? ) ( 51 ? )
( 52 ? ) ( 52 ? )
( 53 GND ) ( 53 ? )
( 54 ? ) ( 54 ? )
( 55 ? ) ( 55 ? )
( 56 ? ) ( 56 ? )
( 57 ? ) ( 57 ? )
( 58 ? ) ( 58 ? )
( 59 GND ) ( 59 ? )
( 60 ? ) ( 60 ? )
( 61 ? ) ( 61 ? )
( 62 ? ) ( 62 ? )
( 63 ? ) ( 63 ? )
( 64 ? ) ( 64 ? )
( 65 ? ) ( 65 ? )
( 66 GND ) ( 66 ? )
( 67 ? ) ( 67 ? )
( 68 ? ) ( 68 ? )
( 69 ? ) ( 69 ? )
@ -312,14 +304,14 @@
( 72 ? ) ( 72 ? )
( 73 ? ) ( 73 ? )
( 74 ? ) ( 74 ? )
( 75 GND ) ( 75 ? )
( 76 ? ) ( 76 ? )
( 77 ? ) ( 77 ? )
( 78 ? ) ( 78 ? )
( 79 ? ) ( 79 ? )
( 80 ? ) ( 80 ? )
( 81 ? ) ( 81 ? )
( 82 GND ) ( 82 ? )
( 83 ? ) ( 83 ? )
( 84 ? ) ( 84 ? )
( 85 ? ) ( 85 ? )
@ -328,7 +320,7 @@
( 88 ? ) ( 88 ? )
( 89 ? ) ( 89 ? )
( 90 ? ) ( 90 ? )
( 91 GND ) ( 91 ? )
( 92 ? ) ( 92 ? )
( 93 ? ) ( 93 ? )
( 94 ? ) ( 94 ? )
@ -336,26 +328,26 @@
( 96 ? ) ( 96 ? )
( 97 ? ) ( 97 ? )
( 98 ? ) ( 98 ? )
( 99 GND ) ( 99 ? )
( 100 ? ) ( 100 ? )
( 101 ? ) ( 101 ? )
( 102 ? ) ( 102 ? )
( 103 ? ) ( 103 ? )
( 104 ? ) ( 104 ? )
( 105 GND ) ( 105 ? )
( 106 ? ) ( 106 ? )
( 107 ? ) ( 107 ? )
( 108 ? ) ( 108 ? )
( 109 ? ) ( 109 ? )
( 110 ? ) ( 110 ? )
( 111 ? ) ( 111 ? )
( 112 GND ) ( 112 ? )
( 113 ? ) ( 113 ? )
( 114 ? ) ( 114 ? )
( 115 ? ) ( 115 ? )
( 116 ? ) ( 116 ? )
( 117 ? ) ( 117 ? )
( 118 GND ) ( 118 ? )
( 119 ? ) ( 119 ? )
( 120 ? ) ( 120 ? )
( 121 ? ) ( 121 ? )
@ -366,12 +358,12 @@
( 126 ? ) ( 126 ? )
( 127 ? ) ( 127 ? )
( 128 ? ) ( 128 ? )
( 129 GND ) ( 129 ? )
( 130 ? ) ( 130 ? )
( 131 ? ) ( 131 ? )
( 132 ? ) ( 132 ? )
( 133 ? ) ( 133 ? )
( 134 GND ) ( 134 ? )
( 135 ? ) ( 135 ? )
( 136 ? ) ( 136 ? )
( 137 ? ) ( 137 ? )
@ -382,32 +374,32 @@
( 142 ? ) ( 142 ? )
( 143 ? ) ( 143 ? )
( 144 ? ) ( 144 ? )
( 145 GND ) ( 145 ? )
( 146 ? ) ( 146 ? )
( 147 ? ) ( 147 ? )
( 148 ? ) ( 148 ? )
( 149 ? ) ( 149 ? )
( 150 ? ) ( 150 ? )
( 151 GND ) ( 151 ? )
( 152 ? ) ( 152 ? )
( 153 ? ) ( 153 ? )
( 154 ? ) ( 154 ? )
( 155 ? ) ( 155 ? )
( 156 ? ) ( 156 ? )
( 157 GND ) ( 157 ? )
( 158 ? ) ( 158 ? )
( 159 ? ) ( 159 ? )
( 160 ? ) ( 160 ? )
( 161 ? ) ( 161 ? )
( 162 ? ) ( 162 ? )
( 163 GND ) ( 163 ? )
( 164 ? ) ( 164 ? )
( 165 ? ) ( 165 ? )
( 166 ? ) ( 166 ? )
( 167 ? ) ( 167 ? )
( 168 ? ) ( 168 ? )
( 169 ? ) ( 169 ? )
( 170 GND ) ( 170 ? )
( 171 ? ) ( 171 ? )
( 172 ? ) ( 172 ? )
( 173 ? ) ( 173 ? )
@ -416,14 +408,14 @@
( 176 ? ) ( 176 ? )
( 177 ? ) ( 177 ? )
( 178 ? ) ( 178 ? )
( 179 GND ) ( 179 ? )
( 180 ? ) ( 180 ? )
( 181 ? ) ( 181 ? )
( 182 ? ) ( 182 ? )
( 183 ? ) ( 183 ? )
( 184 ? ) ( 184 ? )
( 185 ? ) ( 185 ? )
( 186 GND ) ( 186 ? )
( 187 ? ) ( 187 ? )
( 188 ? ) ( 188 ? )
( 189 ? ) ( 189 ? )
@ -432,14 +424,14 @@
( 192 ? ) ( 192 ? )
( 193 ? ) ( 193 ? )
( 194 ? ) ( 194 ? )
( 195 GND ) ( 195 ? )
( 196 ? ) ( 196 ? )
( 197 ? ) ( 197 ? )
( 198 ? ) ( 198 ? )
( 199 ? ) ( 199 ? )
( 200 ? ) ( 200 ? )
( 201 ? ) ( 201 ? )
( 202 GND ) ( 202 ? )
( 203 ? ) ( 203 ? )
( 204 ? ) ( 204 ? )
( 205 ? ) ( 205 ? )
@ -561,5 +553,118 @@
( 79 ? ) ( 79 ? )
( 80 ? ) ( 80 ? )
) )
( /4BAA6ABD/4B868602 VFBGA54 U12 MT45W8MW16
( A1 ? )
( A2 ? )
( A3 ? )
( A4 ? )
( A5 ? )
( A6 ? )
( B1 ? )
( B2 ? )
( B3 ? )
( B4 ? )
( B5 ? )
( B6 ? )
( C1 ? )
( C2 ? )
( C3 ? )
( C4 ? )
( C5 ? )
( C6 ? )
( D1 ? )
( D2 ? )
( D3 ? )
( D4 ? )
( D5 ? )
( D6 ? )
( E1 ? )
( E2 ? )
( E3 ? )
( E4 ? )
( E5 ? )
( E6 ? )
( F1 ? )
( F2 ? )
( F3 ? )
( F4 ? )
( F5 ? )
( F6 ? )
( G1 ? )
( G2 ? )
( G3 ? )
( G4 ? )
( G5 ? )
( G6 ? )
( H1 ? )
( H2 ? )
( H3 ? )
( H4 ? )
( H5 ? )
( H6 ? )
( J1 ? )
( J2 ? )
( J3 ? )
( J4 ? )
)
( /4BAA6ABD/4B86E25C VFBGA36 U13 CY62148EV30-BVXI
( A1 ? )
( A2 ? )
( A3 ? )
( A4 ? )
( A5 ? )
( A6 ? )
( B1 ? )
( B2 ? )
( B3 ? )
( B4 ? )
( B5 ? )
( B6 ? )
( C1 ? )
( C4 ? )
( C6 ? )
( D1 ? )
( D6 ? )
( E1 ? )
( E6 ? )
( F1 ? )
( F3 ? )
( F4 ? )
( F6 ? )
( G1 ? )
( G2 ? )
( G3 ? )
( G4 ? )
( G5 ? )
( G6 ? )
( H1 ? )
( H2 ? )
( H3 ? )
( H4 ? )
( H5 ? )
( H6 ? )
)
( /4B6EC9C3/4BAA9331 TSSOP10 U14 CS4344
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 ? )
( 9 ? )
( 10 ? )
)
( /4B6EC9C3/4BAA92DB SO8N U15 PIC12F629
( 1 ? )
( 2 ? )
( 3 ? )
( 4 ? )
( 5 ? )
( 6 ? )
( 7 ? )
( 8 ? )
)
) )
* *

23
pcb/kicad/sd2snes.pro
View File

@ -1,16 +1,6 @@
update=Tue 09 Feb 2010 11:25:42 PM CET update=Wed 24 Mar 2010 11:33:10 PM CET
version=1 version=1
last_client=eeschema last_client=eeschema
[cvpcb]
version=1
NetITyp=0
NetIExt=.net
PkgIExt=.pkg
NetDir=
LibDir=
NetType=0
[cvpcb/libraries]
EquName1=devcms
[general] [general]
version=1 version=1
[pcbnew] [pcbnew]
@ -36,7 +26,6 @@ TxtLar=120
MSegLar=40 MSegLar=40
WpenSer=2 WpenSer=2
[pcbnew/libraries] [pcbnew/libraries]
LibDir=
LibName1=sockets LibName1=sockets
LibName2=connect LibName2=connect
LibName3=discret LibName3=discret
@ -51,6 +40,12 @@ LibName11=libs/snescart
LibName12=/home/ikari/src/easyflash2-git/easyflash/Hardware/ef2-kicad/ef2-footprints LibName12=/home/ikari/src/easyflash2-git/easyflash/Hardware/ef2-kicad/ef2-footprints
LibName13=libs/mypackages LibName13=libs/mypackages
LibName14=libs/sdcard LibName14=libs/sdcard
LibDir=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[eeschema] [eeschema]
version=1 version=1
LibDir= LibDir=
@ -122,3 +117,7 @@ LibName32=libs/misc-74
LibName33=libs/vreg LibName33=libs/vreg
LibName34=libs/lpc1754 LibName34=libs/lpc1754
LibName35=libs/sdcard LibName35=libs/sdcard
LibName36=libs/sd_card
LibName37=libs/cy62148ev30
LibName38=libs/mt45w8mw16
LibName39=libs/cs4344

17
pcb/kicad/sd2snes.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 11:25:34 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:33:24 PM CET
LIBS:sd2snes-cache LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
@ -35,11 +35,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:testsw LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:cs4344
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 1 5 Sheet 1 6
Title "sd2snes Mark II" Title "sd2snes Mark II"
Date "9 feb 2010" Date "9 feb 2010"
Rev "A" Rev "A"
@ -49,6 +52,14 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Text Notes 750 7700 0 500 ~ 100
sd2snes Mark II
$Sheet
S 1250 3300 1600 1150
U 4BAA6ABD
F0 "Memory" 60
F1 "memory.sch" 60
$EndSheet
$Sheet $Sheet
S 8050 1250 1600 1250 S 8050 1250 1600 1250
U 4B6ED75B U 4B6ED75B

9
pcb/kicad/snesslot.bak
View File

@ -1,5 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 02:04:56 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:32:19 PM CET
LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -35,10 +34,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:sd2snes-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 5 5 Sheet 5 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""

9
pcb/kicad/snesslot.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 09 Feb 2010 11:25:34 PM CET EESchema Schematic File Version 2 date Wed 24 Mar 2010 11:33:24 PM CET
LIBS:sd2snes-cache LIBS:sd2snes-cache
LIBS:power LIBS:power
LIBS:device LIBS:device
@ -35,11 +35,14 @@ LIBS:misc-74
LIBS:vreg LIBS:vreg
LIBS:lpc1754 LIBS:lpc1754
LIBS:sdcard LIBS:sdcard
LIBS:testsw LIBS:sd_card
LIBS:cy62148ev30
LIBS:mt45w8mw16
LIBS:cs4344
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
$Descr A4 11700 8267 $Descr A4 11700 8267
Sheet 5 5 Sheet 5 6
Title "" Title ""
Date "9 feb 2010" Date "9 feb 2010"
Rev "" Rev ""

3
src/main.c
View File

@ -280,8 +280,6 @@ restart:
uart_puts_P(PSTR("SNES GO!\r\n")); uart_puts_P(PSTR("SNES GO!\r\n"));
snes_reset(0); snes_reset(0);
// writetest(); // writetest();
// XXX
uart_putc(uart_getc());
/* snes_reset(1); /* snes_reset(1);
set_avr_ena(0); set_avr_ena(0);
led_std(); led_std();
@ -290,7 +288,6 @@ restart:
set_busy_led(0); set_busy_led(0);
set_avr_ena(1); set_avr_ena(1);
snes_reset(0); */ snes_reset(0); */
while(1)dprintf("ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!");
uint8_t cmd = 0; uint8_t cmd = 0;
while(!sram_reliable()); while(!sram_reliable());

2
src/memory.c
View File

@ -326,7 +326,7 @@ uint8_t sram_reliable() {
} }
if(score<SRAM_RELIABILITY_SCORE) { if(score<SRAM_RELIABILITY_SCORE) {
result = 0; result = 0;
dprintf("score=%d\n", score); // dprintf("score=%d\n", score);
} else { } else {
result = 1; result = 1;
} }

103
verilog/sd2snes/sd2snes.xise
View File

@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header> </header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/> <version xil_pn:ise_version="11.5" xil_pn:schema_version="2"/>
<files> <files>
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
@ -40,14 +40,14 @@
</file> </file>
<file xil_pn:name="tf_spi.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="tf_spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/> <association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/> <association xil_pn:name="PostTranslateSimulation"/>
</file> </file>
<file xil_pn:name="main_tf2.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="main_tf2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/> <association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/> <association xil_pn:name="PostTranslateSimulation"/>
</file> </file>
<file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG">
@ -56,10 +56,9 @@
</file> </file>
<file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/> <association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/> <association xil_pn:name="PostTranslateSimulation"/>
<library xil_pn:name="verilog"/>
</file> </file>
<file xil_pn:name="dcm2.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="dcm2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
@ -75,61 +74,63 @@
</file> </file>
<file xil_pn:name="tf_spi_dma.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="tf_spi_dma.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/> <association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/> <association xil_pn:name="PostTranslateSimulation"/>
</file> </file>
<file xil_pn:name="tf_main_3.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="tf_main_3.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/> <association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/> <association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/> <association xil_pn:name="PostTranslateSimulation"/>
</file> </file>
</files> </files>
<properties> <properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/> <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/> <property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s200"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/> <property xil_pn:name="Done (Output Events)" xil_pn:value="6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="6"/> <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true"/> <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="3"/> <property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Normal"/> <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/> <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/> <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="true"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|main"/> <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main"/> <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High"/> <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Balanced" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true"/> <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High"/> <property xil_pn:name="Package" xil_pn:value="tq144" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Balanced"/> <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main_3"/> <property xil_pn:name="Project Description" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main_3"/> <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="tq144"/> <property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High"/> <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Project Description" xil_pn:value="sd2snes"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="5"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main_3"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main_3"/> <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/> <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes/smartxplorer_results/run9/maptimingextraeffortct3.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/> <!-- -->
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/> <!-- The following properties are for internal use only. These should not be modified.-->
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/> <!-- -->
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes/smartxplorer_results/run9/maptimingextraeffortct3.xds"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings> <bindings>
@ -138,8 +139,6 @@
<libraries/> <libraries/>
<partitions> <partitions/>
<partition xil_pn:name="/main"/>
</partitions>
</project> </project>