FPGA test function, DCM tweak

verilog/sd2snes/avr_cmd.v

@@ -68,6 +68,8 @@ always @(posedge clk) begin
             MAPPER_BUF <= cmd_data[3:0];
          4'h8:
             AVR_DATA_IN_BUF <= avr_data_in;
+         4'hF:
+            AVR_DATA_IN_BUF <= 8'hA5;
       endcase
    end else if (param_ready) begin
       case (cmd_data[7:4])

verilog/sd2snes/dcm.v

@@ -22,8 +22,10 @@ module my_dcm (
          input CLKIN,
          output CLKFX,
          output LOCKED,
+         input CLKFB,
          input RST,
-         output[7:0] STATUS
+         output[7:0] STATUS,
+         output CLK0
     );
 
    // DCM: Digital Clock Manager Circuit
@@ -39,7 +41,7 @@ module my_dcm (
       .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
       .CLKIN_PERIOD(47.000),  // Specify period of input clock
       .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
+      .CLK_FEEDBACK("1X"),  // Specify clock feedback of NONE, 1X or 2X
       .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             //   an integer from 0 to 15
       .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis

verilog/sd2snes/main.v

@@ -114,17 +114,21 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLKFX(CLK2),
                   .LOCKED(DCM_LOCKED),
                   .RST(DCM_RST),
-                  .STATUS(DCM_STATUS)
+                  .STATUS(DCM_STATUS),
+                  .CLKFB(CLKFB),
+                  .CLK0(CLK0)
                 );
-assign DCM_RST = 1'b0;
-                
-/*always @(posedge CLKIN) begin
+reg DCM_RSTr;
+assign DCM_RST = DCM_RSTr;
+assign CLKFB = CLK0;
+wire DCM_FX_STOPPED = DCM_STATUS[2];
+always @(posedge CLKIN) begin
    if(DCM_FX_STOPPED)
-      DCM_RST <= 1'b1;
+      DCM_RSTr <= 1'b1;
    else
-      DCM_RST <= 1'b0;
+      DCM_RSTr <= 1'b0;
 end
-*/
+
 /*reg DO_DCM_RESET, DCM_RESETTING;
 reg DCM_RSTr;
 assign DCM_RST = DCM_RSTr;