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FPGA: more accurate BS-X memory map

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This commit is contained in:
Maximilian Rehkopf 2012-09-24 22:49:54 +02:00
parent 791b688f40
commit 13c24bea9d
2 changed files with 30 additions and 34 deletions
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54
verilog/sd2snes/address.v
View File

@ -101,17 +101,28 @@ assign IS_SAVERAM = SAVERAM_MASK[0]
/* BS-X has 4 MBits of extra RAM that can be mapped to various places */
wire [2:0] BSX_PSRAM_BANK = {bsx_regs[2], bsx_regs[6], bsx_regs[5]};
wire [23:0] BSX_CHKADDR = bsx_regs[2] ? SNES_ADDR : {SNES_ADDR[23], 1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]};
wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
& (( (BSX_CHKADDR[22:20] == BSX_PSRAM_BANK)
&(~SNES_ADDR[15] | ~bsx_regs[2]))
| (bsx_regs[2]
? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
: &SNES_ADDR[22:20]));
wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
|(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
& SNES_ADDR[15];
assign IS_WRITABLE = IS_SAVERAM
|((MAPPER == 3'b011)
?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
|(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
|(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
|(SNES_ADDR[23:19] == 5'b01110)
|(SNES_ADDR[23:21] == 3'b001
&& SNES_ADDR[15:13] == 3'b011)
)
? BSX_IS_PSRAM
: 1'b0);
wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
: {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
@ -142,30 +153,15 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER == 3'b011)
?(IS_SAVERAM
? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE
? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
?( IS_SAVERAM
? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: BSX_IS_CARTROM
? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
: BSX_IS_PSRAM
? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
: bs_page_enable
? (24'h900000 + {bs_page,bs_page_offset})
:((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
?(24'h800000
+ ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& 24'h0FFFFF)
)
:((bsx_regs[1]
? 24'h400000
: 24'h000000
)
+ bsx_regs[2]
?({2'b00, SNES_ADDR[21:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
:({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
)
: BSX_ADDR & ROM_MASK
)
:(MAPPER == 3'b110)
?(IS_SAVERAM

10
verilog/sd2snes/bsx.v
View File

@ -135,8 +135,8 @@ wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55
wire [15:0] rtc_year = (rtc_year100 << 6) + (rtc_year100 << 5) + (rtc_year100 << 2) + rtc_year1;
initial begin
regs_tmpr <= 15'b000000100000000;
regs_outr <= 15'b000000100000000;
regs_tmpr <= 15'b000101111101100;
regs_outr <= 15'b000101111101100;
bsx_counter <= 0;
base_regs[5'h08] <= 0;
base_regs[5'h09] <= 0;
@ -213,7 +213,7 @@ always @(posedge clkin) begin
14: reg_data_outr <= rtc_day;
15: reg_data_outr <= rtc_month;
16: reg_data_outr <= rtc_year[7:0];
17: reg_data_outr <= rtc_year[15:8];
17: reg_data_outr <= rtc_hour;
default: reg_data_outr <= 8'h0;
endcase
end
@ -240,8 +240,8 @@ always @(posedge clkin) begin
regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
end else if(reg_we_rising && cart_enable) begin
if(reg_addr == 4'he && reg_data_in[7])
regs_outr <= regs_tmpr | 15'b100000000000000;
if(reg_addr == 4'he)
regs_outr <= regs_tmpr;
else
regs_tmpr[reg_addr] <= reg_data_in[7];
end else if(reg_we_rising && base_enable) begin