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bugfixes for SD card compatibility in DMA mode

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This commit is contained in:
ikari 2009-12-24 02:19:18 +01:00
parent 63febb92c6
commit 1b65c4fd88
7 changed files with 56 additions and 44 deletions
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14
snes/main.a65
View File

@ -5,9 +5,9 @@ GAME_MAIN:
sep #$20 : .as
jsr snes_init
jsr setup_gfx
jsr colortest
jsr setup_hdma
jsr tests
jsr colortest
sep #$20 : .as
lda #$00
sta @AVR_CMD
@ -154,8 +154,8 @@ snes_init:
stz $2101 ;
stz $2102 ;
stz $2103 ;
stz $2104 ; (OAM Data?!)
stz $2104 ; (OAM Data?!)
; stz $2104 ; (OAM Data?!)
; stz $2104 ; (OAM Data?!)
stz $2105 ;
stz $2106 ;
stz $2107 ;
@ -185,8 +185,8 @@ snes_init:
sta $2115 ;
stz $2116 ;
stz $2117 ;
stz $2118 ;(VRAM Data?!)
stz $2119 ;(VRAM Data?!)
; stz $2118 ;(VRAM Data?!)
; stz $2119 ;(VRAM Data?!)
stz $211a ;
stz $211b ;
lda #$01
@ -202,8 +202,8 @@ snes_init:
stz $2120 ;
stz $2120 ;
stz $2121 ;
stz $2122 ; (CG Data?!)
stz $2122 ; (CG Data?!)
; stz $2122 ; (CG Data?!)
; stz $2122 ; (CG Data?!)
stz $2123 ;
stz $2124 ;
stz $2125 ;

7
src/ff.c
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@ -1504,8 +1504,6 @@ FRESULT f_open (
}
fp->dir_sect = FSBUF.sect; /* Pointer to the directory entry */
/* Moved sync from mode & FA_CREATE_ALWAYS because it can reset FSBUF.sect */
sync(fs); /* not sure if this is needed in all cases, but kept */
fp->dir_ptr = dir;
#endif
fp->flag = mode; /* File access mode */
@ -1516,6 +1514,11 @@ FRESULT f_open (
fp->csect = 1; /* Sector counter */
fp->fs = fs; //fp->id = fs->id; /* Owner file system object of the file */
#if !_FS_READONLY
if (mode & (FA_CREATE_ALWAYS|FA_OPEN_ALWAYS|FA_CREATE_NEW))
sync(fs); /* sync buffer in case the file was just created */
/* can't sync earlier, modifies FSBUF.sect */
#endif
return FR_OK;
}

6
src/main.c
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@ -186,7 +186,8 @@ restart:
while(0) {
SD_SPI_OFFLOAD=1;
sd_read(0, file_buf, 32L, 1);
set_avr_addr(0L);
sd_read(0, file_buf, 8L, 1);
// sram_writeblock((void*)file_buf, 0, 0x200);
sram_hexdump(0,0x10);
uart_putc('+');
@ -264,7 +265,8 @@ restart:
set_rom_mask(0x3fffff); // force mirroring off
uart_putc(')');
uart_putcrlf();
// sram_hexdump(0, 0x200);
// sram_hexdump(0x7ffff0, 0x10);
// sram_hexdump(0, 0x400);
// save_sram((uint8_t*)"/sd2snes/dump", 65536, 0);
sram_writebyte(0, SRAM_CMD_ADDR);

13
src/memory.c
View File

@ -207,18 +207,19 @@ uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
filesize = file_handle.fsize;
if(file_res) return 0;
for(;;) {
FPGA_SS_HIGH();
SPI_SS_LOW();
// FPGA_SS_HIGH();
// SPI_SS_LOW();
SPI_OFFLOAD=1;
bytes_read = file_read();
SPI_SS_HIGH();
// SPI_SS_HIGH();
if (file_res || !bytes_read) break;
FPGA_SS_LOW();
spiTransferByte(0x91);
// FPGA_SS_LOW();
/* spiTransferByte(0x91);
for(int j=0; j<bytes_read; j++) {
spiTransferByte(file_buf[j]);
}
spiTransferByte(0x00); // dummy tx
FPGA_SS_HIGH();
FPGA_SS_HIGH(); // */
}
file_close();
return (uint32_t)filesize;

18
src/sdcard.c
View File

@ -68,7 +68,7 @@
#include "spi.h"
#include "uart.h"
#include "sdcard.h"
#include "fpga_spi.h"
#ifndef TRUE
#define TRUE -1
#endif
@ -540,6 +540,7 @@ DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
if (res != 0) {
uart_putc('?');
dprintf("SD error: %02x\n", res);
SPI_SS_HIGH(drv);
disk_state = DISK_ERROR;
return RES_ERROR;
@ -565,19 +566,18 @@ DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
// uart_putc('O');
PORTB |= _BV(PB2);
DDRB |= _BV(PB2);
_delay_us(1);
PORTB &= ~_BV(PB2);
PORTB |= _BV(PB2);
PORTB &= ~_BV(PB7);
DDRB &= ~_BV(PB7); // tristate SCK
// SPCR=0;
PORTB |= _BV(PB2);
DDRB &= ~_BV(PB2);
_delay_us(1);
loop_until_bit_is_set(PINB, PB2);
DDRB |= _BV(PB2);
// SPCR=0b01010000;
SD_SPI_OFFLOAD = 0;
deselectCard(drv);
while(!(PINB & _BV(PB2)));
DDRB |= _BV(PB7);
DDRB |= _BV(PB2);
// _delay_us(1);
deselectCard(drv);
SD_SPI_OFFLOAD = 0;
return RES_OK;
SPDR = 0xff;
} else {

4
verilog/sd2snes/main.ucf
View File

@ -188,5 +188,7 @@ NET "SRAM_OE" IOSTANDARD = LVCMOS33;
NET "SRAM_WE" IOSTANDARD = LVCMOS33;
NET "SPI_DMA_CTRL" LOC = P41;
NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33;
NET "SPI_DMA_CTRL" PULLUP;
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
NET "SPI_SCK" PULLDOWN;
NET "SPI_SCK" DRIVE = 16;
NET "SPI_SCK" PULLUP;

38
verilog/sd2snes/spi_dma.v
View File

@ -41,7 +41,7 @@ reg [9:0] spi_dma_bytecnt;
reg [3:0] spi_dma_clkcnt;
reg [3:0] spi_dma_sck_int_r;
reg [5:0] spi_dma_trig_r;
reg [1:0] spi_dma_miso_r;
reg [4:0] spi_dma_miso_r;
reg spi_dma_sck_out_r;
reg spi_dma_sck_out_r2;
@ -62,23 +62,24 @@ end
// synthesize clock
wire spi_dma_sck_int = spi_dma_clkcnt[1];
assign spi_dma_sck = spi_dma_sck_out_r & spi_dma_sck_out_r2;
always @(posedge clk) begin
spi_dma_clkcnt <= spi_dma_clkcnt + 1;
spi_dma_sck_int_r <= {spi_dma_sck_int_r[2:0], spi_dma_sck_int};
spi_dma_trig_r <= {spi_dma_trig_r[4:0], spi_dma_trig};
spi_dma_miso_r <= {spi_dma_miso_r[0], spi_dma_miso};
spi_dma_miso_r <= {spi_dma_miso_r[3:0], spi_dma_miso};
end
wire spi_dma_trig_rising = (spi_dma_trig_r[5:1] == 5'b00011);
wire spi_dma_trig_falling = (spi_dma_trig_r[5:1] == 5'b11100);
wire spi_dma_sck_rising = (spi_dma_sck_int_r[1:0] == 2'b01);
wire spi_dma_sck_falling = (spi_dma_sck_int_r[1:0] == 2'b10);
wire spi_dma_sck_rising2 = (spi_dma_sck_int_r[1:0] == 2'b01);
wire spi_dma_sck_falling2 = (spi_dma_sck_int_r[1:0] == 2'b10);
wire spi_dma_sck_rising = (spi_dma_sck_int_r[2:1] == 2'b01);
wire spi_dma_sck_falling = (spi_dma_sck_int_r[2:1] == 2'b10);
wire spi_dma_sck_rising2 = (spi_dma_sck_int_r[2:1] == 2'b01);
wire spi_dma_sck_falling2 = (spi_dma_sck_int_r[2:1] == 2'b10);
assign spi_dma_nextaddr = spi_dma_nextaddr_r;
assign spi_dma_nextaddr = spi_dma_nextaddr_r & (spi_dma_bytecnt < 512);
assign spi_dma_sram_data = spi_dma_sram_data_r;
assign spi_dma_sram_we = spi_dma_sram_we_r;
assign spi_dma_sram_we = spi_dma_sram_we_r | (spi_dma_bytecnt > 511);
assign spi_dma_done = spi_dma_done_r;
assign spi_dma_ovr = spi_dma_ovr_r;
@ -86,7 +87,7 @@ always @(posedge clk) begin
if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
spi_dma_done_r <= 0;
spi_dma_ovr_r <= 1;
end else if (spi_dma_bitcnt == 0 && spi_dma_bytecnt == 512) begin
end else if (spi_dma_bitcnt == 0 && spi_dma_bytecnt == 514) begin
spi_dma_done_r <= 1;
spi_dma_ovr_r <= 0;
end
@ -99,30 +100,33 @@ always @(posedge clk) begin
spi_dma_sck_out_r2 <= 1;
end
always @(posedge clk) begin
if (spi_dma_sck_rising & spi_dma_ovr_r & spi_dma_bitcnt < 8)
spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso};
end
// fetch a little later
//always @(posedge spi_dma_sck) begin
// if (/*spi_dma_sck_rising & */spi_dma_ovr_r & spi_dma_bitcnt <= 8)
// spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
//end
always @(posedge clk) begin
if(spi_dma_sck_rising & spi_dma_ovr_r) begin
if (spi_dma_bitcnt < 8) begin
spi_dma_sck_out_r <= 1;
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
end else if (spi_dma_bitcnt == 8) begin
spi_dma_sck_out_r <= 0;
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
spi_dma_sram_we_r <= 0;
spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
end else if (spi_dma_bitcnt == 9) begin
spi_dma_sck_out_r <= 0;
spi_dma_sram_we_r <= 1;
spi_dma_bytecnt <= spi_dma_bytecnt + 1;
spi_dma_sram_we_r <= 0;
spi_dma_bitcnt <= 10;
end else if (spi_dma_bitcnt == 10) begin
spi_dma_sram_we_r <= 1;
spi_dma_nextaddr_r <= 1;
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
end else if (spi_dma_bitcnt == 11) begin
spi_dma_nextaddr_r <= 0;
spi_dma_bytecnt <= spi_dma_bytecnt + 1;
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
end else if (spi_dma_bitcnt == 12) begin
spi_dma_bitcnt <= 0;
@ -134,7 +138,7 @@ always @(posedge clk) begin
end else if (spi_dma_bitcnt == 4'b1111) begin
spi_dma_bitcnt <= 0;
end
end else if (spi_dma_sck_rising & !spi_dma_ovr_r) begin
end else if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
spi_dma_bitcnt <= 4'b1101;
spi_dma_bytecnt <= 10'b0000000000;
end