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Merge branch 'master' of ssh://shion.micecat.ath.cx/~ikari/public_html/git/sd2snes

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This commit is contained in:
Maximilian Rehkopf 2009-09-15 09:53:43 +02:00
commit 28428019f5
11 changed files with 108 additions and 150 deletions
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71
src/crc16.c
View File

@ -2,20 +2,59 @@
* \file stdout
* Functions and types for CRC checks.
*
* Generated on Tue Jun 30 23:02:59 2009,
* Generated on Tue Sep 15 09:32:35 2009,
* by pycrc v0.7.1, http://www.tty1.net/pycrc/
* using the configuration:
* Width = 16
* Poly = 0x8005
* XorIn = 0x0000
* XorIn = 0xffff
* ReflectIn = True
* XorOut = 0x0000
* XorOut = 0xffff
* ReflectOut = True
* Algorithm = bit-by-bit-fast
* Algorithm = table-driven
* Direct = True
*****************************************************************************/
#include <stdint.h>
#include "crc16.h"
#include <stdint.h>
/**
* Static table used for the table_driven implementation.
*****************************************************************************/
static const crc_t crc_table[256] = {
0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241,
0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440,
0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40,
0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841,
0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40,
0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41,
0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641,
0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040,
0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240,
0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441,
0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41,
0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840,
0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41,
0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40,
0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640,
0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041,
0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240,
0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441,
0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41,
0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840,
0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41,
0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40,
0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640,
0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041,
0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241,
0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440,
0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40,
0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841,
0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40,
0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41,
0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641,
0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040
};
/**
* Update the crc value with new data.
*
@ -26,26 +65,14 @@
*****************************************************************************/
crc_t crc16_update(crc_t crc, const unsigned char *data, size_t data_len)
{
unsigned int i;
uint8_t bit;
unsigned char c;
unsigned int tbl_idx;
while (data_len--) {
c = *data++;
for (i = 0x01; i & 0xff; i <<= 1) {
bit = (crc & 0x8000 ? 1 : 0);
if (c & i) {
bit ^= 1;
}
crc <<= 1;
if (bit) {
crc ^= 0x8005;
}
}
crc &= 0xffff;
tbl_idx = (crc ^ *data) & 0xff;
crc = (crc_table[tbl_idx] ^ (crc >> 8)) & 0xffff;
data++;
}
return crc & 0xffff;
}

24
src/main.c
View File

@ -129,17 +129,9 @@ int main(void) {
clock_prescale_set(CLOCK_PRESCALE);
#endif
/* BUSY_LED_SETDDR();
DIRTY_LED_SETDDR();
AUX_LED_SETDDR();
AUX_LED_OFF();
set_busy_led(1);
set_dirty_led(0);
*/
snes_reset(1);
uart_init();
sei();
// sei(); // interrupts are bad for now, resets the poor AVR when inserting SD card
_delay_ms(100);
disk_init();
snes_init();
@ -151,19 +143,14 @@ int main(void) {
FATFS fatfs;
f_mount(0,&fatfs);
set_busy_led(0);
set_busy_led(1);
uart_putc('W');
fpga_init();
fpga_pgm("/sd2snes/main.bit");
fpga_spi_init();
uart_putc('!');
_delay_ms(100);
//set_avr_bank(0);
set_avr_ena(0);
// set_avr_read(1);
// set_avr_write(1);
// AVR_ADDR_RESET();
// set_avr_addr_en(0);
snes_reset(1);
uart_putc('(');
@ -197,8 +184,13 @@ while(1) {
spiTransferByte(0x81); // read w/ increment... hopefully
spiTransferByte(0x00); // 1 dummy read
uart_putcrlf();
for(uint8_t cnt=0; cnt<16; cnt++) {
uint8_t buff[21];
for(uint8_t cnt=0; cnt<21; cnt++) {
uint8_t data=spiTransferByte(0x00);
buff[cnt]=data;
}
for(uint8_t cnt=0; cnt<21; cnt++) {
uint8_t data = buff[cnt];
_delay_ms(2);
if(data>=0x20 && data <= 0x7a) {
uart_putc(data);

15
src/memory.c
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@ -46,9 +46,8 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
}
uint32_t load_rom(char* filename) {
// TODO Mapper, Mirroring, Bankselect
snes_romprops_t romprops;
// set_avr_bank(0);
set_avr_bank(0);
UINT bytes_read;
DWORD filesize;
UINT count=0;
@ -163,12 +162,12 @@ void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr) {
}
uint32_t calc_sram_crc(uint32_t size) {
uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
uint8_t data;
uint32_t count;
uint16_t crc;
crc=0;
set_avr_bank(3);
set_avr_addr(base_addr);
SPI_SS_HIGH();
FPGA_SS_HIGH();
FPGA_SS_LOW();
@ -176,16 +175,8 @@ uint32_t calc_sram_crc(uint32_t size) {
spiTransferByte(0x00);
for(count=0; count<size; count++) {
data = spiTransferByte(0);
/* uart_putc(hex[(data>>4)]);
uart_putc(hex[data&0xf]);
uart_putc(' ');
_delay_ms(2);*/
crc += crc16_update(crc, &data, 1);
}
FPGA_SS_HIGH();
/* uart_putc(hex[(crc>>28)&0xf]);
uart_putc(hex[(crc>>24)&0xf]);
uart_putc(hex[(crc>>20)&0xf]);
uart_putc(hex[(crc>>16)&0xf]); */
return crc;
}

2
src/memory.h
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@ -6,5 +6,5 @@
uint32_t load_rom(char* filename);
uint32_t load_sram(char* filename);
void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr);
uint32_t calc_sram_crc(uint32_t size);
uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size);
#endif

20
src/snes.c
View File

@ -14,9 +14,9 @@
uint8_t initloop=1;
uint32_t sram_crc, sram_crc_old;
uint32_t sram_size = 8192; // sane default
uint32_t sram_base_addr = 0x600000; // chip 3
uint32_t saveram_crc, saveram_crc_old;
uint32_t saveram_size = 8192; // sane default
uint32_t saveram_base_addr = 0x600000; // chip 3
void snes_init() {
DDRD |= _BV(PD5); // PD5 = RESET_DIR
DDRD |= _BV(PD6); // PD6 = RESET
@ -46,18 +46,18 @@ void snes_reset(int state) {
*/
void snes_main_loop() {
if(initloop) {
sram_crc_old = calc_sram_crc(sram_size);
save_sram("/test.srm", sram_size, sram_base_addr);
saveram_crc_old = calc_sram_crc(saveram_base_addr, saveram_size);
save_sram("/test.srm", saveram_size, saveram_base_addr);
initloop=0;
}
sram_crc = calc_sram_crc(sram_size);
if(sram_crc != sram_crc_old) {
saveram_crc = calc_sram_crc(saveram_base_addr, saveram_size);
if(saveram_crc != saveram_crc_old) {
uart_putc('U');
uart_puthexlong(sram_crc);
uart_puthexshort(saveram_crc);
uart_putcrlf();
set_busy_led(1);
save_sram("/test.srm", sram_size, sram_base_addr);
save_sram("/test.srm", saveram_size, saveram_base_addr);
set_busy_led(0);
}
sram_crc_old = sram_crc;
saveram_crc_old = saveram_crc;
}

6
src/uart.c
View File

@ -79,6 +79,12 @@ void uart_puthexlong(uint32_t num) {
uart_puthex(num&0xff);
}
void uart_puthexshort(uint16_t num) {
uart_puthex((num>>8)&0xff);
uart_puthex(num&0xff);
}
void uart_trace(void *ptr, uint16_t start, uint16_t len) {
uint16_t i;
uint8_t j;

1
src/uart.h
View File

@ -36,6 +36,7 @@ unsigned char uart_getc(void);
void uart_putc(char c);
void uart_puthex(uint8_t num);
void uart_puthexlong(uint32_t num);
void uart_puthexshort(uint16_t num);
void uart_trace(void *ptr, uint16_t start, uint16_t len);
void uart_flush(void);
void uart_puts_P(prog_char *text);

12
verilog/sd2snes/address.v
View File

@ -56,6 +56,7 @@ end
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM
*/
/* HiROM: SRAM @ Bank 0x20-0x3f, 0xa0-0xbf
@ -65,8 +66,9 @@ assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010) ? (!SNES_ADDR[22]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7f, 0xf0-0xff
Offset 0000-7fff */
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
Offset 0000-7fff TODO: 0000-ffff for
small ROMs */
:(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15]
@ -78,8 +80,7 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
|(SNES_ADDR[22]))
: (MAPPER == 3'b001) ? ( (SNES_ADDR[15] & !SNES_ADDR[22])
|(SNES_ADDR[22]))
: (MAPPER == 3'b010) ? ( (!SNES_ADDR[22]
& SNES_ADDR[15])
: (MAPPER == 3'b010) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: 1'b0);
@ -89,7 +90,7 @@ assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
: (SNES_ADDR[22:0] & ROM_MASK))
:(MAPPER == 3'b001) ?
(IS_SAVERAM ? SNES_ADDR[14:0] & SAVERAM_MASK
: {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK)
: ({1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
:(MAPPER == 3'b010) ?
(IS_SAVERAM ? (SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK
: ({!SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
@ -99,7 +100,6 @@ assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
assign SRAM_ADDR = SRAM_ADDR_FULL[20:1];
assign ROM_SEL = (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
// assign ROM_SEL = 4'b0001;
assign SRAM_ADDR0 = SRAM_ADDR_FULL[0];

19
verilog/sd2snes/data.v
View File

@ -51,7 +51,6 @@ assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]);
assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE)
: (AVR_OUT_MEM);
// XXX assign SRAM_DATA = (SRAM_BHE ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ});
assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ)
: (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)))
@ -70,22 +69,4 @@ always @(posedge CLK) begin
AVR_OUT_MEM <= FROM_SRAM_BYTE;
end
/*
always @(posedge SNES_DATA_TO_MEM) begin
SNES_IN_MEM <= SNES_DATA;
end
always @(posedge AVR_DATA_TO_MEM) begin
AVR_IN_MEM <= AVR_DATA;
end
always @(posedge SRAM_DATA_TO_SNES_MEM) begin
SNES_OUT_MEM <= SRAM_DATA;
end
always @(posedge SRAM_DATA_TO_AVR_MEM) begin
AVR_OUT_MEM <= SRAM_DATA;
end
*/
endmodule

70
verilog/sd2snes/main.v
View File

@ -116,50 +116,18 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
.RST(DCM_RST)
);
my_dcm2 snes_dcm2(.CLKIN(CLK2),
.CLKFB(CLKFB2),
.CLKFX(FASTCLK),
.CLK0(CLK0_2));
assign CLKFB2 = CLK0_2;
/*
reg DCM_RESET_ACK;
reg DCM_RST_BUF;
reg [1:0] DCM_LOCKEDr;
assign DCM_RST = DCM_RST_BUF;
assign DCM_FAIL = (DCM_LOCKEDr == 2'b10);
always @(posedge CLKIN) begin
DCM_LOCKEDr <= {DCM_LOCKEDr[0], DCM_LOCKED};
end
always @(posedge CLKIN) begin
if (DCM_FAIL) begin
DCM_RST_BUF <= 1;
end else begin
DCM_RST_BUF <= 0;
end
end*/
/*my_dcm snes_dcm2(.CLKIN(CLK),
.CLK2X(CLK2),
.CLKFB(CLKFB2),
.CLKFX(CLKFX2)
);*/
//assign CLKFB = CLK0;
//assign CLKFB2 = CLK2;
wire SNES_RW;
reg [1:0] SNES_READr;
reg [1:0] SNES_WRITEr;
reg [1:0] SNES_CSr;
reg [1:0] SNES_CPU_CLKr;
reg [3:0] SNES_RWr;
reg [7:0] SNES_RWr;
wire SNES_READs = (SNES_READr == 2'b11);
wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
wire SNES_CSs = (SNES_CSr == 2'b11);
wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
wire SNES_RW_start = (SNES_RWr == 4'b1110); // falling edge marks beginning of cycle
wire SNES_RW_start = (SNES_RWr == 8'b11111110); // falling edge marks beginning of cycle
assign SNES_RW = (SNES_READ & SNES_WRITE);
@ -168,7 +136,7 @@ always @(posedge CLK2) begin
SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
SNES_CSr <= {SNES_CSr[0], SNES_CS};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[0], SNES_CPU_CLK};
SNES_RWr <= {SNES_RWr[2:0], SNES_RW};
SNES_RWr <= {SNES_RWr[6:0], SNES_RW};
end
reg ADDR_WRITE;
@ -177,7 +145,7 @@ address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_CS(SNES_CSs), // "CART" pin from SNES (active low)
.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
.SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low)
.ROM_SEL(SRAM_CE2), // which SRAM unit to access
.AVR_ENA(AVR_ENA), // enable AVR mode (active low)
@ -191,8 +159,8 @@ address snes_addr(
);
data snes_data(.CLK(CLK2),
.SNES_READ(SNES_READs),
.SNES_WRITE(SNES_WRITEs),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.AVR_READ(AVR_READ),
.AVR_WRITE(AVR_WRITE),
.SNES_DATA(SNES_DATA),
@ -222,7 +190,7 @@ parameter STATE_7 = 10'b0010000000;
parameter STATE_8 = 10'b0100000000;
parameter STATE_9 = 10'b1000000000;
reg [10:0] STATE;
reg [9:0] STATE;
reg [3:0] STATEIDX;
reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
@ -284,7 +252,7 @@ initial begin
SNES_DATA_TO_MEM_ARRAY[1'b0] = 10'b1000000000;
SNES_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000100000;
AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000010000;
AVR_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000;
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 10'b0000000000;
@ -296,29 +264,23 @@ end
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
// SNES READ or WRITE always starts @posedge CLK !!
// CPU cycle can be 6, 8 or 12 CLK cycles so we must satisfy
// the minimum of 6 cycles to get everything done.
// CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
// the minimum of 6 SNES cycles to get everything done.
// we have 24 internal cycles to work with. (CLKIN * 4)
reg [1:0] CYCLE_RESET;
always @(posedge CLK2) begin
if (SNES_RW_start /* || !AVR_ENA */) //begin
// if (!CYCLE_RESET_ACK)
CYCLE_RESET <= 1;
else
CYCLE_RESET <= 0;
// end
CYCLE_RESET <= {CYCLE_RESET[0], SNES_RW_start};
end
always @(posedge CLK2) begin
if (SNES_RW_start/* && !CYCLE_RESET_ACK*/) begin
// CYCLE_RESET_ACK <= 1;
if (CYCLE_RESET[1]) begin
STATE <= STATE_0;
SNES_READ_CYCLE <= SNES_READ;
SNES_WRITE_CYCLE <= SNES_WRITE;
AVR_READ_CYCLE <= AVR_READ;
AVR_WRITE_CYCLE <= AVR_WRITE;
// end else if (!DCM_LOCKED) begin
// CYCLE_RESET_ACK <= 0; // ready for new cycle
end else begin
case (STATE)
STATE_0:
@ -340,8 +302,6 @@ always @(posedge CLK2) begin
STATE_8:
STATE <= STATE_9;
STATE_9: begin
if (SNES_RW /* || !AVR_ENA */) // check for end of SNES cycle to avoid looping
CYCLE_RESET_ACK <= 0; // ready for new cycle
STATE <= STATE_9;
end
default:

2
verilog/sd2snes/sd2snes.xise
View File

@ -62,8 +62,8 @@
<library xil_pn:name="verilog"/>
</file>
<file xil_pn:name="dcm2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
</files>