Firmware: preparations for USB
This commit is contained in:
parent
4ff823078f
commit
28949ac307
40
src/clock.c
40
src/clock.c
@ -52,6 +52,15 @@ void clock_init() {
|
||||
enablePLL0();
|
||||
setCCLKDiv(6);
|
||||
connectPLL0();
|
||||
|
||||
|
||||
/* configure PLL1 for USB operation */
|
||||
disconnectPLL1();
|
||||
disablePLL1();
|
||||
LPC_SC->PLL1CFG = 0x23;
|
||||
enablePLL1();
|
||||
connectPLL1();
|
||||
|
||||
}
|
||||
|
||||
void setFlashAccessTime(uint8_t clocks) {
|
||||
@ -84,6 +93,32 @@ void disconnectPLL0() {
|
||||
PLL0feed();
|
||||
}
|
||||
|
||||
void setPLL1MultPrediv(uint16_t mult, uint8_t prediv) {
|
||||
LPC_SC->PLL1CFG=PLL_MULT(mult) | PLL_PREDIV(prediv);
|
||||
PLL1feed();
|
||||
}
|
||||
|
||||
void enablePLL1() {
|
||||
LPC_SC->PLL1CON |= PLLE1;
|
||||
PLL1feed();
|
||||
}
|
||||
|
||||
void disablePLL1() {
|
||||
LPC_SC->PLL1CON &= ~PLLE1;
|
||||
PLL1feed();
|
||||
}
|
||||
|
||||
void connectPLL1() {
|
||||
while(!(LPC_SC->PLL1STAT & PLOCK1));
|
||||
LPC_SC->PLL1CON |= PLLC1;
|
||||
PLL1feed();
|
||||
}
|
||||
|
||||
void disconnectPLL1() {
|
||||
LPC_SC->PLL1CON &= ~PLLC1;
|
||||
PLL1feed();
|
||||
}
|
||||
|
||||
void setCCLKDiv(uint8_t div) {
|
||||
LPC_SC->CCLKCFG=CCLK_DIV(div);
|
||||
}
|
||||
@ -102,6 +137,11 @@ void PLL0feed() {
|
||||
LPC_SC->PLL0FEED=0x55;
|
||||
}
|
||||
|
||||
void PLL1feed() {
|
||||
LPC_SC->PLL1FEED=0xaa;
|
||||
LPC_SC->PLL1FEED=0x55;
|
||||
}
|
||||
|
||||
void setClkSrc(uint8_t src) {
|
||||
LPC_SC->CLKSRCSEL=src;
|
||||
}
|
||||
|
||||
17
src/clock.h
17
src/clock.h
@ -8,6 +8,9 @@
|
||||
#define PLLE0 (1<<0)
|
||||
#define PLLC0 (1<<1)
|
||||
#define PLOCK0 (1<<26)
|
||||
#define PLLE1 (1<<0)
|
||||
#define PLLC1 (1<<1)
|
||||
#define PLOCK1 (1<<10)
|
||||
#define OSCEN (1<<5)
|
||||
#define OSCSTAT (1<<6)
|
||||
#define FLASHTIM(x) (((x-1)<<12)|0x3A)
|
||||
@ -56,14 +59,18 @@ void clock_init(void);
|
||||
void setFlashAccessTime(uint8_t clocks);
|
||||
|
||||
void setPLL0MultPrediv(uint16_t mult, uint8_t prediv);
|
||||
|
||||
void enablePLL0(void);
|
||||
|
||||
void disablePLL0(void);
|
||||
|
||||
void connectPLL0(void);
|
||||
|
||||
void disconnectPLL0(void);
|
||||
void PLL0feed(void);
|
||||
|
||||
void setPLL1MultPrediv(uint16_t mult, uint8_t prediv);
|
||||
void enablePLL1(void);
|
||||
void disablePLL1(void);
|
||||
void connectPLL1(void);
|
||||
void disconnectPLL1(void);
|
||||
void PLL1feed(void);
|
||||
|
||||
void setCCLKDiv(uint8_t div);
|
||||
|
||||
@ -71,7 +78,5 @@ void enableMainOsc(void);
|
||||
|
||||
void disableMainOsc(void);
|
||||
|
||||
void PLL0feed(void);
|
||||
|
||||
void setClkSrc(uint8_t src);
|
||||
#endif
|
||||
|
||||
@ -96,4 +96,7 @@
|
||||
|
||||
#define SD_DAT (LPC_GPIO2->FIOPIN0)
|
||||
|
||||
#define USB_CONNREG LPC_GPIO4
|
||||
#define USB_CONNBIT 28
|
||||
|
||||
#endif
|
||||
|
||||
@ -21,6 +21,6 @@ void power_init() {
|
||||
| BV(PCRTC)
|
||||
| BV(PCGPIO)
|
||||
| BV(PCPWM1)
|
||||
// | BV(PCUSB)
|
||||
| BV(PCUSB)
|
||||
;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user