diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v
index e62071d..c2502d3 100644
--- a/verilog/sd2snes_cx4/address.v
+++ b/verilog/sd2snes_cx4/address.v
@@ -21,6 +21,7 @@ module address(
   input CLK,
   input [2:0] MAPPER,       // MCU detected mapper
   input [23:0] SNES_ADDR,   // requested address from SNES
+  input SNES_CS,            // SNES ROMSEL signal
   output [23:0] ROM_ADDR,   // Address to request from SRAM0
   output ROM_SEL,           // enable SRAM0 (active low)
   output IS_SAVERAM,        // address/CS mapped as SRAM?
@@ -30,7 +31,8 @@ module address(
   input [23:0] ROM_MASK,
   input use_msu1,
   output msu_enable,
-  output cx4_enable
+  output cx4_enable,
+  output cx4_vect_enable
 );
 
 wire [23:0] SRAM_SNES_ADDR;
@@ -40,7 +42,7 @@ wire [23:0] SRAM_SNES_ADDR;
 	 - MMIO @ 6000-7fff
  */
 
-assign IS_ROM = (SNES_ADDR[15]);
+assign IS_ROM = SNES_ADDR[15] & ~SNES_CS;
 
 assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
                                & ROM_MASK);
@@ -61,4 +63,5 @@ initial cx4_enable_r = 6'b000000;
 always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w};
 assign cx4_enable = &cx4_enable_r[5:2];
 
+assign cx4_vect_enable = &SNES_ADDR[15:5];
 endmodule
diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v
index 06d943d..6afdbea 100644
--- a/verilog/sd2snes_cx4/cx4.v
+++ b/verilog/sd2snes_cx4/cx4.v
@@ -23,6 +23,7 @@ module cx4(
   output [7:0] DO,
   input [12:0] ADDR,
   input CS,
+  input SNES_VECT_EN,
   input nRD,
   input nWR,
   input CLK,
@@ -44,7 +45,7 @@ parameter BUSY_CPU   = 2'b10;
 wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
 wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011);
 wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011);
-wire vector_enable = CS & (ADDR[12:5] == 8'b11111011);
+wire vector_enable = (CS & (ADDR[12:5] == 8'b11111011)) | (cx4_active & SNES_VECT_EN);
 wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
 wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
 
diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v
index 182b861..ff82ab7 100644
--- a/verilog/sd2snes_cx4/main.v
+++ b/verilog/sd2snes_cx4/main.v
@@ -268,6 +268,7 @@ address snes_addr(
   .CLK(CLK2),
   .MAPPER(MAPPER),
   .SNES_ADDR(SNES_ADDR), // requested address from SNES
+  .SNES_CS(SNES_CS),
   .ROM_ADDR(MAPPED_SNES_ADDR),   // Address to request from SRAM (active low)
   .ROM_SEL(ROM_SEL),     // which SRAM unit to access
   .IS_SAVERAM(IS_SAVERAM),
@@ -279,7 +280,8 @@ address snes_addr(
   //MSU-1
   .msu_enable(msu_enable),
   //CX4
-  .cx4_enable(cx4_enable)
+  .cx4_enable(cx4_enable),
+  .cx4_vect_enable(cx4_vect_enable)
 );
 
 reg [7:0] CX4_DINr;
@@ -290,6 +292,7 @@ cx4 snes_cx4 (
     .DO(CX4_SNES_DATA_OUT), 
     .ADDR(SNES_ADDR[12:0]),
     .CS(cx4_enable), 
+    .SNES_VECT_EN(cx4_vect_enable),
     .nRD(SNES_READ), 
     .nWR(SNES_WRITE), 
     .CLK(CLK2), 
@@ -344,9 +347,12 @@ assign CX4_SNES_DATA_IN = SNES_DATA;
 reg [7:0] SNES_DINr;
 reg [7:0] ROM_DOUTr;
 
-assign SNES_DATA = (!SNES_READ) ? (msu_enable ? MSU_SNES_DATA_OUT
+assign SNES_DATA = (!SNES_READ) 
+                    ? (msu_enable ? MSU_SNES_DATA_OUT
 											 :cx4_enable ? CX4_SNES_DATA_OUT
-                                  :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
+                       :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
+                       : SNES_DINr)
+                    : 8'bZ;
 
 reg [3:0] ST_MEM_DELAYr;
 reg MCU_RD_PENDr;
@@ -559,8 +565,8 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
 
 assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
                          cx4_enable ? 1'b0 :
-                         ((IS_ROM & SNES_CS)
-                          |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
+                         (cx4_active & cx4_vect_enable) ? 1'b0 :
+                         ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
                           |(SNES_READ & SNES_WRITE)
                          );