diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v index a7413c2..eb755e9 100644 --- a/verilog/sd2snes/address.v +++ b/verilog/sd2snes/address.v @@ -38,7 +38,9 @@ module address( output msu_enable, output srtc_enable, output use_bsx, - input [14:0] bsx_regs + input [14:0] bsx_regs, + output dspx_enable, + output dspx_a0 ); wire [1:0] SRAM_BANK; @@ -154,4 +156,8 @@ assign use_bsx = (MAPPER == 3'b011); assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800)); +// DSP1 1mb lorom: DR=20-3f:8000-bfff; SR=20-3f:c000-ffff +assign dspx_enable = (MAPPER == 3'b001) && (!SNES_ADDR[22] && SNES_ADDR[21] && (SNES_ADDR[15] == 1'b1)); +assign dspx_a0 = SNES_ADDR[14]; + endmodule diff --git a/verilog/sd2snes/bsx.v b/verilog/sd2snes/bsx.v index a2ec578..1047220 100644 --- a/verilog/sd2snes/bsx.v +++ b/verilog/sd2snes/bsx.v @@ -63,8 +63,8 @@ assign data_ovr = cart_enable | base_enable | flash_ovr; reg [5:0] reg_oe_sreg; always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; -wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000); -wire reg_oe_rising = (reg_oe_sreg[5:0] == 6'b000001); +wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); +wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001); reg [1:0] reg_we_sreg; always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we}; diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v index 86ef904..c34130f 100644 --- a/verilog/sd2snes/data.v +++ b/verilog/sd2snes/data.v @@ -41,9 +41,12 @@ module data( input [7:0] BSX_DATA_OUT, output [7:0] SRTC_DATA_IN, input [7:0] SRTC_DATA_OUT, + output [7:0] DSPX_DATA_IN, + input [7:0] DSPX_DATA_OUT, input msu_enable, input bsx_data_ovr, - input srtc_enable + input srtc_enable, + input dspx_enable ); reg [7:0] SNES_IN_MEM; @@ -56,10 +59,12 @@ wire [7:0] FROM_ROM_BYTE; assign MSU_DATA_IN = SNES_DATA; assign BSX_DATA_IN = SNES_DATA; assign SRTC_DATA_IN = SNES_DATA; +assign DSPX_DATA_IN = SNES_DATA; assign SNES_DATA = SNES_READ ? 8'bZ : (!MCU_OVR ? 8'h00 : (msu_enable ? MSU_DATA_OUT : bsx_data_ovr ? BSX_DATA_OUT : - srtc_enable ? SRTC_DATA_OUT : SNES_OUT_MEM)); + srtc_enable ? SRTC_DATA_OUT : + dspx_enable ? DSPX_DATA_OUT : SNES_OUT_MEM)); assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]); diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.v b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v new file mode 100644 index 0000000..360df18 --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v @@ -0,0 +1,141 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file upd77c25_datram.v when simulating +// the core, upd77c25_datram. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module upd77c25_datram( + clka, + wea, + addra, + dina, + douta); + + +input clka; +input [0 : 0] wea; +input [7 : 0] addra; +input [15 : 0] dina; +output [15 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V4_3 #( + .C_ADDRA_WIDTH(8), + .C_ADDRB_WIDTH(8), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(0), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(256), + .C_READ_DEPTH_B(256), + .C_READ_WIDTH_A(16), + .C_READ_WIDTH_B(16), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(256), + .C_WRITE_DEPTH_B(256), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(16), + .C_WRITE_WIDTH_B(16), + .C_XDEVICEFAMILY("spartan3")) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .RSTA(), + .ENA(), + .REGCEA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of upd77c25_datram is "black_box" + +endmodule + diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco new file mode 100644 index 0000000..40d55fd --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco @@ -0,0 +1,66 @@ +############################################################## +############################################################## +############################################################## +SET designentry = Verilog +SET BusFormat = BusFormatAngleBracketNotRipped +SET devicefamily = spartan3 +SET device = xc3s400 +SET package = pq208 +SET speedgrade = -4 +SET FlowVendor = Foundation_ISE +SET VerilogSim = True +SET VHDLSim = True +SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3 +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=upd77c25_datram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET load_init_file=false +CSET memory_type=Single_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=16 +CSET read_width_b=16 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=256 +CSET write_width_a=16 +CSET write_width_b=16 diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v new file mode 100644 index 0000000..54e57b7 --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.v @@ -0,0 +1,145 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file upd77c25_datrom.v when simulating +// the core, upd77c25_datrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module upd77c25_datrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb); + + +input clka; +input [0 : 0] wea; +input [9 : 0] addra; +input [15 : 0] dina; +input clkb; +input [9 : 0] addrb; +output [15 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V4_3 #( + .C_ADDRA_WIDTH(10), + .C_ADDRB_WIDTH(10), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("upd77c25_datrom.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(1024), + .C_READ_DEPTH_B(1024), + .C_READ_WIDTH_A(16), + .C_READ_WIDTH_B(16), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(1024), + .C_WRITE_DEPTH_B(1024), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(16), + .C_WRITE_WIDTH_B(16), + .C_XDEVICEFAMILY("spartan3")) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of upd77c25_datrom is "black_box" + +endmodule + diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco new file mode 100644 index 0000000..0456fb0 --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco @@ -0,0 +1,93 @@ +############################################################## +# +# Xilinx Core Generator version 12.3 +# Date: Mon May 30 11:59:50 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET byte_size=9 +CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_datrom.coe +CSET collision_warnings=ALL +CSET component_name=upd77c25_datrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET load_init_file=true +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=16 +CSET read_width_b=16 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=1024 +CSET write_width_a=16 +CSET write_width_b=16 +# END Parameters +GENERATE +# CRC: 2baeb226 diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v new file mode 100644 index 0000000..eeef4b6 --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v @@ -0,0 +1,145 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file upd77c25_pgmrom.v when simulating +// the core, upd77c25_pgmrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module upd77c25_pgmrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb); + + +input clka; +input [0 : 0] wea; +input [10 : 0] addra; +input [23 : 0] dina; +input clkb; +input [10 : 0] addrb; +output [23 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V4_3 #( + .C_ADDRA_WIDTH(11), + .C_ADDRB_WIDTH(11), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("upd77c25_pgmrom.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(2048), + .C_READ_DEPTH_B(2048), + .C_READ_WIDTH_A(24), + .C_READ_WIDTH_B(24), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(2048), + .C_WRITE_DEPTH_B(2048), + .C_WRITE_MODE_A("NO_CHANGE"), + .C_WRITE_MODE_B("NO_CHANGE"), + .C_WRITE_WIDTH_A(24), + .C_WRITE_WIDTH_B(24), + .C_XDEVICEFAMILY("spartan3")) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of upd77c25_pgmrom is "black_box" + +endmodule + diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco new file mode 100644 index 0000000..f1ff6ce --- /dev/null +++ b/verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco @@ -0,0 +1,66 @@ +############################################################## +############################################################## +############################################################## +SET designentry = Verilog +SET BusFormat = BusFormatAngleBracketNotRipped +SET devicefamily = spartan3 +SET device = xc3s400 +SET package = pq208 +SET speedgrade = -4 +SET FlowVendor = Foundation_ISE +SET VerilogSim = True +SET VHDLSim = True +SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3 +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET byte_size=9 +CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes/dsp1b_pgmrom.coe +CSET collision_warnings=ALL +CSET component_name=upd77c25_pgmrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET load_init_file=true +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=NO_CHANGE +CSET operating_mode_b=NO_CHANGE +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=24 +CSET read_width_b=24 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=24 +CSET write_width_b=24 diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index a818ae3..1e4ec04 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -1,5 +1,5 @@ NET "CLKIN" TNM_NET = "CLKIN"; -TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %; +TIMESPEC TS_CLKIN = PERIOD "CLKIN" 23.95 MHz HIGH 50 %; //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %; NET "SNES_CS" IOSTANDARD = LVCMOS33; NET "SNES_READ" IOSTANDARD = LVCMOS33; @@ -420,6 +420,8 @@ NET "SNES_CPU_CLK" LOC = P95; NET "SNES_CS" LOC = P116; NET "SNES_DATABUS_DIR" LOC = P111; NET "SNES_DATABUS_OE" LOC = P109; +NET "SNES_DATABUS_DIR" DRIVE = 8; +NET "SNES_DATABUS_OE" DRIVE = 8; NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 5cf37ad..ed5e611 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -118,6 +118,9 @@ wire [59:0] srtc_rtc_data_out; wire [7:0] SRTC_SNES_DATA_IN; wire [7:0] SRTC_SNES_DATA_OUT; +wire [7:0] DSPX_SNES_DATA_IN; +wire [7:0] DSPX_SNES_DATA_OUT; + //wire SD_DMA_EN; //SPI_DMA_CTRL; sd_dma snes_sd_dma(.CLK(CLK2), @@ -228,6 +231,23 @@ spi snes_spi(.clk(CLK2), .bit_cnt(spi_bit_cnt) ); +upd77c25 snes_dspx ( + .DI(DSPX_SNES_DATA_IN), + .DO(DSPX_SNES_DATA_OUT), + .A0(DSPX_A0), + .nCS(~dspx_enable), + .nRD(SNES_READ), + .nWR(SNES_WRITE), + .RST(1'b1 /* XXX DSPX_RST*/), + .CLK(CLK2), + .PGM_WR(DSPX_PGM_WR), + .PGM_DI(DSPX_PGM_DI), + .PGM_WR_ADDR(DSPX_PGM_WR_ADDR), + .DAT_WR(DSPX_DAT_WR), + .DAT_DI(DSPX_DAT_DI), + .DAT_WR_ADDR(DSPX_DAT_WR_ADDR) + ); + mcu_cmd snes_mcu_cmd( .clk(CLK2), .snes_sysclk(SNES_SYSCLK), @@ -345,7 +365,7 @@ wire SNES_WRITEs = (SNES_WRITEr == 2'b11); wire SNES_CSs = (SNES_CSr == 2'b11); wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11); wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle -wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001); +wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011); wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr); wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1); @@ -389,7 +409,10 @@ address snes_addr( .use_bsx(use_bsx), .bsx_regs(bsx_regs), //SRTC - .srtc_enable(srtc_enable) + .srtc_enable(srtc_enable), + //uPD77C25 + .dspx_enable(dspx_enable), + .dspx_a0(DSPX_A0) ); wire SNES_READ_CYCLEw; @@ -419,9 +442,12 @@ data snes_data(.CLK(CLK2), .BSX_DATA_OUT(BSX_SNES_DATA_OUT), .SRTC_DATA_IN(SRTC_SNES_DATA_IN), .SRTC_DATA_OUT(SRTC_SNES_DATA_OUT), + .DSPX_DATA_IN(DSPX_SNES_DATA_IN), + .DSPX_DATA_OUT(DSPX_SNES_DATA_OUT), .msu_enable(msu_enable), .bsx_data_ovr(bsx_data_ovr), - .srtc_enable(srtc_enable) + .srtc_enable(srtc_enable), + .dspx_enable(dspx_enable) ); parameter MODE_SNES = 1'b0; @@ -528,6 +554,9 @@ always @(posedge CLK2) begin CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start}; end +reg[7:0] STATECNT; +initial STATECNT = 0; + always @(posedge CLK2) begin MCU_READ_CYCLE <= MCU_READ; MCU_WRITE_CYCLE <= MCU_WRITE; @@ -536,7 +565,9 @@ always @(posedge CLK2) begin SNES_WRITE_CYCLE <= SNES_WRITE; STATE <= STATE_0; STATEIDX <= 12; + STATECNT <= 0; end else begin + STATECNT <= STATECNT + 1; case (STATE) STATE_0: begin SNES_WRITE_CYCLE <= SNES_WRITE; @@ -658,9 +689,9 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; //assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1; //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE); -assign SNES_DATABUS_OE = msu_enable ? 1'b0 : - bsx_data_ovr ? 1'b0 : - srtc_enable ? 1'b0 : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE)); +assign SNES_DATABUS_OE = msu_enable ? (SNES_READ & SNES_WRITE) : + bsx_data_ovr ? (SNES_READ & SNES_WRITE) : + srtc_enable ? (SNES_READ & SNES_WRITE) : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE)); assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX]; diff --git a/verilog/sd2snes/msu.v b/verilog/sd2snes/msu.v index 23cd0d4..bf6d4cb 100644 --- a/verilog/sd2snes/msu.v +++ b/verilog/sd2snes/msu.v @@ -57,8 +57,8 @@ wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01); reg [5:0] reg_oe_sreg; always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; -wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000); -wire reg_oe_rising = (reg_oe_sreg[5:0] == 6'b000001); +wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); +wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001); reg [1:0] reg_we_sreg; always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we}; diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index ee2438c..4cb9517 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -94,6 +94,10 @@ + + + + @@ -106,6 +110,9 @@ + + + @@ -409,8 +416,8 @@ - - + + @@ -432,15 +439,15 @@ - + - - + + @@ -487,7 +494,7 @@ - + @@ -511,7 +518,7 @@ - + diff --git a/verilog/sd2snes/srtc.v b/verilog/sd2snes/srtc.v index 9ad26c4..7a8f471 100644 --- a/verilog/sd2snes/srtc.v +++ b/verilog/sd2snes/srtc.v @@ -52,8 +52,8 @@ assign data_out = data_out_r; reg [5:0] reg_oe_sreg; always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; -wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000); -wire reg_oe_rising = (reg_oe_sreg[5:0] == 6'b000001); +wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); +wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001); reg [1:0] reg_we_sreg; always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};