Firmware/bootldr: size reduction and stability measures

This commit is contained in:
ikari 2012-01-14 01:05:15 +01:00
parent 52d5fc9e92
commit 3506cb0ba2
6 changed files with 23 additions and 113 deletions

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@ -14,8 +14,8 @@ void clock_disconnect() {
void clock_init() { void clock_init() {
/* set flash access time to 5 clks (80<f<=100MHz) */ /* set flash access time to 6 clks (safe setting) */
setFlashAccessTime(5); setFlashAccessTime(6);
/* setup PLL0 for ~44100*256*8 Hz /* setup PLL0 for ~44100*256*8 Hz
Base clock: 12MHz Base clock: 12MHz

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@ -56,7 +56,7 @@
#define CONFIG_UART_PCLKDIV 1 #define CONFIG_UART_PCLKDIV 1
#define CONFIG_UART_TX_BUF_SHIFT 8 #define CONFIG_UART_TX_BUF_SHIFT 8
#define CONFIG_UART_BAUDRATE 921600 #define CONFIG_UART_BAUDRATE 921600
//#define CONFIG_UART_DEADLOCKABLE #define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2 #define SSP_CLK_DIVISOR_FAST 2
#define SSP_CLK_DIVISOR_SLOW 250 #define SSP_CLK_DIVISOR_SLOW 250

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@ -14,7 +14,7 @@
/ Function and Buffer Configurations / Function and Buffer Configurations
/----------------------------------------------------------------------------*/ /----------------------------------------------------------------------------*/
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ #define _FS_TINY 1 /* 0:Normal or 1:Tiny */
/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system /* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
/ object instead of the sector buffer in the individual file object for file / object instead of the sector buffer in the individual file object for file
/ data transfer. This reduces memory consumption 512 bytes each file object. */ / data transfer. This reduces memory consumption 512 bytes each file object. */
@ -57,7 +57,7 @@
/ Locale and Namespace Configurations / Locale and Namespace Configurations
/----------------------------------------------------------------------------*/ /----------------------------------------------------------------------------*/
#define _CODE_PAGE 1252 #define _CODE_PAGE 1
/* The _CODE_PAGE specifies the OEM code page to be used on the target system. /* The _CODE_PAGE specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure. / Incorrect setting of the code page can cause a file open failure.
/ /

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@ -72,10 +72,12 @@ FLASH_RES check_flash() {
} }
IAP_RES iap_wrap(uint32_t *iap_cmd, uint32_t *iap_res) { IAP_RES iap_wrap(uint32_t *iap_cmd, uint32_t *iap_res) {
NVIC_DisableIRQ(RIT_IRQn); // NVIC_DisableIRQ(RIT_IRQn);
NVIC_DisableIRQ(UART_IRQ); // NVIC_DisableIRQ(UART_IRQ);
for(volatile int i=0; i<2048; i++);
iap_entry(iap_cmd, iap_res); iap_entry(iap_cmd, iap_res);
NVIC_EnableIRQ(UART_IRQ); for(volatile int i=0; i<2048; i++);
// NVIC_EnableIRQ(UART_IRQ);
return iap_res[0]; return iap_res[0];
} }
@ -153,12 +155,16 @@ FLASH_RES flash_file(uint8_t *filename) {
writeled(1); writeled(1);
DBG_BL printf("erasing flash...\n"); DBG_BL printf("erasing flash...\n");
DBG_UART uart_putc('P');
if((res = iap_prepare_for_write(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) { if((res = iap_prepare_for_write(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
DBG_BL printf("error %ld while preparing for erase\n", res); DBG_BL printf("error %ld while preparing for erase\n", res);
DBG_UART uart_putc('X');
return ERR_FLASHPREP; return ERR_FLASHPREP;
}; };
DBG_UART uart_putc('E');
if((res = iap_erase(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) { if((res = iap_erase(FW_START / 0x1000, FLASH_SECTORS)) != CMD_SUCCESS) {
DBG_BL printf("error %ld while erasing\n", res); DBG_BL printf("error %ld while erasing\n", res);
DBG_UART uart_putc('X');
return ERR_FLASHERASE; return ERR_FLASHERASE;
} }
DBG_BL printf("writing... @%08lx\n", flash_addr); DBG_BL printf("writing... @%08lx\n", flash_addr);
@ -174,18 +180,23 @@ FLASH_RES flash_file(uint8_t *filename) {
DBG_BL printf("current_sec=%d flash_addr=%08lx\n", current_sec, flash_addr); DBG_BL printf("current_sec=%d flash_addr=%08lx\n", current_sec, flash_addr);
DBG_UART uart_putc('.'); DBG_UART uart_putc('.');
if(current_sec < (FW_START / 0x1000)) return ERR_FLASH; if(current_sec < (FW_START / 0x1000)) return ERR_FLASH;
DBG_UART uart_putc(current_sec["0123456789ABCDEFGH"]);
DBG_UART uart_putc('p');
if((res = iap_prepare_for_write(current_sec, current_sec)) != CMD_SUCCESS) { if((res = iap_prepare_for_write(current_sec, current_sec)) != CMD_SUCCESS) {
DBG_BL printf("error %ld while preparing sector %d for write\n", res, current_sec); DBG_BL printf("error %ld while preparing sector %d for write\n", res, current_sec);
DBG_UART uart_putc('X');
return ERR_FLASH; return ERR_FLASH;
} }
DBG_UART uart_putc('w');
if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) { if((res = iap_ram2flash(flash_addr, file_buf, 512)) != CMD_SUCCESS) {
DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec); DBG_BL printf("error %ld while writing to address %08lx (sector %d)\n", res, flash_addr, current_sec);
DBG_UART uart_putc('X');
return ERR_FLASH; return ERR_FLASH;
} }
} }
if(total_read != (file_header.size + 0x100)) { if(total_read != (file_header.size + 0x100)) {
DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size); DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size);
DBG_UART uart_putc('X'); // DBG_UART uart_putc('X');
return ERR_FILECHK; return ERR_FILECHK;
} }
writeled(0); writeled(0);

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@ -18,32 +18,6 @@ extern volatile int sd_changed;
volatile tick_t ticks; volatile tick_t ticks;
volatile int wokefromrit; volatile int wokefromrit;
void __attribute__((weak,noinline)) SysTick_Hook(void) {
/* Empty function for hooking the systick handler */
}
/* Systick interrupt handler */
void SysTick_Handler(void) {
ticks++;
static uint16_t sdch_state = 0;
sdch_state = (sdch_state << 1) | SDCARD_DETECT | 0xe000;
if((sdch_state == 0xf000) || (sdch_state == 0xefff)) {
sd_changed = 1;
}
sdn_changed();
SysTick_Hook();
}
void __attribute__((weak,noinline)) RIT_Hook(void) {
}
void RIT_IRQHandler(void) {
LPC_RIT->RICTRL = BV(RITINT);
NVIC_ClearPendingIRQ(RIT_IRQn);
wokefromrit = 1;
RIT_Hook();
}
void timer_init(void) { void timer_init(void) {
/* turn on power to RIT */ /* turn on power to RIT */
BITBAND(LPC_SC->PCONP, PCRIT) = 1; BITBAND(LPC_SC->PCONP, PCRIT) = 1;
@ -54,8 +28,6 @@ void timer_init(void) {
/* PCLK = CCLK */ /* PCLK = CCLK */
BITBAND(LPC_SC->PCLKSEL1, 26) = 1; BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1; BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
/* enable SysTick */
SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
} }
void delay_us(unsigned int time) { void delay_us(unsigned int time) {
@ -84,21 +56,3 @@ void delay_ms(unsigned int time) {
LPC_RIT->RICTRL = 0; LPC_RIT->RICTRL = 0;
} }
void sleep_ms(unsigned int time) {
wokefromrit = 0;
/* Prepare RIT */
LPC_RIT->RICOUNTER = 0;
LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time;
LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT);
NVIC_EnableIRQ(RIT_IRQn);
/* Wait until RIT signals an interrupt */
//uart_putc(';');
while(!wokefromrit) {
__WFI();
}
NVIC_DisableIRQ(RIT_IRQn);
/* Disable RIT */
LPC_RIT->RICTRL = BV(RITINT);
}

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@ -74,65 +74,14 @@
} }
} }
*/ */
static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; //static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
static volatile unsigned int read_idx,write_idx; static volatile unsigned int read_idx,write_idx;
void UART_HANDLER(void) {
int iir = UART_REGS->IIR;
if (!(iir & 1)) {
/* Interrupt is pending */
switch (iir & 14) {
#if CONFIG_UART_NUM == 1
case 0: /* modem status */
(void) UART_REGS->MSR; // dummy read to clear
break;
#endif
case 2: /* THR empty - send */
if (read_idx != write_idx) {
int maxchars = 16;
while (read_idx != write_idx && --maxchars > 0) {
UART_REGS->THR = (unsigned char)txbuf[read_idx];
read_idx = (read_idx+1) & (sizeof(txbuf)-1);
}
if (read_idx == write_idx) {
/* buffer empty - turn off THRE interrupt */
BITBAND(UART_REGS->IER, 1) = 0;
}
}
break;
case 12: /* RX timeout */
case 4: /* data received - not implemented yet */
(void) UART_REGS->RBR; // dummy read to clear
break;
case 6: /* RX error */
(void) UART_REGS->LSR; // dummy read to clear
default: break;
}
}
}
void uart_putc(char c) { void uart_putc(char c) {
if (c == '\n') if (c == '\n')
uart_putc('\r'); uart_putc('\r');
while(!(UART_REGS->LSR & (0x20)));
unsigned int tmp = (write_idx+1) & (sizeof(txbuf)-1) ; UART_REGS->THR = c;
if (read_idx == write_idx && (BITBAND(UART_REGS->LSR, 5))) {
/* buffer empty, THR empty -> send immediately */
UART_REGS->THR = (unsigned char)c;
} else {
#ifdef CONFIG_UART_DEADLOCKABLE
while (tmp == read_idx) ;
#endif
BITBAND(UART_REGS->IER, 1) = 0; // turn off UART interrupt
txbuf[write_idx] = c;
write_idx = tmp;
BITBAND(UART_REGS->IER, 1) = 1;
}
} }
/* Polling version only */ /* Polling version only */
@ -183,10 +132,6 @@ void uart_init(void) {
/* reset and enable FIFO */ /* reset and enable FIFO */
UART_REGS->FCR = BV(0); UART_REGS->FCR = BV(0);
/* enable transmit interrupt */
BITBAND(UART_REGS->IER, 1) = 1;
NVIC_EnableIRQ(UART_IRQ);
UART_REGS->THR = '?'; UART_REGS->THR = '?';
} }