diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v
index 30858e8..58d9bb7 100644
--- a/verilog/sd2snes/address.v
+++ b/verilog/sd2snes/address.v
@@ -38,6 +38,8 @@ module address(
   output dspx_dp_enable,
   output dspx_a0,
   output r213f_enable,
+  output snescmd_rd_enable,
+  output snescmd_wr_enable,
   input [8:0] bs_page_offset,
   input [9:0] bs_page,
   input bs_page_enable
@@ -244,4 +246,16 @@ initial r213f_enable_r = 6'b000000;
 always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
 assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F];
 
+wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
+//reg [5:0] snescmd_rd_enable_r;
+//initial snescmd_rd_enable_r = 6'b000000;
+//always @(posedge CLK) snescmd_rd_enable_r <= {snescmd_rd_enable_r[4:0], snescmd_rd_enable_w};
+assign snescmd_rd_enable = snescmd_rd_enable_w /*&snescmd_rd_enable_r[5:1]*/;
+
+assign snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
+//reg [5:0] snescmd_wr_enable_r;
+//initial snescmd_wr_enable_r = 6'b000000;
+//always @(posedge CLK) snescmd_wr_enable_r <= {snescmd_wr_enable_r[4:0], snescmd_wr_enable_w};
+assign snescmd_wr_enable = snescmd_wr_enable_w /*&snescmd_wr_enable_r[5:1]*/;
+
 endmodule
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index dd613a4..1ab88ba 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -407,7 +407,9 @@ address snes_addr(
   .dspx_enable(dspx_enable),
   .dspx_dp_enable(dspx_dp_enable),
   .dspx_a0(DSPX_A0),
-  .r213f_enable(r213f_enable)
+  .r213f_enable(r213f_enable),
+  .snescmd_rd_enable(snescmd_rd_enable),
+  .snescmd_wr_enable(snescmd_wr_enable)
 );
 
 parameter MODE_SNES = 1'b0;
@@ -457,9 +459,11 @@ initial r213f_forceread = 0;
 initial r213f_state = 2'b01;
 initial r213f_delay = 3'b011;
 
+reg[7:0] snescmd_regs[15:0];
 
-assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
-                   :(!SNES_READ ^ r213f_forceread)
+assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
+                   :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
+                   :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
                                 ? (srtc_enable ? SRTC_SNES_DATA_OUT
                                   :dspx_enable ? DSPX_SNES_DATA_OUT
                                   :dspx_dp_enable ? DSPX_SNES_DATA_OUT
@@ -629,6 +633,12 @@ always @(posedge SYSCLK2) begin
   end
 end
 
+always @(posedge CLK2) begin
+  if(SNES_WR_end & snescmd_wr_enable) begin
+    snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
+  end
+end
+
 assign ROM_DATA[7:0] = ROM_ADDR0
                        ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v
index b3f2f50..dd9331e 100644
--- a/verilog/sd2snes_cx4/address.v
+++ b/verilog/sd2snes_cx4/address.v
@@ -34,7 +34,9 @@ module address(
   output msu_enable,
   output cx4_enable,
   output cx4_vect_enable,
-  output r213f_enable
+  output r213f_enable,
+  output snescmd_rd_enable,
+  output snescmd_wr_enable
 );
 
 wire [23:0] SRAM_SNES_ADDR;
@@ -68,9 +70,12 @@ assign cx4_enable = &cx4_enable_r[5:2];
 assign cx4_vect_enable = &SNES_ADDR[15:5];
 
 wire r213f_enable_w = (SNES_PA == 8'h3f);
-reg [5:0] r213f_enable_r;
-initial r213f_enable_r = 6'b000000;
-always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w};
-assign r213f_enable = &r213f_enable_r[5:2];
+assign r213f_enable = r213f_enable_w;
+
+wire snescmd_rd_enable_w = (SNES_PA[7:4] == 4'b1111);
+assign snescmd_rd_enable = snescmd_rd_enable_w;
+
+wire snescmd_wr_enable_w = (SNES_ADDR[23:4] == 20'hccccc);
+assign snescmd_wr_enable = snescmd_wr_enable_w;
 
 endmodule
diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v
index 25382ca..fd97aa6 100644
--- a/verilog/sd2snes_cx4/main.v
+++ b/verilog/sd2snes_cx4/main.v
@@ -304,7 +304,11 @@ address snes_addr(
   //CX4
   .cx4_enable(cx4_enable),
   .cx4_vect_enable(cx4_vect_enable),
-  .r213f_enable(r213f_enable)
+  //region
+  .r213f_enable(r213f_enable),
+  //CMD Interface
+  .snescmd_rd_enable(snescmd_rd_enable),
+  .snescmd_wr_enable(snescmd_wr_enable)
 );
 
 reg [7:0] CX4_DINr;
@@ -379,13 +383,15 @@ initial r213f_forceread = 0;
 initial r213f_state = 2'b01;
 initial r213f_delay = 3'b011;
 
-assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr
-                   :(!SNES_READ ^ r213f_forceread)
-                     ? (msu_enable ? MSU_SNES_DATA_OUT
-                       :cx4_enable ? CX4_SNES_DATA_OUT
-                       :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
-                       :SNES_DINr)
-                    : 8'bZ;
+reg[7:0] snescmd_regs[15:0];
+
+assign SNES_DATA = (snescmd_rd_enable & ~SNES_PARD) ? snescmd_regs[SNES_ADDR[3:0]]
+                   :(r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
+                   :(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
+                                ? (msu_enable ? MSU_SNES_DATA_OUT
+                                  :cx4_enable ? CX4_SNES_DATA_OUT
+											 :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
+                                  :SNES_DOUTr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
 
 reg [3:0] ST_MEM_DELAYr;
 reg MCU_RD_PENDr;