FPGA: improve BS support (more date fields, initial download data support)
This commit is contained in:
Maximilian Rehkopf
parent
f5caf21fac
commit
37a309fd0e
@ -37,7 +37,10 @@ module address(
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output dspx_enable,
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output dspx_dp_enable,
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output dspx_a0,
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output r213f_enable
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output r213f_enable,
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input [8:0] bs_page_offset,
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input [9:0] bs_page,
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input bs_page_enable
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);
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parameter [2:0]
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@ -141,7 +144,9 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
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? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
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: IS_WRITABLE
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? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
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: ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
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: bs_page_enable
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? (24'h900000 + {bs_page,bs_page_offset})
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:((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
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|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
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?(24'h800000
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+ ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
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@ -32,7 +32,10 @@ module bsx(
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input use_bsx,
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output data_ovr,
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output flash_writable,
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input [55:0] rtc_data
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input [59:0] rtc_data,
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output [9:0] bs_page_out, // support only page 0000-03ff
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output bs_page_enable,
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output [8:0] bs_page_offset
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);
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wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff
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@ -67,11 +70,40 @@ assign flash_writable = (use_bsx)
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&& flash_we_r
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&& !is_flash_special_address;
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assign data_ovr = cart_enable | base_enable | flash_ovr;
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assign data_ovr = (cart_enable | base_enable | flash_ovr) & ~bs_page_enable;
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reg [9:0] bs_page0;
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reg [9:0] bs_page1;
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reg [8:0] bs_page0_offset;
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reg [8:0] bs_page1_offset;
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reg [4:0] bs_stb0_offset;
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reg [4:0] bs_stb1_offset;
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wire bs_sta0_en = base_addr == 5'h0a;
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wire bs_stb0_en = base_addr == 5'h0b;
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wire bs_page0_en = base_addr == 5'h0c;
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wire bs_sta1_en = base_addr == 5'h10;
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wire bs_stb1_en = base_addr == 5'h11;
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wire bs_page1_en = base_addr == 5'h12;
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assign bs_page_enable = base_enable & ((|bs_page0 & (bs_page0_en | bs_sta0_en | bs_stb0_en))
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|(|bs_page1 & (bs_page1_en | bs_sta1_en | bs_stb1_en)));
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assign bs_page_out = (bs_page0_en | bs_sta0_en | bs_stb0_en) ? bs_page0 : bs_page1;
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assign bs_page_offset = bs_sta0_en ? 9'h032
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: bs_stb0_en ? (9'h034 + bs_stb0_offset)
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: bs_sta1_en ? 9'h032
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: bs_stb1_en ? (9'h034 + bs_stb1_offset)
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: (9'h048 + (bs_page0_en ? bs_page0_offset : bs_page1_offset));
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reg [3:0] reg_oe_sreg;
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always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe};
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wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000);
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wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001);
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reg [1:0] reg_we_sreg;
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always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we};
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@ -96,40 +128,40 @@ wire [7:0] rtc_sec = rtc_data[3:0] + (rtc_data[7:4] << 3) + (rtc_data[7:4] << 1)
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wire [7:0] rtc_min = rtc_data[11:8] + (rtc_data[15:12] << 3) + (rtc_data[15:12] << 1);
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wire [7:0] rtc_hour = rtc_data[19:16] + (rtc_data[23:20] << 3) + (rtc_data[23:20] << 1);
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wire [7:0] rtc_day = rtc_data[27:24] + (rtc_data[31:28] << 3) + (rtc_data[31:28] << 1);
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/* The following signals are currently unused.
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They are kept in case more Satellaview date registers are discovered. */
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wire [7:0] rtc_month = rtc_data[35:32] + (rtc_data[39:36] << 3) + (rtc_data[39:36] << 1);
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wire [7:0] rtc_dow = {4'b0,rtc_data[59:56]};
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wire [7:0] rtc_year1 = rtc_data[43:40] + (rtc_data[47:44] << 3) + (rtc_data[47:44] << 1);
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wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55:52] << 1);
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wire [15:0] rtc_year = (rtc_year100 << 6) + (rtc_year100 << 5) + (rtc_year100 << 2) + rtc_year1;
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initial begin
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regs_tmpr <= 15'b000000100000000;
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regs_outr <= 15'b000000100000000;
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bsx_counter <= 0;
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base_regs[8] <= 0;
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base_regs[9] <= 0;
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base_regs[10] <= 0;
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base_regs[11] <= 8'h9f;
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base_regs[12] <= 8'h10;
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base_regs[13] <= 8'h9f;
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base_regs[14] <= 0;
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base_regs[15] <= 0;
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base_regs[16] <= 0;
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base_regs[17] <= 8'h9f;
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base_regs[18] <= 8'h01;
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base_regs[19] <= 8'h9f;
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base_regs[20] <= 0;
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base_regs[21] <= 0;
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base_regs[22] <= 8'h02;
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base_regs[23] <= 8'hff;
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base_regs[24] <= 8'h80;
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base_regs[25] <= 8'h01;
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base_regs[26] <= 0;
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base_regs[27] <= 0;
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base_regs[28] <= 0;
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base_regs[29] <= 0;
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base_regs[30] <= 0;
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base_regs[31] <= 0;
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base_regs[5'h08] <= 0;
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base_regs[5'h09] <= 0;
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base_regs[5'h0a] <= 8'h01;
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base_regs[5'h0b] <= 0;
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base_regs[5'h0c] <= 0;
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base_regs[5'h0d] <= 0;
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base_regs[5'h0e] <= 0;
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base_regs[5'h0f] <= 0;
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base_regs[5'h10] <= 8'h01;
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base_regs[5'h11] <= 0;
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base_regs[5'h12] <= 0;
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base_regs[5'h13] <= 0;
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base_regs[5'h14] <= 0;
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base_regs[5'h15] <= 0;
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base_regs[5'h16] <= 0;
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base_regs[5'h17] <= 0;
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base_regs[5'h18] <= 0;
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base_regs[5'h19] <= 0;
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base_regs[5'h1a] <= 0;
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base_regs[5'h1b] <= 0;
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base_regs[5'h1c] <= 0;
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base_regs[5'h1d] <= 0;
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base_regs[5'h1e] <= 0;
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base_regs[5'h1f] <= 0;
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flash_vendor_data[3'h0] <= 8'h4d;
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flash_vendor_data[3'h1] <= 8'h00;
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flash_vendor_data[3'h2] <= 8'h50;
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@ -140,39 +172,54 @@ initial begin
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flash_vendor_data[3'h7] <= 8'h00;
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flash_ovr_r <= 1'b0;
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flash_we_r <= 1'b0;
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bs_page0 <= 10'h0;
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bs_page1 <= 10'h0;
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bs_page0_offset <= 9'h0;
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bs_page1_offset <= 9'h0;
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bs_stb0_offset <= 5'h00;
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bs_stb1_offset <= 5'h00;
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end
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always @(posedge clkin) begin
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if(reg_oe_rising) begin
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if(base_enable) begin
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case(base_addr)
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5'h0b: bs_stb0_offset <= bs_stb0_offset + 1;
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5'h0c: bs_page0_offset <= bs_page0_offset + 1;
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5'h11: bs_stb1_offset <= bs_stb1_offset + 1;
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5'h12: bs_page1_offset <= bs_page1_offset + 1;
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endcase
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end
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end
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if(reg_oe_falling) begin
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if(cart_enable)
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reg_data_outr <= {regs_outr[reg_addr], 7'b0};
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else if(base_enable) begin
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case(base_addr)
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5'b10010: begin
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if(bsx_counter < 18) begin
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bsx_counter <= bsx_counter + 1;
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case (bsx_counter)
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5:
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reg_data_outr <= 8'h1;
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6:
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reg_data_outr <= 8'h1;
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10:
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reg_data_outr <= rtc_sec;
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11:
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reg_data_outr <= rtc_min;
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12:
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reg_data_outr <= rtc_hour;
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default:
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reg_data_outr <= 8'h0;
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endcase
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end else begin
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reg_data_outr <= 8'h0;
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bsx_counter <= 0;
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end
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5'h0b, 5'h11: begin
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base_regs[base_addr+5'h02] <= base_regs[base_addr+5'h02] | reg_data_in;
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end
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5'h0c, 5'h12: begin
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case (bs_page1_offset)
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4: reg_data_outr <= 8'h3;
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5: reg_data_outr <= 8'h1;
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6: reg_data_outr <= 8'h1;
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10: reg_data_outr <= rtc_sec;
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11: reg_data_outr <= rtc_min;
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12: reg_data_outr <= rtc_hour;
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13: reg_data_outr <= rtc_dow;
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14: reg_data_outr <= rtc_day;
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15: reg_data_outr <= rtc_month;
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16: reg_data_outr <= rtc_year[7:0];
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17: reg_data_outr <= rtc_year[15:8];
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default: reg_data_outr <= 8'h0;
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endcase
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end
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5'h0d, 5'h13: begin
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reg_data_outr <= base_regs[base_addr];
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base_regs[base_addr] <= 8'h00;
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end
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5'b10011:
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reg_data_outr <= base_regs[base_addr] & 8'h3f;
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default:
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reg_data_outr <= base_regs[base_addr];
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endcase
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@ -190,7 +237,7 @@ always @(posedge clkin) begin
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end
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end else if(pgm_we_rising) begin
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regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
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regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
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regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
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end else if(reg_we_rising && cart_enable) begin
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if(reg_addr == 4'he && reg_data_in[7])
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regs_outr <= regs_tmpr | 15'b100000000000000;
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@ -198,16 +245,27 @@ always @(posedge clkin) begin
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regs_tmpr[reg_addr] <= reg_data_in[7];
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end else if(reg_we_rising && base_enable) begin
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case(base_addr)
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5'h0f: begin
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base_regs[base_addr-1] <= base_regs[base_addr]-(base_regs[base_addr-1] >> 1);
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base_regs[base_addr] <= base_regs[base_addr] >> 1;
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5'h09: begin
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base_regs[8'h09] <= reg_data_in;
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bs_page0 <= {reg_data_in[1:0], base_regs[8'h08]};
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bs_page0_offset <= 9'h00;
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end
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5'h0b: begin
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bs_stb0_offset <= 5'h00;
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end
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5'h0c: begin
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bs_page0_offset <= 9'h00;
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end
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5'h0f: begin
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base_regs[8'h0f] <= reg_data_in;
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bs_page1 <= {reg_data_in[1:0], base_regs[8'h0e]};
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bs_page1_offset <= 9'h00;
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end
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5'h11: begin
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bsx_counter <= 0;
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base_regs[base_addr] <= reg_data_in;
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bs_stb1_offset <= 5'h00;
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end
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5'h12: begin
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base_regs[8'h10] <= 8'h80;
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bs_page1_offset <= 9'h00;
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end
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default:
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base_regs[base_addr] <= reg_data_in;
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@ -133,6 +133,10 @@ wire [7:0] featurebits;
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wire [23:0] MAPPED_SNES_ADDR;
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wire ROM_ADDR0;
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wire [9:0] bs_page;
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wire [8:0] bs_page_offset;
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wire bs_page_enable;
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sd_dma snes_sd_dma(
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.CLK(CLK2),
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.SD_DAT(SD_DAT),
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@ -227,7 +231,11 @@ bsx snes_bsx(
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.reg_set_bits(bsx_regs_set_bits),
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.data_ovr(bsx_data_ovr),
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.flash_writable(IS_FLASHWR),
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.rtc_data(rtc_data[55:0])
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.rtc_data(rtc_data[59:0]),
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.bs_page_out(bs_page), // support only page 0000-03ff
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.bs_page_enable(bs_page_enable),
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.bs_page_offset(bs_page_offset)
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);
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spi snes_spi(
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@ -390,6 +398,9 @@ address snes_addr(
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//BS-X
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.use_bsx(use_bsx),
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.bsx_regs(bsx_regs),
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.bs_page_offset(bs_page_offset),
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.bs_page(bs_page),
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.bs_page_enable(bs_page_enable),
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//SRTC
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.srtc_enable(srtc_enable),
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//uPD77C25
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@ -429,13 +440,13 @@ parameter ROM_WR_WAIT_MCU = 4'h6;
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reg [17:0] STATE;
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initial STATE = ST_IDLE;
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reg [7:0] SNES_DINr;
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reg [7:0] ROM_DOUTr;
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assign DSPX_SNES_DATA_IN = SNES_DATA;
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assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
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assign MSU_SNES_DATA_IN = SNES_DATA;
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assign BSX_SNES_DATA_IN = SNES_DATA;
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reg [7:0] SNES_DINr;
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reg [7:0] ROM_DOUTr;
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assign BSX_SNES_DATA_IN = bs_page_enable ? SNES_DINr : SNES_DATA;
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reg [7:0] r213fr;
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reg r213f_forceread;
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@ -645,6 +656,7 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
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msu_enable ? 1'b0 :
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bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
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srtc_enable ? (SNES_READ & SNES_WRITE) :
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bs_page_enable ? (SNES_READ) :
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r213f_enable & !SNES_PARD ? 1'b0 :
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((IS_ROM & SNES_CS)
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|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
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