diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v
index 6afdbea..54173f8 100644
--- a/verilog/sd2snes_cx4/cx4.v
+++ b/verilog/sd2snes_cx4/cx4.v
@@ -89,7 +89,7 @@ reg [14:0] cx4_mmio_pagemem[1:0];
 
 reg [23:0] const [15:0];
 
-reg [14:0] cachetag [1:0]; // 14-0: bank number
+reg [14:0] cachetag [1:0];
 reg  [1:0] cachevalid;
 
 reg [14:0] cache_pgmpage;
diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v
index da8b924..a2c52a6 100644
--- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v
+++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v
@@ -7,7 +7,7 @@
 // \   \   \/     Version: O.61xd
 //  \   \         Application: netgen
 //  /   /         Filename: cx4_mul.v
-// /___/   /\     Timestamp: Fri Oct 28 10:30:51 2011
+// /___/   /\     Timestamp: Sun Oct 30 21:22:41 2011
 // \   \  /  \ 
 //  \___\/\___\
 //             
@@ -34,9 +34,10 @@
 `timescale 1 ns/1 ps
 
 module cx4_mul (
-  clk, p, a, b
+  clk, ce, p, a, b
 )/* synthesis syn_black_box syn_noprune=1 */;
   input clk;
+  input ce;
   output [47 : 0] p;
   input [23 : 0] a;
   input [23 : 0] b;
@@ -398,7 +399,28 @@ module cx4_mul (
   wire sig00000161;
   wire sig00000162;
   wire sig00000163;
-  wire sig00000164;
+  wire \NLW_blk00000002_P<35>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<34>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<33>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<32>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<31>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<30>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<29>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<28>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<27>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<26>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<25>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<24>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<23>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<22>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<21>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<20>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<19>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<18>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<17>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<16>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<15>_UNCONNECTED ;
+  wire \NLW_blk00000002_P<14>_UNCONNECTED ;
   wire \NLW_blk00000003_P<35>_UNCONNECTED ;
   wire \NLW_blk00000003_P<34>_UNCONNECTED ;
   wire \NLW_blk00000003_P<33>_UNCONNECTED ;
@@ -411,16 +433,6 @@ module cx4_mul (
   wire \NLW_blk00000003_P<26>_UNCONNECTED ;
   wire \NLW_blk00000003_P<25>_UNCONNECTED ;
   wire \NLW_blk00000003_P<24>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<23>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<22>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<21>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<20>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<19>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<18>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<17>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<16>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<15>_UNCONNECTED ;
-  wire \NLW_blk00000003_P<14>_UNCONNECTED ;
   wire \NLW_blk00000004_P<35>_UNCONNECTED ;
   wire \NLW_blk00000004_P<34>_UNCONNECTED ;
   wire \NLW_blk00000004_P<33>_UNCONNECTED ;
@@ -434,245 +446,212 @@ module cx4_mul (
   wire \NLW_blk00000004_P<25>_UNCONNECTED ;
   wire \NLW_blk00000004_P<24>_UNCONNECTED ;
   wire \NLW_blk00000005_P<35>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<34>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<33>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<32>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<31>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<30>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<29>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<28>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<27>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<26>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<25>_UNCONNECTED ;
-  wire \NLW_blk00000005_P<24>_UNCONNECTED ;
-  wire \NLW_blk00000006_P<35>_UNCONNECTED ;
   GND   blk00000001 (
     .G(sig00000001)
   );
-  VCC   blk00000002 (
-    .P(sig00000002)
+  MULT18X18S   blk00000002 (
+    .C(clk),
+    .CE(ce),
+    .R(sig00000001),
+    .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
+    .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
+    .P({\NLW_blk00000002_P<35>_UNCONNECTED , \NLW_blk00000002_P<34>_UNCONNECTED , \NLW_blk00000002_P<33>_UNCONNECTED , 
+\NLW_blk00000002_P<32>_UNCONNECTED , \NLW_blk00000002_P<31>_UNCONNECTED , \NLW_blk00000002_P<30>_UNCONNECTED , \NLW_blk00000002_P<29>_UNCONNECTED , 
+\NLW_blk00000002_P<28>_UNCONNECTED , \NLW_blk00000002_P<27>_UNCONNECTED , \NLW_blk00000002_P<26>_UNCONNECTED , \NLW_blk00000002_P<25>_UNCONNECTED , 
+\NLW_blk00000002_P<24>_UNCONNECTED , \NLW_blk00000002_P<23>_UNCONNECTED , \NLW_blk00000002_P<22>_UNCONNECTED , \NLW_blk00000002_P<21>_UNCONNECTED , 
+\NLW_blk00000002_P<20>_UNCONNECTED , \NLW_blk00000002_P<19>_UNCONNECTED , \NLW_blk00000002_P<18>_UNCONNECTED , \NLW_blk00000002_P<17>_UNCONNECTED , 
+\NLW_blk00000002_P<16>_UNCONNECTED , \NLW_blk00000002_P<15>_UNCONNECTED , \NLW_blk00000002_P<14>_UNCONNECTED , sig000000e4, sig000000e3, sig000000e2, 
+sig000000e1, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e5, sig000000e0})
   );
   MULT18X18S   blk00000003 (
     .C(clk),
-    .CE(sig00000002),
+    .CE(ce),
     .R(sig00000001),
     .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
-    .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
+    .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
     .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , 
 \NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED , 
 \NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , 
-\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , 
-\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , 
-\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, 
-sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1})
+\NLW_blk00000003_P<24>_UNCONNECTED , sig000000d7, sig000000d6, sig000000d5, sig000000d4, sig000000d2, sig000000d1, sig000000d0, sig000000cf, 
+sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000c9, sig000000df, sig000000de, sig000000dd, sig000000dc, sig000000db, 
+sig000000da, sig000000d9, sig000000d8, sig000000d3, sig000000c8})
   );
   MULT18X18S   blk00000004 (
     .C(clk),
-    .CE(sig00000002),
-    .R(sig00000001),
-    .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
-    .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
-    .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , 
-\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , 
-\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , 
-\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, 
-sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, 
-sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9})
-  );
-  MULT18X18S   blk00000005 (
-    .C(clk),
-    .CE(sig00000002),
+    .CE(ce),
     .R(sig00000001),
     .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
     .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
-    .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , 
-\NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , 
-\NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , 
-\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, 
-sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, 
-sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1})
+    .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , 
+\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , 
+\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , 
+\NLW_blk00000004_P<24>_UNCONNECTED , sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000ba, sig000000b9, sig000000b8, sig000000b7, 
+sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000b1, sig000000c7, sig000000c6, sig000000c5, sig000000c4, sig000000c3, 
+sig000000c2, sig000000c1, sig000000c0, sig000000bb, sig000000b0})
   );
-  MULT18X18S   blk00000006 (
+  MULT18X18S   blk00000005 (
     .C(clk),
-    .CE(sig00000002),
+    .CE(ce),
     .R(sig00000001),
     .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
     .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
-    .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, 
-sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, 
-sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, 
-sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
+    .P({\NLW_blk00000005_P<35>_UNCONNECTED , sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a4, sig000000a2, sig000000a1, sig000000a0, 
+sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000099, sig00000097, sig00000096, sig00000095, sig00000094, 
+sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig0000008e, sig000000af, sig000000ae, sig000000ad, sig000000ac, sig000000ab, 
+sig000000aa, sig000000a9, sig000000a3, sig00000098, sig0000008d})
   );
-  XORCY   blk00000007 (
-    .CI(sig00000065),
-    .LI(sig00000086),
+  XORCY   blk00000006 (
+    .CI(sig00000064),
+    .LI(sig00000085),
     .O(p[47])
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000008 (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
-    .O(sig00000086)
-  );
-  MUXCY   blk00000009 (
-    .CI(sig00000064),
-    .DI(sig0000014e),
-    .S(sig00000085),
-    .O(sig00000065)
-  );
-  LUT2 #(
-    .INIT ( 4'h6 ))
-  blk0000000a (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
+  blk00000007 (
+    .I0(sig0000014d),
+    .I1(sig0000015a),
     .O(sig00000085)
   );
-  MUXCY   blk0000000b (
-    .CI(sig00000062),
-    .DI(sig0000014e),
+  MUXCY   blk00000008 (
+    .CI(sig00000063),
+    .DI(sig0000014d),
     .S(sig00000084),
     .O(sig00000064)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000000c (
-    .I0(sig0000014e),
-    .I1(sig0000015b),
+  blk00000009 (
+    .I0(sig0000014d),
+    .I1(sig0000015a),
     .O(sig00000084)
   );
-  XORCY   blk0000000d (
+  MUXCY   blk0000000a (
     .CI(sig00000061),
-    .LI(sig00000082),
-    .O(p[46])
-  );
-  MUXCY   blk0000000e (
-    .CI(sig00000061),
-    .DI(sig0000014e),
-    .S(sig00000082),
-    .O(sig00000062)
+    .DI(sig0000014d),
+    .S(sig00000083),
+    .O(sig00000063)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000000f (
-    .I0(sig0000014e),
+  blk0000000b (
+    .I0(sig0000014d),
     .I1(sig0000015a),
-    .O(sig00000082)
+    .O(sig00000083)
   );
-  XORCY   blk00000010 (
+  XORCY   blk0000000c (
     .CI(sig00000060),
     .LI(sig00000081),
-    .O(p[45])
+    .O(p[46])
   );
-  MUXCY   blk00000011 (
+  MUXCY   blk0000000d (
     .CI(sig00000060),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig00000081),
     .O(sig00000061)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000012 (
-    .I0(sig0000014e),
+  blk0000000e (
+    .I0(sig0000014d),
     .I1(sig00000159),
     .O(sig00000081)
   );
-  XORCY   blk00000013 (
+  XORCY   blk0000000f (
     .CI(sig0000005f),
     .LI(sig00000080),
-    .O(p[44])
+    .O(p[45])
   );
-  MUXCY   blk00000014 (
+  MUXCY   blk00000010 (
     .CI(sig0000005f),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig00000080),
     .O(sig00000060)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000015 (
-    .I0(sig0000014e),
+  blk00000011 (
+    .I0(sig0000014d),
     .I1(sig00000158),
     .O(sig00000080)
   );
-  XORCY   blk00000016 (
+  XORCY   blk00000012 (
     .CI(sig0000005e),
     .LI(sig0000007f),
-    .O(p[43])
+    .O(p[44])
   );
-  MUXCY   blk00000017 (
+  MUXCY   blk00000013 (
     .CI(sig0000005e),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig0000007f),
     .O(sig0000005f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000018 (
-    .I0(sig0000014e),
-    .I1(sig00000164),
+  blk00000014 (
+    .I0(sig0000014d),
+    .I1(sig00000157),
     .O(sig0000007f)
   );
-  XORCY   blk00000019 (
+  XORCY   blk00000015 (
     .CI(sig0000005d),
     .LI(sig0000007e),
-    .O(p[42])
+    .O(p[43])
   );
-  MUXCY   blk0000001a (
+  MUXCY   blk00000016 (
     .CI(sig0000005d),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig0000007e),
     .O(sig0000005e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000001b (
-    .I0(sig0000014e),
+  blk00000017 (
+    .I0(sig0000014d),
     .I1(sig00000163),
     .O(sig0000007e)
   );
-  XORCY   blk0000001c (
+  XORCY   blk00000018 (
     .CI(sig0000005c),
     .LI(sig0000007d),
-    .O(p[41])
+    .O(p[42])
   );
-  MUXCY   blk0000001d (
+  MUXCY   blk00000019 (
     .CI(sig0000005c),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig0000007d),
     .O(sig0000005d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000001e (
-    .I0(sig0000014e),
+  blk0000001a (
+    .I0(sig0000014d),
     .I1(sig00000162),
     .O(sig0000007d)
   );
-  XORCY   blk0000001f (
+  XORCY   blk0000001b (
     .CI(sig0000005b),
     .LI(sig0000007c),
-    .O(p[40])
+    .O(p[41])
   );
-  MUXCY   blk00000020 (
+  MUXCY   blk0000001c (
     .CI(sig0000005b),
-    .DI(sig0000014e),
+    .DI(sig0000014d),
     .S(sig0000007c),
     .O(sig0000005c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000021 (
-    .I0(sig0000014e),
+  blk0000001d (
+    .I0(sig0000014d),
     .I1(sig00000161),
     .O(sig0000007c)
   );
-  XORCY   blk00000022 (
+  XORCY   blk0000001e (
     .CI(sig0000005a),
     .LI(sig0000007b),
-    .O(p[39])
+    .O(p[40])
   );
-  MUXCY   blk00000023 (
+  MUXCY   blk0000001f (
     .CI(sig0000005a),
     .DI(sig0000014d),
     .S(sig0000007b),
@@ -680,17 +659,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000024 (
+  blk00000020 (
     .I0(sig0000014d),
     .I1(sig00000160),
     .O(sig0000007b)
   );
-  XORCY   blk00000025 (
+  XORCY   blk00000021 (
     .CI(sig00000059),
     .LI(sig0000007a),
-    .O(p[38])
+    .O(p[39])
   );
-  MUXCY   blk00000026 (
+  MUXCY   blk00000022 (
     .CI(sig00000059),
     .DI(sig0000014c),
     .S(sig0000007a),
@@ -698,53 +677,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000027 (
+  blk00000023 (
     .I0(sig0000014c),
     .I1(sig0000015f),
     .O(sig0000007a)
   );
-  XORCY   blk00000028 (
-    .CI(sig00000057),
+  XORCY   blk00000024 (
+    .CI(sig00000058),
     .LI(sig00000079),
-    .O(p[37])
+    .O(p[38])
   );
-  MUXCY   blk00000029 (
-    .CI(sig00000057),
+  MUXCY   blk00000025 (
+    .CI(sig00000058),
     .DI(sig0000014b),
     .S(sig00000079),
     .O(sig00000059)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000002a (
+  blk00000026 (
     .I0(sig0000014b),
     .I1(sig0000015e),
     .O(sig00000079)
   );
-  XORCY   blk0000002b (
+  XORCY   blk00000027 (
     .CI(sig00000056),
-    .LI(sig00000077),
-    .O(p[36])
+    .LI(sig00000078),
+    .O(p[37])
   );
-  MUXCY   blk0000002c (
+  MUXCY   blk00000028 (
     .CI(sig00000056),
-    .DI(sig00000149),
-    .S(sig00000077),
-    .O(sig00000057)
+    .DI(sig0000014a),
+    .S(sig00000078),
+    .O(sig00000058)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000002d (
-    .I0(sig00000149),
+  blk00000029 (
+    .I0(sig0000014a),
     .I1(sig0000015d),
-    .O(sig00000077)
+    .O(sig00000078)
   );
-  XORCY   blk0000002e (
+  XORCY   blk0000002a (
     .CI(sig00000055),
     .LI(sig00000076),
-    .O(p[35])
+    .O(p[36])
   );
-  MUXCY   blk0000002f (
+  MUXCY   blk0000002b (
     .CI(sig00000055),
     .DI(sig00000148),
     .S(sig00000076),
@@ -752,17 +731,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000030 (
+  blk0000002c (
     .I0(sig00000148),
     .I1(sig0000015c),
     .O(sig00000076)
   );
-  XORCY   blk00000031 (
+  XORCY   blk0000002d (
     .CI(sig00000054),
     .LI(sig00000075),
-    .O(p[34])
+    .O(p[35])
   );
-  MUXCY   blk00000032 (
+  MUXCY   blk0000002e (
     .CI(sig00000054),
     .DI(sig00000147),
     .S(sig00000075),
@@ -770,17 +749,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000033 (
+  blk0000002f (
     .I0(sig00000147),
-    .I1(sig00000157),
+    .I1(sig0000015b),
     .O(sig00000075)
   );
-  XORCY   blk00000034 (
+  XORCY   blk00000030 (
     .CI(sig00000053),
     .LI(sig00000074),
-    .O(p[33])
+    .O(p[34])
   );
-  MUXCY   blk00000035 (
+  MUXCY   blk00000031 (
     .CI(sig00000053),
     .DI(sig00000146),
     .S(sig00000074),
@@ -788,17 +767,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000036 (
+  blk00000032 (
     .I0(sig00000146),
-    .I1(sig00000121),
+    .I1(sig00000156),
     .O(sig00000074)
   );
-  XORCY   blk00000037 (
+  XORCY   blk00000033 (
     .CI(sig00000052),
     .LI(sig00000073),
-    .O(p[32])
+    .O(p[33])
   );
-  MUXCY   blk00000038 (
+  MUXCY   blk00000034 (
     .CI(sig00000052),
     .DI(sig00000145),
     .S(sig00000073),
@@ -806,17 +785,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000039 (
+  blk00000035 (
     .I0(sig00000145),
     .I1(sig00000120),
     .O(sig00000073)
   );
-  XORCY   blk0000003a (
+  XORCY   blk00000036 (
     .CI(sig00000051),
     .LI(sig00000072),
-    .O(p[31])
+    .O(p[32])
   );
-  MUXCY   blk0000003b (
+  MUXCY   blk00000037 (
     .CI(sig00000051),
     .DI(sig00000144),
     .S(sig00000072),
@@ -824,17 +803,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000003c (
+  blk00000038 (
     .I0(sig00000144),
     .I1(sig0000011f),
     .O(sig00000072)
   );
-  XORCY   blk0000003d (
+  XORCY   blk00000039 (
     .CI(sig00000050),
     .LI(sig00000071),
-    .O(p[30])
+    .O(p[31])
   );
-  MUXCY   blk0000003e (
+  MUXCY   blk0000003a (
     .CI(sig00000050),
     .DI(sig00000143),
     .S(sig00000071),
@@ -842,17 +821,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000003f (
+  blk0000003b (
     .I0(sig00000143),
     .I1(sig0000011e),
     .O(sig00000071)
   );
-  XORCY   blk00000040 (
+  XORCY   blk0000003c (
     .CI(sig0000004f),
     .LI(sig00000070),
-    .O(p[29])
+    .O(p[30])
   );
-  MUXCY   blk00000041 (
+  MUXCY   blk0000003d (
     .CI(sig0000004f),
     .DI(sig00000142),
     .S(sig00000070),
@@ -860,17 +839,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000042 (
+  blk0000003e (
     .I0(sig00000142),
     .I1(sig0000011d),
     .O(sig00000070)
   );
-  XORCY   blk00000043 (
+  XORCY   blk0000003f (
     .CI(sig0000004e),
     .LI(sig0000006f),
-    .O(p[28])
+    .O(p[29])
   );
-  MUXCY   blk00000044 (
+  MUXCY   blk00000040 (
     .CI(sig0000004e),
     .DI(sig00000141),
     .S(sig0000006f),
@@ -878,53 +857,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000045 (
+  blk00000041 (
     .I0(sig00000141),
     .I1(sig0000011c),
     .O(sig0000006f)
   );
-  XORCY   blk00000046 (
-    .CI(sig0000006c),
+  XORCY   blk00000042 (
+    .CI(sig0000004d),
     .LI(sig0000006e),
-    .O(p[27])
+    .O(p[28])
   );
-  MUXCY   blk00000047 (
-    .CI(sig0000006c),
+  MUXCY   blk00000043 (
+    .CI(sig0000004d),
     .DI(sig00000140),
     .S(sig0000006e),
     .O(sig0000004e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000048 (
+  blk00000044 (
     .I0(sig00000140),
     .I1(sig0000011b),
     .O(sig0000006e)
   );
-  XORCY   blk00000049 (
+  XORCY   blk00000045 (
     .CI(sig0000006b),
-    .LI(sig0000008d),
-    .O(p[26])
+    .LI(sig0000006d),
+    .O(p[27])
   );
-  MUXCY   blk0000004a (
+  MUXCY   blk00000046 (
     .CI(sig0000006b),
-    .DI(sig00000156),
-    .S(sig0000008d),
-    .O(sig0000006c)
+    .DI(sig0000013f),
+    .S(sig0000006d),
+    .O(sig0000004d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000004b (
-    .I0(sig00000156),
-    .I1(sig00000130),
-    .O(sig0000008d)
+  blk00000047 (
+    .I0(sig0000013f),
+    .I1(sig0000011a),
+    .O(sig0000006d)
   );
-  XORCY   blk0000004c (
+  XORCY   blk00000048 (
     .CI(sig0000006a),
     .LI(sig0000008c),
-    .O(p[25])
+    .O(p[26])
   );
-  MUXCY   blk0000004d (
+  MUXCY   blk00000049 (
     .CI(sig0000006a),
     .DI(sig00000155),
     .S(sig0000008c),
@@ -932,17 +911,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000004e (
+  blk0000004a (
     .I0(sig00000155),
     .I1(sig0000012f),
     .O(sig0000008c)
   );
-  XORCY   blk0000004f (
+  XORCY   blk0000004b (
     .CI(sig00000069),
     .LI(sig0000008b),
-    .O(p[24])
+    .O(p[25])
   );
-  MUXCY   blk00000050 (
+  MUXCY   blk0000004c (
     .CI(sig00000069),
     .DI(sig00000154),
     .S(sig0000008b),
@@ -950,17 +929,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000051 (
+  blk0000004d (
     .I0(sig00000154),
     .I1(sig0000012e),
     .O(sig0000008b)
   );
-  XORCY   blk00000052 (
+  XORCY   blk0000004e (
     .CI(sig00000068),
     .LI(sig0000008a),
-    .O(p[23])
+    .O(p[24])
   );
-  MUXCY   blk00000053 (
+  MUXCY   blk0000004f (
     .CI(sig00000068),
     .DI(sig00000153),
     .S(sig0000008a),
@@ -968,17 +947,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000054 (
+  blk00000050 (
     .I0(sig00000153),
     .I1(sig0000012d),
     .O(sig0000008a)
   );
-  XORCY   blk00000055 (
+  XORCY   blk00000051 (
     .CI(sig00000067),
     .LI(sig00000089),
-    .O(p[22])
+    .O(p[23])
   );
-  MUXCY   blk00000056 (
+  MUXCY   blk00000052 (
     .CI(sig00000067),
     .DI(sig00000152),
     .S(sig00000089),
@@ -986,17 +965,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000057 (
+  blk00000053 (
     .I0(sig00000152),
     .I1(sig0000012c),
     .O(sig00000089)
   );
-  XORCY   blk00000058 (
+  XORCY   blk00000054 (
     .CI(sig00000066),
     .LI(sig00000088),
-    .O(p[21])
+    .O(p[22])
   );
-  MUXCY   blk00000059 (
+  MUXCY   blk00000055 (
     .CI(sig00000066),
     .DI(sig00000151),
     .S(sig00000088),
@@ -1004,209 +983,209 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000005a (
+  blk00000056 (
     .I0(sig00000151),
     .I1(sig0000012b),
     .O(sig00000088)
   );
-  XORCY   blk0000005b (
-    .CI(sig00000063),
+  XORCY   blk00000057 (
+    .CI(sig00000065),
     .LI(sig00000087),
-    .O(p[20])
+    .O(p[21])
   );
-  MUXCY   blk0000005c (
-    .CI(sig00000063),
+  MUXCY   blk00000058 (
+    .CI(sig00000065),
     .DI(sig00000150),
     .S(sig00000087),
     .O(sig00000066)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000005d (
+  blk00000059 (
     .I0(sig00000150),
     .I1(sig0000012a),
     .O(sig00000087)
   );
-  XORCY   blk0000005e (
-    .CI(sig00000058),
-    .LI(sig00000083),
+  XORCY   blk0000005a (
+    .CI(sig00000062),
+    .LI(sig00000086),
+    .O(p[20])
+  );
+  MUXCY   blk0000005b (
+    .CI(sig00000062),
+    .DI(sig0000014f),
+    .S(sig00000086),
+    .O(sig00000065)
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  blk0000005c (
+    .I0(sig0000014f),
+    .I1(sig00000129),
+    .O(sig00000086)
+  );
+  XORCY   blk0000005d (
+    .CI(sig00000057),
+    .LI(sig00000082),
     .O(p[19])
   );
-  MUXCY   blk0000005f (
-    .CI(sig00000058),
-    .DI(sig0000014f),
-    .S(sig00000083),
-    .O(sig00000063)
+  MUXCY   blk0000005e (
+    .CI(sig00000057),
+    .DI(sig0000014e),
+    .S(sig00000082),
+    .O(sig00000062)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000060 (
-    .I0(sig0000014f),
-    .I1(sig00000125),
-    .O(sig00000083)
+  blk0000005f (
+    .I0(sig0000014e),
+    .I1(sig00000124),
+    .O(sig00000082)
   );
-  XORCY   blk00000061 (
-    .CI(sig0000004d),
-    .LI(sig00000078),
+  XORCY   blk00000060 (
+    .CI(sig0000004c),
+    .LI(sig00000077),
     .O(p[18])
   );
-  MUXCY   blk00000062 (
-    .CI(sig0000004d),
-    .DI(sig0000014a),
-    .S(sig00000078),
-    .O(sig00000058)
+  MUXCY   blk00000061 (
+    .CI(sig0000004c),
+    .DI(sig00000149),
+    .S(sig00000077),
+    .O(sig00000057)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000063 (
-    .I0(sig0000014a),
-    .I1(sig0000011a),
-    .O(sig00000078)
+  blk00000062 (
+    .I0(sig00000149),
+    .I1(sig00000119),
+    .O(sig00000077)
   );
-  XORCY   blk00000064 (
+  XORCY   blk00000063 (
     .CI(sig00000001),
-    .LI(sig0000006d),
+    .LI(sig0000006c),
     .O(p[17])
   );
-  MUXCY   blk00000065 (
+  MUXCY   blk00000064 (
     .CI(sig00000001),
-    .DI(sig0000013f),
-    .S(sig0000006d),
-    .O(sig0000004d)
+    .DI(sig0000013e),
+    .S(sig0000006c),
+    .O(sig0000004c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000066 (
-    .I0(sig0000013f),
-    .I1(sig00000119),
-    .O(sig0000006d)
+  blk00000065 (
+    .I0(sig0000013e),
+    .I1(sig00000118),
+    .O(sig0000006c)
   );
-  XORCY   blk00000067 (
-    .CI(sig00000011),
-    .LI(sig00000029),
-    .O(sig0000014e)
-  );
-  LUT2 #(
-    .INIT ( 4'h6 ))
-  blk00000068 (
-    .I0(sig00000100),
-    .I1(sig00000111),
-    .O(sig00000029)
-  );
-  XORCY   blk00000069 (
+  XORCY   blk00000066 (
     .CI(sig00000010),
     .LI(sig00000028),
     .O(sig0000014d)
   );
-  MUXCY   blk0000006a (
-    .CI(sig00000010),
-    .DI(sig00000100),
-    .S(sig00000028),
-    .O(sig00000011)
-  );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000006b (
-    .I0(sig00000100),
+  blk00000067 (
+    .I0(sig000000ff),
     .I1(sig00000110),
     .O(sig00000028)
   );
-  XORCY   blk0000006c (
+  XORCY   blk00000068 (
     .CI(sig0000000f),
     .LI(sig00000027),
     .O(sig0000014c)
   );
-  MUXCY   blk0000006d (
+  MUXCY   blk00000069 (
     .CI(sig0000000f),
-    .DI(sig00000100),
+    .DI(sig000000ff),
     .S(sig00000027),
     .O(sig00000010)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000006e (
-    .I0(sig00000100),
+  blk0000006a (
+    .I0(sig000000ff),
     .I1(sig0000010f),
     .O(sig00000027)
   );
-  XORCY   blk0000006f (
-    .CI(sig0000000d),
+  XORCY   blk0000006b (
+    .CI(sig0000000e),
     .LI(sig00000026),
     .O(sig0000014b)
   );
-  MUXCY   blk00000070 (
-    .CI(sig0000000d),
-    .DI(sig00000100),
+  MUXCY   blk0000006c (
+    .CI(sig0000000e),
+    .DI(sig000000ff),
     .S(sig00000026),
     .O(sig0000000f)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000071 (
-    .I0(sig00000100),
+  blk0000006d (
+    .I0(sig000000ff),
     .I1(sig0000010e),
     .O(sig00000026)
   );
-  XORCY   blk00000072 (
+  XORCY   blk0000006e (
     .CI(sig0000000c),
-    .LI(sig00000024),
-    .O(sig00000149)
+    .LI(sig00000025),
+    .O(sig0000014a)
   );
-  MUXCY   blk00000073 (
+  MUXCY   blk0000006f (
     .CI(sig0000000c),
-    .DI(sig00000100),
-    .S(sig00000024),
-    .O(sig0000000d)
+    .DI(sig000000ff),
+    .S(sig00000025),
+    .O(sig0000000e)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000074 (
-    .I0(sig00000100),
-    .I1(sig0000010c),
-    .O(sig00000024)
+  blk00000070 (
+    .I0(sig000000ff),
+    .I1(sig0000010d),
+    .O(sig00000025)
   );
-  XORCY   blk00000075 (
+  XORCY   blk00000071 (
     .CI(sig0000000b),
     .LI(sig00000023),
     .O(sig00000148)
   );
-  MUXCY   blk00000076 (
+  MUXCY   blk00000072 (
     .CI(sig0000000b),
-    .DI(sig00000100),
+    .DI(sig000000ff),
     .S(sig00000023),
     .O(sig0000000c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000077 (
-    .I0(sig00000100),
+  blk00000073 (
+    .I0(sig000000ff),
     .I1(sig0000010b),
     .O(sig00000023)
   );
-  XORCY   blk00000078 (
+  XORCY   blk00000074 (
     .CI(sig0000000a),
     .LI(sig00000022),
     .O(sig00000147)
   );
-  MUXCY   blk00000079 (
+  MUXCY   blk00000075 (
     .CI(sig0000000a),
-    .DI(sig00000100),
+    .DI(sig000000ff),
     .S(sig00000022),
     .O(sig0000000b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000007a (
-    .I0(sig00000100),
+  blk00000076 (
+    .I0(sig000000ff),
     .I1(sig0000010a),
     .O(sig00000022)
   );
-  XORCY   blk0000007b (
+  XORCY   blk00000077 (
     .CI(sig00000009),
     .LI(sig00000021),
     .O(sig00000146)
   );
-  MUXCY   blk0000007c (
+  MUXCY   blk00000078 (
     .CI(sig00000009),
     .DI(sig000000ff),
     .S(sig00000021),
@@ -1214,17 +1193,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000007d (
+  blk00000079 (
     .I0(sig000000ff),
     .I1(sig00000109),
     .O(sig00000021)
   );
-  XORCY   blk0000007e (
+  XORCY   blk0000007a (
     .CI(sig00000008),
     .LI(sig00000020),
     .O(sig00000145)
   );
-  MUXCY   blk0000007f (
+  MUXCY   blk0000007b (
     .CI(sig00000008),
     .DI(sig000000fe),
     .S(sig00000020),
@@ -1232,17 +1211,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000080 (
+  blk0000007c (
     .I0(sig000000fe),
     .I1(sig00000108),
     .O(sig00000020)
   );
-  XORCY   blk00000081 (
+  XORCY   blk0000007d (
     .CI(sig00000007),
     .LI(sig0000001f),
     .O(sig00000144)
   );
-  MUXCY   blk00000082 (
+  MUXCY   blk0000007e (
     .CI(sig00000007),
     .DI(sig000000fd),
     .S(sig0000001f),
@@ -1250,17 +1229,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000083 (
+  blk0000007f (
     .I0(sig000000fd),
     .I1(sig00000107),
     .O(sig0000001f)
   );
-  XORCY   blk00000084 (
+  XORCY   blk00000080 (
     .CI(sig00000006),
     .LI(sig0000001e),
     .O(sig00000143)
   );
-  MUXCY   blk00000085 (
+  MUXCY   blk00000081 (
     .CI(sig00000006),
     .DI(sig000000fc),
     .S(sig0000001e),
@@ -1268,17 +1247,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000086 (
+  blk00000082 (
     .I0(sig000000fc),
     .I1(sig00000106),
     .O(sig0000001e)
   );
-  XORCY   blk00000087 (
+  XORCY   blk00000083 (
     .CI(sig00000005),
     .LI(sig0000001d),
     .O(sig00000142)
   );
-  MUXCY   blk00000088 (
+  MUXCY   blk00000084 (
     .CI(sig00000005),
     .DI(sig000000fb),
     .S(sig0000001d),
@@ -1286,17 +1265,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000089 (
+  blk00000085 (
     .I0(sig000000fb),
     .I1(sig00000105),
     .O(sig0000001d)
   );
-  XORCY   blk0000008a (
+  XORCY   blk00000086 (
     .CI(sig00000004),
     .LI(sig0000001c),
     .O(sig00000141)
   );
-  MUXCY   blk0000008b (
+  MUXCY   blk00000087 (
     .CI(sig00000004),
     .DI(sig000000fa),
     .S(sig0000001c),
@@ -1304,53 +1283,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000008c (
+  blk00000088 (
     .I0(sig000000fa),
     .I1(sig00000104),
     .O(sig0000001c)
   );
-  XORCY   blk0000008d (
-    .CI(sig00000019),
+  XORCY   blk00000089 (
+    .CI(sig00000003),
     .LI(sig0000001b),
     .O(sig00000140)
   );
-  MUXCY   blk0000008e (
-    .CI(sig00000019),
+  MUXCY   blk0000008a (
+    .CI(sig00000003),
     .DI(sig000000f9),
     .S(sig0000001b),
     .O(sig00000004)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000008f (
+  blk0000008b (
     .I0(sig000000f9),
     .I1(sig00000103),
     .O(sig0000001b)
   );
-  XORCY   blk00000090 (
+  XORCY   blk0000008c (
     .CI(sig00000018),
-    .LI(sig00000031),
-    .O(sig00000156)
+    .LI(sig0000001a),
+    .O(sig0000013f)
   );
-  MUXCY   blk00000091 (
+  MUXCY   blk0000008d (
     .CI(sig00000018),
     .DI(sig000000f8),
-    .S(sig00000031),
-    .O(sig00000019)
+    .S(sig0000001a),
+    .O(sig00000003)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000092 (
+  blk0000008e (
     .I0(sig000000f8),
-    .I1(sig00000118),
-    .O(sig00000031)
+    .I1(sig00000102),
+    .O(sig0000001a)
   );
-  XORCY   blk00000093 (
+  XORCY   blk0000008f (
     .CI(sig00000017),
     .LI(sig00000030),
     .O(sig00000155)
   );
-  MUXCY   blk00000094 (
+  MUXCY   blk00000090 (
     .CI(sig00000017),
     .DI(sig000000f7),
     .S(sig00000030),
@@ -1358,17 +1337,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000095 (
+  blk00000091 (
     .I0(sig000000f7),
     .I1(sig00000117),
     .O(sig00000030)
   );
-  XORCY   blk00000096 (
+  XORCY   blk00000092 (
     .CI(sig00000016),
     .LI(sig0000002f),
     .O(sig00000154)
   );
-  MUXCY   blk00000097 (
+  MUXCY   blk00000093 (
     .CI(sig00000016),
     .DI(sig000000f6),
     .S(sig0000002f),
@@ -1376,17 +1355,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk00000098 (
+  blk00000094 (
     .I0(sig000000f6),
     .I1(sig00000116),
     .O(sig0000002f)
   );
-  XORCY   blk00000099 (
+  XORCY   blk00000095 (
     .CI(sig00000015),
     .LI(sig0000002e),
     .O(sig00000153)
   );
-  MUXCY   blk0000009a (
+  MUXCY   blk00000096 (
     .CI(sig00000015),
     .DI(sig000000f5),
     .S(sig0000002e),
@@ -1394,17 +1373,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000009b (
+  blk00000097 (
     .I0(sig000000f5),
     .I1(sig00000115),
     .O(sig0000002e)
   );
-  XORCY   blk0000009c (
+  XORCY   blk00000098 (
     .CI(sig00000014),
     .LI(sig0000002d),
     .O(sig00000152)
   );
-  MUXCY   blk0000009d (
+  MUXCY   blk00000099 (
     .CI(sig00000014),
     .DI(sig000000f4),
     .S(sig0000002d),
@@ -1412,17 +1391,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk0000009e (
+  blk0000009a (
     .I0(sig000000f4),
     .I1(sig00000114),
     .O(sig0000002d)
   );
-  XORCY   blk0000009f (
+  XORCY   blk0000009b (
     .CI(sig00000013),
     .LI(sig0000002c),
     .O(sig00000151)
   );
-  MUXCY   blk000000a0 (
+  MUXCY   blk0000009c (
     .CI(sig00000013),
     .DI(sig000000f3),
     .S(sig0000002c),
@@ -1430,17 +1409,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000a1 (
+  blk0000009d (
     .I0(sig000000f3),
     .I1(sig00000113),
     .O(sig0000002c)
   );
-  XORCY   blk000000a2 (
+  XORCY   blk0000009e (
     .CI(sig00000012),
     .LI(sig0000002b),
     .O(sig00000150)
   );
-  MUXCY   blk000000a3 (
+  MUXCY   blk0000009f (
     .CI(sig00000012),
     .DI(sig000000f2),
     .S(sig0000002b),
@@ -1448,209 +1427,209 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000a4 (
+  blk000000a0 (
     .I0(sig000000f2),
     .I1(sig00000112),
     .O(sig0000002b)
   );
-  XORCY   blk000000a5 (
-    .CI(sig0000000e),
+  XORCY   blk000000a1 (
+    .CI(sig00000011),
     .LI(sig0000002a),
     .O(sig0000014f)
   );
-  MUXCY   blk000000a6 (
-    .CI(sig0000000e),
+  MUXCY   blk000000a2 (
+    .CI(sig00000011),
     .DI(sig000000f1),
     .S(sig0000002a),
     .O(sig00000012)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000a7 (
+  blk000000a3 (
     .I0(sig000000f1),
-    .I1(sig0000010d),
+    .I1(sig00000111),
     .O(sig0000002a)
   );
-  XORCY   blk000000a8 (
-    .CI(sig00000003),
-    .LI(sig00000025),
-    .O(sig0000014a)
+  XORCY   blk000000a4 (
+    .CI(sig0000000d),
+    .LI(sig00000029),
+    .O(sig0000014e)
   );
-  MUXCY   blk000000a9 (
-    .CI(sig00000003),
+  MUXCY   blk000000a5 (
+    .CI(sig0000000d),
     .DI(sig000000f0),
-    .S(sig00000025),
-    .O(sig0000000e)
+    .S(sig00000029),
+    .O(sig00000011)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000aa (
+  blk000000a6 (
     .I0(sig000000f0),
-    .I1(sig00000102),
-    .O(sig00000025)
+    .I1(sig0000010c),
+    .O(sig00000029)
   );
-  XORCY   blk000000ab (
-    .CI(sig00000001),
-    .LI(sig0000001a),
-    .O(sig0000013f)
+  XORCY   blk000000a7 (
+    .CI(sig00000002),
+    .LI(sig00000024),
+    .O(sig00000149)
   );
-  MUXCY   blk000000ac (
-    .CI(sig00000001),
+  MUXCY   blk000000a8 (
+    .CI(sig00000002),
     .DI(sig000000ef),
-    .S(sig0000001a),
-    .O(sig00000003)
+    .S(sig00000024),
+    .O(sig0000000d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000ad (
+  blk000000a9 (
     .I0(sig000000ef),
     .I1(sig00000101),
-    .O(sig0000001a)
+    .O(sig00000024)
   );
-  XORCY   blk000000ae (
-    .CI(sig00000035),
-    .LI(sig00000043),
-    .O(sig0000015b)
+  XORCY   blk000000aa (
+    .CI(sig00000001),
+    .LI(sig00000019),
+    .O(sig0000013e)
+  );
+  MUXCY   blk000000ab (
+    .CI(sig00000001),
+    .DI(sig000000ee),
+    .S(sig00000019),
+    .O(sig00000002)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000af (
-    .I0(sig00000129),
-    .I1(sig00000136),
-    .O(sig00000043)
+  blk000000ac (
+    .I0(sig000000ee),
+    .I1(sig00000100),
+    .O(sig00000019)
   );
-  XORCY   blk000000b0 (
+  XORCY   blk000000ad (
     .CI(sig00000034),
     .LI(sig00000042),
     .O(sig0000015a)
   );
-  MUXCY   blk000000b1 (
-    .CI(sig00000034),
-    .DI(sig00000129),
-    .S(sig00000042),
-    .O(sig00000035)
-  );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000b2 (
-    .I0(sig00000129),
+  blk000000ae (
+    .I0(sig00000128),
     .I1(sig00000135),
     .O(sig00000042)
   );
-  XORCY   blk000000b3 (
+  XORCY   blk000000af (
     .CI(sig00000033),
     .LI(sig00000041),
     .O(sig00000159)
   );
-  MUXCY   blk000000b4 (
+  MUXCY   blk000000b0 (
     .CI(sig00000033),
-    .DI(sig00000129),
+    .DI(sig00000128),
     .S(sig00000041),
     .O(sig00000034)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000b5 (
-    .I0(sig00000129),
+  blk000000b1 (
+    .I0(sig00000128),
     .I1(sig00000134),
     .O(sig00000041)
   );
-  XORCY   blk000000b6 (
-    .CI(sig0000003e),
+  XORCY   blk000000b2 (
+    .CI(sig00000032),
     .LI(sig00000040),
     .O(sig00000158)
   );
-  MUXCY   blk000000b7 (
-    .CI(sig0000003e),
-    .DI(sig00000129),
+  MUXCY   blk000000b3 (
+    .CI(sig00000032),
+    .DI(sig00000128),
     .S(sig00000040),
     .O(sig00000033)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000b8 (
-    .I0(sig00000129),
+  blk000000b4 (
+    .I0(sig00000128),
     .I1(sig00000133),
     .O(sig00000040)
   );
-  XORCY   blk000000b9 (
+  XORCY   blk000000b5 (
     .CI(sig0000003d),
-    .LI(sig0000004c),
-    .O(sig00000164)
+    .LI(sig0000003f),
+    .O(sig00000157)
   );
-  MUXCY   blk000000ba (
+  MUXCY   blk000000b6 (
     .CI(sig0000003d),
-    .DI(sig00000129),
-    .S(sig0000004c),
-    .O(sig0000003e)
+    .DI(sig00000128),
+    .S(sig0000003f),
+    .O(sig00000032)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000bb (
-    .I0(sig00000129),
-    .I1(sig0000013e),
-    .O(sig0000004c)
+  blk000000b7 (
+    .I0(sig00000128),
+    .I1(sig00000132),
+    .O(sig0000003f)
   );
-  XORCY   blk000000bc (
+  XORCY   blk000000b8 (
     .CI(sig0000003c),
     .LI(sig0000004b),
     .O(sig00000163)
   );
-  MUXCY   blk000000bd (
+  MUXCY   blk000000b9 (
     .CI(sig0000003c),
-    .DI(sig00000129),
+    .DI(sig00000128),
     .S(sig0000004b),
     .O(sig0000003d)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000be (
-    .I0(sig00000129),
+  blk000000ba (
+    .I0(sig00000128),
     .I1(sig0000013d),
     .O(sig0000004b)
   );
-  XORCY   blk000000bf (
+  XORCY   blk000000bb (
     .CI(sig0000003b),
     .LI(sig0000004a),
     .O(sig00000162)
   );
-  MUXCY   blk000000c0 (
+  MUXCY   blk000000bc (
     .CI(sig0000003b),
-    .DI(sig00000129),
+    .DI(sig00000128),
     .S(sig0000004a),
     .O(sig0000003c)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000c1 (
-    .I0(sig00000129),
+  blk000000bd (
+    .I0(sig00000128),
     .I1(sig0000013c),
     .O(sig0000004a)
   );
-  XORCY   blk000000c2 (
+  XORCY   blk000000be (
     .CI(sig0000003a),
     .LI(sig00000049),
     .O(sig00000161)
   );
-  MUXCY   blk000000c3 (
+  MUXCY   blk000000bf (
     .CI(sig0000003a),
-    .DI(sig00000129),
+    .DI(sig00000128),
     .S(sig00000049),
     .O(sig0000003b)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000c4 (
-    .I0(sig00000129),
+  blk000000c0 (
+    .I0(sig00000128),
     .I1(sig0000013b),
     .O(sig00000049)
   );
-  XORCY   blk000000c5 (
+  XORCY   blk000000c1 (
     .CI(sig00000039),
     .LI(sig00000048),
     .O(sig00000160)
   );
-  MUXCY   blk000000c6 (
+  MUXCY   blk000000c2 (
     .CI(sig00000039),
     .DI(sig00000128),
     .S(sig00000048),
@@ -1658,17 +1637,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000c7 (
+  blk000000c3 (
     .I0(sig00000128),
     .I1(sig0000013a),
     .O(sig00000048)
   );
-  XORCY   blk000000c8 (
+  XORCY   blk000000c4 (
     .CI(sig00000038),
     .LI(sig00000047),
     .O(sig0000015f)
   );
-  MUXCY   blk000000c9 (
+  MUXCY   blk000000c5 (
     .CI(sig00000038),
     .DI(sig00000127),
     .S(sig00000047),
@@ -1676,17 +1655,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000ca (
+  blk000000c6 (
     .I0(sig00000127),
     .I1(sig00000139),
     .O(sig00000047)
   );
-  XORCY   blk000000cb (
+  XORCY   blk000000c7 (
     .CI(sig00000037),
     .LI(sig00000046),
     .O(sig0000015e)
   );
-  MUXCY   blk000000cc (
+  MUXCY   blk000000c8 (
     .CI(sig00000037),
     .DI(sig00000126),
     .S(sig00000046),
@@ -1694,742 +1673,857 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e})
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000cd (
+  blk000000c9 (
     .I0(sig00000126),
     .I1(sig00000138),
     .O(sig00000046)
   );
-  XORCY   blk000000ce (
+  XORCY   blk000000ca (
     .CI(sig00000036),
     .LI(sig00000045),
     .O(sig0000015d)
   );
-  MUXCY   blk000000cf (
+  MUXCY   blk000000cb (
     .CI(sig00000036),
-    .DI(sig00000124),
+    .DI(sig00000125),
     .S(sig00000045),
     .O(sig00000037)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000d0 (
-    .I0(sig00000124),
+  blk000000cc (
+    .I0(sig00000125),
     .I1(sig00000137),
     .O(sig00000045)
   );
-  XORCY   blk000000d1 (
-    .CI(sig00000032),
+  XORCY   blk000000cd (
+    .CI(sig00000035),
     .LI(sig00000044),
     .O(sig0000015c)
   );
-  MUXCY   blk000000d2 (
-    .CI(sig00000032),
+  MUXCY   blk000000ce (
+    .CI(sig00000035),
     .DI(sig00000123),
     .S(sig00000044),
     .O(sig00000036)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000d3 (
+  blk000000cf (
     .I0(sig00000123),
-    .I1(sig00000132),
+    .I1(sig00000136),
     .O(sig00000044)
   );
-  XORCY   blk000000d4 (
-    .CI(sig00000001),
-    .LI(sig0000003f),
-    .O(sig00000157)
+  XORCY   blk000000d0 (
+    .CI(sig00000031),
+    .LI(sig00000043),
+    .O(sig0000015b)
   );
-  MUXCY   blk000000d5 (
-    .CI(sig00000001),
+  MUXCY   blk000000d1 (
+    .CI(sig00000031),
     .DI(sig00000122),
-    .S(sig0000003f),
-    .O(sig00000032)
+    .S(sig00000043),
+    .O(sig00000035)
   );
   LUT2 #(
     .INIT ( 4'h6 ))
-  blk000000d6 (
+  blk000000d2 (
     .I0(sig00000122),
     .I1(sig00000131),
-    .O(sig0000003f)
+    .O(sig00000043)
   );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000d7 (
-    .C(clk),
-    .D(sig000000d8),
-    .Q(sig00000129)
+  XORCY   blk000000d3 (
+    .CI(sig00000001),
+    .LI(sig0000003e),
+    .O(sig00000156)
   );
-  FD #(
+  MUXCY   blk000000d4 (
+    .CI(sig00000001),
+    .DI(sig00000121),
+    .S(sig0000003e),
+    .O(sig00000031)
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  blk000000d5 (
+    .I0(sig00000121),
+    .I1(sig00000130),
+    .O(sig0000003e)
+  );
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000d8 (
+  blk000000d6 (
     .C(clk),
+    .CE(ce),
     .D(sig000000d7),
     .Q(sig00000128)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000d9 (
+  blk000000d7 (
     .C(clk),
+    .CE(ce),
     .D(sig000000d6),
     .Q(sig00000127)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000da (
+  blk000000d8 (
     .C(clk),
+    .CE(ce),
     .D(sig000000d5),
     .Q(sig00000126)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000db (
+  blk000000d9 (
     .C(clk),
-    .D(sig000000d3),
-    .Q(sig00000124)
+    .CE(ce),
+    .D(sig000000d4),
+    .Q(sig00000125)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000dc (
+  blk000000da (
     .C(clk),
+    .CE(ce),
     .D(sig000000d2),
     .Q(sig00000123)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000dd (
+  blk000000db (
     .C(clk),
+    .CE(ce),
     .D(sig000000d1),
     .Q(sig00000122)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000de (
+  blk000000dc (
     .C(clk),
+    .CE(ce),
     .D(sig000000d0),
     .Q(sig00000121)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000df (
+  blk000000dd (
     .C(clk),
+    .CE(ce),
     .D(sig000000cf),
     .Q(sig00000120)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e0 (
+  blk000000de (
     .C(clk),
+    .CE(ce),
     .D(sig000000ce),
     .Q(sig0000011f)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e1 (
+  blk000000df (
     .C(clk),
+    .CE(ce),
     .D(sig000000cd),
     .Q(sig0000011e)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e2 (
+  blk000000e0 (
     .C(clk),
+    .CE(ce),
     .D(sig000000cc),
     .Q(sig0000011d)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e3 (
+  blk000000e1 (
     .C(clk),
+    .CE(ce),
     .D(sig000000cb),
     .Q(sig0000011c)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e4 (
+  blk000000e2 (
     .C(clk),
+    .CE(ce),
     .D(sig000000ca),
     .Q(sig0000011b)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e5 (
+  blk000000e3 (
     .C(clk),
-    .D(sig000000e0),
-    .Q(sig00000130)
+    .CE(ce),
+    .D(sig000000c9),
+    .Q(sig0000011a)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e6 (
+  blk000000e4 (
     .C(clk),
+    .CE(ce),
     .D(sig000000df),
     .Q(sig0000012f)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e7 (
+  blk000000e5 (
     .C(clk),
+    .CE(ce),
     .D(sig000000de),
     .Q(sig0000012e)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e8 (
+  blk000000e6 (
     .C(clk),
+    .CE(ce),
     .D(sig000000dd),
     .Q(sig0000012d)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000e9 (
+  blk000000e7 (
     .C(clk),
+    .CE(ce),
     .D(sig000000dc),
     .Q(sig0000012c)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000ea (
+  blk000000e8 (
     .C(clk),
+    .CE(ce),
     .D(sig000000db),
     .Q(sig0000012b)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000eb (
+  blk000000e9 (
     .C(clk),
+    .CE(ce),
     .D(sig000000da),
     .Q(sig0000012a)
   );
-  FD #(
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000ea (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000d9),
+    .Q(sig00000129)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000eb (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000d8),
+    .Q(sig00000124)
+  );
+  FDE #(
     .INIT ( 1'b0 ))
   blk000000ec (
     .C(clk),
-    .D(sig000000d9),
-    .Q(sig00000125)
+    .CE(ce),
+    .D(sig000000d3),
+    .Q(sig00000119)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk000000ed (
     .C(clk),
-    .D(sig000000d4),
-    .Q(sig0000011a)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000ee (
-    .C(clk),
-    .D(sig000000c9),
-    .Q(sig00000119)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000ef (
-    .C(clk),
-    .D(sig000000c0),
-    .Q(sig00000111)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f0 (
-    .C(clk),
-    .D(sig000000bf),
-    .Q(sig00000110)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f1 (
-    .C(clk),
-    .D(sig000000be),
-    .Q(sig0000010f)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f2 (
-    .C(clk),
-    .D(sig000000bd),
-    .Q(sig0000010e)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f3 (
-    .C(clk),
-    .D(sig000000bb),
-    .Q(sig0000010c)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f4 (
-    .C(clk),
-    .D(sig000000ba),
-    .Q(sig0000010b)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f5 (
-    .C(clk),
-    .D(sig000000b9),
-    .Q(sig0000010a)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f6 (
-    .C(clk),
-    .D(sig000000b8),
-    .Q(sig00000109)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f7 (
-    .C(clk),
-    .D(sig000000b7),
-    .Q(sig00000108)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f8 (
-    .C(clk),
-    .D(sig000000b6),
-    .Q(sig00000107)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000f9 (
-    .C(clk),
-    .D(sig000000b5),
-    .Q(sig00000106)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000fa (
-    .C(clk),
-    .D(sig000000b4),
-    .Q(sig00000105)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000fb (
-    .C(clk),
-    .D(sig000000b3),
-    .Q(sig00000104)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000fc (
-    .C(clk),
-    .D(sig000000b2),
-    .Q(sig00000103)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk000000fd (
-    .C(clk),
+    .CE(ce),
     .D(sig000000c8),
     .Q(sig00000118)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000fe (
+  blk000000ee (
     .C(clk),
+    .CE(ce),
+    .D(sig000000bf),
+    .Q(sig00000110)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000ef (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000be),
+    .Q(sig0000010f)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f0 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000bd),
+    .Q(sig0000010e)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f1 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000bc),
+    .Q(sig0000010d)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f2 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000ba),
+    .Q(sig0000010b)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f3 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b9),
+    .Q(sig0000010a)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f4 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b8),
+    .Q(sig00000109)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f5 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b7),
+    .Q(sig00000108)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f6 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b6),
+    .Q(sig00000107)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f7 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b5),
+    .Q(sig00000106)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f8 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b4),
+    .Q(sig00000105)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000f9 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b3),
+    .Q(sig00000104)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000fa (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b2),
+    .Q(sig00000103)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000fb (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000b1),
+    .Q(sig00000102)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk000000fc (
+    .C(clk),
+    .CE(ce),
     .D(sig000000c7),
     .Q(sig00000117)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk000000ff (
+  blk000000fd (
     .C(clk),
+    .CE(ce),
     .D(sig000000c6),
     .Q(sig00000116)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000100 (
+  blk000000fe (
     .C(clk),
+    .CE(ce),
     .D(sig000000c5),
     .Q(sig00000115)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000101 (
+  blk000000ff (
     .C(clk),
+    .CE(ce),
     .D(sig000000c4),
     .Q(sig00000114)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000102 (
+  blk00000100 (
     .C(clk),
+    .CE(ce),
     .D(sig000000c3),
     .Q(sig00000113)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000103 (
+  blk00000101 (
     .C(clk),
+    .CE(ce),
     .D(sig000000c2),
     .Q(sig00000112)
   );
-  FD #(
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000102 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000c1),
+    .Q(sig00000111)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000103 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000c0),
+    .Q(sig0000010c)
+  );
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000104 (
     .C(clk),
-    .D(sig000000c1),
-    .Q(sig0000010d)
+    .CE(ce),
+    .D(sig000000bb),
+    .Q(sig00000101)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000105 (
     .C(clk),
-    .D(sig000000bc),
-    .Q(sig00000102)
+    .CE(ce),
+    .D(sig000000b0),
+    .Q(sig00000100)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000106 (
     .C(clk),
-    .D(sig000000b1),
-    .Q(sig00000101)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000107 (
-    .C(clk),
-    .D(sig000000e5),
-    .Q(sig00000136)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000108 (
-    .C(clk),
+    .CE(ce),
     .D(sig000000e4),
     .Q(sig00000135)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000109 (
+  blk00000107 (
     .C(clk),
+    .CE(ce),
     .D(sig000000e3),
     .Q(sig00000134)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010a (
+  blk00000108 (
     .C(clk),
+    .CE(ce),
     .D(sig000000e2),
     .Q(sig00000133)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010b (
+  blk00000109 (
     .C(clk),
-    .D(sig000000ee),
-    .Q(sig0000013e)
+    .CE(ce),
+    .D(sig000000e1),
+    .Q(sig00000132)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010c (
+  blk0000010a (
     .C(clk),
+    .CE(ce),
     .D(sig000000ed),
     .Q(sig0000013d)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010d (
+  blk0000010b (
     .C(clk),
+    .CE(ce),
     .D(sig000000ec),
     .Q(sig0000013c)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010e (
+  blk0000010c (
     .C(clk),
+    .CE(ce),
     .D(sig000000eb),
     .Q(sig0000013b)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000010f (
+  blk0000010d (
     .C(clk),
+    .CE(ce),
     .D(sig000000ea),
     .Q(sig0000013a)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000110 (
+  blk0000010e (
     .C(clk),
+    .CE(ce),
     .D(sig000000e9),
     .Q(sig00000139)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000111 (
+  blk0000010f (
     .C(clk),
+    .CE(ce),
     .D(sig000000e8),
     .Q(sig00000138)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000112 (
+  blk00000110 (
     .C(clk),
+    .CE(ce),
     .D(sig000000e7),
     .Q(sig00000137)
   );
-  FD #(
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000111 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000e6),
+    .Q(sig00000136)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000112 (
+    .C(clk),
+    .CE(ce),
+    .D(sig000000e5),
+    .Q(sig00000131)
+  );
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000113 (
     .C(clk),
-    .D(sig000000e6),
-    .Q(sig00000132)
+    .CE(ce),
+    .D(sig000000e0),
+    .Q(sig00000130)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000114 (
     .C(clk),
-    .D(sig000000e1),
-    .Q(sig00000131)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000115 (
-    .C(clk),
-    .D(sig000000a9),
-    .Q(sig00000100)
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000116 (
-    .C(clk),
+    .CE(ce),
     .D(sig000000a8),
     .Q(sig000000ff)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000117 (
+  blk00000115 (
     .C(clk),
+    .CE(ce),
     .D(sig000000a7),
     .Q(sig000000fe)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000118 (
+  blk00000116 (
     .C(clk),
+    .CE(ce),
     .D(sig000000a6),
     .Q(sig000000fd)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000119 (
+  blk00000117 (
     .C(clk),
+    .CE(ce),
     .D(sig000000a5),
     .Q(sig000000fc)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011a (
+  blk00000118 (
     .C(clk),
-    .D(sig000000a3),
+    .CE(ce),
+    .D(sig000000a4),
     .Q(sig000000fb)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011b (
+  blk00000119 (
     .C(clk),
+    .CE(ce),
     .D(sig000000a2),
     .Q(sig000000fa)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011c (
+  blk0000011a (
     .C(clk),
+    .CE(ce),
     .D(sig000000a1),
     .Q(sig000000f9)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011d (
+  blk0000011b (
     .C(clk),
+    .CE(ce),
     .D(sig000000a0),
     .Q(sig000000f8)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011e (
+  blk0000011c (
     .C(clk),
+    .CE(ce),
     .D(sig0000009f),
     .Q(sig000000f7)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk0000011f (
+  blk0000011d (
     .C(clk),
+    .CE(ce),
     .D(sig0000009e),
     .Q(sig000000f6)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000120 (
+  blk0000011e (
     .C(clk),
+    .CE(ce),
     .D(sig0000009d),
     .Q(sig000000f5)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000121 (
+  blk0000011f (
     .C(clk),
+    .CE(ce),
     .D(sig0000009c),
     .Q(sig000000f4)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000122 (
+  blk00000120 (
     .C(clk),
+    .CE(ce),
     .D(sig0000009b),
     .Q(sig000000f3)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000123 (
+  blk00000121 (
     .C(clk),
+    .CE(ce),
     .D(sig0000009a),
     .Q(sig000000f2)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000124 (
+  blk00000122 (
     .C(clk),
-    .D(sig00000098),
+    .CE(ce),
+    .D(sig00000099),
     .Q(sig000000f1)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000125 (
+  blk00000123 (
     .C(clk),
+    .CE(ce),
     .D(sig00000097),
     .Q(sig000000f0)
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
-  blk00000126 (
+  blk00000124 (
     .C(clk),
+    .CE(ce),
     .D(sig00000096),
     .Q(sig000000ef)
   );
-  FD #(
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000125 (
+    .C(clk),
+    .CE(ce),
+    .D(sig00000095),
+    .Q(sig000000ee)
+  );
+  FDE #(
+    .INIT ( 1'b0 ))
+  blk00000126 (
+    .C(clk),
+    .CE(ce),
+    .D(sig00000094),
+    .Q(p[16])
+  );
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000127 (
     .C(clk),
-    .D(sig00000095),
-    .Q(p[16])
+    .CE(ce),
+    .D(sig00000093),
+    .Q(p[15])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000128 (
     .C(clk),
-    .D(sig00000094),
-    .Q(p[15])
+    .CE(ce),
+    .D(sig00000092),
+    .Q(p[14])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000129 (
     .C(clk),
-    .D(sig00000093),
-    .Q(p[14])
+    .CE(ce),
+    .D(sig00000091),
+    .Q(p[13])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012a (
     .C(clk),
-    .D(sig00000092),
-    .Q(p[13])
+    .CE(ce),
+    .D(sig00000090),
+    .Q(p[12])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012b (
     .C(clk),
-    .D(sig00000091),
-    .Q(p[12])
+    .CE(ce),
+    .D(sig0000008f),
+    .Q(p[11])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012c (
     .C(clk),
-    .D(sig00000090),
-    .Q(p[11])
+    .CE(ce),
+    .D(sig0000008e),
+    .Q(p[10])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012d (
     .C(clk),
-    .D(sig0000008f),
-    .Q(p[10])
+    .CE(ce),
+    .D(sig000000af),
+    .Q(p[9])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012e (
     .C(clk),
-    .D(sig000000b0),
-    .Q(p[9])
+    .CE(ce),
+    .D(sig000000ae),
+    .Q(p[8])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk0000012f (
     .C(clk),
-    .D(sig000000af),
-    .Q(p[8])
+    .CE(ce),
+    .D(sig000000ad),
+    .Q(p[7])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000130 (
     .C(clk),
-    .D(sig000000ae),
-    .Q(p[7])
+    .CE(ce),
+    .D(sig000000ac),
+    .Q(p[6])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000131 (
     .C(clk),
-    .D(sig000000ad),
-    .Q(p[6])
+    .CE(ce),
+    .D(sig000000ab),
+    .Q(p[5])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000132 (
     .C(clk),
-    .D(sig000000ac),
-    .Q(p[5])
+    .CE(ce),
+    .D(sig000000aa),
+    .Q(p[4])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000133 (
     .C(clk),
-    .D(sig000000ab),
-    .Q(p[4])
+    .CE(ce),
+    .D(sig000000a9),
+    .Q(p[3])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000134 (
     .C(clk),
-    .D(sig000000aa),
-    .Q(p[3])
+    .CE(ce),
+    .D(sig000000a3),
+    .Q(p[2])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000135 (
     .C(clk),
-    .D(sig000000a4),
-    .Q(p[2])
+    .CE(ce),
+    .D(sig00000098),
+    .Q(p[1])
   );
-  FD #(
+  FDE #(
     .INIT ( 1'b0 ))
   blk00000136 (
     .C(clk),
-    .D(sig00000099),
-    .Q(p[1])
-  );
-  FD #(
-    .INIT ( 1'b0 ))
-  blk00000137 (
-    .C(clk),
-    .D(sig0000008e),
+    .CE(ce),
+    .D(sig0000008d),
     .Q(p[0])
   );
 
diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco
index 13cf374..0935e67 100644
--- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco
+++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.2
-# Date: Fri Oct 28 08:30:26 2011
+# Date: Sun Oct 30 20:22:20 2011
 #
 ##############################################################
 #
@@ -40,7 +40,7 @@ SELECT Multiplier xilinx.com:ip:mult_gen:11.2
 # END Select
 # BEGIN Parameters
 CSET ccmimp=Distributed_Memory
-CSET clockenable=false
+CSET clockenable=true
 CSET component_name=cx4_mul
 CSET constvalue=129
 CSET internaluser=0
@@ -65,4 +65,4 @@ CSET zerodetect=false
 MISC pkg_timestamp=2011-06-21T06:26:54.000Z
 # END Extra information
 GENERATE
-# CRC: efe4d30e
+# CRC:  4f144c3
diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
index 60829e7..ed5595c 100644
--- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
+++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise
@@ -29,29 +29,335 @@
   </files>
 
   <properties>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|cx4_mul" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="cx4_mul.ngc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/cx4_mul" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="cx4_mul" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="cx4_mul_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="cx4_mul_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="cx4_mul_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="cx4_mul_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="cx4_mul" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-28T10:30:58" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5048768FEE0CA0B8A63A1C80E928CC84" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-30T21:22:43" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7C4ED2F86A69C26BC7F2AA5B611C709F" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise
index a182ee5..ca19fae 100644
--- a/verilog/sd2snes_cx4/sd2snes_cx4.xise
+++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise
@@ -238,7 +238,7 @@
     <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
@@ -253,7 +253,7 @@
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="30" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
@@ -290,7 +290,7 @@
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
@@ -321,7 +321,7 @@
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="30" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="30" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
@@ -330,7 +330,7 @@
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -366,8 +366,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="5" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>