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mk2 fw: iap preparation, so96 mapper, reduce db size, delay with real sleep mode, cli

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This commit is contained in:
ikari 2010-10-04 09:36:32 +02:00
parent 220b8c32a4
commit 46a42fe5ac
14 changed files with 101 additions and 35 deletions
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2
src/Makefile
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@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes
# List C source files here. (C dependencies are automatically generated.)
SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c sdcard.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c
SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c sdcard.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c
# List Assembler source files here.

18
src/config.h
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@ -27,9 +27,21 @@
#define SSP_CLK_DIVISOR_FPGA_FAST 6
#define SSP_CLK_DIVISOR_FPGA_SLOW 16
#define SNES_RESET_REG LPC_GPIO1
#define SNES_RESET_BIT 29
/* XXX Rev.B: 26 */
#define SNES_RESET_REG LPC_GPIO1
#define SNES_RESET_BIT 29
/* XXX Rev.B: 1.26 */
#define SNES_CIC_D0_REG LPC_GPIO1
#define SNES_CIC_D0_BIT 26
/* XXX Rev.B: 0.1 */
#define SNES_CIC_D1_REG LPC_GPIO1
#define SNES_CIC_D1_BIT 25
/* XXX Rev.B: 0.0 */
#define SNES_CIC_STATUS_REG LPC_GPIO0
#define SNES_CIC_STATUS_BIT 1
/* XXX Rev.B: 1.29 */
#define SNES_CIC_PAIR_REG LPC_GPIO0
#define SNES_CIC_PAIR_BIT 0
/* XXX Rev.B: 1.25 */
#define QSORT_MAXELEM 1024

2
src/crc32.c
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@ -22,7 +22,7 @@
/**
* Static table used for the table_driven implementation.
*****************************************************************************/
static const uint32_t crc32_table[256] IN_AHBRAM = {
static const uint32_t crc32_table[256] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,

2
src/ffconf.h
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@ -110,7 +110,7 @@
/ enable LFN feature and set _LFN_UNICODE to 1. */
#define _FS_RPATH 0 /* 0 to 2 */
#define _FS_RPATH 2 /* 0 to 2 */
/* The _FS_RPATH option configures relative path feature.
/
/ 0: Disable relative path feature and remove related functions.

2
src/fileops.h
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@ -33,7 +33,7 @@ BYTE file_buf[512];
FATFS fatfs;
FIL file_handle;
FRESULT file_res;
uint8_t file_lfn[256];
uint8_t file_lfn[258];
void file_init(void);
void file_open(uint8_t* filename, BYTE flags);

4
src/filetypes.c
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@ -184,7 +184,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
file_close();
*/
/* write element pointer to current dir structure */
printf("d=%d Saving %lX to Address %lX [file]\n", depth, db_tgt, dir_tgt);
/* printf("d=%d Saving %lX to Address %lX [file]\n", depth, db_tgt, dir_tgt); */
if((db_tgt&0xffff) > ((0x10000-(sizeof(romprops) + sizeof(len) + pathlen + 1))&0xffff)) {
printf("switch! old=%lx ", db_tgt);
db_tgt &= 0xffff0000;
@ -222,8 +222,6 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
}
} else uart_putc(0x30+res);
}
/*printf("%x\n", crc);
_delay_ms(50); */
sram_writelong(db_tgt, SRAM_DB_ADDR+4);
sram_writelong(dir_end, SRAM_DB_ADDR+8);
return crc;

4
src/fpga.c
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@ -52,10 +52,6 @@
#include "led.h"
#include "timer.h"
/*
DWORD get_fattime(void) {
return 0L;
}*/
void fpga_set_prog_b(uint8_t val) {
if(val)
BITBAND(PROGBREG->FIOSET, PROGBBIT) = 1;

6
src/lpc1754.ld
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@ -10,9 +10,9 @@ ENTRY(_start)
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x03fe0 /* leave room for IAP */
ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000
}
SECTIONS

25
src/main.c
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@ -19,8 +19,9 @@
#include "snes.h"
#include "led.h"
#include "sort.h"
#include "cic.h"
#include "tests.h"
#include "cli.h"
#define EMC0TOGGLE (3<<4)
#define MR0R (1<<1)
@ -29,7 +30,7 @@ int i;
/* FIXME HACK */
volatile enum diskstates disk_state;
extern volatile tick_t ticks;
int main(void) {
LPC_GPIO2->FIODIR = BV(0) | BV(1) | BV(2);
LPC_GPIO1->FIODIR = 0;
@ -40,10 +41,11 @@ int main(void) {
| BV(3) | BV(5); /* SSP0 (FPGA) except SS */
LPC_PINCON->PINSEL0 = BV(31) /* SSP0 */
| BV(13) | BV(15) | BV(17) | BV(19) /* SSP1 (SD) */
| BV(20) | BV(21); /* MAT3.0 */
| BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
/* enable pull-downs for CIC data lines */
/* pull-down CIC data lines */
LPC_PINCON->PINMODE3 = BV(18) | BV(19) | BV(20) | BV(21);
clock_disconnect();
snes_init();
snes_reset(1);
@ -53,7 +55,7 @@ int main(void) {
fpga_spi_init();
spi_preinit(SPI_FPGA);
spi_preinit(SPI_SD);
/* do this last because the peripheral init()s change PCLK dividers */
/* do this last because the peripheral init()s change PCLK dividers */
clock_init();
sd_init();
@ -61,6 +63,8 @@ int main(void) {
delay_ms(10);
printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
file_init();
cic_init(1);
/* uart_putc('S');
for(p1=0; p1<8192; p1++) {
file_read();
@ -80,6 +84,10 @@ int main(void) {
fpga_init();
fpga_pgm((uint8_t*)"/sd2snes/main.bit");
restart:
if(get_cic_state() == CIC_PAIR) {
printf("PAIR MODE ENGAGED!\n");
cic_pair(CIC_NTSC, CIC_NTSC);
}
rdyled(1);
readled(0);
writeled(0);
@ -149,12 +157,13 @@ restart:
uint8_t cmd = 0;
printf("test sram\n");
while(!sram_reliable()) uart_puts("DERP");
while(!sram_reliable());
printf("ok\n");
sram_hexdump(SRAM_DB_ADDR, 0x200);
while(!cmd) {
cmd=menu_main_loop();
sleep_ms(50);
switch(cmd) {
case SNES_CMD_LOADROM:
get_selected_name(file_lfn);
@ -187,6 +196,10 @@ sram_hexdump(SRAM_DB_ADDR, 0x200);
uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
uint16_t reset_count=0;
while(fpga_test() == FPGA_TEST_TOKEN) {
cli_entrycheck();
sleep_ms(250);
sram_reliable();
printf("%s ", get_cic_statename(get_cic_state()));
snes_reset_now=get_snes_reset();
if(snes_reset_now) {
if(!snes_reset_prev) {

29
src/smc.c
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@ -98,7 +98,7 @@ void smc_id(snes_romprops_t* props) {
}
}
}
/* dprintf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); */
printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */
if(score>=maxscore) {
score_idx=num;
maxscore=score;
@ -111,19 +111,26 @@ void smc_id(snes_romprops_t* props) {
props->offset = 0;
}
/* restore the chosen one */
/* restore the chosen one */
/*dprintf("winner is %d\n", score_idx); */
file_readblock(header, hdr_addr[score_idx], sizeof(snes_header_t));
switch(header->map & 0xef) {
case 0x20:
props->mapper_id = 1;
break;
case 0x21:
case 0x21: /* HiROM */
props->mapper_id = 0;
break;
case 0x25:
case 0x20: /* LoROM */
props->mapper_id = 1;
break;
case 0x25: /* ExHiROM */
props->mapper_id = 2;
break;
case 0x22: /* ExLoROM */
if(file_handle.fsize > 0x400200) {
props->mapper_id = 6; /* SO96 */
} else {
props->mapper_id = 3;
}
break;
default: /* invalid/unsupported mapper, use header location */
switch(score_idx) {
case 0:
@ -132,7 +139,13 @@ void smc_id(snes_romprops_t* props) {
break;
case 2:
case 3:
props->mapper_id = 1;
if(file_handle.fsize > 0x800200) {
props->mapper_id = 6; /* SO96 interleaved */
} else if(file_handle.fsize > 0x400200) {
props->mapper_id = 3; /* ExLoROM */
} else {
props->mapper_id = 1; /* LoROM */
}
break;
case 4:
case 5:

4
src/snes.c
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@ -34,6 +34,8 @@
#include "ff.h"
#include "led.h"
#include "smc.h"
#include "timer.h"
#include "cli.h"
uint8_t initloop=1;
uint32_t saveram_crc, saveram_crc_old;
@ -124,6 +126,8 @@ uint8_t menu_main_loop() {
if(get_snes_reset()) {
cmd = 0;
}
sleep_ms(20);
cli_entrycheck();
}
return cmd;
}

36
src/timer.c
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@ -5,7 +5,7 @@
#include "config.h"
#include "timer.h"
#include "clock.h"
#include "uart.h"
/* bit definitions */
#define RITINT 0
@ -14,6 +14,7 @@
#define PCRIT 16
volatile tick_t ticks;
volatile int wokefromrit;
void __attribute__((weak,noinline)) SysTick_Hook(void) {
/* Empty function for hooking the systick handler */
@ -25,6 +26,16 @@ void SysTick_Handler(void) {
SysTick_Hook();
}
void __attribute__((weak,noinline)) RIT_Hook(void) {
}
void RIT_IRQHandler(void) {
LPC_RIT->RICTRL = BV(RITINT);
NVIC_ClearPendingIRQ(RIT_IRQn);
wokefromrit = 1;
RIT_Hook();
}
void timer_init(void) {
/* turn on power to RIT */
BITBAND(LPC_SC->PCONP, PCRIT) = 1;
@ -36,7 +47,7 @@ void timer_init(void) {
BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
/* enable SysTick */
SysTick_Config(SysTick->CALIB & SysTick_CALIB_TENMS_Msk);
// XXX SysTick_Config(SysTick->CALIB & SysTick_CALIB_TENMS_Msk);
}
extern int testval;
@ -57,8 +68,8 @@ void delay_us(unsigned int time) {
void delay_ms(unsigned int time) {
/* Prepare RIT */
LPC_RIT->RICOUNTER = 0;
LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT);
LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time;
LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT);
/* Wait until RIT signals an interrupt */
while (!(BITBAND(LPC_RIT->RICTRL, RITINT))) ;
@ -66,3 +77,22 @@ void delay_ms(unsigned int time) {
/* Disable RIT */
LPC_RIT->RICTRL = 0;
}
void sleep_ms(unsigned int time) {
wokefromrit = 0;
/* Prepare RIT */
LPC_RIT->RICOUNTER = 0;
LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time;
LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT);
NVIC_EnableIRQ(RIT_IRQn);
/* Wait until RIT signals an interrupt */
//uart_putc(';');
while(!wokefromrit) {
__WFI();
}
NVIC_DisableIRQ(RIT_IRQn);
/* Disable RIT */
LPC_RIT->RICTRL = BV(RITINT);
}

1
src/timer.h
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@ -46,5 +46,6 @@ void delay_us(unsigned int time);
/* delay for "time" milliseconds - uses the RIT */
void delay_ms(unsigned int time);
void sleep_ms(unsigned int time);
#endif

1
src/uart.c
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@ -172,7 +172,6 @@ void uart_putc(char c) {
unsigned char uart_getc(void) {
/* wait for character */
while (!(BITBAND(UART_REGS->LSR, 0))) ;
return UART_REGS->RBR;
}