From 4d7d2102c1c4bbbb1fdcece1108cf36813ba0504 Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Mon, 10 Oct 2011 18:42:00 +0200 Subject: [PATCH 01/66] Add DIP36 footprint (not used) --- pcb/kicad/libs/mypackages.mod | 618 ++++++++++++++++++++++++++++++++-- 1 file changed, 595 insertions(+), 23 deletions(-) diff --git a/pcb/kicad/libs/mypackages.mod b/pcb/kicad/libs/mypackages.mod index a90702e..28caf95 100644 --- a/pcb/kicad/libs/mypackages.mod +++ b/pcb/kicad/libs/mypackages.mod @@ -1,34 +1,36 @@ -PCBNEW-LibModule-V1 Sat 23 Jul 2011 01:19:59 PM CEST +PCBNEW-LibModule-V1 Wed 14 Sep 2011 12:39:55 AM CEST # encoding utf-8 $INDEX -TSSOP48 -PQFP208_ALTPADS -SOT563 -LQFP80-.5 -VFBGA48 -VFBGA54 -VFBGA36 -TSSOP10 -CP_TANTAL_SMD_D BT_KEYSTONE_1059_20MM -XTAL_SMD_05019 -XTAL_SMD_05032 -USB-MINIB-THT -pin_array_7x2 -SM0805_FIXEDMASK +CP_TANTAL_SMD_D +DIP-36 +HC49US LED-3MM-FIXED -QFN10-2x2 +LQFP80-.5 PAD_1x1mm +PQFP208_ALTPADS +QFN10-2x2 +QFN10-2x2_LONGPADS +R_PACK_0804 +SM0805_FIXEDMASK SM1210L SM1210L_NEW -HC49US +SMD_5.7X5.7 +SMD_DO1608 +SOT23-5_LARGEPADS +SOT563 +TSOP40 TSOPII-32 TSOPII-44 -R_PACK_0804 -SMD_5.7X5.7 -SOT23-5_LARGEPADS -SMD_DO1608 -QFN10-2x2_LONGPADS +TSSOP10 +TSSOP48 +USB-MINIB-THT +VFBGA36 +VFBGA48 +VFBGA54 +XTAL_SMD_05019 +XTAL_SMD_05032 +pin_array_7x2 $EndINDEX $MODULE TSSOP48 Po 0 0 0 15 4B6E17E6 00000000 ~~ @@ -5043,7 +5045,7 @@ Cd SOT23-5 Sc 00000000 AR /4B6EC9C3/4B6ED134 Op 0 0 0 -At SMD +At SMD T0 0 -150 300 320 0 70 N V 21 N "U321" T1 0 150 300 250 0 50 N I 21 N "MCP1824-2502E/OT" DS 600 -350 600 350 80 21 @@ -5096,4 +5098,574 @@ Of 0.000000 0.000000 0.000000 Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SOT23-5_LARGEPADS +$MODULE DIP-36 +Po 0 0 0 15 4E6FC26F 00000000 ~~ +Li DIP-36 +Cd Module Dil 36 pins, pads elliptiques, e=600 mils +Kw DIL +Sc 00000000 +AR /4E6FAF78 +Op 0 0 0 +T0 -7500 -1500 700 697 0 113 N V 21 N "U2" +T1 -1300 0 700 700 0 120 N V 21 N "SNESMASKROM" +DS 8000 2500 -10000 2500 118 21 +DS -10000 -2500 8000 -2500 118 21 +DS -10000 600 -10000 2500 118 21 +DS -10000 -2500 -10000 -600 118 21 +DA -10000 0 -9400 0 900 118 21 +DA -10000 0 -10000 -600 900 118 21 +DS 8000 -2500 8000 2500 118 21 +$PAD +Sh "1" R 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 32 "N-000034" +Po -9500 3000 +$EndPAD +$PAD +Sh "2" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 21 "N-000023" +Po -8500 3000 +$EndPAD +$PAD +Sh "3" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 24 "N-000026" +Po -7500 3000 +$EndPAD +$PAD +Sh "4" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 23 "N-000025" +Po -6500 3000 +$EndPAD +$PAD +Sh "5" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 26 "N-000028" +Po -5500 3000 +$EndPAD +$PAD +Sh "6" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 29 "N-000031" +Po -4500 3000 +$EndPAD +$PAD +Sh "7" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 18 "N-000019" +Po -3500 3000 +$EndPAD +$PAD +Sh "8" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 19 "N-000020" +Po -2500 3000 +$EndPAD +$PAD +Sh "9" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 20 "N-000022" +Po -1500 3000 +$EndPAD +$PAD +Sh "10" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 30 "N-000032" +Po -500 3000 +$EndPAD +$PAD +Sh "11" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 33 "N-000035" +Po 500 3000 +$EndPAD +$PAD +Sh "12" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 35 "N-000037" +Po 1500 3000 +$EndPAD +$PAD +Sh "13" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 12 "N-000010" +Po 2500 3000 +$EndPAD +$PAD +Sh "14" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 14 "N-000013" +Po 3500 3000 +$EndPAD +$PAD +Sh "15" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 1 "/D0" +Po 4500 3000 +$EndPAD +$PAD +Sh "16" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 2 "/D1" +Po 5500 3000 +$EndPAD +$PAD +Sh "17" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 3 "/D2" +Po 6500 3000 +$EndPAD +$PAD +Sh "18" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 31 "N-000033" +Po 7500 3000 +$EndPAD +$PAD +Sh "19" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 4 "/D3" +Po 7500 -3000 +$EndPAD +$PAD +Sh "20" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 5 "/D4" +Po 6500 -3000 +$EndPAD +$PAD +Sh "21" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 6 "/D5" +Po 5500 -3000 +$EndPAD +$PAD +Sh "22" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 7 "/D6" +Po 4500 -3000 +$EndPAD +$PAD +Sh "23" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 8 "/D7" +Po 3500 -3000 +$EndPAD +$PAD +Sh "24" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 9 "N-000007" +Po 2500 -3000 +$EndPAD +$PAD +Sh "25" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 13 "N-000012" +Po 1500 -3000 +$EndPAD +$PAD +Sh "26" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 25 "N-000027" +Po 500 -3000 +$EndPAD +$PAD +Sh "27" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 17 "N-000018" +Po -500 -3000 +$EndPAD +$PAD +Sh "28" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 15 "N-000015" +Po -1500 -3000 +$EndPAD +$PAD +Sh "29" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 16 "N-000017" +Po -2500 -3000 +$EndPAD +$PAD +Sh "30" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 28 "N-000030" +Po -3500 -3000 +$EndPAD +$PAD +Sh "31" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 27 "N-000029" +Po -4500 -3000 +$EndPAD +$PAD +Sh "32" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 22 "N-000024" +Po -5500 -3000 +$EndPAD +$PAD +Sh "33" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 10 "N-000008" +Po -6500 -3000 +$EndPAD +$PAD +Sh "34" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 34 "N-000036" +Po -7500 -3000 +$EndPAD +$PAD +Sh "35" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -8500 -3000 +$EndPAD +$PAD +Sh "36" O 620 900 0 0 0 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 11 "N-000009" +Po -9500 -3000 +$EndPAD +$SHAPE3D +Na "dil\\dil_40-w600.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE DIP-36 +$MODULE TSOP40 +Po 0 0 0 15 4E6FDB9E 00000000 ~~ +Li TSOP40 +Sc 00000000 +AR /4E6FAB7B +Op 0 0 0 +T0 1141 906 600 600 0 120 N I 21 N "U1" +T1 0 0 600 600 0 120 N V 21 N "29F032" +DS 3268 -1969 3268 1969 79 21 +DS 3268 1969 -3268 1969 79 21 +DS -3268 -1969 3268 -1969 79 21 +DS -3268 1969 -3268 -1969 79 21 +DC 2896 1615 3071 1690 79 21 +$PAD +Sh "1" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 24 "N-000025" +Po 3828 1870 +$EndPAD +$PAD +Sh "2" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 25 "N-000026" +Po 3828 1673 +$EndPAD +$PAD +Sh "3" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 26 "N-000027" +Po 3828 1476 +$EndPAD +$PAD +Sh "4" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 27 "N-000028" +Po 3828 1279 +$EndPAD +$PAD +Sh "5" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 28 "N-000029" +Po 3828 1082 +$EndPAD +$PAD +Sh "6" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 29 "N-000030" +Po 3828 885 +$EndPAD +$PAD +Sh "7" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 30 "N-000031" +Po 3828 688 +$EndPAD +$PAD +Sh "8" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 31 "N-000032" +Po 3828 492 +$EndPAD +$PAD +Sh "9" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "N-000009" +Po 3828 295 +$EndPAD +$PAD +Sh "10" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+5V" +Po 3828 98 +$EndPAD +$PAD +Sh "11" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3828 -98 +$EndPAD +$PAD +Sh "12" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+5V" +Po 3828 -295 +$EndPAD +$PAD +Sh "13" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 18 "N-000019" +Po 3828 -492 +$EndPAD +$PAD +Sh "14" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "N-000013" +Po 3828 -688 +$EndPAD +$PAD +Sh "15" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 16 "N-000016" +Po 3828 -885 +$EndPAD +$PAD +Sh "16" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "N-000018" +Po 3828 -1082 +$EndPAD +$PAD +Sh "17" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 19 "N-000020" +Po 3828 -1279 +$EndPAD +$PAD +Sh "18" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 20 "N-000021" +Po 3828 -1476 +$EndPAD +$PAD +Sh "19" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 21 "N-000022" +Po 3828 -1673 +$EndPAD +$PAD +Sh "20" R 110 708 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 32 "N-000033" +Po 3828 -1870 +$EndPAD +$PAD +Sh "21" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 34 "N-000036" +Po -3828 -1870 +$EndPAD +$PAD +Sh "22" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 35 "N-000038" +Po -3828 -1673 +$EndPAD +$PAD +Sh "23" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "N-000011" +Po -3828 -1476 +$EndPAD +$PAD +Sh "24" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "N-000014" +Po -3828 -1279 +$EndPAD +$PAD +Sh "25" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "/D0" +Po -3828 -1082 +$EndPAD +$PAD +Sh "26" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "/D1" +Po -3828 -885 +$EndPAD +$PAD +Sh "27" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "/D2" +Po -3828 -688 +$EndPAD +$PAD +Sh "28" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "/D3" +Po -3828 -492 +$EndPAD +$PAD +Sh "29" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "GND" +Po -3828 -295 +$EndPAD +$PAD +Sh "30" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "GND" +Po -3828 -98 +$EndPAD +$PAD +Sh "31" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+5V" +Po -3828 98 +$EndPAD +$PAD +Sh "32" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/D4" +Po -3828 295 +$EndPAD +$PAD +Sh "33" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/D5" +Po -3828 492 +$EndPAD +$PAD +Sh "34" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "/D6" +Po -3828 688 +$EndPAD +$PAD +Sh "35" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/D7" +Po -3828 885 +$EndPAD +$PAD +Sh "36" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3828 1082 +$EndPAD +$PAD +Sh "37" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "N-000010" +Po -3828 1279 +$EndPAD +$PAD +Sh "38" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 23 "N-000024" +Po -3828 1476 +$EndPAD +$PAD +Sh "39" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 22 "N-000023" +Po -3828 1673 +$EndPAD +$PAD +Sh "40" R 110 708 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 33 "N-000035" +Po -3828 1870 +$EndPAD +$EndMODULE TSOP40 $EndLIBRARY From cdf4342edd0dfcd3c543382971617444491b55b3 Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Mon, 10 Oct 2011 18:53:52 +0200 Subject: [PATCH 02/66] Firmware: remove debug statements; disable SuperCIC pair mode by default --- src/main.c | 4 +--- src/memory.c | 4 ++-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/main.c b/src/main.c index 5a1cf09..366072c 100644 --- a/src/main.c +++ b/src/main.c @@ -79,7 +79,7 @@ led_pwm(); printf("PCONP=%lx\n", LPC_SC->PCONP); file_init(); - cic_init(1); + cic_init(0); /* setup timer (fpga clk) */ LPC_TIM3->CTCR=0; LPC_TIM3->EMR=EMC0TOGGLE; @@ -95,7 +95,6 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); newcard = 1; } load_bootrle(SRAM_MENU_ADDR); -sram_hexdump(SRAM_MENU_ADDR+0xffc0, 16); set_saveram_mask(0x1fff); set_rom_mask(0x3fffff); set_mapper(0x7); @@ -222,7 +221,6 @@ sram_hexdump(SRAM_MENU_ADDR+0xffc0, 16); printf("test sram\n"); while(!sram_reliable()) cli_entrycheck(); printf("ok\n"); -sram_hexdump(SRAM_DIR_ADDR, 0x300); //while(1) { // delay_ms(1000); // printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk()); diff --git a/src/memory.c b/src/memory.c index fcb5b3d..784a115 100644 --- a/src/memory.c +++ b/src/memory.c @@ -439,8 +439,8 @@ uint8_t sram_reliable() { val=sram_readlong(SRAM_SCRATCHPAD); if(val==0x12345678) { score++; -/* } else { - dprintf("i=%d val=%08lX\n", i, val); */ + } else { + printf("i=%d val=%08lX\n", i, val); } } if(score Date: Thu, 13 Oct 2011 11:17:19 +0200 Subject: [PATCH 03/66] FPGA: prevent erasure of first ROM byte on reconfiguration --- verilog/sd2snes/sd_dma.v | 1 + 1 file changed, 1 insertion(+) diff --git a/verilog/sd2snes/sd_dma.v b/verilog/sd2snes/sd_dma.v index f3e9618..0d7d2c8 100644 --- a/verilog/sd2snes/sd_dma.v +++ b/verilog/sd2snes/sd_dma.v @@ -59,6 +59,7 @@ reg [10:0] cyclecnt; initial cyclecnt = 11'd0; reg SD_DMA_SRAM_WEr; +initial SD_DMA_SRAM_WEr = 1'b1; assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1; reg SD_DMA_NEXTADDRr; From cce68a82f62dee310e1dff61502b654bbf6e03fa Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Mon, 10 Oct 2011 18:53:52 +0200 Subject: [PATCH 04/66] Firmware: remove debug statements; disable SuperCIC pair mode by default --- src/main.c | 4 +--- src/memory.c | 4 ++-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/main.c b/src/main.c index 5a1cf09..366072c 100644 --- a/src/main.c +++ b/src/main.c @@ -79,7 +79,7 @@ led_pwm(); printf("PCONP=%lx\n", LPC_SC->PCONP); file_init(); - cic_init(1); + cic_init(0); /* setup timer (fpga clk) */ LPC_TIM3->CTCR=0; LPC_TIM3->EMR=EMC0TOGGLE; @@ -95,7 +95,6 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); newcard = 1; } load_bootrle(SRAM_MENU_ADDR); -sram_hexdump(SRAM_MENU_ADDR+0xffc0, 16); set_saveram_mask(0x1fff); set_rom_mask(0x3fffff); set_mapper(0x7); @@ -222,7 +221,6 @@ sram_hexdump(SRAM_MENU_ADDR+0xffc0, 16); printf("test sram\n"); while(!sram_reliable()) cli_entrycheck(); printf("ok\n"); -sram_hexdump(SRAM_DIR_ADDR, 0x300); //while(1) { // delay_ms(1000); // printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk()); diff --git a/src/memory.c b/src/memory.c index fcb5b3d..784a115 100644 --- a/src/memory.c +++ b/src/memory.c @@ -439,8 +439,8 @@ uint8_t sram_reliable() { val=sram_readlong(SRAM_SCRATCHPAD); if(val==0x12345678) { score++; -/* } else { - dprintf("i=%d val=%08lX\n", i, val); */ + } else { + printf("i=%d val=%08lX\n", i, val); } } if(score Date: Sun, 16 Oct 2011 13:46:59 +0200 Subject: [PATCH 05/66] Firmware/CLI: add memory write commands (w8/w16) --- src/cli.c | 50 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/src/cli.c b/src/cli.c index 90b053f..3ddf70a 100644 --- a/src/cli.c +++ b/src/cli.c @@ -58,8 +58,8 @@ static char *curchar; /* Word lists */ static char command_words[] = - "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0"; -enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP }; + "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0"; +enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 }; /* ------------------------------------------------------------------------- */ /* Parse functions */ @@ -76,7 +76,7 @@ static uint8_t skip_spaces(void) { } /* Parse the string in curchar for an integer with bounds [lower,upper] */ -static int32_t parse_unsigned(uint32_t lower, uint32_t upper) { +static int32_t parse_unsigned(uint32_t lower, uint32_t upper, uint8_t base) { char *end; uint32_t result; @@ -85,7 +85,7 @@ static int32_t parse_unsigned(uint32_t lower, uint32_t upper) { return -2; } - result = strtoul(curchar, &end, 10); + result = strtoul(curchar, &end, base); if ((*end != ' ' && *end != 0) || errno != 0) { printf("Invalid numeric argument\n"); return -1; @@ -287,13 +287,13 @@ static void cmd_loadrom(void) { } static void cmd_loadraw(void) { - uint32_t address = parse_unsigned(0,16777216); + uint32_t address = parse_unsigned(0,16777216,16); load_sram((uint8_t*)curchar, address); } static void cmd_saveraw(void) { - uint32_t address = parse_unsigned(0,16777216); - uint32_t length = parse_unsigned(0,16777216); + uint32_t address = parse_unsigned(0,16777216,16); + uint32_t length = parse_unsigned(0,16777216,16); save_sram((uint8_t*)curchar, length, address); } @@ -303,7 +303,7 @@ static void cmd_d4(void) { if(get_cic_state() != CIC_PAIR) { printf("not in pair mode\n"); } else { - hz = parse_unsigned(50,60); + hz = parse_unsigned(50,60,10); if(hz==50) { cic_d4(CIC_PAL); } else { @@ -318,7 +318,7 @@ static void cmd_vmode(void) { if(get_cic_state() != CIC_PAIR) { printf("not in pair mode\n"); } else { - hz = parse_unsigned(50,60); + hz = parse_unsigned(50,60,10); if(hz==50) { cic_videomode(CIC_PAL); } else { @@ -345,7 +345,7 @@ void cmd_put(void) { void cmd_mapper(void) { int32_t mapper; - mapper = parse_unsigned(0,7); + mapper = parse_unsigned(0,7,10); set_mapper((uint8_t)mapper & 0x7); printf("mapper set to %ld\n", mapper); } @@ -353,7 +353,7 @@ void cmd_mapper(void) { void cmd_sreset(void) { if(*curchar != 0) { int32_t resetstate; - resetstate = parse_unsigned(0,1); + resetstate = parse_unsigned(0,1,10); snes_reset(resetstate); } else { snes_reset(1); @@ -389,15 +389,28 @@ void cmd_time(void) { } void cmd_setfeature(void) { - uint8_t feat = parse_unsigned(0, 255); + uint8_t feat = parse_unsigned(0, 255, 16); fpga_set_features(feat); } void cmd_hexdump(void) { - uint32_t offset = parse_unsigned(0, 16777215); - uint32_t len = parse_unsigned(0, 16777216); + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint32_t len = parse_unsigned(0, 16777216, 16); sram_hexdump(offset, len); } + +void cmd_w8(void) { + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint8_t val = parse_unsigned(0, 255, 16); + sram_writebyte(val, offset); +} + +void cmd_w16(void) { + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint16_t val = parse_unsigned(0, 65535, 16); + sram_writeshort(val, offset); +} + /* ------------------------------------------------------------------------- */ /* CLI interface functions */ /* ------------------------------------------------------------------------- */ @@ -531,6 +544,15 @@ void cli_loop(void) { case CMD_HEXDUMP: cmd_hexdump(); break; + + case CMD_W8: + cmd_w8(); + break; + + case CMD_W16: + cmd_w16(); + break; } + } } From e57c4aa450ffe2d30ab52af797503c033dfe0b7f Mon Sep 17 00:00:00 2001 From: ikari Date: Sun, 23 Oct 2011 04:10:55 +0200 Subject: [PATCH 06/66] FPGA/cx4: initial commit --- verilog/sd2snes_cx4/address.v | 64 + verilog/sd2snes_cx4/cx4.v | 636 +++++ verilog/sd2snes_cx4/dac.v | 160 ++ verilog/sd2snes_cx4/dcm.v | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v | 187 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_datram.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_datrom.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v | 2511 +++++++++++++++++ verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco | 68 + verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise | 378 +++ verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/dac_buf.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco | 105 + verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise | 79 + verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v | 181 ++ .../sd2snes_cx4/ipcore_dir/msu_databuf.xco | 105 + .../sd2snes_cx4/ipcore_dir/msu_databuf.xise | 79 + verilog/sd2snes_cx4/main.v | 564 ++++ verilog/sd2snes_cx4/msu.v | 194 ++ verilog/sd2snes_cx4/sd2snes_cx4.xise | 456 +++ verilog/sd2snes_cx4/sd_dma.v | 132 + verilog/sd2snes_cx4/spi.v | 113 + 27 files changed, 7158 insertions(+) create mode 100644 verilog/sd2snes_cx4/address.v create mode 100644 verilog/sd2snes_cx4/cx4.v create mode 100644 verilog/sd2snes_cx4/dac.v create mode 100644 verilog/sd2snes_cx4/dcm.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise create mode 100644 verilog/sd2snes_cx4/main.v create mode 100644 verilog/sd2snes_cx4/msu.v create mode 100644 verilog/sd2snes_cx4/sd2snes_cx4.xise create mode 100644 verilog/sd2snes_cx4/sd_dma.v create mode 100644 verilog/sd2snes_cx4/spi.v diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v new file mode 100644 index 0000000..e62071d --- /dev/null +++ b/verilog/sd2snes_cx4/address.v @@ -0,0 +1,64 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: address +// Project Name: +// Target Devices: +// Tool versions: +// Description: Address logic w/ SaveRAM masking +// +// Dependencies: +// +// Revision: +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module address( + input CLK, + input [2:0] MAPPER, // MCU detected mapper + input [23:0] SNES_ADDR, // requested address from SNES + output [23:0] ROM_ADDR, // Address to request from SRAM0 + output ROM_SEL, // enable SRAM0 (active low) + output IS_SAVERAM, // address/CS mapped as SRAM? + output IS_ROM, // address mapped as ROM? + output IS_WRITABLE, // address somehow mapped as writable area? + input [23:0] SAVERAM_MASK, + input [23:0] ROM_MASK, + input use_msu1, + output msu_enable, + output cx4_enable +); + +wire [23:0] SRAM_SNES_ADDR; + +/* Cx4 mapper: + - LoROM (extended to 00-7d, 80-ff) + - MMIO @ 6000-7fff + */ + +assign IS_ROM = (SNES_ADDR[15]); + +assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} + & ROM_MASK); + +assign ROM_ADDR = SRAM_SNES_ADDR; + +assign ROM_SEL = 1'b0; + +wire msu_enable_w = use_msu1 & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000)); +reg [5:0] msu_enable_r; +initial msu_enable_r = 6'b000000; +always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w}; +assign msu_enable = &msu_enable_r[5:2]; + +wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011)); +reg [5:0] cx4_enable_r; +initial cx4_enable_r = 6'b000000; +always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w}; +assign cx4_enable = &cx4_enable_r[5:2]; + +endmodule diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v new file mode 100644 index 0000000..97286be --- /dev/null +++ b/verilog/sd2snes_cx4/cx4.v @@ -0,0 +1,636 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:14:37 10/13/2011 +// Design Name: +// Module Name: cx4 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module cx4( + input [7:0] DI, + output [7:0] DO, + input [12:0] ADDR, + input CS, + input nRD, + input nWR, + input CLK, + input [23:0] DATROM_DI, + input DATROM_WE, + input [9:0] DATROM_ADDR, + input [7:0] BUS_DI, + output [23:0] BUS_ADDR, + output BUS_RRQ, + input BUS_RDY, + output cx4_active + ); + +reg [2:0] cx4_busy; +parameter BUSY_CACHE = 2'b00; +parameter BUSY_DMA = 2'b01; +parameter BUSY_CPU = 2'b10; + +wire datram_enable = CS & (ADDR[11:0] < 12'hc00); +wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11000); +wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11000); +wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); +wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); +wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); + +wire [7:0] DATRAM_DO; +reg [7:0] MMIO_DOr; +wire [7:0] MMIO_DO; +wire [7:0] STATUS_DO; +wire [7:0] VECTOR_DO; +wire [7:0] GPR_DO; + +assign DO = datram_enable ? DATRAM_DO + : mmio_enable ? MMIO_DO + : status_enable ? STATUS_DO + : vector_enable ? VECTOR_DO + : gpr_enable ? GPR_DO + : 8'h00; + +/* 0x1f40 - 0x1f52: MMIO + SNES: 8 bits / CX4: various */ +reg [23:0] cx4_mmio_dmasrc; +reg [15:0] cx4_mmio_dmalen; +reg [23:0] cx4_mmio_dmatgt; +reg cx4_mmio_cachepage; +reg [23:0] cx4_mmio_pgmoff; +reg [1:0] cx4_mmio_r1f4c; +reg [14:0] cx4_mmio_pgmpage; +reg [7:0] cx4_mmio_pc; +reg [7:0] cx4_mmio_r1f50; +reg cx4_mmio_r1f51; +reg cx4_mmio_r1f52; +/* 0x1f53 - 0x1f5f: status register */ +assign cx4_active = |cx4_busy; +/* 0x1f60 - 0x1f7f: reset vectors */ +reg [7:0] vector [31:0]; +/* 0x1f80 - 0x1faf (0x1fc0 - 0x1fef): general purpose register file + SNES: 8 bits / CX4: 24 bits */ +reg [7:0] gpr [47:0]; +wire [47:0] cpu_mul_result; + +reg [23:0] const [15:0]; + +reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number +initial begin + cachetag[0] = 16'h0000; + cachetag[1] = 16'h0000; + cx4_busy = 3'b000; + cx4_mmio_pgmoff = 24'h000000; + cx4_mmio_pgmpage = 15'h0000; + cx4_mmio_dmasrc = 24'h000000; + cx4_mmio_dmalen = 16'h0000; + cx4_mmio_dmatgt = 24'h000000; + const[0] = 24'h000000; + const[1] = 24'hffffff; + const[2] = 24'h00ff00; + const[3] = 24'hff0000; + const[4] = 24'h00ffff; + const[5] = 24'hffff00; + const[6] = 24'h800000; + const[7] = 24'h7fffff; + const[8] = 24'h008000; + const[9] = 24'h007fff; + const[10] = 24'hff7fff; + const[11] = 24'hffff7f; + const[12] = 24'h010000; + const[13] = 24'hfeffff; + const[14] = 24'h000100; + const[15] = 24'h00feff; +end + +assign MMIO_DO = MMIO_DOr; +assign VECTOR_DO = vector [ADDR[4:0]]; +assign GPR_DO = gpr [ADDR[5:0]]; +assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0}; + +reg [7:0] DIr; +always @(posedge CLK) DIr <= DI; + +reg [4:0] datram_enable_sreg; +initial datram_enable_sreg = 5'b11111; +always @(posedge CLK) datram_enable_sreg <= {datram_enable_sreg[3:0], datram_enable}; + +reg [5:0] nWR_sreg; +always @(posedge CLK) nWR_sreg <= {nWR_sreg[4:0], nWR}; +wire WR_EN = (nWR_sreg[5:0] == 6'b000001); +wire DATRAM_WR_EN = datram_enable & WR_EN; +wire MMIO_WR_EN = mmio_enable & WR_EN; +wire VECTOR_WR_EN = vector_enable & WR_EN; +wire GPR_WR_EN = gpr_enable & WR_EN; + +reg [23:0] cpu_idb; // tmp register for reg file read + +/* Need to cache when: + 1f48 is written + AND (selected cache page is invalid + OR selected cache page does not contain requested page already) +*/ +reg CACHE_TRIG_ENr; +reg CACHE_TRIG_EN2r; +initial begin + CACHE_TRIG_ENr = 1'b0; + CACHE_TRIG_EN2r = 1'b0; +end +always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr; +wire CACHE_TRIG_EN = CACHE_TRIG_EN2r; + +reg DMA_TRIG_ENr; +initial DMA_TRIG_ENr = 1'b0; +wire DMA_TRIG_EN = DMA_TRIG_ENr; + +reg CACHE_BUS_RRQr; +reg DMA_BUS_RRQr; +initial begin + CACHE_BUS_RRQr = 1'b0; + DMA_BUS_RRQr = 1'b0; +end +assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr; + +initial begin + cx4_mmio_r1f50 = 8'h33; + cx4_mmio_r1f51 = 1'b0; + cx4_mmio_r1f52 = 1'b1; +end + +always @(posedge CLK) begin + case (ADDR[4:0]) + 5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40 + 5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41 + 5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42 + 5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43 + 5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44 + 5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45 + 5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46 + 5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47 + 5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage}; + 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 + 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a + 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b + 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c + 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d + 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e + 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f + 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 + 5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51 + 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 + + 5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40 + 5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40 + 5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40 + 5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40 + 5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40 + 5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40 + + +// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40 +// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41 +// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42 +// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43 + default: MMIO_DOr <= 8'hff; + endcase +end + +always @(posedge CLK) begin + if(MMIO_WR_EN) begin + case(ADDR[4:0]) + 5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 + 5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 + 5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 + 5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 + 5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 + 5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 + 5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 + 5'h07: begin + cx4_mmio_dmatgt[23:16] <= DI; // 1f47 + DMA_TRIG_ENr <= 1'b1; + end + 5'h08: begin + cx4_mmio_cachepage <= DI[0]; // 1f48 + CACHE_TRIG_ENr <= 1'b1; + end + 5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 + 5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a + 5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b + 5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c + 5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d + 5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e + 5'h0f: cx4_mmio_pc <= DI; // 1f4f + 5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 + 5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 + 5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 + endcase + end else begin + CACHE_TRIG_ENr <= 1'b0; + DMA_TRIG_ENr <= 1'b0; + end +end + +always @(posedge CLK) begin + if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI; +end + +always @(posedge CLK) begin + if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; +end + +reg [4:0] CACHE_ST; +parameter ST_CACHE_IDLE = 5'b00001; +parameter ST_CACHE_START = 5'b00010; +parameter ST_CACHE_WAIT = 5'b00100; +parameter ST_CACHE_ADDR = 5'b01000; +parameter ST_CACHE_END = 5'b10000; +initial CACHE_ST = ST_CACHE_IDLE; + +reg [4:0] DMA_ST; +parameter ST_DMA_IDLE = 5'b00001; +parameter ST_DMA_START = 5'b00010; +parameter ST_DMA_WAIT = 5'b00100; +parameter ST_DMA_ADDR = 5'b01000; +parameter ST_DMA_END = 5'b10000; +initial DMA_ST = ST_DMA_IDLE; + +reg [23:0] CACHE_SRC_ADDRr; +wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]}; +reg [23:0] DMA_SRC_ADDRr; +wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]}; + +assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR + : cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR + : 24'h000000 /* XXX cx4_bus_addr */; + +reg cx4_pgmrom_we; +initial cx4_pgmrom_we = 1'b0; +reg [9:0] cx4_pgmrom_addr; +reg [19:0] cache_count; +initial cache_count = 20'b0; + +always @(posedge CLK) begin + case(CACHE_ST) + ST_CACHE_IDLE: begin + if(CACHE_TRIG_EN + & (~cachetag[cx4_mmio_cachepage][15] + | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) + begin + CACHE_ST <= ST_CACHE_START; + end else CACHE_ST <= ST_CACHE_IDLE; + end + ST_CACHE_START: begin + cx4_busy[BUSY_CACHE] <= 1'b1; + CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0}; + cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0}; + CACHE_ST <= ST_CACHE_WAIT; + cache_count <= 10'b0; + CACHE_BUS_RRQr <= 1'b1; + end + ST_CACHE_WAIT: begin + CACHE_BUS_RRQr <= 1'b0; + if(~CACHE_BUS_RRQr & BUS_RDY) begin + CACHE_ST <= ST_CACHE_ADDR; + cx4_pgmrom_we <= 1'b1; + cache_count <= cache_count + 1; + end else CACHE_ST <= ST_CACHE_WAIT; + end + ST_CACHE_ADDR: begin + cx4_pgmrom_we <= 1'b0; + CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1; + cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; + if(cache_count == 9'h1ff) begin + cx4_busy[BUSY_CACHE] <= 1'b0; + cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage}; + CACHE_ST <= ST_CACHE_IDLE; + end else begin + CACHE_BUS_RRQr <= 1'b1; + CACHE_ST <= ST_CACHE_WAIT; + end + end + endcase +end + +reg cx4_datram_we; +initial cx4_datram_we = 1'b0; +reg [11:0] cx4_datram_addr; +reg [15:0] dma_count; +initial dma_count = 16'b0; + +always @(posedge CLK) begin + case(DMA_ST) + ST_DMA_IDLE: begin + if(DMA_TRIG_EN) begin + DMA_ST <= ST_DMA_START; + end else DMA_ST <= ST_DMA_IDLE; + end + ST_DMA_START: begin + cx4_busy[BUSY_DMA] <= 1'b1; + DMA_SRC_ADDRr <= cx4_mmio_dmasrc; + /* XXX Rename to DMA_TGT_ADDRr and switch */ + cx4_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff); + DMA_ST <= ST_DMA_WAIT; + dma_count <= cx4_mmio_dmalen; + DMA_BUS_RRQr <= 1'b1; + end + ST_DMA_WAIT: begin + DMA_BUS_RRQr <= 1'b0; + if(~DMA_BUS_RRQr & BUS_RDY) begin + DMA_ST <= ST_DMA_ADDR; + /* XXX Rename to DMA_TGT_WEr and switch */ + cx4_datram_we <= 1'b1; + dma_count <= dma_count - 1; + end else DMA_ST <= ST_DMA_WAIT; + end + ST_DMA_ADDR: begin + /* XXX Rename to DMA_TGT_WEr and switch */ + cx4_datram_we <= 1'b0; + DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1; + cx4_datram_addr <= cx4_datram_addr + 1; + if(dma_count == 16'h0000) begin + cx4_busy[BUSY_DMA] <= 1'b0; + DMA_ST <= ST_DMA_IDLE; + end else begin + DMA_BUS_RRQr <= 1'b1; + DMA_ST <= ST_DMA_WAIT; + end + end + endcase +end + +/*************************** + =========== CPU =========== + ***************************/ +reg [7:0] CPU_STATE; +reg cpu_page; +reg [7:0] cpu_pc; +reg [8:0] cpu_stack [7:0]; +reg [2:0] cpu_sp; +wire [15:0] cpu_op_w; +reg [15:0] cpu_op; +reg [23:0] cpu_a; +reg [23:0] cpu_busdata; +reg [23:0] cpu_romdata; +reg [23:0] cpu_ramdata; +reg [23:0] cpu_busaddr; +reg [23:0] cpu_romaddr; +reg [23:0] cpu_ramaddr; +reg [23:0] cpu_acch; +reg [23:0] cpu_accl; +reg [23:0] cpu_mul_src; + +reg [23:0] cpu_sa; // tmp register for shifted accumulator +reg fl_n; +reg fl_z; +reg fl_c; +reg [15:0] cpu_p; + +reg [9:0] cx4_datrom_addr; +wire [23:0] cx4_datrom_do; +wire [7:0] cx4_datram_do; + +parameter ST_CPU_IDLE = 8'b00000001; +parameter ST_CPU_0 = 8'b00000010; +parameter ST_CPU_1 = 8'b00000100; +parameter ST_CPU_2 = 8'b00001000; +parameter ST_CPU_3 = 8'b00010000; + +initial CPU_STATE <= ST_CPU_IDLE; + +parameter OP_ALU = 4'b0000; +parameter OP_LD = 4'b0001; +parameter OP_ST = 4'b0010; +parameter OP_JP = 4'b0011; +parameter OP_SWP = 4'b0100; +parameter OP_HLT = 4'b0101; +parameter OP_BUS = 4'b0110; +parameter OP_STA = 4'b0111; +parameter OP_NOP = 4'b1111; + + +wire [6:0] op_id = cpu_op_w[15:10]; +reg [7:0] op_param; +reg [2:0] op; +reg [1:0] op_sa; +reg op_imm; +reg op_p; +reg op_call; +reg op_jump; +reg cond_true; +reg cpu_go_rq; +reg cpu_bus_rq; + +always @(posedge CLK) begin + case(CPU_STATE) + ST_CPU_IDLE: begin + if(cpu_go_rq) begin + cpu_pc <= cx4_mmio_pc; + op <= OP_NOP; + CPU_STATE <= ST_CPU_2; + end + else CPU_STATE <= ST_CPU_IDLE; + end + ST_CPU_0: begin // Phase 0: + CPU_STATE <= ST_CPU_1; + case(op) + OP_ALU, OP_LD, OP_SWP: begin + if(cpu_op[15:10] == 6'b111000) cpu_idb <= cpu_a; // reg[imm] <- a + else if(op_imm) cpu_idb <= {16'b0, op_param}; + else casex(op_param) + 8'h00: cpu_idb <= cpu_a; + 8'h01: cpu_idb <= cpu_acch; + 8'h02: cpu_idb <= cpu_accl; + 8'h03: cpu_idb <= cpu_busdata; + 8'h08: cpu_idb <= cpu_romdata; + 8'h0c: cpu_idb <= cpu_ramdata; + 8'h13: cpu_idb <= cpu_busaddr; + 8'h1c: cpu_idb <= cpu_ramaddr; + 8'h5x: cpu_idb <= const[op_param[3:0]]; + 8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]}; + default: cpu_idb <= 24'b0; + endcase + if(op==OP_ALU) begin + case(op_sa) + 2'b00: cpu_sa <= cpu_a; + 2'b01: cpu_sa <= cpu_a << 1; + 2'b10: cpu_sa <= cpu_a << 8; + 2'b11: cpu_sa <= cpu_a << 16; + endcase + end + end + OP_JP: begin + casex(cpu_op[12:8]) + 5'b010xx: cond_true <= 1'b1; + 5'b011xx: cond_true <= fl_z; + 5'b100xx: cond_true <= fl_c; + 5'b101xx: cond_true <= fl_n; + 5'b00101: cond_true <= (fl_c == cpu_op[0]); + 5'b00110: cond_true <= (fl_z == cpu_op[0]); + 5'b00111: cond_true <= (fl_n == cpu_op[0]); + default: cond_true <= 1'b1; + endcase + end + OP_BUS: cpu_bus_rq <= 1'b1; + endcase + end + ST_CPU_1: begin + CPU_STATE <= ST_CPU_2; + case(op) + OP_LD: begin + cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); + cx4_datrom_addr <= cpu_a[9:0]; + end + OP_ST: begin + cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); + cx4_datram_we <= 1'b1; + end + OP_JP: begin + if(cond_true) begin + casex(cpu_op[12:11]) + 2'b01, 2'b10: begin + // TODO if(op_p) + if(op_call) begin + cpu_stack[cpu_sp] <= {cpu_page, cpu_pc+1}; + cpu_sp <= cpu_sp - 1; + end + cpu_pc <= op_param; + end + 2'b00: begin + cpu_pc <= cpu_pc + 2; + end + 2'b11: begin + if(cpu_op[13]) begin + {cpu_page, cpu_pc} <= cpu_stack[cpu_sp+1]; + cpu_sp <= cpu_sp + 1; + end else begin + if(BUS_RDY) cpu_pc <= cpu_pc + 1; + end + end + default: cpu_pc <= cpu_pc + 1; + endcase + end + end + OP_BUS: cpu_bus_rq <= 1'b0; + endcase + end + ST_CPU_2: begin + CPU_STATE <= ST_CPU_3; + case(op) + OP_ST: begin + cx4_datram_we <= 1'b0; + end + endcase + end + ST_CPU_3: begin + CPU_STATE <= ST_CPU_0; + case(op) + OP_LD, OP_SWP: begin + casex(cpu_op[15:8]) + 8'b01100x00: cpu_a <= cpu_idb; + 8'b01100x11: cpu_p <= cpu_idb; + 8'b01111100: cpu_p[7:0] <= op_param; + 8'b01111101: cpu_p[15:8] <= op_param; + 8'b01110000: cpu_romdata <= cx4_datrom_do; + 8'b01101x00: cpu_ramdata[7:0] <= cx4_datram_do; + 8'b01101x01: cpu_ramdata[15:8] <= cx4_datram_do; + 8'b01101x10: cpu_ramdata[23:16] <= cx4_datram_do; + 8'b11110000, 8'b11100000: begin + if(cpu_op[12]) cpu_a <= cpu_idb; + casex(op_param) + 8'h00: cpu_a <= cpu_a; + 8'h01: cpu_acch <= cpu_a; + 8'h02: cpu_accl <= cpu_a; + 8'h03: cpu_busdata <= cpu_a; + 8'h08: cpu_romdata <= cpu_a; + 8'h0c: cpu_ramdata <= cpu_a; + 8'h13: cpu_busaddr <= cpu_a; + 8'h1c: cpu_ramaddr <= cpu_a; + 8'h6x: {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]} <= cpu_a; + endcase + end + endcase + end + endcase + cpu_op <= cpu_op_w; + op_param <= cpu_op_w[7:0]; + op <= &(op_id) ? OP_HLT + :(op_id[5:4] == 2'b00) ? OP_JP + :(op_id[5:2] == 4'b0110 + || op_id[5:2] == 4'b0111 + ) ? OP_LD + :(op_id[5:1] == 5'b11101) ? OP_ST + :(op_id[5:1] == 5'b01000) ? OP_BUS + :(op_id[5:3] == 3'b010 + || op_id[5:3] == 3'b100 + || op_id[5:3] == 3'b101 + || op_id[5:3] == 3'b110) ? OP_ALU + : (op_id == 6'b111100 || op_id == 6'b111000) ? OP_SWP + : OP_NOP; + op_imm <= cpu_op_w[10]; + op_sa <= cpu_op_w[9:8]; + op_p <= cpu_op_w[9]; + op_call <= cpu_op_w[13]; + cond_true <= 1'b0; + end + endcase +end + + +/*************************** + =========== MEM =========== + ***************************/ +cx4_datrom cx4_datrom ( + .clka(CLK), // input clka + .wea(DATROM_WE), // input [0 : 0] wea + .addra(DATROM_ADDR), // input [9 : 0] addra + .dina(DATROM_DI), // input [23 : 0] dina + .clkb(CLK), // input clkb + .addrb(cx4_datrom_addr), // input [9 : 0] addrb + .doutb(cx4_datrom_do) // output [23 : 0] doutb +); + +cx4_datram cx4_datram ( + .clka(CLK), // input clka + .wea(DATRAM_WR_EN), // input [0 : 0] wea + .addra(ADDR[11:0]), // input [11 : 0] addra + .dina(DI), // input [7 : 0] dina + .douta(DATRAM_DO), // output [7 : 0] douta + .clkb(CLK), // input clkb + .web(cx4_datram_we), // input [0 : 0] web + .addrb(cx4_datram_addr), // input [11 : 0] addrb + .dinb(BUS_DI), // input [7 : 0] dinb + .doutb(cx4_datram_do) // output [7 : 0] doutb +); + +cx4_pgmrom cx4_pgmrom ( + .clka(CLK), // input clka + .wea(cx4_pgmrom_we), // input [0 : 0] wea + .addra(cx4_pgmrom_addr), // input [9 : 0] addra + .dina(BUS_DI), // input [7 : 0] dina + .clkb(CLK), // input clkb + .addrb(cpu_pc), // input [8 : 0] addrb + .doutb(cpu_op_w) // output [15 : 0] doutb +); + +cx4_mul cx4_mul ( + .clk(CLK), // input clk + .a(cpu_a), // input [23 : 0] a + .b(cpu_mul_src), // input [23 : 0] b + .p(cpu_mul_result) // output [47 : 0] p +); +endmodule diff --git a/verilog/sd2snes_cx4/dac.v b/verilog/sd2snes_cx4/dac.v new file mode 100644 index 0000000..6eca076 --- /dev/null +++ b/verilog/sd2snes_cx4/dac.v @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:26:11 07/23/2010 +// Design Name: +// Module Name: dac_test +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dac( + input clkin, + input sysclk, + input we, + input[10:0] pgm_address, + input[7:0] pgm_data, + input[7:0] volume, + input vol_latch, + input play, + input reset, + output sdout, + output lrck, + output mclk, + output DAC_STATUS +); + +reg[8:0] dac_address_r; +wire[8:0] dac_address = dac_address_r; + +wire[31:0] dac_data; +assign DAC_STATUS = dac_address_r[8]; +reg[7:0] vol_reg; +reg[7:0] vol_target_reg; +reg[1:0] vol_latch_reg; +reg vol_valid; +reg[2:0] sysclk_sreg; +wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01); + +reg [25:0] interpol_count; + +always @(posedge clkin) begin + sysclk_sreg <= {sysclk_sreg[1:0], sysclk}; +end + +dac_buf snes_dac_buf ( + .clka(clkin), + .wea(~we), // Bus [0 : 0] + .addra(pgm_address), // Bus [10 : 0] + .dina(pgm_data), // Bus [7 : 0] + .clkb(clkin), + .addrb(dac_address), // Bus [8 : 0] + .doutb(dac_data)); // Bus [31 : 0] + +reg [8:0] cnt; +reg [15:0] smpcnt; +reg [1:0] samples; +reg [15:0] smpshift; + +assign mclk = cnt[2]; // mclk = clk/8 +assign lrck = cnt[8]; // lrck = mclk/128 +wire sclk = cnt[3]; // sclk = lrck*32 + +reg [2:0] lrck_sreg; +reg [2:0] sclk_sreg; +wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01); +wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10); + +wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01); + +wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01); +reg sdout_reg; +assign sdout = sdout_reg; + +reg [1:0] reset_sreg; +wire reset_rising = (reset_sreg[1:0] == 2'b01); + +reg play_r; + +initial begin + cnt = 9'h100; + smpcnt = 16'b0; + lrck_sreg = 2'b11; + sclk_sreg = 1'b0; + dac_address_r = 10'b0; + vol_valid = 1'b0; + vol_latch_reg = 1'b0; + vol_reg = 8'h0; + vol_target_reg = 8'hff; + samples <= 2'b00; +end + +always @(posedge clkin) begin + if(reset_rising) begin + dac_address_r <= 0; + interpol_count <= 0; + end else if(sysclk_rising) begin + if(interpol_count > 59378938) begin + interpol_count <= interpol_count + 122500 - 59501439; + dac_address_r <= dac_address_r + play_r; + end else begin + interpol_count <= interpol_count + 122500; + end + end +end + +always @(posedge clkin) begin + cnt <= cnt + 1; + lrck_sreg <= {lrck_sreg[1:0], lrck}; + sclk_sreg <= {sclk_sreg[1:0], sclk}; + vol_latch_reg <= {vol_latch_reg[0], vol_latch}; + play_r <= play; + reset_sreg <= {reset_sreg[0], reset}; +end + +always @(posedge clkin) begin + if (vol_latch_rising) begin + vol_valid <= 1'b1; + end + else if(vol_valid) begin + vol_target_reg <= volume; + vol_valid <= 1'b0; + end +end + +// ramp volume only every 4 samples +always @(posedge clkin) begin + if (lrck_rising && &samples[1:0]) begin + if(vol_reg > vol_target_reg) + vol_reg <= vol_reg - 1; + else if(vol_reg < vol_target_reg) + vol_reg <= vol_reg + 1; + end +end + +always @(posedge clkin) begin + if (lrck_rising) begin // right channel + smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + samples <= samples + 1; + end else if (lrck_falling) begin // left channel + smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + end else begin + if (sclk_rising) begin + smpcnt <= smpcnt + 1; + sdout_reg <= smpshift[15]; + smpshift <= {smpshift[14:0], 1'b0}; + end + end +end + +endmodule diff --git a/verilog/sd2snes_cx4/dcm.v b/verilog/sd2snes_cx4/dcm.v new file mode 100644 index 0000000..90b516e --- /dev/null +++ b/verilog/sd2snes_cx4/dcm.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:06:52 06/28/2009 +// Design Name: +// Module Name: dcm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module my_dcm ( + input CLKIN, + output CLKFX, + output LOCKED, + input RST, + output[7:0] STATUS + ); + + // DCM: Digital Clock Manager Circuit + // Spartan-3 + // Xilinx HDL Language Template, version 11.1 + + DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(41.667), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hFFFF), // FACTORY JF values +// .LOC("DCM_X0Y0"), + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_inst ( + .CLK0(CLK0), // 0 degree DCM CLK output + .CLK180(CLK180), // 180 degree DCM CLK output + .CLK270(CLK270), // 270 degree DCM CLK output + .CLK2X(CLK2X), // 2X DCM CLK output + .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out + .CLK90(CLK90), // 90 degree DCM CLK output + .CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(CLKFX), // DCM CLK synthesis out (M/D) + .CLKFX180(CLKFX180), // 180 degree CLK synthesis out + .LOCKED(LOCKED), // DCM LOCK status output + .PSDONE(PSDONE), // Dynamic phase adjust done output + .STATUS(STATUS), // 8-bit DCM status bits output + .CLKFB(CLKFB), // DCM clock feedback + .CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(PSCLK), // Dynamic phase adjust clock input + .PSEN(PSEN), // Dynamic phase adjust enable input + .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement + .RST(RST) // DCM asynchronous reset input + ); +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v new file mode 100644 index 0000000..329617f --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v @@ -0,0 +1,187 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_datram.v when simulating +// the core, cx4_datram. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_datram( + clka, + wea, + addra, + dina, + douta, + clkb, + web, + addrb, + dinb, + doutb +); + +input clka; +input [0 : 0] wea; +input [11 : 0] addra; +input [7 : 0] dina; +output [7 : 0] douta; +input clkb; +input [0 : 0] web; +input [11 : 0] addrb; +input [7 : 0] dinb; +output [7 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(12), + .C_ADDRB_WIDTH(12), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("77"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(2), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(3072), + .C_READ_DEPTH_B(3072), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(8), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(1), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(3072), + .C_WRITE_DEPTH_B(3072), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(8), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .CLKB(clkb), + .WEB(web), + .ADDRB(addrb), + .DINB(dinb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .RSTB(), + .ENB(), + .REGCEB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco new file mode 100644 index 0000000..a793578 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Sun Oct 16 18:54:12 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_datram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=true +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=77 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=3072 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: a7d60fbd diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise new file mode 100644 index 0000000..511d066 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v new file mode 100644 index 0000000..3825bab --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_datrom.v when simulating +// the core, cx4_datrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_datrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [9 : 0] addra; +input [23 : 0] dina; +input clkb; +input [9 : 0] addrb; +output [23 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(10), + .C_ADDRB_WIDTH(10), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(1024), + .C_READ_DEPTH_B(1024), + .C_READ_WIDTH_A(24), + .C_READ_WIDTH_B(24), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(1024), + .C_WRITE_DEPTH_B(1024), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(24), + .C_WRITE_WIDTH_B(24), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco new file mode 100644 index 0000000..83d9d34 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Sun Oct 16 12:57:23 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_datrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=24 +CSET read_width_b=24 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=1024 +CSET write_width_a=24 +CSET write_width_b=24 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: a25bf9a3 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise new file mode 100644 index 0000000..ded48b2 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v new file mode 100644 index 0000000..32e9bad --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v @@ -0,0 +1,2511 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: O.61xd +// \ \ Application: netgen +// / / Filename: cx4_mul.v +// /___/ /\ Timestamp: Fri Oct 21 22:38:27 2011 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v +// Device : 3s400pq208-4 +// Input file : /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc +// Output file : /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v +// # of Modules : 1 +// Design Name : cx4_mul +// Xilinx : /mnt/store/bin/Xilinx/13.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module cx4_mul ( + clk, p, a, b +)/* synthesis syn_black_box syn_noprune=1 */; + input clk; + output [47 : 0] p; + input [23 : 0] a; + input [23 : 0] b; + + // synthesis translate_off + + wire sig00000001; + wire sig00000002; + wire sig00000003; + wire sig00000004; + wire sig00000005; + wire sig00000006; + wire sig00000007; + wire sig00000008; + wire sig00000009; + wire sig0000000a; + wire sig0000000b; + wire sig0000000c; + wire sig0000000d; + wire sig0000000e; + wire sig0000000f; + wire sig00000010; + wire sig00000011; + wire sig00000012; + wire sig00000013; + wire sig00000014; + wire sig00000015; + wire sig00000016; + wire sig00000017; + wire sig00000018; + wire sig00000019; + wire sig0000001a; + wire sig0000001b; + wire sig0000001c; + wire sig0000001d; + wire sig0000001e; + wire sig0000001f; + wire sig00000020; + wire sig00000021; + wire sig00000022; + wire sig00000023; + wire sig00000024; + wire sig00000025; + wire sig00000026; + wire sig00000027; + wire sig00000028; + wire sig00000029; + wire sig0000002a; + wire sig0000002b; + wire sig0000002c; + wire sig0000002d; + wire sig0000002e; + wire sig0000002f; + wire sig00000030; + wire sig00000031; + wire sig00000032; + wire sig00000033; + wire sig00000034; + wire sig00000035; + wire sig00000036; + wire sig00000037; + wire sig00000038; + wire sig00000039; + wire sig0000003a; + wire sig0000003b; + wire sig0000003c; + wire sig0000003d; + wire sig0000003e; + wire sig0000003f; + wire sig00000040; + wire sig00000041; + wire sig00000042; + wire sig00000043; + wire sig00000044; + wire sig00000045; + wire sig00000046; + wire sig00000047; + wire sig00000048; + wire sig00000049; + wire sig0000004a; + wire sig0000004b; + wire sig0000004c; + wire sig0000004d; + wire sig0000004e; + wire sig0000004f; + wire sig00000050; + wire sig00000051; + wire sig00000052; + wire sig00000053; + wire sig00000054; + wire sig00000055; + wire sig00000056; + wire sig00000057; + wire sig00000058; + wire sig00000059; + wire sig0000005a; + wire sig0000005b; + wire sig0000005c; + wire sig0000005d; + wire sig0000005e; + wire sig0000005f; + wire sig00000060; + wire sig00000061; + wire sig00000062; + wire sig00000063; + wire sig00000064; + wire sig00000065; + wire sig00000066; + wire sig00000067; + wire sig00000068; + wire sig00000069; + wire sig0000006a; + wire sig0000006b; + wire sig0000006c; + wire sig0000006d; + wire sig0000006e; + wire sig0000006f; + wire sig00000070; + wire sig00000071; + wire sig00000072; + wire sig00000073; + wire sig00000074; + wire sig00000075; + wire sig00000076; + wire sig00000077; + wire sig00000078; + wire sig00000079; + wire sig0000007a; + wire sig0000007b; + wire sig0000007c; + wire sig0000007d; + wire sig0000007e; + wire sig0000007f; + wire sig00000080; + wire sig00000081; + wire sig00000082; + wire sig00000083; + wire sig00000084; + wire sig00000085; + wire sig00000086; + wire sig00000087; + wire sig00000088; + wire sig00000089; + wire sig0000008a; + wire sig0000008b; + wire sig0000008c; + wire sig0000008d; + wire sig0000008e; + wire sig0000008f; + wire sig00000090; + wire sig00000091; + wire sig00000092; + wire sig00000093; + wire sig00000094; + wire sig00000095; + wire sig00000096; + wire sig00000097; + wire sig00000098; + wire sig00000099; + wire sig0000009a; + wire sig0000009b; + wire sig0000009c; + wire sig0000009d; + wire sig0000009e; + wire sig0000009f; + wire sig000000a0; + wire sig000000a1; + wire sig000000a2; + wire sig000000a3; + wire sig000000a4; + wire sig000000a5; + wire sig000000a6; + wire sig000000a7; + wire sig000000a8; + wire sig000000a9; + wire sig000000aa; + wire sig000000ab; + wire sig000000ac; + wire sig000000ad; + wire sig000000ae; + wire sig000000af; + wire sig000000b0; + wire sig000000b1; + wire sig000000b2; + wire sig000000b3; + wire sig000000b4; + wire sig000000b5; + wire sig000000b6; + wire sig000000b7; + wire sig000000b8; + wire sig000000b9; + wire sig000000ba; + wire sig000000bb; + wire sig000000bc; + wire sig000000bd; + wire sig000000be; + wire sig000000bf; + wire sig000000c0; + wire sig000000c1; + wire sig000000c2; + wire sig000000c3; + wire sig000000c4; + wire sig000000c5; + wire sig000000c6; + wire sig000000c7; + wire sig000000c8; + wire sig000000c9; + wire sig000000ca; + wire sig000000cb; + wire sig000000cc; + wire sig000000cd; + wire sig000000ce; + wire sig000000cf; + wire sig000000d0; + wire sig000000d1; + wire sig000000d2; + wire sig000000d3; + wire sig000000d4; + wire sig000000d5; + wire sig000000d6; + wire sig000000d7; + wire sig000000d8; + wire sig000000d9; + wire sig000000da; + wire sig000000db; + wire sig000000dc; + wire sig000000dd; + wire sig000000de; + wire sig000000df; + wire sig000000e0; + wire sig000000e1; + wire sig000000e2; + wire sig000000e3; + wire sig000000e4; + wire sig000000e5; + wire sig000000e6; + wire sig000000e7; + wire sig000000e8; + wire sig000000e9; + wire sig000000ea; + wire sig000000eb; + wire sig000000ec; + wire sig000000ed; + wire sig000000ee; + wire sig000000ef; + wire sig000000f0; + wire sig000000f1; + wire sig000000f2; + wire sig000000f3; + wire sig000000f4; + wire sig000000f5; + wire sig000000f6; + wire sig000000f7; + wire sig000000f8; + wire sig000000f9; + wire sig000000fa; + wire sig000000fb; + wire sig000000fc; + wire sig000000fd; + wire sig000000fe; + wire sig000000ff; + wire sig00000100; + wire sig00000101; + wire sig00000102; + wire sig00000103; + wire sig00000104; + wire sig00000105; + wire sig00000106; + wire sig00000107; + wire sig00000108; + wire sig00000109; + wire sig0000010a; + wire sig0000010b; + wire sig0000010c; + wire sig0000010d; + wire sig0000010e; + wire sig0000010f; + wire sig00000110; + wire sig00000111; + wire sig00000112; + wire sig00000113; + wire sig00000114; + wire sig00000115; + wire sig00000116; + wire sig00000117; + wire sig00000118; + wire sig00000119; + wire sig0000011a; + wire sig0000011b; + wire sig0000011c; + wire sig0000011d; + wire sig0000011e; + wire sig0000011f; + wire sig00000120; + wire sig00000121; + wire sig00000122; + wire sig00000123; + wire sig00000124; + wire sig00000125; + wire sig00000126; + wire sig00000127; + wire sig00000128; + wire sig00000129; + wire sig0000012a; + wire sig0000012b; + wire sig0000012c; + wire sig0000012d; + wire sig0000012e; + wire sig0000012f; + wire sig00000130; + wire sig00000131; + wire sig00000132; + wire sig00000133; + wire sig00000134; + wire sig00000135; + wire sig00000136; + wire sig00000137; + wire sig00000138; + wire sig00000139; + wire sig0000013a; + wire sig0000013b; + wire sig0000013c; + wire sig0000013d; + wire sig0000013e; + wire sig0000013f; + wire sig00000140; + wire sig00000141; + wire sig00000142; + wire sig00000143; + wire sig00000144; + wire sig00000145; + wire sig00000146; + wire sig00000147; + wire sig00000148; + wire sig00000149; + wire sig0000014a; + wire sig0000014b; + wire sig0000014c; + wire sig0000014d; + wire sig0000014e; + wire sig0000014f; + wire sig00000150; + wire sig00000151; + wire sig00000152; + wire sig00000153; + wire sig00000154; + wire sig00000155; + wire sig00000156; + wire sig00000157; + wire sig00000158; + wire sig00000159; + wire sig0000015a; + wire sig0000015b; + wire sig0000015c; + wire sig0000015d; + wire sig0000015e; + wire sig0000015f; + wire sig00000160; + wire sig00000161; + wire sig00000162; + wire sig00000163; + wire sig00000164; + wire \NLW_blk00000003_P<35>_UNCONNECTED ; + wire \NLW_blk00000003_P<34>_UNCONNECTED ; + wire \NLW_blk00000003_P<33>_UNCONNECTED ; + wire \NLW_blk00000003_P<32>_UNCONNECTED ; + wire \NLW_blk00000003_P<31>_UNCONNECTED ; + wire \NLW_blk00000003_P<30>_UNCONNECTED ; + wire \NLW_blk00000003_P<29>_UNCONNECTED ; + wire \NLW_blk00000003_P<28>_UNCONNECTED ; + wire \NLW_blk00000003_P<27>_UNCONNECTED ; + wire \NLW_blk00000003_P<26>_UNCONNECTED ; + wire \NLW_blk00000003_P<25>_UNCONNECTED ; + wire \NLW_blk00000003_P<24>_UNCONNECTED ; + wire \NLW_blk00000003_P<23>_UNCONNECTED ; + wire \NLW_blk00000003_P<22>_UNCONNECTED ; + wire \NLW_blk00000003_P<21>_UNCONNECTED ; + wire \NLW_blk00000003_P<20>_UNCONNECTED ; + wire \NLW_blk00000003_P<19>_UNCONNECTED ; + wire \NLW_blk00000003_P<18>_UNCONNECTED ; + wire \NLW_blk00000003_P<17>_UNCONNECTED ; + wire \NLW_blk00000003_P<16>_UNCONNECTED ; + wire \NLW_blk00000003_P<15>_UNCONNECTED ; + wire \NLW_blk00000003_P<14>_UNCONNECTED ; + wire \NLW_blk00000004_P<35>_UNCONNECTED ; + wire \NLW_blk00000004_P<34>_UNCONNECTED ; + wire \NLW_blk00000004_P<33>_UNCONNECTED ; + wire \NLW_blk00000004_P<32>_UNCONNECTED ; + wire \NLW_blk00000004_P<31>_UNCONNECTED ; + wire \NLW_blk00000004_P<30>_UNCONNECTED ; + wire \NLW_blk00000004_P<29>_UNCONNECTED ; + wire \NLW_blk00000004_P<28>_UNCONNECTED ; + wire \NLW_blk00000004_P<27>_UNCONNECTED ; + wire \NLW_blk00000004_P<26>_UNCONNECTED ; + wire \NLW_blk00000004_P<25>_UNCONNECTED ; + wire \NLW_blk00000004_P<24>_UNCONNECTED ; + wire \NLW_blk00000005_P<35>_UNCONNECTED ; + wire \NLW_blk00000005_P<34>_UNCONNECTED ; + wire \NLW_blk00000005_P<33>_UNCONNECTED ; + wire \NLW_blk00000005_P<32>_UNCONNECTED ; + wire \NLW_blk00000005_P<31>_UNCONNECTED ; + wire \NLW_blk00000005_P<30>_UNCONNECTED ; + wire \NLW_blk00000005_P<29>_UNCONNECTED ; + wire \NLW_blk00000005_P<28>_UNCONNECTED ; + wire \NLW_blk00000005_P<27>_UNCONNECTED ; + wire \NLW_blk00000005_P<26>_UNCONNECTED ; + wire \NLW_blk00000005_P<25>_UNCONNECTED ; + wire \NLW_blk00000005_P<24>_UNCONNECTED ; + wire \NLW_blk00000006_P<35>_UNCONNECTED ; + GND blk00000001 ( + .G(sig00000001) + ); + VCC blk00000002 ( + .P(sig00000002) + ); + MULT18X18S blk00000003 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), + .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , +\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED , +\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , +\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , +\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , +\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, +sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1}) + ); + MULT18X18S blk00000004 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , +\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , +\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , +\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, +sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, +sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9}) + ); + MULT18X18S blk00000005 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , +\NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , +\NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , +\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, +sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, +sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1}) + ); + MULT18X18S blk00000006 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, +sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, +sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, +sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) + ); + XORCY blk00000007 ( + .CI(sig00000065), + .LI(sig00000086), + .O(p[47]) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000008 ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000086) + ); + MUXCY blk00000009 ( + .CI(sig00000064), + .DI(sig0000014e), + .S(sig00000085), + .O(sig00000065) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000a ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000085) + ); + MUXCY blk0000000b ( + .CI(sig00000062), + .DI(sig0000014e), + .S(sig00000084), + .O(sig00000064) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000c ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000084) + ); + XORCY blk0000000d ( + .CI(sig00000061), + .LI(sig00000082), + .O(p[46]) + ); + MUXCY blk0000000e ( + .CI(sig00000061), + .DI(sig0000014e), + .S(sig00000082), + .O(sig00000062) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000f ( + .I0(sig0000014e), + .I1(sig0000015a), + .O(sig00000082) + ); + XORCY blk00000010 ( + .CI(sig00000060), + .LI(sig00000081), + .O(p[45]) + ); + MUXCY blk00000011 ( + .CI(sig00000060), + .DI(sig0000014e), + .S(sig00000081), + .O(sig00000061) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000012 ( + .I0(sig0000014e), + .I1(sig00000159), + .O(sig00000081) + ); + XORCY blk00000013 ( + .CI(sig0000005f), + .LI(sig00000080), + .O(p[44]) + ); + MUXCY blk00000014 ( + .CI(sig0000005f), + .DI(sig0000014e), + .S(sig00000080), + .O(sig00000060) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000015 ( + .I0(sig0000014e), + .I1(sig00000158), + .O(sig00000080) + ); + XORCY blk00000016 ( + .CI(sig0000005e), + .LI(sig0000007f), + .O(p[43]) + ); + MUXCY blk00000017 ( + .CI(sig0000005e), + .DI(sig0000014e), + .S(sig0000007f), + .O(sig0000005f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000018 ( + .I0(sig0000014e), + .I1(sig00000164), + .O(sig0000007f) + ); + XORCY blk00000019 ( + .CI(sig0000005d), + .LI(sig0000007e), + .O(p[42]) + ); + MUXCY blk0000001a ( + .CI(sig0000005d), + .DI(sig0000014e), + .S(sig0000007e), + .O(sig0000005e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001b ( + .I0(sig0000014e), + .I1(sig00000163), + .O(sig0000007e) + ); + XORCY blk0000001c ( + .CI(sig0000005c), + .LI(sig0000007d), + .O(p[41]) + ); + MUXCY blk0000001d ( + .CI(sig0000005c), + .DI(sig0000014e), + .S(sig0000007d), + .O(sig0000005d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001e ( + .I0(sig0000014e), + .I1(sig00000162), + .O(sig0000007d) + ); + XORCY blk0000001f ( + .CI(sig0000005b), + .LI(sig0000007c), + .O(p[40]) + ); + MUXCY blk00000020 ( + .CI(sig0000005b), + .DI(sig0000014e), + .S(sig0000007c), + .O(sig0000005c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000021 ( + .I0(sig0000014e), + .I1(sig00000161), + .O(sig0000007c) + ); + XORCY blk00000022 ( + .CI(sig0000005a), + .LI(sig0000007b), + .O(p[39]) + ); + MUXCY blk00000023 ( + .CI(sig0000005a), + .DI(sig0000014d), + .S(sig0000007b), + .O(sig0000005b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000024 ( + .I0(sig0000014d), + .I1(sig00000160), + .O(sig0000007b) + ); + XORCY blk00000025 ( + .CI(sig00000059), + .LI(sig0000007a), + .O(p[38]) + ); + MUXCY blk00000026 ( + .CI(sig00000059), + .DI(sig0000014c), + .S(sig0000007a), + .O(sig0000005a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000027 ( + .I0(sig0000014c), + .I1(sig0000015f), + .O(sig0000007a) + ); + XORCY blk00000028 ( + .CI(sig00000057), + .LI(sig00000079), + .O(p[37]) + ); + MUXCY blk00000029 ( + .CI(sig00000057), + .DI(sig0000014b), + .S(sig00000079), + .O(sig00000059) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002a ( + .I0(sig0000014b), + .I1(sig0000015e), + .O(sig00000079) + ); + XORCY blk0000002b ( + .CI(sig00000056), + .LI(sig00000077), + .O(p[36]) + ); + MUXCY blk0000002c ( + .CI(sig00000056), + .DI(sig00000149), + .S(sig00000077), + .O(sig00000057) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002d ( + .I0(sig00000149), + .I1(sig0000015d), + .O(sig00000077) + ); + XORCY blk0000002e ( + .CI(sig00000055), + .LI(sig00000076), + .O(p[35]) + ); + MUXCY blk0000002f ( + .CI(sig00000055), + .DI(sig00000148), + .S(sig00000076), + .O(sig00000056) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000030 ( + .I0(sig00000148), + .I1(sig0000015c), + .O(sig00000076) + ); + XORCY blk00000031 ( + .CI(sig00000054), + .LI(sig00000075), + .O(p[34]) + ); + MUXCY blk00000032 ( + .CI(sig00000054), + .DI(sig00000147), + .S(sig00000075), + .O(sig00000055) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000033 ( + .I0(sig00000147), + .I1(sig00000157), + .O(sig00000075) + ); + XORCY blk00000034 ( + .CI(sig00000053), + .LI(sig00000074), + .O(p[33]) + ); + MUXCY blk00000035 ( + .CI(sig00000053), + .DI(sig00000146), + .S(sig00000074), + .O(sig00000054) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000036 ( + .I0(sig00000146), + .I1(sig00000121), + .O(sig00000074) + ); + XORCY blk00000037 ( + .CI(sig00000052), + .LI(sig00000073), + .O(p[32]) + ); + MUXCY blk00000038 ( + .CI(sig00000052), + .DI(sig00000145), + .S(sig00000073), + .O(sig00000053) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000039 ( + .I0(sig00000145), + .I1(sig00000120), + .O(sig00000073) + ); + XORCY blk0000003a ( + .CI(sig00000051), + .LI(sig00000072), + .O(p[31]) + ); + MUXCY blk0000003b ( + .CI(sig00000051), + .DI(sig00000144), + .S(sig00000072), + .O(sig00000052) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000003c ( + .I0(sig00000144), + .I1(sig0000011f), + .O(sig00000072) + ); + XORCY blk0000003d ( + .CI(sig00000050), + .LI(sig00000071), + .O(p[30]) + ); + MUXCY blk0000003e ( + .CI(sig00000050), + .DI(sig00000143), + .S(sig00000071), + .O(sig00000051) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000003f ( + .I0(sig00000143), + .I1(sig0000011e), + .O(sig00000071) + ); + XORCY blk00000040 ( + .CI(sig0000004f), + .LI(sig00000070), + .O(p[29]) + ); + MUXCY blk00000041 ( + .CI(sig0000004f), + .DI(sig00000142), + .S(sig00000070), + .O(sig00000050) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000042 ( + .I0(sig00000142), + .I1(sig0000011d), + .O(sig00000070) + ); + XORCY blk00000043 ( + .CI(sig0000004e), + .LI(sig0000006f), + .O(p[28]) + ); + MUXCY blk00000044 ( + .CI(sig0000004e), + .DI(sig00000141), + .S(sig0000006f), + .O(sig0000004f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000045 ( + .I0(sig00000141), + .I1(sig0000011c), + .O(sig0000006f) + ); + XORCY blk00000046 ( + .CI(sig0000006c), + .LI(sig0000006e), + .O(p[27]) + ); + MUXCY blk00000047 ( + .CI(sig0000006c), + .DI(sig00000140), + .S(sig0000006e), + .O(sig0000004e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000048 ( + .I0(sig00000140), + .I1(sig0000011b), + .O(sig0000006e) + ); + XORCY blk00000049 ( + .CI(sig0000006b), + .LI(sig0000008d), + .O(p[26]) + ); + MUXCY blk0000004a ( + .CI(sig0000006b), + .DI(sig00000156), + .S(sig0000008d), + .O(sig0000006c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004b ( + .I0(sig00000156), + .I1(sig00000130), + .O(sig0000008d) + ); + XORCY blk0000004c ( + .CI(sig0000006a), + .LI(sig0000008c), + .O(p[25]) + ); + MUXCY blk0000004d ( + .CI(sig0000006a), + .DI(sig00000155), + .S(sig0000008c), + .O(sig0000006b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004e ( + .I0(sig00000155), + .I1(sig0000012f), + .O(sig0000008c) + ); + XORCY blk0000004f ( + .CI(sig00000069), + .LI(sig0000008b), + .O(p[24]) + ); + MUXCY blk00000050 ( + .CI(sig00000069), + .DI(sig00000154), + .S(sig0000008b), + .O(sig0000006a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000051 ( + .I0(sig00000154), + .I1(sig0000012e), + .O(sig0000008b) + ); + XORCY blk00000052 ( + .CI(sig00000068), + .LI(sig0000008a), + .O(p[23]) + ); + MUXCY blk00000053 ( + .CI(sig00000068), + .DI(sig00000153), + .S(sig0000008a), + .O(sig00000069) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000054 ( + .I0(sig00000153), + .I1(sig0000012d), + .O(sig0000008a) + ); + XORCY blk00000055 ( + .CI(sig00000067), + .LI(sig00000089), + .O(p[22]) + ); + MUXCY blk00000056 ( + .CI(sig00000067), + .DI(sig00000152), + .S(sig00000089), + .O(sig00000068) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000057 ( + .I0(sig00000152), + .I1(sig0000012c), + .O(sig00000089) + ); + XORCY blk00000058 ( + .CI(sig00000066), + .LI(sig00000088), + .O(p[21]) + ); + MUXCY blk00000059 ( + .CI(sig00000066), + .DI(sig00000151), + .S(sig00000088), + .O(sig00000067) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005a ( + .I0(sig00000151), + .I1(sig0000012b), + .O(sig00000088) + ); + XORCY blk0000005b ( + .CI(sig00000063), + .LI(sig00000087), + .O(p[20]) + ); + MUXCY blk0000005c ( + .CI(sig00000063), + .DI(sig00000150), + .S(sig00000087), + .O(sig00000066) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005d ( + .I0(sig00000150), + .I1(sig0000012a), + .O(sig00000087) + ); + XORCY blk0000005e ( + .CI(sig00000058), + .LI(sig00000083), + .O(p[19]) + ); + MUXCY blk0000005f ( + .CI(sig00000058), + .DI(sig0000014f), + .S(sig00000083), + .O(sig00000063) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000060 ( + .I0(sig0000014f), + .I1(sig00000125), + .O(sig00000083) + ); + XORCY blk00000061 ( + .CI(sig0000004d), + .LI(sig00000078), + .O(p[18]) + ); + MUXCY blk00000062 ( + .CI(sig0000004d), + .DI(sig0000014a), + .S(sig00000078), + .O(sig00000058) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000063 ( + .I0(sig0000014a), + .I1(sig0000011a), + .O(sig00000078) + ); + XORCY blk00000064 ( + .CI(sig00000001), + .LI(sig0000006d), + .O(p[17]) + ); + MUXCY blk00000065 ( + .CI(sig00000001), + .DI(sig0000013f), + .S(sig0000006d), + .O(sig0000004d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000066 ( + .I0(sig0000013f), + .I1(sig00000119), + .O(sig0000006d) + ); + XORCY blk00000067 ( + .CI(sig00000011), + .LI(sig00000029), + .O(sig0000014e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000068 ( + .I0(sig00000100), + .I1(sig00000111), + .O(sig00000029) + ); + XORCY blk00000069 ( + .CI(sig00000010), + .LI(sig00000028), + .O(sig0000014d) + ); + MUXCY blk0000006a ( + .CI(sig00000010), + .DI(sig00000100), + .S(sig00000028), + .O(sig00000011) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006b ( + .I0(sig00000100), + .I1(sig00000110), + .O(sig00000028) + ); + XORCY blk0000006c ( + .CI(sig0000000f), + .LI(sig00000027), + .O(sig0000014c) + ); + MUXCY blk0000006d ( + .CI(sig0000000f), + .DI(sig00000100), + .S(sig00000027), + .O(sig00000010) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006e ( + .I0(sig00000100), + .I1(sig0000010f), + .O(sig00000027) + ); + XORCY blk0000006f ( + .CI(sig0000000d), + .LI(sig00000026), + .O(sig0000014b) + ); + MUXCY blk00000070 ( + .CI(sig0000000d), + .DI(sig00000100), + .S(sig00000026), + .O(sig0000000f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000071 ( + .I0(sig00000100), + .I1(sig0000010e), + .O(sig00000026) + ); + XORCY blk00000072 ( + .CI(sig0000000c), + .LI(sig00000024), + .O(sig00000149) + ); + MUXCY blk00000073 ( + .CI(sig0000000c), + .DI(sig00000100), + .S(sig00000024), + .O(sig0000000d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000074 ( + .I0(sig00000100), + .I1(sig0000010c), + .O(sig00000024) + ); + XORCY blk00000075 ( + .CI(sig0000000b), + .LI(sig00000023), + .O(sig00000148) + ); + MUXCY blk00000076 ( + .CI(sig0000000b), + .DI(sig00000100), + .S(sig00000023), + .O(sig0000000c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000077 ( + .I0(sig00000100), + .I1(sig0000010b), + .O(sig00000023) + ); + XORCY blk00000078 ( + .CI(sig0000000a), + .LI(sig00000022), + .O(sig00000147) + ); + MUXCY blk00000079 ( + .CI(sig0000000a), + .DI(sig00000100), + .S(sig00000022), + .O(sig0000000b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007a ( + .I0(sig00000100), + .I1(sig0000010a), + .O(sig00000022) + ); + XORCY blk0000007b ( + .CI(sig00000009), + .LI(sig00000021), + .O(sig00000146) + ); + MUXCY blk0000007c ( + .CI(sig00000009), + .DI(sig000000ff), + .S(sig00000021), + .O(sig0000000a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007d ( + .I0(sig000000ff), + .I1(sig00000109), + .O(sig00000021) + ); + XORCY blk0000007e ( + .CI(sig00000008), + .LI(sig00000020), + .O(sig00000145) + ); + MUXCY blk0000007f ( + .CI(sig00000008), + .DI(sig000000fe), + .S(sig00000020), + .O(sig00000009) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000080 ( + .I0(sig000000fe), + .I1(sig00000108), + .O(sig00000020) + ); + XORCY blk00000081 ( + .CI(sig00000007), + .LI(sig0000001f), + .O(sig00000144) + ); + MUXCY blk00000082 ( + .CI(sig00000007), + .DI(sig000000fd), + .S(sig0000001f), + .O(sig00000008) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000083 ( + .I0(sig000000fd), + .I1(sig00000107), + .O(sig0000001f) + ); + XORCY blk00000084 ( + .CI(sig00000006), + .LI(sig0000001e), + .O(sig00000143) + ); + MUXCY blk00000085 ( + .CI(sig00000006), + .DI(sig000000fc), + .S(sig0000001e), + .O(sig00000007) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000086 ( + .I0(sig000000fc), + .I1(sig00000106), + .O(sig0000001e) + ); + XORCY blk00000087 ( + .CI(sig00000005), + .LI(sig0000001d), + .O(sig00000142) + ); + MUXCY blk00000088 ( + .CI(sig00000005), + .DI(sig000000fb), + .S(sig0000001d), + .O(sig00000006) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000089 ( + .I0(sig000000fb), + .I1(sig00000105), + .O(sig0000001d) + ); + XORCY blk0000008a ( + .CI(sig00000004), + .LI(sig0000001c), + .O(sig00000141) + ); + MUXCY blk0000008b ( + .CI(sig00000004), + .DI(sig000000fa), + .S(sig0000001c), + .O(sig00000005) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008c ( + .I0(sig000000fa), + .I1(sig00000104), + .O(sig0000001c) + ); + XORCY blk0000008d ( + .CI(sig00000019), + .LI(sig0000001b), + .O(sig00000140) + ); + MUXCY blk0000008e ( + .CI(sig00000019), + .DI(sig000000f9), + .S(sig0000001b), + .O(sig00000004) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008f ( + .I0(sig000000f9), + .I1(sig00000103), + .O(sig0000001b) + ); + XORCY blk00000090 ( + .CI(sig00000018), + .LI(sig00000031), + .O(sig00000156) + ); + MUXCY blk00000091 ( + .CI(sig00000018), + .DI(sig000000f8), + .S(sig00000031), + .O(sig00000019) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000092 ( + .I0(sig000000f8), + .I1(sig00000118), + .O(sig00000031) + ); + XORCY blk00000093 ( + .CI(sig00000017), + .LI(sig00000030), + .O(sig00000155) + ); + MUXCY blk00000094 ( + .CI(sig00000017), + .DI(sig000000f7), + .S(sig00000030), + .O(sig00000018) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000095 ( + .I0(sig000000f7), + .I1(sig00000117), + .O(sig00000030) + ); + XORCY blk00000096 ( + .CI(sig00000016), + .LI(sig0000002f), + .O(sig00000154) + ); + MUXCY blk00000097 ( + .CI(sig00000016), + .DI(sig000000f6), + .S(sig0000002f), + .O(sig00000017) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000098 ( + .I0(sig000000f6), + .I1(sig00000116), + .O(sig0000002f) + ); + XORCY blk00000099 ( + .CI(sig00000015), + .LI(sig0000002e), + .O(sig00000153) + ); + MUXCY blk0000009a ( + .CI(sig00000015), + .DI(sig000000f5), + .S(sig0000002e), + .O(sig00000016) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009b ( + .I0(sig000000f5), + .I1(sig00000115), + .O(sig0000002e) + ); + XORCY blk0000009c ( + .CI(sig00000014), + .LI(sig0000002d), + .O(sig00000152) + ); + MUXCY blk0000009d ( + .CI(sig00000014), + .DI(sig000000f4), + .S(sig0000002d), + .O(sig00000015) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009e ( + .I0(sig000000f4), + .I1(sig00000114), + .O(sig0000002d) + ); + XORCY blk0000009f ( + .CI(sig00000013), + .LI(sig0000002c), + .O(sig00000151) + ); + MUXCY blk000000a0 ( + .CI(sig00000013), + .DI(sig000000f3), + .S(sig0000002c), + .O(sig00000014) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a1 ( + .I0(sig000000f3), + .I1(sig00000113), + .O(sig0000002c) + ); + XORCY blk000000a2 ( + .CI(sig00000012), + .LI(sig0000002b), + .O(sig00000150) + ); + MUXCY blk000000a3 ( + .CI(sig00000012), + .DI(sig000000f2), + .S(sig0000002b), + .O(sig00000013) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a4 ( + .I0(sig000000f2), + .I1(sig00000112), + .O(sig0000002b) + ); + XORCY blk000000a5 ( + .CI(sig0000000e), + .LI(sig0000002a), + .O(sig0000014f) + ); + MUXCY blk000000a6 ( + .CI(sig0000000e), + .DI(sig000000f1), + .S(sig0000002a), + .O(sig00000012) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a7 ( + .I0(sig000000f1), + .I1(sig0000010d), + .O(sig0000002a) + ); + XORCY blk000000a8 ( + .CI(sig00000003), + .LI(sig00000025), + .O(sig0000014a) + ); + MUXCY blk000000a9 ( + .CI(sig00000003), + .DI(sig000000f0), + .S(sig00000025), + .O(sig0000000e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000aa ( + .I0(sig000000f0), + .I1(sig00000102), + .O(sig00000025) + ); + XORCY blk000000ab ( + .CI(sig00000001), + .LI(sig0000001a), + .O(sig0000013f) + ); + MUXCY blk000000ac ( + .CI(sig00000001), + .DI(sig000000ef), + .S(sig0000001a), + .O(sig00000003) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000ad ( + .I0(sig000000ef), + .I1(sig00000101), + .O(sig0000001a) + ); + XORCY blk000000ae ( + .CI(sig00000035), + .LI(sig00000043), + .O(sig0000015b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000af ( + .I0(sig00000129), + .I1(sig00000136), + .O(sig00000043) + ); + XORCY blk000000b0 ( + .CI(sig00000034), + .LI(sig00000042), + .O(sig0000015a) + ); + MUXCY blk000000b1 ( + .CI(sig00000034), + .DI(sig00000129), + .S(sig00000042), + .O(sig00000035) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b2 ( + .I0(sig00000129), + .I1(sig00000135), + .O(sig00000042) + ); + XORCY blk000000b3 ( + .CI(sig00000033), + .LI(sig00000041), + .O(sig00000159) + ); + MUXCY blk000000b4 ( + .CI(sig00000033), + .DI(sig00000129), + .S(sig00000041), + .O(sig00000034) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b5 ( + .I0(sig00000129), + .I1(sig00000134), + .O(sig00000041) + ); + XORCY blk000000b6 ( + .CI(sig0000003e), + .LI(sig00000040), + .O(sig00000158) + ); + MUXCY blk000000b7 ( + .CI(sig0000003e), + .DI(sig00000129), + .S(sig00000040), + .O(sig00000033) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b8 ( + .I0(sig00000129), + .I1(sig00000133), + .O(sig00000040) + ); + XORCY blk000000b9 ( + .CI(sig0000003d), + .LI(sig0000004c), + .O(sig00000164) + ); + MUXCY blk000000ba ( + .CI(sig0000003d), + .DI(sig00000129), + .S(sig0000004c), + .O(sig0000003e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000bb ( + .I0(sig00000129), + .I1(sig0000013e), + .O(sig0000004c) + ); + XORCY blk000000bc ( + .CI(sig0000003c), + .LI(sig0000004b), + .O(sig00000163) + ); + MUXCY blk000000bd ( + .CI(sig0000003c), + .DI(sig00000129), + .S(sig0000004b), + .O(sig0000003d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000be ( + .I0(sig00000129), + .I1(sig0000013d), + .O(sig0000004b) + ); + XORCY blk000000bf ( + .CI(sig0000003b), + .LI(sig0000004a), + .O(sig00000162) + ); + MUXCY blk000000c0 ( + .CI(sig0000003b), + .DI(sig00000129), + .S(sig0000004a), + .O(sig0000003c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c1 ( + .I0(sig00000129), + .I1(sig0000013c), + .O(sig0000004a) + ); + XORCY blk000000c2 ( + .CI(sig0000003a), + .LI(sig00000049), + .O(sig00000161) + ); + MUXCY blk000000c3 ( + .CI(sig0000003a), + .DI(sig00000129), + .S(sig00000049), + .O(sig0000003b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c4 ( + .I0(sig00000129), + .I1(sig0000013b), + .O(sig00000049) + ); + XORCY blk000000c5 ( + .CI(sig00000039), + .LI(sig00000048), + .O(sig00000160) + ); + MUXCY blk000000c6 ( + .CI(sig00000039), + .DI(sig00000128), + .S(sig00000048), + .O(sig0000003a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c7 ( + .I0(sig00000128), + .I1(sig0000013a), + .O(sig00000048) + ); + XORCY blk000000c8 ( + .CI(sig00000038), + .LI(sig00000047), + .O(sig0000015f) + ); + MUXCY blk000000c9 ( + .CI(sig00000038), + .DI(sig00000127), + .S(sig00000047), + .O(sig00000039) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000ca ( + .I0(sig00000127), + .I1(sig00000139), + .O(sig00000047) + ); + XORCY blk000000cb ( + .CI(sig00000037), + .LI(sig00000046), + .O(sig0000015e) + ); + MUXCY blk000000cc ( + .CI(sig00000037), + .DI(sig00000126), + .S(sig00000046), + .O(sig00000038) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000cd ( + .I0(sig00000126), + .I1(sig00000138), + .O(sig00000046) + ); + XORCY blk000000ce ( + .CI(sig00000036), + .LI(sig00000045), + .O(sig0000015d) + ); + MUXCY blk000000cf ( + .CI(sig00000036), + .DI(sig00000124), + .S(sig00000045), + .O(sig00000037) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d0 ( + .I0(sig00000124), + .I1(sig00000137), + .O(sig00000045) + ); + XORCY blk000000d1 ( + .CI(sig00000032), + .LI(sig00000044), + .O(sig0000015c) + ); + MUXCY blk000000d2 ( + .CI(sig00000032), + .DI(sig00000123), + .S(sig00000044), + .O(sig00000036) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d3 ( + .I0(sig00000123), + .I1(sig00000132), + .O(sig00000044) + ); + XORCY blk000000d4 ( + .CI(sig00000001), + .LI(sig0000003f), + .O(sig00000157) + ); + MUXCY blk000000d5 ( + .CI(sig00000001), + .DI(sig00000122), + .S(sig0000003f), + .O(sig00000032) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d6 ( + .I0(sig00000122), + .I1(sig00000131), + .O(sig0000003f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d7 ( + .C(clk), + .D(sig000000d8), + .Q(sig00000129) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d8 ( + .C(clk), + .D(sig000000d7), + .Q(sig00000128) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d9 ( + .C(clk), + .D(sig000000d6), + .Q(sig00000127) + ); + FD #( + .INIT ( 1'b0 )) + blk000000da ( + .C(clk), + .D(sig000000d5), + .Q(sig00000126) + ); + FD #( + .INIT ( 1'b0 )) + blk000000db ( + .C(clk), + .D(sig000000d3), + .Q(sig00000124) + ); + FD #( + .INIT ( 1'b0 )) + blk000000dc ( + .C(clk), + .D(sig000000d2), + .Q(sig00000123) + ); + FD #( + .INIT ( 1'b0 )) + blk000000dd ( + .C(clk), + .D(sig000000d1), + .Q(sig00000122) + ); + FD #( + .INIT ( 1'b0 )) + blk000000de ( + .C(clk), + .D(sig000000d0), + .Q(sig00000121) + ); + FD #( + .INIT ( 1'b0 )) + blk000000df ( + .C(clk), + .D(sig000000cf), + .Q(sig00000120) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e0 ( + .C(clk), + .D(sig000000ce), + .Q(sig0000011f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e1 ( + .C(clk), + .D(sig000000cd), + .Q(sig0000011e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e2 ( + .C(clk), + .D(sig000000cc), + .Q(sig0000011d) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e3 ( + .C(clk), + .D(sig000000cb), + .Q(sig0000011c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e4 ( + .C(clk), + .D(sig000000ca), + .Q(sig0000011b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e5 ( + .C(clk), + .D(sig000000e0), + .Q(sig00000130) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e6 ( + .C(clk), + .D(sig000000df), + .Q(sig0000012f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e7 ( + .C(clk), + .D(sig000000de), + .Q(sig0000012e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e8 ( + .C(clk), + .D(sig000000dd), + .Q(sig0000012d) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e9 ( + .C(clk), + .D(sig000000dc), + .Q(sig0000012c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ea ( + .C(clk), + .D(sig000000db), + .Q(sig0000012b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000eb ( + .C(clk), + .D(sig000000da), + .Q(sig0000012a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ec ( + .C(clk), + .D(sig000000d9), + .Q(sig00000125) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ed ( + .C(clk), + .D(sig000000d4), + .Q(sig0000011a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ee ( + .C(clk), + .D(sig000000c9), + .Q(sig00000119) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ef ( + .C(clk), + .D(sig000000c0), + .Q(sig00000111) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f0 ( + .C(clk), + .D(sig000000bf), + .Q(sig00000110) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f1 ( + .C(clk), + .D(sig000000be), + .Q(sig0000010f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f2 ( + .C(clk), + .D(sig000000bd), + .Q(sig0000010e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f3 ( + .C(clk), + .D(sig000000bb), + .Q(sig0000010c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f4 ( + .C(clk), + .D(sig000000ba), + .Q(sig0000010b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f5 ( + .C(clk), + .D(sig000000b9), + .Q(sig0000010a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f6 ( + .C(clk), + .D(sig000000b8), + .Q(sig00000109) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f7 ( + .C(clk), + .D(sig000000b7), + .Q(sig00000108) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f8 ( + .C(clk), + .D(sig000000b6), + .Q(sig00000107) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f9 ( + .C(clk), + .D(sig000000b5), + .Q(sig00000106) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fa ( + .C(clk), + .D(sig000000b4), + .Q(sig00000105) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fb ( + .C(clk), + .D(sig000000b3), + .Q(sig00000104) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fc ( + .C(clk), + .D(sig000000b2), + .Q(sig00000103) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fd ( + .C(clk), + .D(sig000000c8), + .Q(sig00000118) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fe ( + .C(clk), + .D(sig000000c7), + .Q(sig00000117) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ff ( + .C(clk), + .D(sig000000c6), + .Q(sig00000116) + ); + FD #( + .INIT ( 1'b0 )) + blk00000100 ( + .C(clk), + .D(sig000000c5), + .Q(sig00000115) + ); + FD #( + .INIT ( 1'b0 )) + blk00000101 ( + .C(clk), + .D(sig000000c4), + .Q(sig00000114) + ); + FD #( + .INIT ( 1'b0 )) + blk00000102 ( + .C(clk), + .D(sig000000c3), + .Q(sig00000113) + ); + FD #( + .INIT ( 1'b0 )) + blk00000103 ( + .C(clk), + .D(sig000000c2), + .Q(sig00000112) + ); + FD #( + .INIT ( 1'b0 )) + blk00000104 ( + .C(clk), + .D(sig000000c1), + .Q(sig0000010d) + ); + FD #( + .INIT ( 1'b0 )) + blk00000105 ( + .C(clk), + .D(sig000000bc), + .Q(sig00000102) + ); + FD #( + .INIT ( 1'b0 )) + blk00000106 ( + .C(clk), + .D(sig000000b1), + .Q(sig00000101) + ); + FD #( + .INIT ( 1'b0 )) + blk00000107 ( + .C(clk), + .D(sig000000e5), + .Q(sig00000136) + ); + FD #( + .INIT ( 1'b0 )) + blk00000108 ( + .C(clk), + .D(sig000000e4), + .Q(sig00000135) + ); + FD #( + .INIT ( 1'b0 )) + blk00000109 ( + .C(clk), + .D(sig000000e3), + .Q(sig00000134) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010a ( + .C(clk), + .D(sig000000e2), + .Q(sig00000133) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010b ( + .C(clk), + .D(sig000000ee), + .Q(sig0000013e) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010c ( + .C(clk), + .D(sig000000ed), + .Q(sig0000013d) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010d ( + .C(clk), + .D(sig000000ec), + .Q(sig0000013c) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010e ( + .C(clk), + .D(sig000000eb), + .Q(sig0000013b) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010f ( + .C(clk), + .D(sig000000ea), + .Q(sig0000013a) + ); + FD #( + .INIT ( 1'b0 )) + blk00000110 ( + .C(clk), + .D(sig000000e9), + .Q(sig00000139) + ); + FD #( + .INIT ( 1'b0 )) + blk00000111 ( + .C(clk), + .D(sig000000e8), + .Q(sig00000138) + ); + FD #( + .INIT ( 1'b0 )) + blk00000112 ( + .C(clk), + .D(sig000000e7), + .Q(sig00000137) + ); + FD #( + .INIT ( 1'b0 )) + blk00000113 ( + .C(clk), + .D(sig000000e6), + .Q(sig00000132) + ); + FD #( + .INIT ( 1'b0 )) + blk00000114 ( + .C(clk), + .D(sig000000e1), + .Q(sig00000131) + ); + FD #( + .INIT ( 1'b0 )) + blk00000115 ( + .C(clk), + .D(sig000000a9), + .Q(sig00000100) + ); + FD #( + .INIT ( 1'b0 )) + blk00000116 ( + .C(clk), + .D(sig000000a8), + .Q(sig000000ff) + ); + FD #( + .INIT ( 1'b0 )) + blk00000117 ( + .C(clk), + .D(sig000000a7), + .Q(sig000000fe) + ); + FD #( + .INIT ( 1'b0 )) + blk00000118 ( + .C(clk), + .D(sig000000a6), + .Q(sig000000fd) + ); + FD #( + .INIT ( 1'b0 )) + blk00000119 ( + .C(clk), + .D(sig000000a5), + .Q(sig000000fc) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011a ( + .C(clk), + .D(sig000000a3), + .Q(sig000000fb) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011b ( + .C(clk), + .D(sig000000a2), + .Q(sig000000fa) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011c ( + .C(clk), + .D(sig000000a1), + .Q(sig000000f9) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011d ( + .C(clk), + .D(sig000000a0), + .Q(sig000000f8) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011e ( + .C(clk), + .D(sig0000009f), + .Q(sig000000f7) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011f ( + .C(clk), + .D(sig0000009e), + .Q(sig000000f6) + ); + FD #( + .INIT ( 1'b0 )) + blk00000120 ( + .C(clk), + .D(sig0000009d), + .Q(sig000000f5) + ); + FD #( + .INIT ( 1'b0 )) + blk00000121 ( + .C(clk), + .D(sig0000009c), + .Q(sig000000f4) + ); + FD #( + .INIT ( 1'b0 )) + blk00000122 ( + .C(clk), + .D(sig0000009b), + .Q(sig000000f3) + ); + FD #( + .INIT ( 1'b0 )) + blk00000123 ( + .C(clk), + .D(sig0000009a), + .Q(sig000000f2) + ); + FD #( + .INIT ( 1'b0 )) + blk00000124 ( + .C(clk), + .D(sig00000098), + .Q(sig000000f1) + ); + FD #( + .INIT ( 1'b0 )) + blk00000125 ( + .C(clk), + .D(sig00000097), + .Q(sig000000f0) + ); + FD #( + .INIT ( 1'b0 )) + blk00000126 ( + .C(clk), + .D(sig00000096), + .Q(sig000000ef) + ); + FD #( + .INIT ( 1'b0 )) + blk00000127 ( + .C(clk), + .D(sig00000095), + .Q(p[16]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000128 ( + .C(clk), + .D(sig00000094), + .Q(p[15]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000129 ( + .C(clk), + .D(sig00000093), + .Q(p[14]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012a ( + .C(clk), + .D(sig00000092), + .Q(p[13]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012b ( + .C(clk), + .D(sig00000091), + .Q(p[12]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012c ( + .C(clk), + .D(sig00000090), + .Q(p[11]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012d ( + .C(clk), + .D(sig0000008f), + .Q(p[10]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012e ( + .C(clk), + .D(sig000000b0), + .Q(p[9]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012f ( + .C(clk), + .D(sig000000af), + .Q(p[8]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000130 ( + .C(clk), + .D(sig000000ae), + .Q(p[7]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000131 ( + .C(clk), + .D(sig000000ad), + .Q(p[6]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000132 ( + .C(clk), + .D(sig000000ac), + .Q(p[5]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000133 ( + .C(clk), + .D(sig000000ab), + .Q(p[4]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000134 ( + .C(clk), + .D(sig000000aa), + .Q(p[3]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000135 ( + .C(clk), + .D(sig000000a4), + .Q(p[2]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000136 ( + .C(clk), + .D(sig00000099), + .Q(p[1]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000137 ( + .C(clk), + .D(sig0000008e), + .Q(p[0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco new file mode 100644 index 0000000..89401df --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco @@ -0,0 +1,68 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Fri Oct 21 20:38:07 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:mult_gen:11.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Multiplier xilinx.com:ip:mult_gen:11.2 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=false +CSET component_name=cx4_mul +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=47 +CSET outputwidthlow=0 +CSET pipestages=2 +CSET portatype=Signed +CSET portawidth=24 +CSET portbtype=Signed +CSET portbwidth=24 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:26:54.000Z +# END Extra information +GENERATE +# CRC: efe4d30e diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise new file mode 100644 index 0000000..12daee6 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise @@ -0,0 +1,378 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v new file mode 100644 index 0000000..88379dd --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_pgmrom.v when simulating +// the core, cx4_pgmrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_pgmrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [9 : 0] addra; +input [7 : 0] dina; +input clkb; +input [8 : 0] addrb; +output [15 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(10), + .C_ADDRB_WIDTH(9), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(1024), + .C_READ_DEPTH_B(512), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(16), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(1024), + .C_WRITE_DEPTH_B(512), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(16), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco new file mode 100644 index 0000000..59cb743 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Tue Oct 18 18:45:53 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_pgmrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=16 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=1024 +CSET write_width_a=8 +CSET write_width_b=16 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: 30264765 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise new file mode 100644 index 0000000..72cb4ec --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v new file mode 100644 index 0000000..8e2574d --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file dac_buf.v when simulating +// the core, dac_buf. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module dac_buf( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [10 : 0] addra; +input [7 : 0] dina; +input clkb; +input [8 : 0] addrb; +output [31 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_1 #( + .C_ADDRA_WIDTH(11), + .C_ADDRB_WIDTH(9), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(2048), + .C_READ_DEPTH_B(512), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(32), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(2048), + .C_WRITE_DEPTH_B(512), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(32), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco new file mode 100644 index 0000000..24fdf34 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Mon Oct 10 19:47:34 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dac_buf +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=32 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=32 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:43:52.000Z +# END Extra information +GENERATE +# CRC: 60863d15 diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise new file mode 100644 index 0000000..e094ff8 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise @@ -0,0 +1,79 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v new file mode 100644 index 0000000..4528b98 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file msu_databuf.v when simulating +// the core, msu_databuf. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module msu_databuf( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [13 : 0] addra; +input [7 : 0] dina; +input clkb; +input [13 : 0] addrb; +output [7 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_1 #( + .C_ADDRA_WIDTH(14), + .C_ADDRB_WIDTH(14), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(16384), + .C_READ_DEPTH_B(16384), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(8), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(16384), + .C_WRITE_DEPTH_B(16384), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(8), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco new file mode 100644 index 0000000..61a41b5 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Mon Oct 10 19:48:38 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=msu_databuf +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=16384 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:43:52.000Z +# END Extra information +GENERATE +# CRC: bebc21bb diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise new file mode 100644 index 0000000..4d2c480 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise @@ -0,0 +1,79 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v new file mode 100644 index 0000000..b8fcf11 --- /dev/null +++ b/verilog/sd2snes_cx4/main.v @@ -0,0 +1,564 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: main +// Project Name: +// Target Devices: +// Tool versions: +// Description: Master Control FSM +// +// Dependencies: address +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module main( + /* input clock */ + input CLKIN, + + /* SNES signals */ + input [23:0] SNES_ADDR, + input SNES_READ, + input SNES_WRITE, + input SNES_CS, + inout [7:0] SNES_DATA, + input SNES_CPU_CLK, + input SNES_REFRESH, + output SNES_IRQ, + output SNES_DATABUS_OE, + output SNES_DATABUS_DIR, + input SNES_SYSCLK, + + /* SRAM signals */ + /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */ + inout [15:0] ROM_DATA, + output [22:0] ROM_ADDR, + output ROM_CE, + output ROM_OE, + output ROM_WE, + output ROM_BHE, + output ROM_BLE, + + /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */ + inout [7:0] RAM_DATA, + output [18:0] RAM_ADDR, + output RAM_CE, + output RAM_OE, + output RAM_WE, + + /* MCU signals */ + input SPI_MOSI, + inout SPI_MISO, + input SPI_SS, + inout SPI_SCK, + input MCU_OVR, + output MCU_RDY, + + output DAC_MCLK, + output DAC_LRCK, + output DAC_SDOUT, + + /* SD signals */ + input [3:0] SD_DAT, + inout SD_CMD, + inout SD_CLK, + + /* debug */ + output p113_out +); + +wire [7:0] spi_cmd_data; +wire [7:0] spi_param_data; +wire [7:0] spi_input_data; +wire [31:0] spi_byte_cnt; +wire [2:0] spi_bit_cnt; +wire [23:0] MCU_ADDR; +wire [2:0] MAPPER; +wire [23:0] SAVERAM_MASK; +wire [23:0] ROM_MASK; +wire [7:0] SD_DMA_SRAM_DATA; +wire [1:0] SD_DMA_TGT; +wire [10:0] SD_DMA_PARTIAL_START; +wire [10:0] SD_DMA_PARTIAL_END; + +wire [10:0] dac_addr; +//wire [7:0] dac_volume; +wire [7:0] msu_volumerq_out; +wire [6:0] msu_status_out; +wire [31:0] msu_addressrq_out; +wire [15:0] msu_trackrq_out; +wire [13:0] msu_write_addr; +wire [13:0] msu_ptr_addr; +wire [7:0] MSU_SNES_DATA_IN; +wire [7:0] MSU_SNES_DATA_OUT; +wire [5:0] msu_status_reset_bits; +wire [5:0] msu_status_set_bits; + +wire [7:0] CX4_SNES_DATA_IN; +wire [7:0] CX4_SNES_DATA_OUT; + +wire [23:0] MAPPED_SNES_ADDR; +wire ROM_ADDR0; + +sd_dma snes_sd_dma( + .CLK(CLK2), + .SD_DAT(SD_DAT), + .SD_CLK(SD_CLK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) +); + +wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)); + +dac snes_dac( + .clkin(CLK2), + .sysclk(SNES_SYSCLK), + .mclk(DAC_MCLK), + .lrck(DAC_LRCK), + .sdout(DAC_SDOUT), + .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1), + .pgm_address(dac_addr), + .pgm_data(SD_DMA_SRAM_DATA), + .DAC_STATUS(DAC_STATUS), + .volume(msu_volumerq_out), + .vol_latch(msu_volume_latch_out), + .play(dac_play), + .reset(dac_reset) +); + +msu snes_msu ( + .clkin(CLK2), + .enable(msu_enable), + .pgm_address(msu_write_addr), + .pgm_data(SD_DMA_SRAM_DATA), + .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1), + .reg_addr(SNES_ADDR[2:0]), + .reg_data_in(MSU_SNES_DATA_IN), + .reg_data_out(MSU_SNES_DATA_OUT), + .reg_oe(SNES_READ), + .reg_we(SNES_WRITE), + .status_out(msu_status_out), + .volume_out(msu_volumerq_out), + .volume_latch_out(msu_volume_latch_out), + .addr_out(msu_addressrq_out), + .track_out(msu_trackrq_out), + .status_reset_bits(msu_status_reset_bits), + .status_set_bits(msu_status_set_bits), + .status_reset_we(msu_status_reset_we), + .msu_address_ext(msu_ptr_addr), + .msu_address_ext_write(msu_addr_reset) +); + +spi snes_spi( + .clk(CLK2), + .MOSI(SPI_MOSI), + .MISO(SPI_MISO), + .SSEL(SPI_SS), + .SCK(SPI_SCK), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .endmessage(spi_endmessage), + .startmessage(spi_startmessage), + .input_data(spi_input_data), + .byte_cnt(spi_byte_cnt), + .bit_cnt(spi_bit_cnt) +); + +reg [7:0] MCU_DINr; +wire [7:0] MCU_DOUT; + +mcu_cmd snes_mcu_cmd( + .clk(CLK2), + .snes_sysclk(SNES_SYSCLK), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .mcu_mapper(MAPPER), + .mcu_write(MCU_WRITE), + .mcu_data_in(MCU_DINr), + .mcu_data_out(MCU_DOUT), + .spi_byte_cnt(spi_byte_cnt), + .spi_bit_cnt(spi_bit_cnt), + .spi_data_out(spi_input_data), + .addr_out(MCU_ADDR), + .saveram_mask_out(SAVERAM_MASK), + .rom_mask_out(ROM_MASK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_TGT(SD_DMA_TGT), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .dac_addr_out(dac_addr), + .DAC_STATUS(DAC_STATUS), +// .dac_volume_out(dac_volume), +// .dac_volume_latch_out(dac_vol_latch), + .dac_play_out(dac_play), + .dac_reset_out(dac_reset), + .msu_addr_out(msu_write_addr), + .MSU_STATUS(msu_status_out), + .msu_status_reset_out(msu_status_reset_bits), + .msu_status_set_out(msu_status_set_bits), + .msu_status_reset_we(msu_status_reset_we), + .msu_volumerq(msu_volumerq_out), + .msu_addressrq(msu_addressrq_out), + .msu_trackrq(msu_trackrq_out), + .msu_ptr_out(msu_ptr_addr), + .msu_reset_out(msu_addr_reset), + .mcu_rrq(MCU_RRQ), + .mcu_wrq(MCU_WRQ), + .mcu_rq_rdy(MCU_RDY), + .use_msu1(use_msu1) +); + +wire [7:0] DCM_STATUS; +// dcm1: dfs 4x +my_dcm snes_dcm( + .CLKIN(CLKIN), + .CLKFX(CLK2), + .LOCKED(DCM_LOCKED), + .RST(DCM_RST), + .STATUS(DCM_STATUS) +); + +assign DCM_RST=0; + +reg [5:0] SNES_READr; +reg [5:0] SNES_WRITEr; +reg [5:0] SNES_CPU_CLKr; + +wire SNES_RD_start = (SNES_READr == 6'b111110); +wire SNES_WR_start = (SNES_WRITEr == 6'b111110); +wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); +wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); + +always @(posedge CLK2) begin + SNES_READr <= {SNES_READr[4:0], SNES_READ}; + SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; + SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK}; +end + +address snes_addr( + .CLK(CLK2), + .MAPPER(MAPPER), + .SNES_ADDR(SNES_ADDR), // requested address from SNES + .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) + .ROM_SEL(ROM_SEL), // which SRAM unit to access + .IS_SAVERAM(IS_SAVERAM), + .IS_ROM(IS_ROM), + .IS_WRITABLE(IS_WRITABLE), + .SAVERAM_MASK(SAVERAM_MASK), + .ROM_MASK(ROM_MASK), + .use_msu1(use_msu1), + //MSU-1 + .msu_enable(msu_enable), + //CX4 + .cx4_enable(cx4_enable) +); + +reg [7:0] CX4_DINr; +wire [23:0] CX4_ADDR; + +cx4 snes_cx4 ( + .DI(CX4_SNES_DATA_IN), + .DO(CX4_SNES_DATA_OUT), + .ADDR(SNES_ADDR[12:0]), + .CS(cx4_enable), + .nRD(SNES_READ), + .nWR(SNES_WRITE), + .CLK(CLK2), + .DATROM_DI(DATROM_DI), + .DATROM_WE(DATROM_WE), + .DATROM_ADDR(DATROM_ADDR), + .BUS_DI(CX4_DINr), + .BUS_ADDR(CX4_ADDR), + .BUS_RRQ(CX4_RRQ), + .BUS_RDY(CX4_RDY) + ); + +parameter MODE_SNES = 1'b0; +parameter MODE_MCU = 1'b1; + +parameter ST_IDLE = 21'b000000000000000000001; +parameter ST_SNES_RD_ADDR = 21'b000000000000000000010; +parameter ST_SNES_RD_WAIT = 21'b000000000000000000100; +parameter ST_SNES_RD_END = 21'b000000000000000001000; +parameter ST_SNES_WR_ADDR = 21'b000000000000000010000; +parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000; +parameter ST_SNES_WR_DATA = 21'b000000000000001000000; +parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000; +parameter ST_SNES_WR_END = 21'b000000000000100000000; +parameter ST_MCU_RD_ADDR = 21'b000000000001000000000; +parameter ST_MCU_RD_WAIT = 21'b000000000010000000000; +parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000; +parameter ST_MCU_RD_END = 21'b000000001000000000000; +parameter ST_MCU_WR_ADDR = 21'b000000010000000000000; +parameter ST_MCU_WR_WAIT = 21'b000000100000000000000; +parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000; +parameter ST_MCU_WR_END = 21'b000010000000000000000; +parameter ST_CX4_RD_ADDR = 21'b000100000000000000000; +parameter ST_CX4_RD_WAIT = 21'b001000000000000000000; +parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000; +parameter ST_CX4_RD_END = 21'b100000000000000000000; + +parameter ROM_RD_WAIT = 4'h4; +parameter ROM_RD_WAIT_MCU = 4'h6; +parameter ROM_WR_WAIT1 = 4'h2; +parameter ROM_WR_WAIT2 = 4'h3; +parameter ROM_WR_WAIT_MCU = 4'h6; +parameter ROM_RD_WAIT_CX4 = 4'h6; + +reg [20:0] STATE; +initial STATE = ST_IDLE; + +assign MSU_SNES_DATA_IN = SNES_DATA; +assign CX4_SNES_DATA_IN = SNES_DATA; + +reg [7:0] SNES_DINr; +reg [7:0] ROM_DOUTr; + +assign SNES_DATA = (!SNES_READ) ? (msu_enable ? MSU_SNES_DATA_OUT + :cx4_enable ? CX4_SNES_DATA_OUT + :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ; + +reg [3:0] ST_MEM_DELAYr; +reg MCU_RD_PENDr; +reg MCU_WR_PENDr; +reg CX4_RD_PENDr; +reg [23:0] ROM_ADDRr; +reg NEED_SNES_ADDRr; +always @(posedge CLK2) begin + if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1; + else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0; +end + +wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE; +wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART; + +assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1]; +assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0]; + +reg ROM_WEr; +initial ROM_WEr = 1'b1; + +reg RQ_MCU_RDYr; +initial RQ_MCU_RDYr = 1'b1; +assign MCU_RDY = RQ_MCU_RDYr; + +always @(posedge CLK2) begin + if(MCU_RRQ) begin + MCU_RD_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(MCU_WRQ) begin + MCU_WR_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin + MCU_RD_PENDr <= 1'b0; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; + end +end + +reg RQ_CX4_RDYr; +initial RQ_CX4_RDYr = 1'b1; +assign CX4_RDY = RQ_CX4_RDYr; + +always @(posedge CLK2) begin + if(CX4_RRQ) begin + CX4_RD_PENDr <= 1'b1; + RQ_CX4_RDYr <= 1'b0; + end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin + CX4_RD_PENDr <= 1'b0; + RQ_CX4_RDYr <= 1'b1; + end +end + +reg snes_wr_cycle; + +always @(posedge CLK2) begin + if(SNES_cycle_start & IS_CART) begin + STATE <= ST_SNES_RD_ADDR; + end else if(SNES_WR_start & IS_CART) begin + STATE <= ST_SNES_WR_ADDR; + end else begin + case(STATE) + ST_IDLE: begin + ROM_ADDRr <= MAPPED_SNES_ADDR; + if(CX4_RRQ | CX4_RD_PENDr) begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + else if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; + else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; + else STATE <= ST_IDLE; + end + ST_SNES_RD_ADDR: begin + STATE <= ST_SNES_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT; + end + ST_SNES_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; + else STATE <= ST_SNES_RD_WAIT; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_RD_END: begin + STATE <= ST_IDLE; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_WR_ADDR: begin + ROM_WEr <= (!IS_WRITABLE); + snes_wr_cycle <= 1'b1; + STATE <= ST_SNES_WR_WAIT1; + ST_MEM_DELAYr <= ROM_WR_WAIT1; + end + ST_SNES_WR_WAIT1: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; + else STATE <= ST_SNES_WR_WAIT1; + end + ST_SNES_WR_DATA: begin + ROM_DOUTr <= SNES_DATA; + ST_MEM_DELAYr <= ROM_WR_WAIT2; + STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; + else STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_END: begin + STATE <= ST_IDLE; + ROM_WEr <= 1'b1; + snes_wr_cycle <= 1'b0; + end + ST_MCU_RD_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; + end + ST_MCU_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_RD_WAIT; + if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; + else MCU_DINr <= ROM_DATA[15:8]; + end + ST_MCU_RD_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_END; + end else STATE <= ST_MCU_RD_WAIT2; + end + ST_MCU_RD_END: begin + STATE <= ST_IDLE; + end + ST_MCU_WR_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_WR_WAIT; + ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; + ROM_DOUTr <= MCU_DOUT; + ROM_WEr <= 1'b0; + end + ST_MCU_WR_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + ROM_WEr <= 1'b1; + STATE <= ST_MCU_WR_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_WR_WAIT; + end + ST_MCU_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_WR_END; + end else STATE <= ST_MCU_WR_WAIT2; + end + ST_MCU_WR_END: begin + STATE <= ST_IDLE; + end + + ST_CX4_RD_ADDR: begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + ST_CX4_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_IDLE; + end + else STATE <= ST_CX4_RD_WAIT; + if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; + else CX4_DINr <= ROM_DATA[15:8]; + end + ST_CX4_RD_END: begin + STATE <= ST_IDLE; + end + endcase + end +end + +assign ROM_DATA[7:0] = ROM_ADDR0 + ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ) + :8'bZ; + +assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ + :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ); + +assign ROM_WE = SD_DMA_TO_ROM + ?MCU_WRITE + :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); + +// OE always active. Overridden by WE when needed. +assign ROM_OE = 1'b0; + +assign ROM_CE = 1'b0; + +assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0; +assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; + +assign SNES_DATABUS_OE = msu_enable ? 1'b0 : + cx4_enable ? 1'b0 : + ((IS_ROM & SNES_CS) + |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE) + |(SNES_READ & SNES_WRITE) + ); + +assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; + +assign IRQ_DIR = 1'b0; +assign SNES_IRQ = 1'bZ; + +assign p113_out = 1'b0; + +endmodule diff --git a/verilog/sd2snes_cx4/msu.v b/verilog/sd2snes_cx4/msu.v new file mode 100644 index 0000000..32b106a --- /dev/null +++ b/verilog/sd2snes_cx4/msu.v @@ -0,0 +1,194 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:55:04 12/14/2010 +// Design Name: +// Module Name: msu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module msu( + input clkin, + input enable, + input [13:0] pgm_address, + input [7:0] pgm_data, + input pgm_we, + input [2:0] reg_addr, + input [7:0] reg_data_in, + output [7:0] reg_data_out, + input reg_oe, + input reg_we, + output [6:0] status_out, + output [7:0] volume_out, + output volume_latch_out, + output [31:0] addr_out, + output [15:0] track_out, + input [5:0] status_reset_bits, + input [5:0] status_set_bits, + input status_reset_we, + input [13:0] msu_address_ext, + input msu_address_ext_write +); + +reg [2:0] reg_addr_r [3:0]; +always @(posedge clkin) begin + reg_addr_r[3] <= reg_addr_r[2]; + reg_addr_r[2] <= reg_addr_r[1]; + reg_addr_r[1] <= reg_addr_r[0]; + reg_addr_r[0] <= reg_addr; +end + + +reg [1:0] status_reset_we_r; +always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we}; +wire status_reset_en = (status_reset_we_r == 2'b01); + +reg [13:0] msu_address_r; +wire [13:0] msu_address = msu_address_r; + +wire [7:0] msu_data; + +reg [1:0] msu_address_ext_write_sreg; +always @(posedge clkin) + msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write}; +wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01); + +reg [4:0] reg_enable_sreg; +initial reg_enable_sreg = 5'b11111; +always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable}; + +reg [5:0] reg_oe_sreg; +always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; +wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001); + +reg [5:0] reg_we_sreg; +always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we}; +wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001); + +reg [31:0] addr_out_r; +assign addr_out = addr_out_r; + +reg [15:0] track_out_r; +assign track_out = track_out_r; + +reg [7:0] volume_r; +assign volume_out = volume_r; + +reg volume_start_r; +assign volume_latch_out = volume_start_r; + +reg audio_start_r; +reg audio_busy_r; +reg data_start_r; +reg data_busy_r; +reg ctrl_start_r; +reg [1:0] audio_ctrl_r; +reg [1:0] audio_status_r; + +initial begin + audio_busy_r <= 1'b1; + data_busy_r <= 1'b1; +end + +assign status_out = {msu_address_r[13], // 6 + audio_start_r, // 5 + data_start_r, // 4 + volume_start_r, // 3 + audio_ctrl_r, // 2:1 + ctrl_start_r}; // 0 + +initial msu_address_r = 14'h1234; + +msu_databuf snes_msu_databuf ( + .clka(clkin), + .wea(~pgm_we), // Bus [0 : 0] + .addra(pgm_address), // Bus [13 : 0] + .dina(pgm_data), // Bus [7 : 0] + .clkb(clkin), + .addrb(msu_address), // Bus [13 : 0] + .doutb(msu_data) +); // Bus [7 : 0] + +reg [7:0] data_out_r; +assign reg_data_out = data_out_r; + +always @(posedge clkin) begin + case(reg_addr_r[3]) + 3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001}; + 3'h1: data_out_r <= msu_data; + 3'h2: data_out_r <= 8'h53; + 3'h3: data_out_r <= 8'h2d; + 3'h4: data_out_r <= 8'h4d; + 3'h5: data_out_r <= 8'h53; + 3'h6: data_out_r <= 8'h55; + 3'h7: data_out_r <= 8'h31; + endcase +end + +always @(posedge clkin) begin + if(reg_we_rising) begin + case(reg_addr_r[3]) + 3'h0: addr_out_r[7:0] <= reg_data_in; + 3'h1: addr_out_r[15:8] <= reg_data_in; + 3'h2: addr_out_r[23:16] <= reg_data_in; + 3'h3: begin + addr_out_r[31:24] <= reg_data_in; + data_start_r <= 1'b1; + data_busy_r <= 1'b1; + end + 3'h4: begin + track_out_r[7:0] <= reg_data_in; + end + 3'h5: begin + track_out_r[15:8] <= reg_data_in; + audio_start_r <= 1'b1; + audio_busy_r <= 1'b1; + end + 3'h6: begin + volume_r <= reg_data_in; + volume_start_r <= 1'b1; + end + 3'h7: begin + if(!audio_busy_r) begin + audio_ctrl_r <= reg_data_in[1:0]; + ctrl_start_r <= 1'b1; + end + end + endcase + end else if (status_reset_en) begin + audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5]; + if(status_reset_bits[5]) audio_start_r <= 1'b0; + + data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4]; + if(status_reset_bits[4]) data_start_r <= 1'b0; + +// volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3]; + + audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1]; + + ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0]; + end else begin + volume_start_r <= 1'b0; + end +end + +always @(posedge clkin) begin + if(msu_address_ext_write_rising) + msu_address_r <= msu_address_ext; + else if(reg_addr_r[3] == 3'h1 && reg_oe_rising) begin + msu_address_r <= msu_address_r + 1; + end +end + +endmodule diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise new file mode 100644 index 0000000..0c67fd3 --- /dev/null +++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise @@ -0,0 +1,456 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/sd_dma.v b/verilog/sd2snes_cx4/sd_dma.v new file mode 100644 index 0000000..0d7d2c8 --- /dev/null +++ b/verilog/sd2snes_cx4/sd_dma.v @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:19:08 12/01/2010 +// Design Name: +// Module Name: sd_dma +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module sd_dma( + input [3:0] SD_DAT, + inout SD_CLK, + input CLK, + input SD_DMA_EN, + output SD_DMA_STATUS, + output SD_DMA_SRAM_WE, + output SD_DMA_NEXTADDR, + output [7:0] SD_DMA_SRAM_DATA, + input SD_DMA_PARTIAL, + input [10:0] SD_DMA_PARTIAL_START, + input [10:0] SD_DMA_PARTIAL_END +); + +reg [10:0] SD_DMA_STARTr; +reg [10:0] SD_DMA_ENDr; +reg SD_DMA_PARTIALr; +always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL; + +reg SD_DMA_DONEr; +reg[1:0] SD_DMA_DONEr2; +initial begin + SD_DMA_DONEr2 = 2'b00; + SD_DMA_DONEr = 1'b0; +end +always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr}; +wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01); + +reg [1:0] SD_DMA_ENr; +initial SD_DMA_ENr = 2'b00; +always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN}; +wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01); + +reg SD_DMA_STATUSr; +assign SD_DMA_STATUS = SD_DMA_STATUSr; + +// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit) +reg [10:0] cyclecnt; +initial cyclecnt = 11'd0; + +reg SD_DMA_SRAM_WEr; +initial SD_DMA_SRAM_WEr = 1'b1; +assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1; + +reg SD_DMA_NEXTADDRr; +assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0; + +reg[7:0] SD_DMA_SRAM_DATAr; +assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; + +// we have 4 internal cycles per SD clock, 8 per RAM byte write +reg [2:0] clkcnt; +initial clkcnt = 3'b000; +reg SD_CLKr; +always @(posedge CLK) SD_CLKr <= clkcnt[1]; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; + +always @(posedge CLK) begin + if(SD_DMA_EN_rising) begin + SD_DMA_STATUSr <= 1'b1; + SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0); + SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024); + end + else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0; +end + +always @(posedge CLK) begin + if(cyclecnt == 1042) SD_DMA_DONEr <= 1; + else SD_DMA_DONEr <= 0; +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin + clkcnt <= 0; + end else begin + if(SD_DMA_STATUSr) begin + clkcnt <= clkcnt + 1; + end + end +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0; + else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1; +end + +// we have 8 clk cycles to complete one RAM write +// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte) +always @(posedge CLK) begin + if(SD_DMA_STATUSr) begin + case(clkcnt[2:0]) + 3'h0: begin + SD_DMA_SRAM_WEr <= 1'b1; + SD_DMA_SRAM_DATAr[7:4] <= SD_DAT; + if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1; + end + 3'h1: + SD_DMA_NEXTADDRr <= 1'b0; +// 3'h2: + 3'h3: + if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0; + 3'h4: + SD_DMA_SRAM_DATAr[3:0] <= SD_DAT; +// 3'h5: +// 3'h6: +// 3'h7: + endcase + end +end + +endmodule + diff --git a/verilog/sd2snes_cx4/spi.v b/verilog/sd2snes_cx4/spi.v new file mode 100644 index 0000000..cb6bf79 --- /dev/null +++ b/verilog/sd2snes_cx4/spi.v @@ -0,0 +1,113 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:16:09 07/10/2009 +// Design Name: +// Module Name: spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// + +////////////////////////////////////////////////////////////////////////////////// +module spi( + input clk, + input SCK, + input MOSI, + inout MISO, + input SSEL, + output cmd_ready, + output param_ready, + output [7:0] cmd_data, + output [7:0] param_data, + output endmessage, + output startmessage, + input [7:0] input_data, + output [31:0] byte_cnt, + output [2:0] bit_cnt +); + +reg [7:0] cmd_data_r; +reg [7:0] param_data_r; + +reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL}; +wire SSEL_active = ~SSELr[1]; // SSEL is active low +wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge +wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge +assign endmessage = SSEL_endmessage; +assign startmessage = SSEL_startmessage; + +// bit count for one SPI byte + byte count for the message +reg [2:0] bitcnt; +reg [31:0] byte_cnt_r; + +reg byte_received; // high when a byte has been received +reg [7:0] byte_data_received; + +assign bit_cnt = bitcnt; + +always @(posedge SCK) begin + if(SSEL) bitcnt <= 3'b000; + else begin + bitcnt <= bitcnt + 3'b001; + byte_data_received <= {byte_data_received[6:0], MOSI}; + end + if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1; + else byte_received <= 1'b0; +end + +reg [1:0] byte_received_r; +always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received}; +wire byte_received_sync = (byte_received_r == 2'b01); + +always @(posedge clk) begin + if(~SSEL_active) + byte_cnt_r <= 16'h0000; + else if(byte_received_sync) begin + byte_cnt_r <= byte_cnt_r + 16'h0001; + end +end + +reg [7:0] byte_data_sent; + +assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first + +reg cmd_ready_r; +reg param_ready_r; +reg cmd_ready_r2; +reg param_ready_r2; +assign cmd_ready = cmd_ready_r; +assign param_ready = param_ready_r; +assign cmd_data = cmd_data_r; +assign param_data = param_data_r; +assign byte_cnt = byte_cnt_r; + +always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0; +always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0; + +// fill registers +always @(posedge clk) begin + if (SSEL_startmessage) + cmd_data_r <= 8'h00; + else if(cmd_ready_r2) + cmd_data_r <= byte_data_received; + else if(param_ready_r2) + param_data_r <= byte_data_received; +end + +// delay ready signals by one clock +always @(posedge clk) begin + cmd_ready_r <= cmd_ready_r2; + param_ready_r <= param_ready_r2; +end + +endmodule From fb9a28bf38cb63d12eef8a916dd160736bf64c5f Mon Sep 17 00:00:00 2001 From: ikari Date: Sun, 23 Oct 2011 20:56:07 +0200 Subject: [PATCH 07/66] FPGA/cx4: rework CPU FSM (ALU still missing) --- verilog/sd2snes_cx4/cx4.v | 751 +++++++++++++++++++++----------------- 1 file changed, 421 insertions(+), 330 deletions(-) diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index 97286be..6d62b47 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -19,22 +19,22 @@ // ////////////////////////////////////////////////////////////////////////////////// module cx4( - input [7:0] DI, - output [7:0] DO, - input [12:0] ADDR, - input CS, - input nRD, - input nWR, - input CLK, - input [23:0] DATROM_DI, - input DATROM_WE, - input [9:0] DATROM_ADDR, - input [7:0] BUS_DI, - output [23:0] BUS_ADDR, - output BUS_RRQ, - input BUS_RDY, - output cx4_active - ); + input [7:0] DI, + output [7:0] DO, + input [12:0] ADDR, + input CS, + input nRD, + input nWR, + input CLK, + input [23:0] DATROM_DI, + input DATROM_WE, + input [9:0] DATROM_ADDR, + input [7:0] BUS_DI, + output [23:0] BUS_ADDR, + output BUS_RRQ, + input BUS_RDY, + output cx4_active +); reg [2:0] cx4_busy; parameter BUSY_CACHE = 2'b00; @@ -57,10 +57,10 @@ wire [7:0] GPR_DO; assign DO = datram_enable ? DATRAM_DO : mmio_enable ? MMIO_DO - : status_enable ? STATUS_DO - : vector_enable ? VECTOR_DO - : gpr_enable ? GPR_DO - : 8'h00; + : status_enable ? STATUS_DO + : vector_enable ? VECTOR_DO + : gpr_enable ? GPR_DO + : 8'h00; /* 0x1f40 - 0x1f52: MMIO SNES: 8 bits / CX4: various */ @@ -138,8 +138,8 @@ reg [23:0] cpu_idb; // tmp register for reg file read /* Need to cache when: 1f48 is written - AND (selected cache page is invalid - OR selected cache page does not contain requested page already) + AND (selected cache page is invalid + OR selected cache page does not contain requested page already) */ reg CACHE_TRIG_ENr; reg CACHE_TRIG_EN2r; @@ -162,6 +162,9 @@ initial begin end assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr; +reg cpu_go_en_r; +initial cpu_go_en_r = 1'b0; + initial begin cx4_mmio_r1f50 = 8'h33; cx4_mmio_r1f51 = 1'b0; @@ -170,74 +173,78 @@ end always @(posedge CLK) begin case (ADDR[4:0]) - 5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40 - 5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41 - 5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42 - 5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43 - 5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44 - 5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45 - 5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46 - 5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47 - 5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage}; - 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 - 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a - 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b - 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c - 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d - 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e - 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f - 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 + 5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40 + 5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41 + 5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42 + 5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43 + 5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44 + 5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45 + 5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46 + 5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47 + 5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage}; + 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 + 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a + 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b + 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c + 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d + 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e + 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f + 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51 - 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 - - 5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40 - 5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40 - 5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40 - 5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40 - 5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40 - 5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40 + 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 - -// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40 -// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41 -// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42 -// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43 - default: MMIO_DOr <= 8'hff; + 5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40 + 5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40 + 5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40 + 5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40 + 5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40 + 5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40 + + +// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40 +// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41 +// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42 +// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43 + default: MMIO_DOr <= 8'hff; endcase end always @(posedge CLK) begin if(MMIO_WR_EN) begin case(ADDR[4:0]) - 5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 - 5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 - 5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 - 5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 - 5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 - 5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 - 5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 - 5'h07: begin - cx4_mmio_dmatgt[23:16] <= DI; // 1f47 - DMA_TRIG_ENr <= 1'b1; - end - 5'h08: begin - cx4_mmio_cachepage <= DI[0]; // 1f48 - CACHE_TRIG_ENr <= 1'b1; - end - 5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 - 5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a - 5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b - 5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c - 5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d - 5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e - 5'h0f: cx4_mmio_pc <= DI; // 1f4f - 5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 - 5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 - 5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 - endcase + 5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 + 5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 + 5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 + 5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 + 5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 + 5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 + 5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 + 5'h07: begin + cx4_mmio_dmatgt[23:16] <= DI; // 1f47 + DMA_TRIG_ENr <= 1'b1; + end + 5'h08: begin + cx4_mmio_cachepage <= DI[0]; // 1f48 + CACHE_TRIG_ENr <= 1'b1; + end + 5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 + 5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a + 5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b + 5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c + 5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d + 5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e + 5'h0f: begin + cx4_mmio_pc <= DI; // 1f4f + cpu_go_en_r <= 1'b1; + end + 5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 + 5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 + 5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 + endcase end else begin CACHE_TRIG_ENr <= 1'b0; - DMA_TRIG_ENr <= 1'b0; + DMA_TRIG_ENr <= 1'b0; + cpu_go_en_r <= 1'b0; end end @@ -245,10 +252,6 @@ always @(posedge CLK) begin if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI; end -always @(posedge CLK) begin - if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; -end - reg [4:0] CACHE_ST; parameter ST_CACHE_IDLE = 5'b00001; parameter ST_CACHE_START = 5'b00010; @@ -272,7 +275,7 @@ wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]}; assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR : cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR - : 24'h000000 /* XXX cx4_bus_addr */; + : 24'h800000 /* XXX cx4_bus_addr */; reg cx4_pgmrom_we; initial cx4_pgmrom_we = 1'b0; @@ -282,97 +285,101 @@ initial cache_count = 20'b0; always @(posedge CLK) begin case(CACHE_ST) - ST_CACHE_IDLE: begin - if(CACHE_TRIG_EN - & (~cachetag[cx4_mmio_cachepage][15] - | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) + ST_CACHE_IDLE: begin + if(CACHE_TRIG_EN + & (~cachetag[cx4_mmio_cachepage][15] + | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin - CACHE_ST <= ST_CACHE_START; - end else CACHE_ST <= ST_CACHE_IDLE; - end - ST_CACHE_START: begin - cx4_busy[BUSY_CACHE] <= 1'b1; - CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0}; - cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0}; - CACHE_ST <= ST_CACHE_WAIT; - cache_count <= 10'b0; + CACHE_ST <= ST_CACHE_START; + end else CACHE_ST <= ST_CACHE_IDLE; + end + ST_CACHE_START: begin + cx4_busy[BUSY_CACHE] <= 1'b1; + CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0}; + cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0}; + CACHE_ST <= ST_CACHE_WAIT; + cache_count <= 10'b0; CACHE_BUS_RRQr <= 1'b1; - end - ST_CACHE_WAIT: begin - CACHE_BUS_RRQr <= 1'b0; - if(~CACHE_BUS_RRQr & BUS_RDY) begin - CACHE_ST <= ST_CACHE_ADDR; - cx4_pgmrom_we <= 1'b1; - cache_count <= cache_count + 1; - end else CACHE_ST <= ST_CACHE_WAIT; - end - ST_CACHE_ADDR: begin - cx4_pgmrom_we <= 1'b0; - CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1; - cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; - if(cache_count == 9'h1ff) begin - cx4_busy[BUSY_CACHE] <= 1'b0; - cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage}; - CACHE_ST <= ST_CACHE_IDLE; - end else begin - CACHE_BUS_RRQr <= 1'b1; - CACHE_ST <= ST_CACHE_WAIT; - end - end + end + ST_CACHE_WAIT: begin + CACHE_BUS_RRQr <= 1'b0; + if(~CACHE_BUS_RRQr & BUS_RDY) begin + CACHE_ST <= ST_CACHE_ADDR; + cx4_pgmrom_we <= 1'b1; + cache_count <= cache_count + 1; + end else CACHE_ST <= ST_CACHE_WAIT; + end + ST_CACHE_ADDR: begin + cx4_pgmrom_we <= 1'b0; + CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1; + cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; + if(cache_count == 9'h1ff) begin + cx4_busy[BUSY_CACHE] <= 1'b0; + cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage}; + CACHE_ST <= ST_CACHE_IDLE; + end else begin + CACHE_BUS_RRQr <= 1'b1; + CACHE_ST <= ST_CACHE_WAIT; + end + end endcase end -reg cx4_datram_we; -initial cx4_datram_we = 1'b0; -reg [11:0] cx4_datram_addr; +reg cx4_dma_datram_we; +reg cx4_cpu_datram_we; +initial cx4_dma_datram_we = 1'b0; +initial cx4_cpu_datram_we = 1'b0; +wire cx4_datram_we = cx4_dma_datram_we | cx4_cpu_datram_we; +reg [11:0] cx4_dma_datram_addr; +reg [11:0] cx4_cpu_datram_addr; +wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr; +reg [23:0] cx4_cpu_datram_di; +wire [23:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di; reg [15:0] dma_count; initial dma_count = 16'b0; always @(posedge CLK) begin case(DMA_ST) - ST_DMA_IDLE: begin - if(DMA_TRIG_EN) begin - DMA_ST <= ST_DMA_START; - end else DMA_ST <= ST_DMA_IDLE; - end - ST_DMA_START: begin - cx4_busy[BUSY_DMA] <= 1'b1; - DMA_SRC_ADDRr <= cx4_mmio_dmasrc; - /* XXX Rename to DMA_TGT_ADDRr and switch */ - cx4_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff); - DMA_ST <= ST_DMA_WAIT; - dma_count <= cx4_mmio_dmalen; + ST_DMA_IDLE: begin + if(DMA_TRIG_EN) begin + DMA_ST <= ST_DMA_START; + end else DMA_ST <= ST_DMA_IDLE; + end + ST_DMA_START: begin + cx4_busy[BUSY_DMA] <= 1'b1; + DMA_SRC_ADDRr <= cx4_mmio_dmasrc; + cx4_dma_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff); + DMA_ST <= ST_DMA_WAIT; + dma_count <= cx4_mmio_dmalen; DMA_BUS_RRQr <= 1'b1; - end - ST_DMA_WAIT: begin - DMA_BUS_RRQr <= 1'b0; - if(~DMA_BUS_RRQr & BUS_RDY) begin - DMA_ST <= ST_DMA_ADDR; - /* XXX Rename to DMA_TGT_WEr and switch */ - cx4_datram_we <= 1'b1; - dma_count <= dma_count - 1; - end else DMA_ST <= ST_DMA_WAIT; - end - ST_DMA_ADDR: begin - /* XXX Rename to DMA_TGT_WEr and switch */ - cx4_datram_we <= 1'b0; - DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1; - cx4_datram_addr <= cx4_datram_addr + 1; - if(dma_count == 16'h0000) begin - cx4_busy[BUSY_DMA] <= 1'b0; - DMA_ST <= ST_DMA_IDLE; - end else begin - DMA_BUS_RRQr <= 1'b1; - DMA_ST <= ST_DMA_WAIT; - end - end + end + ST_DMA_WAIT: begin + DMA_BUS_RRQr <= 1'b0; + if(~DMA_BUS_RRQr & BUS_RDY) begin + DMA_ST <= ST_DMA_ADDR; + cx4_dma_datram_we <= 1'b1; + dma_count <= dma_count - 1; + end else DMA_ST <= ST_DMA_WAIT; + end + ST_DMA_ADDR: begin + cx4_dma_datram_we <= 1'b0; + DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1; + cx4_dma_datram_addr <= cx4_dma_datram_addr + 1; + if(dma_count == 16'h0000) begin + cx4_busy[BUSY_DMA] <= 1'b0; + DMA_ST <= ST_DMA_IDLE; + end else begin + DMA_BUS_RRQr <= 1'b1; + DMA_ST <= ST_DMA_WAIT; + end + end endcase end /*************************** =========== CPU =========== ***************************/ -reg [7:0] CPU_STATE; +reg [4:0] CPU_STATE; reg cpu_page; reg [7:0] cpu_pc; reg [8:0] cpu_stack [7:0]; @@ -396,200 +403,284 @@ reg fl_z; reg fl_c; reg [15:0] cpu_p; -reg [9:0] cx4_datrom_addr; +wire [9:0] cx4_datrom_addr = cpu_a[9:0]; wire [23:0] cx4_datrom_do; wire [7:0] cx4_datram_do; -parameter ST_CPU_IDLE = 8'b00000001; -parameter ST_CPU_0 = 8'b00000010; -parameter ST_CPU_1 = 8'b00000100; -parameter ST_CPU_2 = 8'b00001000; -parameter ST_CPU_3 = 8'b00010000; +parameter ST_CPU_IDLE = 5'b00001; +parameter ST_CPU_0 = 5'b00010; +parameter ST_CPU_1 = 5'b00100; +parameter ST_CPU_2 = 5'b01000; +parameter ST_CPU_3 = 5'b10000; initial CPU_STATE <= ST_CPU_IDLE; -parameter OP_ALU = 4'b0000; -parameter OP_LD = 4'b0001; -parameter OP_ST = 4'b0010; -parameter OP_JP = 4'b0011; -parameter OP_SWP = 4'b0100; -parameter OP_HLT = 4'b0101; -parameter OP_BUS = 4'b0110; -parameter OP_STA = 4'b0111; -parameter OP_NOP = 4'b1111; - +parameter OP_NOP = 4'b0000; +parameter OP_JP = 4'b0001; +parameter OP_SKIP = 4'b0010; +parameter OP_RT = 4'b0011; +parameter OP_LD = 4'b0100; +parameter OP_ST = 4'b0101; +parameter OP_SWP = 4'b0110; +parameter OP_RDROM = 4'b0111; +parameter OP_RDRAM = 4'b1000; +parameter OP_WRRAM = 4'b1001; +parameter OP_ALU = 4'b1010; +parameter OP_MUL = 4'b1011; +parameter OP_WAI = 4'b1100; +parameter OP_BUS = 4'b1101; +parameter OP_HLT = 4'b1110; wire [6:0] op_id = cpu_op_w[15:10]; reg [7:0] op_param; -reg [2:0] op; +reg [3:0] op; reg [1:0] op_sa; reg op_imm; reg op_p; reg op_call; reg op_jump; -reg cond_true; -reg cpu_go_rq; +reg condtrue; reg cpu_bus_rq; always @(posedge CLK) begin case(CPU_STATE) ST_CPU_IDLE: begin - if(cpu_go_rq) begin - cpu_pc <= cx4_mmio_pc; - op <= OP_NOP; - CPU_STATE <= ST_CPU_2; - end - else CPU_STATE <= ST_CPU_IDLE; - end - ST_CPU_0: begin // Phase 0: - CPU_STATE <= ST_CPU_1; + if(cpu_go_en_r) begin + cpu_pc <= cx4_mmio_pc; + op <= OP_NOP; + CPU_STATE <= ST_CPU_2; + cx4_busy[BUSY_CPU] <= 1'b1; + end + else CPU_STATE <= ST_CPU_IDLE; + end + ST_CPU_0: begin // Phase 0: + if(op == OP_HLT) begin + cx4_busy[BUSY_CPU] <= 1'b0; + CPU_STATE <= ST_CPU_IDLE; + end + else CPU_STATE <= ST_CPU_1; case(op) - OP_ALU, OP_LD, OP_SWP: begin - if(cpu_op[15:10] == 6'b111000) cpu_idb <= cpu_a; // reg[imm] <- a - else if(op_imm) cpu_idb <= {16'b0, op_param}; - else casex(op_param) - 8'h00: cpu_idb <= cpu_a; - 8'h01: cpu_idb <= cpu_acch; - 8'h02: cpu_idb <= cpu_accl; - 8'h03: cpu_idb <= cpu_busdata; - 8'h08: cpu_idb <= cpu_romdata; - 8'h0c: cpu_idb <= cpu_ramdata; - 8'h13: cpu_idb <= cpu_busaddr; - 8'h1c: cpu_idb <= cpu_ramaddr; - 8'h5x: cpu_idb <= const[op_param[3:0]]; - 8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2], - gpr[op_param[3:0]*3+1], - gpr[op_param[3:0]*3]}; - default: cpu_idb <= 24'b0; - endcase - if(op==OP_ALU) begin - case(op_sa) - 2'b00: cpu_sa <= cpu_a; - 2'b01: cpu_sa <= cpu_a << 1; - 2'b10: cpu_sa <= cpu_a << 8; - 2'b11: cpu_sa <= cpu_a << 16; - endcase - end - end - OP_JP: begin - casex(cpu_op[12:8]) - 5'b010xx: cond_true <= 1'b1; - 5'b011xx: cond_true <= fl_z; - 5'b100xx: cond_true <= fl_c; - 5'b101xx: cond_true <= fl_n; - 5'b00101: cond_true <= (fl_c == cpu_op[0]); - 5'b00110: cond_true <= (fl_z == cpu_op[0]); - 5'b00111: cond_true <= (fl_n == cpu_op[0]); - default: cond_true <= 1'b1; - endcase - end - OP_BUS: cpu_bus_rq <= 1'b1; - endcase - end - ST_CPU_1: begin - CPU_STATE <= ST_CPU_2; - case(op) - OP_LD: begin - cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); - cx4_datrom_addr <= cpu_a[9:0]; - end - OP_ST: begin - cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); - cx4_datram_we <= 1'b1; - end - OP_JP: begin - if(cond_true) begin - casex(cpu_op[12:11]) - 2'b01, 2'b10: begin - // TODO if(op_p) - if(op_call) begin - cpu_stack[cpu_sp] <= {cpu_page, cpu_pc+1}; - cpu_sp <= cpu_sp - 1; - end - cpu_pc <= op_param; - end - 2'b00: begin - cpu_pc <= cpu_pc + 2; - end - 2'b11: begin - if(cpu_op[13]) begin - {cpu_page, cpu_pc} <= cpu_stack[cpu_sp+1]; - cpu_sp <= cpu_sp + 1; - end else begin - if(BUS_RDY) cpu_pc <= cpu_pc + 1; - end - end - default: cpu_pc <= cpu_pc + 1; - endcase - end - end - OP_BUS: cpu_bus_rq <= 1'b0; - endcase - end - ST_CPU_2: begin + OP_JP: begin + case(cpu_op[11:10]) + 2'b10: condtrue <= 1'b1; + 2'b11: condtrue <= fl_z; + 2'b00: condtrue <= fl_c; + 2'b01: condtrue <= fl_n; + endcase + end + OP_SKIP: begin + case(cpu_op[9:8]) + 2'b01: condtrue <= (fl_c == cpu_op[0]); + 2'b10: condtrue <= (fl_z == cpu_op[0]); + 2'b11: condtrue <= (fl_n == cpu_op[0]); + endcase + end + OP_LD, OP_SWP, OP_ALU, OP_MUL: begin + if(op_imm) cpu_idb <= {16'b0, op_param}; + else casex(op_param) + 8'h00: cpu_idb <= cpu_a; + 8'h01: cpu_idb <= cpu_acch; + 8'h02: cpu_idb <= cpu_accl; + 8'h03: cpu_idb <= cpu_busdata; + 8'h08: cpu_idb <= cpu_romdata; + 8'h0c: cpu_idb <= cpu_ramdata; + 8'h13: cpu_idb <= cpu_busaddr; + 8'h1c: cpu_idb <= cpu_ramaddr; + 8'h5x: cpu_idb <= const[op_param[3:0]]; + 8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]}; + default: cpu_idb <= 24'b0; + endcase + if(op==OP_ALU) begin + case(op_sa) + 2'b00: cpu_sa <= cpu_a; + 2'b01: cpu_sa <= cpu_a << 1; + 2'b10: cpu_sa <= cpu_a << 8; + 2'b11: cpu_sa <= cpu_a << 16; + endcase + end + end + OP_ST: begin + cpu_idb <= cpu_a; + end + OP_RDRAM, OP_WRRAM: begin + if(op_imm) cpu_ramaddr <= {16'b0, op_param}; + else casex(op_param) + 8'h00: cx4_cpu_datram_addr <= cpu_a; + 8'h01: cx4_cpu_datram_addr <= cpu_acch; + 8'h02: cx4_cpu_datram_addr <= cpu_accl; + 8'h03: cx4_cpu_datram_addr <= cpu_busdata; + 8'h08: cx4_cpu_datram_addr <= cpu_romdata; + 8'h0c: cx4_cpu_datram_addr <= cpu_ramdata; + 8'h13: cx4_cpu_datram_addr <= cpu_busaddr; + 8'h1c: cx4_cpu_datram_addr <= cpu_ramaddr; + 8'h5x: cx4_cpu_datram_addr <= const[op_param[3:0]]; + 8'h6x: cx4_cpu_datram_addr <= {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]}; + default: cx4_cpu_datram_addr <= 24'b0; + endcase + end + endcase + end + ST_CPU_1: begin + CPU_STATE <= ST_CPU_2; + case(op) + OP_JP: begin + if(condtrue) begin + if(op_call) begin + cpu_stack[cpu_sp] <= cpu_pc + 1; + cpu_sp <= cpu_sp + 1; + end + cpu_pc <= op_param; + end + end + OP_SKIP: begin + if(condtrue) begin + cpu_pc <= cpu_pc + 2; + end + end + OP_RT: begin + cpu_pc <= cpu_stack[cpu_sp - 1]; + cpu_sp <= cpu_sp - 1; + end + OP_LD, OP_ST, OP_SWP, OP_RDROM, OP_RDRAM, OP_WRRAM, OP_ALU, OP_MUL, OP_BUS: + cpu_pc <= cpu_pc + 1; + OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1; + default: cpu_pc <= cpu_pc + 1; + endcase + end + ST_CPU_2: begin CPU_STATE <= ST_CPU_3; - case(op) - OP_ST: begin - cx4_datram_we <= 1'b0; - end - endcase - end - ST_CPU_3: begin + case(op) + OP_LD: begin + casex(cpu_op[11:8]) + 4'b0x00: cpu_a <= cpu_idb; + 4'b0x11: cpu_p <= cpu_idb; + 4'b1100: cpu_p[7:0] <= op_param; + 4'b1101: cpu_p[15:8] <= op_param; + endcase + end + OP_ST: begin + casex(op_param) + 8'h00: cpu_a <= cpu_idb; + 8'h01: cpu_acch <= cpu_idb; + 8'h02: cpu_accl <= cpu_idb; + 8'h03: cpu_busdata <= cpu_idb; + 8'h08: cpu_romdata <= cpu_idb; + 8'h0c: cpu_ramdata <= cpu_idb; + 8'h13: cpu_busaddr <= cpu_idb; + 8'h1c: cpu_ramaddr <= cpu_idb; + endcase + end + OP_SWP: begin + casex(op_param) + 8'h00: cpu_a <= cpu_a; + 8'h01: cpu_acch <= cpu_a; + 8'h02: cpu_accl <= cpu_a; + 8'h03: cpu_busdata <= cpu_a; + 8'h08: cpu_romdata <= cpu_a; + 8'h0c: cpu_ramdata <= cpu_a; + 8'h13: cpu_busaddr <= cpu_a; + 8'h1c: cpu_ramaddr <= cpu_a; + endcase + end + OP_RDROM: cpu_romdata <= cx4_datrom_do; + OP_RDRAM: cpu_ramdata <= cx4_datram_do; + OP_WRRAM: begin + case(cpu_op[9:8]) + 2'b00: cx4_cpu_datram_di[7:0] <= cpu_ramdata[7:0]; + 2'b01: cx4_cpu_datram_di[15:8] <= cpu_ramdata[15:8]; + 2'b10: cx4_cpu_datram_di[23:16] <= cpu_ramdata[23:16]; + endcase + cx4_cpu_datram_we <= 1'b1; + end + OP_ALU: begin + /* XXX TODO FUCK YEAH ALU */ + end + OP_BUS: cpu_bus_rq <= 1'b1; + endcase + end + ST_CPU_3: begin CPU_STATE <= ST_CPU_0; - case(op) - OP_LD, OP_SWP: begin - casex(cpu_op[15:8]) - 8'b01100x00: cpu_a <= cpu_idb; - 8'b01100x11: cpu_p <= cpu_idb; - 8'b01111100: cpu_p[7:0] <= op_param; - 8'b01111101: cpu_p[15:8] <= op_param; - 8'b01110000: cpu_romdata <= cx4_datrom_do; - 8'b01101x00: cpu_ramdata[7:0] <= cx4_datram_do; - 8'b01101x01: cpu_ramdata[15:8] <= cx4_datram_do; - 8'b01101x10: cpu_ramdata[23:16] <= cx4_datram_do; - 8'b11110000, 8'b11100000: begin - if(cpu_op[12]) cpu_a <= cpu_idb; - casex(op_param) - 8'h00: cpu_a <= cpu_a; - 8'h01: cpu_acch <= cpu_a; - 8'h02: cpu_accl <= cpu_a; - 8'h03: cpu_busdata <= cpu_a; - 8'h08: cpu_romdata <= cpu_a; - 8'h0c: cpu_ramdata <= cpu_a; - 8'h13: cpu_busaddr <= cpu_a; - 8'h1c: cpu_ramaddr <= cpu_a; - 8'h6x: {gpr[op_param[3:0]*3+2], - gpr[op_param[3:0]*3+1], - gpr[op_param[3:0]*3]} <= cpu_a; - endcase - end - endcase - end - endcase - cpu_op <= cpu_op_w; - op_param <= cpu_op_w[7:0]; - op <= &(op_id) ? OP_HLT - :(op_id[5:4] == 2'b00) ? OP_JP - :(op_id[5:2] == 4'b0110 - || op_id[5:2] == 4'b0111 - ) ? OP_LD - :(op_id[5:1] == 5'b11101) ? OP_ST - :(op_id[5:1] == 5'b01000) ? OP_BUS - :(op_id[5:3] == 3'b010 - || op_id[5:3] == 3'b100 - || op_id[5:3] == 3'b101 - || op_id[5:3] == 3'b110) ? OP_ALU - : (op_id == 6'b111100 || op_id == 6'b111000) ? OP_SWP - : OP_NOP; - op_imm <= cpu_op_w[10]; - op_sa <= cpu_op_w[9:8]; - op_p <= cpu_op_w[9]; - op_call <= cpu_op_w[13]; - cond_true <= 1'b0; - end + case(op) + OP_SWP: cpu_a <= cpu_idb; + OP_WRRAM: cx4_cpu_datram_we <= 1'b0; + OP_ALU: begin + /* XXX TODO FUCKING FLAGS */ + end + OP_MUL: begin + cpu_acch <= cpu_mul_result[47:24]; + cpu_accl <= cpu_mul_result[23:0]; + fl_z <= (cpu_mul_result == 48'b0); + fl_n <= cpu_mul_result[47]; + end + OP_BUS: cpu_bus_rq <= 1'b0; + endcase + cpu_op <= cpu_op_w; + casex(cpu_op_w[15:11]) + 5'b00000: op <= OP_NOP; + + 5'b00x01: op <= OP_JP; + 5'b00x10: op <= OP_JP; + 5'b00100: op <= OP_SKIP; + 5'b00111: op <= OP_RT; + + 5'b01100: op <= OP_LD; + 5'b01111: op <= OP_LD; + 5'b11100: op <= OP_ST; + 5'b11110: op <= OP_SWP; + + 5'b01110: op <= OP_RDROM; + 5'b01101: op <= OP_RDRAM; + 5'b11101: op <= OP_WRRAM; + + 5'b01001: op <= OP_ALU; + 5'b01010: op <= OP_ALU; + 5'b01011: op <= OP_ALU; + 5'b10000: op <= OP_ALU; + 5'b10001: op <= OP_ALU; + 5'b10010: op <= OP_ALU; + 5'b10101: op <= OP_ALU; + 5'b10110: op <= OP_ALU; + 5'b10111: op <= OP_ALU; + 5'b11000: op <= OP_ALU; + 5'b11001: op <= OP_ALU; + 5'b11010: op <= OP_ALU; + 5'b11011: op <= OP_ALU; + 5'b10011: op <= OP_MUL; + + 5'b00011: op <= OP_WAI; + 5'b01000: op <= OP_BUS; + + 5'b11111: op <= OP_HLT; + endcase + op_imm <= cpu_op_w[10]; + op_p <= cpu_op_w[9]; + op_call <= cpu_op_w[13]; + end endcase end +// gpr write, either by CPU or by MMIO +always @(posedge CLK) begin + if(CPU_STATE == ST_CPU_2 + && (op == OP_SWP) + && (op_param[7:4] == 8'h6)) begin + gpr[op_param[3:0]*3+2] <= cpu_a[23:16]; + gpr[op_param[3:0]*3+1] <= cpu_a[15:8]; + gpr[op_param[3:0]*3] <= cpu_a[7:0]; + end + else if(CPU_STATE == ST_CPU_2 + && (op == OP_ST) + && (op_param[7:4] == 8'h6)) begin + gpr[op_param[3:0]*3+2] <= cpu_idb[23:16]; + gpr[op_param[3:0]*3+1] <= cpu_idb[15:8]; + gpr[op_param[3:0]*3] <= cpu_idb[7:0]; + end + else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; +end /*************************** =========== MEM =========== @@ -613,7 +704,7 @@ cx4_datram cx4_datram ( .clkb(CLK), // input clkb .web(cx4_datram_we), // input [0 : 0] web .addrb(cx4_datram_addr), // input [11 : 0] addrb - .dinb(BUS_DI), // input [7 : 0] dinb + .dinb(cx4_datram_di), // input [7 : 0] dinb .doutb(cx4_datram_do) // output [7 : 0] doutb ); @@ -630,7 +721,7 @@ cx4_pgmrom cx4_pgmrom ( cx4_mul cx4_mul ( .clk(CLK), // input clk .a(cpu_a), // input [23 : 0] a - .b(cpu_mul_src), // input [23 : 0] b + .b(cpu_idb), // input [23 : 0] b .p(cpu_mul_result) // output [47 : 0] p ); endmodule From fc53d173bf259117d490b1088165de0151591f81 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 27 Oct 2011 15:37:44 +0200 Subject: [PATCH 08/66] basic build instructions --- src/README | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 src/README diff --git a/src/README b/src/README new file mode 100644 index 0000000..8829d25 --- /dev/null +++ b/src/README @@ -0,0 +1,85 @@ +How to build: + +a) Build requirements + * make + * Cortex M3 toolchain + * snescom/sneslink + * Xilinx FPGA synthesis tool (e.g. ISE WebPack) + * PIC assembler + +b) Cortex M3 toolchain + * obtain the cm3-toolchain builder: + git clone http://snowcat.de/toolchain-cm3.git/ + * build the cm3-toolchain. Some tools, libraries, and headers are required, + including but probably not limited to: + - libz-dev + - libcloog-ppl-dev + - texinfo + - libmpfr-dev + - libgmp3-dev + - gawk + - bison + - recode + - flex + - libncurses5-dev + - libexpat-dev + - make + - gcc + Newer gccs complain when compiling binutils, so you may have to add + '--disable-werror' to the compiler options for binutils in the Makefile. + The Makefile will install immediately so make sure you can write to the + installation directory. + +c) snescom/sneslink + * http://bisqwit.iki.fi/source/snescom.html + +d) ISE WebPack + * http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm + +e) PIC assembler + * e.g. GPUTILS, http://gputils.sourceforge.net/ + +f) general order of operations + 1) program the PIC (cic/supercic/supercic-key.asm) + 2) build and program the bootloader. + 3) build the firmware and copy it to the memory card + 4) build the snes menu and copy it to the memory card + 5) build and compress the FPGA configuration and copy it to the memory card + 6) insert memory card, power on; the bootloader should begin flashing the + firmware and boot it + +1) Programming the PIC +Use a PIC assembler + programmer of your choice and program a PIC12F629 with +cic/supercic/supercic-key.asm. Make sure that the clock source is set to +EC_OSC and MCLRE is disabled. +After programming you can solder the PIC to the board and short JP401. +Open JP401 in case you need to reprogram the PIC on board. + +2) Building & programming the bootloader +The Makefile is prepared for JTAG programming using OpenOCD 0.4 and an FT2232 +based USB-JTAG adapter. +Connect a JTAG cable to J401 (14-pin header). The pinout is printed on the +board. cd to src/bootldr and make && make program. + +3) Building the firmware +cd to src/utils and make. +cd to src/ and make. +You should obtain a firmware file called obj/firmware.img. Copy this file to +/sd2snes/firmware.img. + +4) Building the SNES menu +snescom is required. +cd to snes/ and make. +Copy the resulting file menu.bin to /sd2snes/menu.bin. + +5) Building the FPGA configuration +Compile the RLE compressor in utils/rle.c: + $ gcc -Wall -o rle rle.c + +Load verilog/sd2snes/sd2snes.xise in Xilinx ISE (or create your own project). +Target is a XC3S400-4PQ208. +Generate the programming file and compress it using utils/rle.c: + $ rle main.bit fpga_base.bit + +Copy fpga_base.bit to /sd2snes/fpga_base.bit + From 8c76dfbeb67cf17be69bd92f2e867a0f5080cb2a Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 27 Oct 2011 15:42:13 +0200 Subject: [PATCH 09/66] FPGA/Cx4: WIP --- src/fpga_spi.h | 1 + src/memory.c | 37 +- src/smc.c | 22 +- src/smc.h | 4 +- verilog/sd2snes/sd2snes.xise | 38 +- verilog/sd2snes_cx4/cx4.v | 368 ++- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v | 2844 ++++++++++------- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco | 6 +- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise | 314 +- verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v | 4 +- verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco | 8 +- .../sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise | 4 +- verilog/sd2snes_cx4/main.v | 16 +- verilog/sd2snes_cx4/sd2snes_cx4.xise | 22 +- 14 files changed, 2009 insertions(+), 1679 deletions(-) diff --git a/src/fpga_spi.h b/src/fpga_spi.h index 201179f..d04a954 100644 --- a/src/fpga_spi.h +++ b/src/fpga_spi.h @@ -50,6 +50,7 @@ #define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST) #define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW) +#define FEAT_CX4 (1 << 4) #define FEAT_MSU1 (1 << 3) #define FEAT_SRTC (1 << 2) #define FEAT_ST0010 (1 << 1) diff --git a/src/memory.c b/src/memory.c index 784a115..3797114 100644 --- a/src/memory.c +++ b/src/memory.c @@ -226,18 +226,16 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) { sram_writebyte(0xfc, rombase+0xd5); set_fpga_time(0x0220110301180530LL); } - if(romprops.has_dspx) { - printf("DSPx game. Loading firmware image %s...\n", romprops.necdsp_fw); - if(romprops.has_st0010) { - load_dspx(romprops.necdsp_fw, 1); - } else { - load_dspx(romprops.necdsp_fw, 0); - if(file_res && romprops.necdsp_fw == DSPFW_1) { - load_dspx(DSPFW_1B, 0); - } +fpga_pgm((uint8_t*)"/sd2snes/cx4.bit"); + if(romprops.has_dspx || romprops.has_cx4) { + printf("DSPx game. Loading firmware image %s...\n", romprops.dsp_fw); + load_dspx(romprops.dsp_fw, romprops.fpga_features); + /* fallback to DSP1B firmware if DSP1.bin is not present */ + if(file_res && romprops.dsp_fw == DSPFW_1) { + load_dspx(DSPFW_1B, romprops.fpga_features); } if(file_res) { - snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.necdsp_fw); + snes_menu_errmsg(MENU_ERR_NODSP, (void*)romprops.dsp_fw); } } uint32_t rammask; @@ -494,22 +492,29 @@ uint64_t sram_gettime(uint32_t base_addr) { return result & 0x00ffffffffffffffLL; } -void load_dspx(const uint8_t *filename, uint8_t st0010) { +void load_dspx(const uint8_t *filename, uint8_t coretype) { UINT bytes_read; DWORD filesize; uint16_t word_cnt; uint8_t wordsize_cnt = 0; uint16_t sector_remaining = 0; uint16_t sector_cnt = 0; - uint16_t pgmsize = 2048; - uint16_t datsize; + uint16_t pgmsize = 0; + uint16_t datsize = 0; uint32_t pgmdata = 0; uint16_t datdata = 0; - if(st0010) { + if(coretype & FEAT_ST0010) { datsize = 1536; - } else { + pgmsize = 2048; + } else if (coretype & FEAT_DSPX) { datsize = 1024; + pgmsize = 2048; + } else if (coretype & FEAT_CX4) { + datsize = 0; + pgmsize = 1024; /* Cx4 data ROM */ + } else { + printf("load_dspx: unknown core (%02x)!\n", coretype); } file_open((uint8_t*)filename, FA_READ); @@ -539,7 +544,7 @@ void load_dspx(const uint8_t *filename, uint8_t st0010) { } wordsize_cnt = 0; - if(st0010) { + if(coretype & FEAT_ST0010) { file_seek(0xc000); sector_remaining = 0; } diff --git a/src/smc.c b/src/smc.c index 0cf17b6..202c2ff 100644 --- a/src/smc.c +++ b/src/smc.c @@ -83,6 +83,7 @@ void smc_id(snes_romprops_t* props) { props->has_dspx = 0; props->has_st0010 = 0; + props->has_cx4 = 0; props->fpga_features = 0; for(uint8_t num = 0; num < 6; num++) { if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t)) @@ -144,39 +145,44 @@ void smc_id(snes_romprops_t* props) { props->mapper_id = 0; if(header->map == 0x31 && (header->carttype == 0x03 || header->carttype == 0x05)) { props->has_dspx = 1; - props->necdsp_fw = DSPFW_1B; + props->dsp_fw = DSPFW_1B; props->fpga_features |= FEAT_DSPX; } break; case 0x20: /* LoROM */ props->mapper_id = 1; - if ((header->map == 0x20 && header->carttype == 0x03) || + if (header->map == 0x20 && header->carttype == 0xf3) { + props->has_cx4 = 1; + props->dsp_fw = CX4FW; + props->fpga_features |= FEAT_CX4; + } + else if ((header->map == 0x20 && header->carttype == 0x03) || (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) { props->has_dspx = 1; props->fpga_features |= FEAT_DSPX; // Pilotwings uses DSP1 instead of DSP1B if(!memcmp(header->name, "PILOTWINGS", 10)) { - props->necdsp_fw = DSPFW_1; + props->dsp_fw = DSPFW_1; } else { - props->necdsp_fw = DSPFW_1B; + props->dsp_fw = DSPFW_1B; } } else if (header->map == 0x20 && header->carttype == 0x05) { props->has_dspx = 1; - props->necdsp_fw = DSPFW_2; + props->dsp_fw = DSPFW_2; props->fpga_features |= FEAT_DSPX; } else if (header->map == 0x30 && header->carttype == 0x05 && header->licensee == 0xb2) { props->has_dspx = 1; - props->necdsp_fw = DSPFW_3; + props->dsp_fw = DSPFW_3; props->fpga_features |= FEAT_DSPX; } else if (header->map == 0x30 && header->carttype == 0x03) { props->has_dspx = 1; - props->necdsp_fw = DSPFW_4; + props->dsp_fw = DSPFW_4; props->fpga_features |= FEAT_DSPX; } else if (header->map == 0x30 && header->carttype == 0xf6 && header->romsize >= 0xa) { props->has_dspx = 1; props->has_st0010 = 1; - props->necdsp_fw = DSPFW_ST0010; + props->dsp_fw = DSPFW_ST0010; props->fpga_features |= FEAT_ST0010; header->ramsize = 2; } diff --git a/src/smc.h b/src/smc.h index 54062fe..561078f 100644 --- a/src/smc.h +++ b/src/smc.h @@ -33,6 +33,7 @@ #define DSPFW_4 ((const uint8_t*)"/sd2snes/dsp4.bin") #define DSPFW_1B ((const uint8_t*)"/sd2snes/dsp1b.bin") #define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin") +#define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin") typedef struct _snes_header { uint8_t maker[2]; /* 0xB0 */ @@ -60,10 +61,11 @@ typedef struct _snes_romprops { uint32_t expramsize_bytes; /* ExpRAM size in bytes */ uint32_t ramsize_bytes; /* CartRAM size in bytes */ uint32_t romsize_bytes; /* ROM size in bytes (rounded up) */ - const uint8_t* necdsp_fw; /* NEC DSP ROM filename */ + const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */ uint8_t has_dspx; /* DSP[1-4] presence flag */ uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/ uint8_t has_msu1; /* MSU1 presence flag */ + uint8_t has_cx4; /* CX4 presence flag */ uint8_t fpga_features; /* feature/peripheral enable bits*/ snes_header_t header; /* original header from ROM image */ } snes_romprops_t; diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index c897c80..2923d2b 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -16,55 +16,55 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -72,7 +72,7 @@ - + @@ -90,11 +90,11 @@ - + - + @@ -377,8 +377,8 @@ - - + + @@ -433,7 +433,7 @@ - + diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index 6d62b47..4eb055b 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -42,11 +42,12 @@ parameter BUSY_DMA = 2'b01; parameter BUSY_CPU = 2'b10; wire datram_enable = CS & (ADDR[11:0] < 12'hc00); -wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11000); -wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11000); +wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001); +wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001); wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); +wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4])); wire [7:0] DATRAM_DO; reg [7:0] MMIO_DOr; @@ -54,12 +55,15 @@ wire [7:0] MMIO_DO; wire [7:0] STATUS_DO; wire [7:0] VECTOR_DO; wire [7:0] GPR_DO; +wire [7:0] DEBUG_DO; +reg [7:0] DEBUG_DOr; assign DO = datram_enable ? DATRAM_DO : mmio_enable ? MMIO_DO : status_enable ? STATUS_DO : vector_enable ? VECTOR_DO : gpr_enable ? GPR_DO + : debug_enable ? DEBUG_DO : 8'h00; /* 0x1f40 - 0x1f52: MMIO @@ -87,7 +91,20 @@ wire [47:0] cpu_mul_result; reg [23:0] const [15:0]; reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number +reg [14:0] cache_pgmpage; +reg [14:0] cpu_cache_pgmpage; +reg cache_cachepage; +reg cpu_cache_cachepage; +reg cpu_cache_done; +reg [7:0] cpu_pc_stack [7:0]; +reg [7:0] cpu_page_stack; + initial begin + cache_pgmpage = 15'b0; + cpu_cache_pgmpage = 15'b0; + cache_cachepage = 1'b0; + cpu_cache_cachepage = 1'b0; + cpu_cache_done = 1'b0; cachetag[0] = 16'h0000; cachetag[1] = 16'h0000; cx4_busy = 3'b000; @@ -112,12 +129,22 @@ initial begin const[13] = 24'hfeffff; const[14] = 24'h000100; const[15] = 24'h00feff; + cpu_pc_stack[0] = 8'b0; + cpu_pc_stack[1] = 8'b0; + cpu_pc_stack[2] = 8'b0; + cpu_pc_stack[3] = 8'b0; + cpu_pc_stack[4] = 8'b0; + cpu_pc_stack[5] = 8'b0; + cpu_pc_stack[6] = 8'b0; + cpu_pc_stack[7] = 8'b0; + cpu_page_stack = 8'b0; end assign MMIO_DO = MMIO_DOr; assign VECTOR_DO = vector [ADDR[4:0]]; assign GPR_DO = gpr [ADDR[5:0]]; assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0}; +assign DEBUG_DO = DEBUG_DOr; reg [7:0] DIr; always @(posedge CLK) DIr <= DI; @@ -143,9 +170,11 @@ reg [23:0] cpu_idb; // tmp register for reg file read */ reg CACHE_TRIG_ENr; reg CACHE_TRIG_EN2r; +reg cpu_cache_en; initial begin CACHE_TRIG_ENr = 1'b0; CACHE_TRIG_EN2r = 1'b0; + cpu_cache_en = 1'b0; end always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr; wire CACHE_TRIG_EN = CACHE_TRIG_EN2r; @@ -156,11 +185,19 @@ wire DMA_TRIG_EN = DMA_TRIG_ENr; reg CACHE_BUS_RRQr; reg DMA_BUS_RRQr; +reg cpu_bus_rq; + initial begin CACHE_BUS_RRQr = 1'b0; DMA_BUS_RRQr = 1'b0; + cpu_bus_rq = 1'b0; end -assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr; + +assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq; + +reg cpu_page; +reg [14:0] cpu_p; +reg [7:0] cpu_pc; reg cpu_go_en_r; initial cpu_go_en_r = 1'b0; @@ -192,23 +229,31 @@ always @(posedge CLK) begin 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 - - 5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40 - 5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40 - 5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40 - 5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40 - 5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40 - 5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40 - - -// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40 -// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41 -// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42 -// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43 default: MMIO_DOr <= 8'hff; endcase end +always @(posedge CLK) begin + case(ADDR[3:0]) + 4'h0: DEBUG_DOr <= cachetag[0][15:8]; // 1f40 + 4'h1: DEBUG_DOr <= cachetag[0][7:0]; // 1f41 + 4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42 + 4'h3: DEBUG_DOr <= cachetag[1][7:0]; // 1f43 + 4'h4: DEBUG_DOr <= cpu_page; + 4'h5: DEBUG_DOr <= cpu_p; + 4'h6: DEBUG_DOr <= cpu_pc; + 4'h7: DEBUG_DOr <= cx4_busy; + 4'h8: DEBUG_DOr <= cpu_page_stack[0]; + 4'h9: DEBUG_DOr <= cpu_pc_stack[0]; + 4'ha: DEBUG_DOr <= cpu_page_stack[1]; + 4'hb: DEBUG_DOr <= cpu_pc_stack[1]; + 4'hc: DEBUG_DOr <= cpu_page_stack[2]; + 4'hd: DEBUG_DOr <= cpu_pc_stack[2]; + 4'he: DEBUG_DOr <= cpu_page_stack[3]; + 4'hf: DEBUG_DOr <= cpu_pc_stack[3]; + endcase +end + always @(posedge CLK) begin if(MMIO_WR_EN) begin case(ADDR[4:0]) @@ -272,10 +317,11 @@ reg [23:0] CACHE_SRC_ADDRr; wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]}; reg [23:0] DMA_SRC_ADDRr; wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]}; +wire [22:0] MAPPED_CPU_BUS_ADDR; assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR : cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR - : 24'h800000 /* XXX cx4_bus_addr */; + : MAPPED_CPU_BUS_ADDR; reg cx4_pgmrom_we; initial cx4_pgmrom_we = 1'b0; @@ -288,15 +334,24 @@ always @(posedge CLK) begin ST_CACHE_IDLE: begin if(CACHE_TRIG_EN & (~cachetag[cx4_mmio_cachepage][15] - | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) - begin + | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin CACHE_ST <= ST_CACHE_START; - end else CACHE_ST <= ST_CACHE_IDLE; + cache_pgmpage <= cx4_mmio_pgmpage; + cache_cachepage <= cx4_mmio_cachepage; + end else if(cpu_cache_en + & (~cachetag[~cpu_page][15] + | |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin + CACHE_ST <= ST_CACHE_START; + cache_pgmpage <= cpu_p; + cache_cachepage <= ~cpu_page; + cx4_busy[BUSY_CACHE] <= 1'b1; + end + else CACHE_ST <= ST_CACHE_IDLE; end ST_CACHE_START: begin cx4_busy[BUSY_CACHE] <= 1'b1; - CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0}; - cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0}; + CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cache_pgmpage, 9'b0}; + cx4_pgmrom_addr <= {cache_cachepage, 9'b0}; CACHE_ST <= ST_CACHE_WAIT; cache_count <= 10'b0; CACHE_BUS_RRQr <= 1'b1; @@ -315,7 +370,7 @@ always @(posedge CLK) begin cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; if(cache_count == 9'h1ff) begin cx4_busy[BUSY_CACHE] <= 1'b0; - cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage}; + cachetag[cache_cachepage] <= {1'b1,cache_pgmpage}; CACHE_ST <= ST_CACHE_IDLE; end else begin CACHE_BUS_RRQr <= 1'b1; @@ -334,7 +389,7 @@ reg [11:0] cx4_dma_datram_addr; reg [11:0] cx4_cpu_datram_addr; wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr; reg [23:0] cx4_cpu_datram_di; -wire [23:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di; +wire [7:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di; reg [15:0] dma_count; initial dma_count = 16'b0; @@ -380,10 +435,8 @@ end =========== CPU =========== ***************************/ reg [4:0] CPU_STATE; -reg cpu_page; -reg [7:0] cpu_pc; -reg [8:0] cpu_stack [7:0]; reg [2:0] cpu_sp; +initial cpu_sp = 3'b000; wire [15:0] cpu_op_w; reg [15:0] cpu_op; reg [23:0] cpu_a; @@ -391,17 +444,20 @@ reg [23:0] cpu_busdata; reg [23:0] cpu_romdata; reg [23:0] cpu_ramdata; reg [23:0] cpu_busaddr; +assign MAPPED_CPU_BUS_ADDR = {cpu_busaddr[23:16], cpu_busaddr[14:0]}; reg [23:0] cpu_romaddr; reg [23:0] cpu_ramaddr; reg [23:0] cpu_acch; reg [23:0] cpu_accl; reg [23:0] cpu_mul_src; +reg [24:0] cpu_alu_res; +reg [23:0] cpu_dummy; +reg [23:0] cpu_tmp; reg [23:0] cpu_sa; // tmp register for shifted accumulator reg fl_n; reg fl_z; reg fl_c; -reg [15:0] cpu_p; wire [9:0] cx4_datrom_addr = cpu_a[9:0]; wire [23:0] cx4_datrom_do; @@ -413,49 +469,63 @@ parameter ST_CPU_1 = 5'b00100; parameter ST_CPU_2 = 5'b01000; parameter ST_CPU_3 = 5'b10000; -initial CPU_STATE <= ST_CPU_IDLE; +initial CPU_STATE = ST_CPU_IDLE; -parameter OP_NOP = 4'b0000; -parameter OP_JP = 4'b0001; -parameter OP_SKIP = 4'b0010; -parameter OP_RT = 4'b0011; -parameter OP_LD = 4'b0100; -parameter OP_ST = 4'b0101; -parameter OP_SWP = 4'b0110; -parameter OP_RDROM = 4'b0111; -parameter OP_RDRAM = 4'b1000; -parameter OP_WRRAM = 4'b1001; -parameter OP_ALU = 4'b1010; -parameter OP_MUL = 4'b1011; -parameter OP_WAI = 4'b1100; -parameter OP_BUS = 4'b1101; -parameter OP_HLT = 4'b1110; +parameter OP_NOP = 5'b00000; +parameter OP_JP = 5'b00001; +parameter OP_SKIP = 5'b00010; +parameter OP_RT = 5'b00011; +parameter OP_LD = 5'b00100; +parameter OP_ST = 5'b00101; +parameter OP_SWP = 5'b00110; +parameter OP_RDROM = 5'b00111; +parameter OP_RDRAM = 5'b01000; +parameter OP_WRRAM = 5'b01001; +parameter OP_ALU = 5'b01010; +parameter OP_MUL = 5'b01011; +parameter OP_WAI = 5'b01100; +parameter OP_BUS = 5'b01101; +parameter OP_CMP = 5'b01110; +parameter OP_SEX = 5'b01111; +parameter OP_HLT = 5'b10000; wire [6:0] op_id = cpu_op_w[15:10]; reg [7:0] op_param; -reg [3:0] op; +reg [4:0] op; reg [1:0] op_sa; reg op_imm; reg op_p; reg op_call; reg op_jump; reg condtrue; -reg cpu_bus_rq; + +/* XXX DEBUG */ +reg [23:0] dbg_cnt; +initial dbg_cnt = 24'b0; +always @(posedge CLK) dbg_cnt <= dbg_cnt + 1; +wire step_enable = 1'b1; always @(posedge CLK) begin + if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1; + else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0; +end + +always @(posedge CLK) begin +if(step_enable | cpu_go_en_r) begin case(CPU_STATE) ST_CPU_IDLE: begin if(cpu_go_en_r) begin cpu_pc <= cx4_mmio_pc; + cpu_page <= cx4_mmio_cachepage; + cpu_p <= cx4_mmio_pgmpage; op <= OP_NOP; CPU_STATE <= ST_CPU_2; - cx4_busy[BUSY_CPU] <= 1'b1; end else CPU_STATE <= ST_CPU_IDLE; end ST_CPU_0: begin // Phase 0: + cpu_cache_en <= 1'b0; if(op == OP_HLT) begin - cx4_busy[BUSY_CPU] <= 1'b0; CPU_STATE <= ST_CPU_IDLE; end else CPU_STATE <= ST_CPU_1; @@ -475,7 +545,7 @@ always @(posedge CLK) begin 2'b11: condtrue <= (fl_n == cpu_op[0]); endcase end - OP_LD, OP_SWP, OP_ALU, OP_MUL: begin + OP_LD, OP_ALU, OP_MUL, OP_CMP, OP_SEX: begin if(op_imm) cpu_idb <= {16'b0, op_param}; else casex(op_param) 8'h00: cpu_idb <= cpu_a; @@ -492,7 +562,7 @@ always @(posedge CLK) begin gpr[op_param[3:0]*3]}; default: cpu_idb <= 24'b0; endcase - if(op==OP_ALU) begin + if(op==OP_ALU || op==OP_CMP) begin case(op_sa) 2'b00: cpu_sa <= cpu_a; 2'b01: cpu_sa <= cpu_a << 1; @@ -504,8 +574,26 @@ always @(posedge CLK) begin OP_ST: begin cpu_idb <= cpu_a; end + OP_SWP: begin + cpu_idb <= cpu_a; + casex(op_param) + 8'h00: cpu_tmp <= cpu_a; + 8'h01: cpu_tmp <= cpu_acch; + 8'h02: cpu_tmp <= cpu_accl; + 8'h03: cpu_tmp <= cpu_busdata; + 8'h08: cpu_tmp <= cpu_romdata; + 8'h0c: cpu_tmp <= cpu_ramdata; + 8'h13: cpu_tmp <= cpu_busaddr; + 8'h1c: cpu_tmp <= cpu_ramaddr; + 8'h5x: cpu_tmp <= const[op_param[3:0]]; + 8'h6x: cpu_tmp <= {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]}; + default: cpu_tmp <= 24'b0; + endcase + end OP_RDRAM, OP_WRRAM: begin - if(op_imm) cpu_ramaddr <= {16'b0, op_param}; + if(op_imm) cx4_cpu_datram_addr <= {16'b0, op_param} + cpu_ramaddr; else casex(op_param) 8'h00: cx4_cpu_datram_addr <= cpu_a; 8'h01: cx4_cpu_datram_addr <= cpu_acch; @@ -522,32 +610,39 @@ always @(posedge CLK) begin default: cx4_cpu_datram_addr <= 24'b0; endcase end + OP_BUS: cpu_bus_rq <= 1'b1; endcase end ST_CPU_1: begin CPU_STATE <= ST_CPU_2; case(op) OP_JP: begin - if(condtrue) begin - if(op_call) begin - cpu_stack[cpu_sp] <= cpu_pc + 1; - cpu_sp <= cpu_sp + 1; - end - cpu_pc <= op_param; + if(!cx4_busy[BUSY_CACHE]) begin + if(condtrue) begin + if(op_call) begin + cpu_page_stack[cpu_sp] <= cpu_page; + cpu_pc_stack[cpu_sp] <= cpu_pc + 1; + cpu_sp <= cpu_sp + 1; + end + cpu_pc <= op_param; + cpu_page <= cpu_page ^ op_p; + end else cpu_pc <= cpu_pc + 1; end end OP_SKIP: begin - if(condtrue) begin - cpu_pc <= cpu_pc + 2; - end + if(condtrue) cpu_pc <= cpu_pc + 2; + else cpu_pc <= cpu_pc + 1; end OP_RT: begin - cpu_pc <= cpu_stack[cpu_sp - 1]; + cpu_page <= cpu_page_stack[cpu_sp - 1]; + cpu_pc <= cpu_pc_stack[cpu_sp - 1]; cpu_sp <= cpu_sp - 1; end - OP_LD, OP_ST, OP_SWP, OP_RDROM, OP_RDRAM, OP_WRRAM, OP_ALU, OP_MUL, OP_BUS: - cpu_pc <= cpu_pc + 1; OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1; + OP_BUS: begin + cpu_bus_rq <= 1'b0; + cpu_pc <= cpu_pc + 1; + end default: cpu_pc <= cpu_pc + 1; endcase end @@ -559,56 +654,101 @@ always @(posedge CLK) begin 4'b0x00: cpu_a <= cpu_idb; 4'b0x11: cpu_p <= cpu_idb; 4'b1100: cpu_p[7:0] <= op_param; - 4'b1101: cpu_p[15:8] <= op_param; + 4'b1101: cpu_p[14:8] <= op_param; endcase end - OP_ST: begin - casex(op_param) - 8'h00: cpu_a <= cpu_idb; + OP_ST, OP_SWP: begin + casex(op_param) +// 8'h00: cpu_a <= cpu_idb; 8'h01: cpu_acch <= cpu_idb; 8'h02: cpu_accl <= cpu_idb; - 8'h03: cpu_busdata <= cpu_idb; +// 8'h03: cpu_busdata <= cpu_idb; 8'h08: cpu_romdata <= cpu_idb; 8'h0c: cpu_ramdata <= cpu_idb; 8'h13: cpu_busaddr <= cpu_idb; 8'h1c: cpu_ramaddr <= cpu_idb; endcase - end - OP_SWP: begin - casex(op_param) - 8'h00: cpu_a <= cpu_a; - 8'h01: cpu_acch <= cpu_a; - 8'h02: cpu_accl <= cpu_a; - 8'h03: cpu_busdata <= cpu_a; - 8'h08: cpu_romdata <= cpu_a; - 8'h0c: cpu_ramdata <= cpu_a; - 8'h13: cpu_busaddr <= cpu_a; - 8'h1c: cpu_ramaddr <= cpu_a; - endcase + if(op==OP_SWP) cpu_a <= cpu_tmp; end OP_RDROM: cpu_romdata <= cx4_datrom_do; - OP_RDRAM: cpu_ramdata <= cx4_datram_do; + OP_RDRAM: begin + case(cpu_op[9:8]) + 2'b00: cpu_ramdata[7:0] <= cx4_datram_do; + 2'b01: cpu_ramdata[15:8] <= cx4_datram_do; + 2'b10: cpu_ramdata[23:16] <= cx4_datram_do; + endcase + end OP_WRRAM: begin case(cpu_op[9:8]) - 2'b00: cx4_cpu_datram_di[7:0] <= cpu_ramdata[7:0]; - 2'b01: cx4_cpu_datram_di[15:8] <= cpu_ramdata[15:8]; - 2'b10: cx4_cpu_datram_di[23:16] <= cpu_ramdata[23:16]; + 2'b00: cx4_cpu_datram_di <= cpu_ramdata[7:0]; + 2'b01: cx4_cpu_datram_di <= cpu_ramdata[15:8]; + 2'b10: cx4_cpu_datram_di <= cpu_ramdata[23:16]; endcase cx4_cpu_datram_we <= 1'b1; end - OP_ALU: begin - /* XXX TODO FUCK YEAH ALU */ + OP_CMP: begin + case(cpu_op[15:11]) + 5'b01001: cpu_alu_res <= cpu_idb - cpu_sa; + 5'b01010: cpu_alu_res <= cpu_sa - cpu_idb; + endcase + end + OP_SEX: begin + case(cpu_op[9:8]) + 2'b01: cpu_alu_res <= {{16{cpu_idb[7]}}, cpu_idb[7:0]}; + 2'b10: cpu_alu_res <= {{8{cpu_idb[15]}}, cpu_idb[15:0]}; + endcase + end + OP_ALU: begin + case(cpu_op[15:11]) + 5'b10000: cpu_alu_res <= cpu_sa + cpu_idb; + 5'b10001: cpu_alu_res <= cpu_idb - cpu_sa; + 5'b10010: cpu_alu_res <= cpu_sa - cpu_idb; + 5'b10101: cpu_alu_res <= cpu_sa ^ cpu_idb; + 5'b10110: cpu_alu_res <= cpu_sa & cpu_idb; + 5'b10111: cpu_alu_res <= cpu_sa | cpu_idb; + 5'b11000: cpu_alu_res <= cpu_a >> cpu_idb; + 5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb; + 5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb; + 5'b11011: cpu_alu_res <= cpu_a << cpu_idb; + endcase end - OP_BUS: cpu_bus_rq <= 1'b1; endcase end ST_CPU_3: begin CPU_STATE <= ST_CPU_0; case(op) - OP_SWP: cpu_a <= cpu_idb; + OP_LD: begin + casex(cpu_op[11:8]) + 4'b0x11: cpu_cache_en <= 1'b1; + 4'b1100: cpu_cache_en <= 1'b1; + endcase + end + OP_BUS: cpu_busaddr <= cpu_busaddr + 1; OP_WRRAM: cx4_cpu_datram_we <= 1'b0; + OP_CMP: begin + fl_n <= cpu_alu_res[23]; + fl_z <= cpu_alu_res[23:0] == 24'b0; + fl_c <= ~cpu_alu_res[24]; + end + OP_SEX: cpu_a <= cpu_alu_res[23:0]; OP_ALU: begin - /* XXX TODO FUCKING FLAGS */ + cpu_a <= cpu_alu_res[23:0]; + case(cpu_op[15:11]) + 5'b10000: begin + fl_n <= cpu_alu_res[23]; + fl_z <= cpu_alu_res[23:0] == 24'b0; + fl_c <= cpu_alu_res[24]; + end + 5'b10001, 5'b10010: begin + fl_n <= cpu_alu_res[23]; + fl_z <= cpu_alu_res[23:0] == 24'b0; + fl_c <= ~cpu_alu_res[24]; + end + default: begin + fl_n <= cpu_alu_res[23]; + fl_z <= cpu_alu_res[23:0] == 24'b0; + end + endcase end OP_MUL: begin cpu_acch <= cpu_mul_result[47:24]; @@ -616,7 +756,6 @@ always @(posedge CLK) begin fl_z <= (cpu_mul_result == 48'b0); fl_n <= cpu_mul_result[47]; end - OP_BUS: cpu_bus_rq <= 1'b0; endcase cpu_op <= cpu_op_w; casex(cpu_op_w[15:11]) @@ -636,9 +775,9 @@ always @(posedge CLK) begin 5'b01101: op <= OP_RDRAM; 5'b11101: op <= OP_WRRAM; - 5'b01001: op <= OP_ALU; - 5'b01010: op <= OP_ALU; - 5'b01011: op <= OP_ALU; + 5'b01001: op <= OP_CMP; + 5'b01010: op <= OP_CMP; + 5'b01011: op <= OP_SEX; 5'b10000: op <= OP_ALU; 5'b10001: op <= OP_ALU; 5'b10010: op <= OP_ALU; @@ -659,22 +798,45 @@ always @(posedge CLK) begin op_imm <= cpu_op_w[10]; op_p <= cpu_op_w[9]; op_call <= cpu_op_w[13]; + op_param <= cpu_op_w[7:0]; + op_sa <= cpu_op_w[9:8]; end endcase end +end + +reg[2:0] BUSRD_STATE; +parameter ST_BUSRD_IDLE = 2'b01; +parameter ST_BUSRD_WAIT = 2'b10; +initial BUSRD_STATE = ST_BUSRD_IDLE; + +always @(posedge CLK) begin + if(CPU_STATE == ST_CPU_2 + && (op == OP_ST || op == OP_SWP) + && op_param == 8'h03) + cpu_busdata <= cpu_idb; + else begin + case(BUSRD_STATE) + ST_BUSRD_IDLE: begin + if(cpu_bus_rq) begin + BUSRD_STATE <= ST_BUSRD_WAIT; + end + end + ST_BUSRD_WAIT: begin + if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE; + else BUSRD_STATE <= ST_BUSRD_WAIT; + if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI; + else cpu_busdata <= 8'h00; + end + endcase + end +end // gpr write, either by CPU or by MMIO always @(posedge CLK) begin if(CPU_STATE == ST_CPU_2 - && (op == OP_SWP) - && (op_param[7:4] == 8'h6)) begin - gpr[op_param[3:0]*3+2] <= cpu_a[23:16]; - gpr[op_param[3:0]*3+1] <= cpu_a[15:8]; - gpr[op_param[3:0]*3] <= cpu_a[7:0]; - end - else if(CPU_STATE == ST_CPU_2 - && (op == OP_ST) - && (op_param[7:4] == 8'h6)) begin + && (op == OP_ST || op == OP_SWP) + && (op_param[7:4] == 4'h6)) begin gpr[op_param[3:0]*3+2] <= cpu_idb[23:16]; gpr[op_param[3:0]*3+1] <= cpu_idb[15:8]; gpr[op_param[3:0]*3] <= cpu_idb[7:0]; @@ -714,7 +876,7 @@ cx4_pgmrom cx4_pgmrom ( .addra(cx4_pgmrom_addr), // input [9 : 0] addra .dina(BUS_DI), // input [7 : 0] dina .clkb(CLK), // input clkb - .addrb(cpu_pc), // input [8 : 0] addrb + .addrb({cpu_page,cpu_pc}), // input [8 : 0] addrb .doutb(cpu_op_w) // output [15 : 0] doutb ); diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v index 32e9bad..ebb89bc 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v @@ -7,7 +7,7 @@ // \ \ \/ Version: O.61xd // \ \ Application: netgen // / / Filename: cx4_mul.v -// /___/ /\ Timestamp: Fri Oct 21 22:38:27 2011 +// /___/ /\ Timestamp: Tue Oct 25 00:04:23 2011 // \ \ / \ // \___\/\___\ // @@ -399,6 +399,54 @@ module cx4_mul ( wire sig00000162; wire sig00000163; wire sig00000164; + wire sig00000165; + wire sig00000166; + wire sig00000167; + wire sig00000168; + wire sig00000169; + wire sig0000016a; + wire sig0000016b; + wire sig0000016c; + wire sig0000016d; + wire sig0000016e; + wire sig0000016f; + wire sig00000170; + wire sig00000171; + wire sig00000172; + wire sig00000173; + wire sig00000174; + wire sig00000175; + wire sig00000176; + wire sig00000177; + wire sig00000178; + wire sig00000179; + wire sig0000017a; + wire sig0000017b; + wire sig0000017c; + wire sig0000017d; + wire sig0000017e; + wire sig0000017f; + wire sig00000180; + wire sig00000181; + wire sig00000182; + wire sig00000183; + wire sig00000184; + wire sig00000185; + wire sig00000186; + wire sig00000187; + wire sig00000188; + wire sig00000189; + wire sig0000018a; + wire sig0000018b; + wire sig0000018c; + wire sig0000018d; + wire sig0000018e; + wire sig0000018f; + wire sig00000190; + wire sig00000191; + wire sig00000192; + wire sig00000193; + wire sig00000194; wire \NLW_blk00000003_P<35>_UNCONNECTED ; wire \NLW_blk00000003_P<34>_UNCONNECTED ; wire \NLW_blk00000003_P<33>_UNCONNECTED ; @@ -447,15 +495,15 @@ module cx4_mul ( wire \NLW_blk00000005_P<24>_UNCONNECTED ; wire \NLW_blk00000006_P<35>_UNCONNECTED ; GND blk00000001 ( - .G(sig00000001) + .G(sig00000012) ); VCC blk00000002 ( - .P(sig00000002) + .P(sig00000013) ); MULT18X18S blk00000003 ( .C(clk), - .CE(sig00000002), - .R(sig00000001), + .CE(sig00000013), + .R(sig00000012), .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , @@ -463,1638 +511,1638 @@ module cx4_mul ( \NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , \NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , \NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , -\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, -sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1}) +\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000f6, sig000000f5, sig000000f4, +sig000000f3, sig000000ff, sig000000fe, sig000000fd, sig000000fc, sig000000fb, sig000000fa, sig000000f9, sig000000f8, sig000000f7, sig000000f2}) ); MULT18X18S blk00000004 ( .C(clk), - .CE(sig00000002), - .R(sig00000001), + .CE(sig00000013), + .R(sig00000012), .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), - .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , \NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , \NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , -\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, -sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, -sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9}) +\NLW_blk00000004_P<24>_UNCONNECTED , sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e4, sig000000e3, sig000000e2, sig000000e1, +sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, sig000000db, sig000000f1, sig000000f0, sig000000ef, sig000000ee, sig000000ed, +sig000000ec, sig000000eb, sig000000ea, sig000000e5, sig000000da}) ); MULT18X18S blk00000005 ( .C(clk), - .CE(sig00000002), - .R(sig00000001), - .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .CE(sig00000013), + .R(sig00000012), + .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , \NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , \NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , -\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, -sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, -sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1}) +\NLW_blk00000005_P<24>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf, sig000000ce, sig000000cc, sig000000cb, sig000000ca, sig000000c9, +sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, sig000000c3, sig000000d9, sig000000d8, sig000000d7, sig000000d6, sig000000d5, +sig000000d4, sig000000d3, sig000000d2, sig000000cd, sig000000c2}) ); MULT18X18S blk00000006 ( .C(clk), - .CE(sig00000002), - .R(sig00000001), - .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), - .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), - .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, -sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, -sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, -sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) + .CE(sig00000013), + .R(sig00000012), + .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000ba, sig000000b9, sig000000b8, sig000000b7, sig000000b6, sig000000b4, sig000000b3, sig000000b2, +sig000000b1, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, sig000000ab, sig000000a9, sig000000a8, sig000000a7, sig000000a6, +sig000000a5, sig000000a4, sig000000a3, sig000000a2, sig000000a1, sig000000a0, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, +sig000000bc, sig000000bb, sig000000b5, sig000000aa, sig0000009f}) ); XORCY blk00000007 ( - .CI(sig00000065), - .LI(sig00000086), - .O(p[47]) + .CI(sig00000076), + .LI(sig00000097), + .O(sig0000018f) ); LUT2 #( .INIT ( 4'h6 )) blk00000008 ( - .I0(sig0000014e), - .I1(sig0000015b), - .O(sig00000086) + .I0(sig0000016c), + .I1(sig0000015f), + .O(sig00000097) ); MUXCY blk00000009 ( + .CI(sig00000075), + .DI(sig0000015f), + .S(sig00000096), + .O(sig00000076) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000a ( + .I0(sig0000016c), + .I1(sig0000015f), + .O(sig00000096) + ); + MUXCY blk0000000b ( + .CI(sig00000073), + .DI(sig0000015f), + .S(sig00000095), + .O(sig00000075) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000c ( + .I0(sig0000016c), + .I1(sig0000015f), + .O(sig00000095) + ); + XORCY blk0000000d ( + .CI(sig00000072), + .LI(sig00000093), + .O(sig0000018b) + ); + MUXCY blk0000000e ( + .CI(sig00000072), + .DI(sig0000015f), + .S(sig00000093), + .O(sig00000073) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000f ( + .I0(sig0000016b), + .I1(sig0000015f), + .O(sig00000093) + ); + XORCY blk00000010 ( + .CI(sig00000071), + .LI(sig00000092), + .O(sig0000018a) + ); + MUXCY blk00000011 ( + .CI(sig00000071), + .DI(sig0000015f), + .S(sig00000092), + .O(sig00000072) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000012 ( + .I0(sig0000016a), + .I1(sig0000015f), + .O(sig00000092) + ); + XORCY blk00000013 ( + .CI(sig00000070), + .LI(sig00000091), + .O(sig00000189) + ); + MUXCY blk00000014 ( + .CI(sig00000070), + .DI(sig0000015f), + .S(sig00000091), + .O(sig00000071) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000015 ( + .I0(sig00000169), + .I1(sig0000015f), + .O(sig00000091) + ); + XORCY blk00000016 ( + .CI(sig0000006f), + .LI(sig00000090), + .O(sig00000188) + ); + MUXCY blk00000017 ( + .CI(sig0000006f), + .DI(sig0000015f), + .S(sig00000090), + .O(sig00000070) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000018 ( + .I0(sig00000175), + .I1(sig0000015f), + .O(sig00000090) + ); + XORCY blk00000019 ( + .CI(sig0000006e), + .LI(sig0000008f), + .O(sig00000187) + ); + MUXCY blk0000001a ( + .CI(sig0000006e), + .DI(sig0000015f), + .S(sig0000008f), + .O(sig0000006f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001b ( + .I0(sig00000174), + .I1(sig0000015f), + .O(sig0000008f) + ); + XORCY blk0000001c ( + .CI(sig0000006d), + .LI(sig0000008e), + .O(sig00000186) + ); + MUXCY blk0000001d ( + .CI(sig0000006d), + .DI(sig0000015f), + .S(sig0000008e), + .O(sig0000006e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001e ( + .I0(sig00000173), + .I1(sig0000015f), + .O(sig0000008e) + ); + XORCY blk0000001f ( + .CI(sig0000006c), + .LI(sig0000008d), + .O(sig00000185) + ); + MUXCY blk00000020 ( + .CI(sig0000006c), + .DI(sig0000015f), + .S(sig0000008d), + .O(sig0000006d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000021 ( + .I0(sig00000172), + .I1(sig0000015f), + .O(sig0000008d) + ); + XORCY blk00000022 ( + .CI(sig0000006b), + .LI(sig0000008c), + .O(sig00000184) + ); + MUXCY blk00000023 ( + .CI(sig0000006b), + .DI(sig0000015e), + .S(sig0000008c), + .O(sig0000006c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000024 ( + .I0(sig00000171), + .I1(sig0000015e), + .O(sig0000008c) + ); + XORCY blk00000025 ( + .CI(sig0000006a), + .LI(sig0000008b), + .O(sig00000183) + ); + MUXCY blk00000026 ( + .CI(sig0000006a), + .DI(sig0000015d), + .S(sig0000008b), + .O(sig0000006b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000027 ( + .I0(sig00000170), + .I1(sig0000015d), + .O(sig0000008b) + ); + XORCY blk00000028 ( + .CI(sig00000068), + .LI(sig0000008a), + .O(sig00000182) + ); + MUXCY blk00000029 ( + .CI(sig00000068), + .DI(sig0000015c), + .S(sig0000008a), + .O(sig0000006a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002a ( + .I0(sig0000016f), + .I1(sig0000015c), + .O(sig0000008a) + ); + XORCY blk0000002b ( + .CI(sig00000067), + .LI(sig00000088), + .O(sig00000180) + ); + MUXCY blk0000002c ( + .CI(sig00000067), + .DI(sig0000015a), + .S(sig00000088), + .O(sig00000068) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002d ( + .I0(sig0000016e), + .I1(sig0000015a), + .O(sig00000088) + ); + XORCY blk0000002e ( + .CI(sig00000066), + .LI(sig00000087), + .O(sig0000017f) + ); + MUXCY blk0000002f ( + .CI(sig00000066), + .DI(sig00000159), + .S(sig00000087), + .O(sig00000067) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000030 ( + .I0(sig0000016d), + .I1(sig00000159), + .O(sig00000087) + ); + XORCY blk00000031 ( + .CI(sig00000065), + .LI(sig00000086), + .O(sig0000017e) + ); + MUXCY blk00000032 ( + .CI(sig00000065), + .DI(sig00000158), + .S(sig00000086), + .O(sig00000066) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000033 ( + .I0(sig00000168), + .I1(sig00000158), + .O(sig00000086) + ); + XORCY blk00000034 ( .CI(sig00000064), - .DI(sig0000014e), + .LI(sig00000085), + .O(sig0000017d) + ); + MUXCY blk00000035 ( + .CI(sig00000064), + .DI(sig00000157), .S(sig00000085), .O(sig00000065) ); LUT2 #( .INIT ( 4'h6 )) - blk0000000a ( - .I0(sig0000014e), - .I1(sig0000015b), + blk00000036 ( + .I0(sig00000132), + .I1(sig00000157), .O(sig00000085) ); - MUXCY blk0000000b ( - .CI(sig00000062), - .DI(sig0000014e), + XORCY blk00000037 ( + .CI(sig00000063), + .LI(sig00000084), + .O(sig0000017c) + ); + MUXCY blk00000038 ( + .CI(sig00000063), + .DI(sig00000156), .S(sig00000084), .O(sig00000064) ); LUT2 #( .INIT ( 4'h6 )) - blk0000000c ( - .I0(sig0000014e), - .I1(sig0000015b), + blk00000039 ( + .I0(sig00000131), + .I1(sig00000156), .O(sig00000084) ); - XORCY blk0000000d ( - .CI(sig00000061), - .LI(sig00000082), - .O(p[46]) - ); - MUXCY blk0000000e ( - .CI(sig00000061), - .DI(sig0000014e), - .S(sig00000082), - .O(sig00000062) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000000f ( - .I0(sig0000014e), - .I1(sig0000015a), - .O(sig00000082) - ); - XORCY blk00000010 ( - .CI(sig00000060), - .LI(sig00000081), - .O(p[45]) - ); - MUXCY blk00000011 ( - .CI(sig00000060), - .DI(sig0000014e), - .S(sig00000081), - .O(sig00000061) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000012 ( - .I0(sig0000014e), - .I1(sig00000159), - .O(sig00000081) - ); - XORCY blk00000013 ( - .CI(sig0000005f), - .LI(sig00000080), - .O(p[44]) - ); - MUXCY blk00000014 ( - .CI(sig0000005f), - .DI(sig0000014e), - .S(sig00000080), - .O(sig00000060) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000015 ( - .I0(sig0000014e), - .I1(sig00000158), - .O(sig00000080) - ); - XORCY blk00000016 ( - .CI(sig0000005e), - .LI(sig0000007f), - .O(p[43]) - ); - MUXCY blk00000017 ( - .CI(sig0000005e), - .DI(sig0000014e), - .S(sig0000007f), - .O(sig0000005f) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000018 ( - .I0(sig0000014e), - .I1(sig00000164), - .O(sig0000007f) - ); - XORCY blk00000019 ( - .CI(sig0000005d), - .LI(sig0000007e), - .O(p[42]) - ); - MUXCY blk0000001a ( - .CI(sig0000005d), - .DI(sig0000014e), - .S(sig0000007e), - .O(sig0000005e) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000001b ( - .I0(sig0000014e), - .I1(sig00000163), - .O(sig0000007e) - ); - XORCY blk0000001c ( - .CI(sig0000005c), - .LI(sig0000007d), - .O(p[41]) - ); - MUXCY blk0000001d ( - .CI(sig0000005c), - .DI(sig0000014e), - .S(sig0000007d), - .O(sig0000005d) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000001e ( - .I0(sig0000014e), - .I1(sig00000162), - .O(sig0000007d) - ); - XORCY blk0000001f ( - .CI(sig0000005b), - .LI(sig0000007c), - .O(p[40]) - ); - MUXCY blk00000020 ( - .CI(sig0000005b), - .DI(sig0000014e), - .S(sig0000007c), - .O(sig0000005c) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000021 ( - .I0(sig0000014e), - .I1(sig00000161), - .O(sig0000007c) - ); - XORCY blk00000022 ( - .CI(sig0000005a), - .LI(sig0000007b), - .O(p[39]) - ); - MUXCY blk00000023 ( - .CI(sig0000005a), - .DI(sig0000014d), - .S(sig0000007b), - .O(sig0000005b) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000024 ( - .I0(sig0000014d), - .I1(sig00000160), - .O(sig0000007b) - ); - XORCY blk00000025 ( - .CI(sig00000059), - .LI(sig0000007a), - .O(p[38]) - ); - MUXCY blk00000026 ( - .CI(sig00000059), - .DI(sig0000014c), - .S(sig0000007a), - .O(sig0000005a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000027 ( - .I0(sig0000014c), - .I1(sig0000015f), - .O(sig0000007a) - ); - XORCY blk00000028 ( - .CI(sig00000057), - .LI(sig00000079), - .O(p[37]) - ); - MUXCY blk00000029 ( - .CI(sig00000057), - .DI(sig0000014b), - .S(sig00000079), - .O(sig00000059) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000002a ( - .I0(sig0000014b), - .I1(sig0000015e), - .O(sig00000079) - ); - XORCY blk0000002b ( - .CI(sig00000056), - .LI(sig00000077), - .O(p[36]) - ); - MUXCY blk0000002c ( - .CI(sig00000056), - .DI(sig00000149), - .S(sig00000077), - .O(sig00000057) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000002d ( - .I0(sig00000149), - .I1(sig0000015d), - .O(sig00000077) - ); - XORCY blk0000002e ( - .CI(sig00000055), - .LI(sig00000076), - .O(p[35]) - ); - MUXCY blk0000002f ( - .CI(sig00000055), - .DI(sig00000148), - .S(sig00000076), - .O(sig00000056) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000030 ( - .I0(sig00000148), - .I1(sig0000015c), - .O(sig00000076) - ); - XORCY blk00000031 ( - .CI(sig00000054), - .LI(sig00000075), - .O(p[34]) - ); - MUXCY blk00000032 ( - .CI(sig00000054), - .DI(sig00000147), - .S(sig00000075), - .O(sig00000055) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000033 ( - .I0(sig00000147), - .I1(sig00000157), - .O(sig00000075) - ); - XORCY blk00000034 ( - .CI(sig00000053), - .LI(sig00000074), - .O(p[33]) - ); - MUXCY blk00000035 ( - .CI(sig00000053), - .DI(sig00000146), - .S(sig00000074), - .O(sig00000054) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000036 ( - .I0(sig00000146), - .I1(sig00000121), - .O(sig00000074) - ); - XORCY blk00000037 ( - .CI(sig00000052), - .LI(sig00000073), - .O(p[32]) - ); - MUXCY blk00000038 ( - .CI(sig00000052), - .DI(sig00000145), - .S(sig00000073), - .O(sig00000053) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000039 ( - .I0(sig00000145), - .I1(sig00000120), - .O(sig00000073) - ); XORCY blk0000003a ( - .CI(sig00000051), - .LI(sig00000072), - .O(p[31]) + .CI(sig00000062), + .LI(sig00000083), + .O(sig0000017b) ); MUXCY blk0000003b ( - .CI(sig00000051), - .DI(sig00000144), - .S(sig00000072), - .O(sig00000052) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000003c ( - .I0(sig00000144), - .I1(sig0000011f), - .O(sig00000072) - ); - XORCY blk0000003d ( - .CI(sig00000050), - .LI(sig00000071), - .O(p[30]) - ); - MUXCY blk0000003e ( - .CI(sig00000050), - .DI(sig00000143), - .S(sig00000071), - .O(sig00000051) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000003f ( - .I0(sig00000143), - .I1(sig0000011e), - .O(sig00000071) - ); - XORCY blk00000040 ( - .CI(sig0000004f), - .LI(sig00000070), - .O(p[29]) - ); - MUXCY blk00000041 ( - .CI(sig0000004f), - .DI(sig00000142), - .S(sig00000070), - .O(sig00000050) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000042 ( - .I0(sig00000142), - .I1(sig0000011d), - .O(sig00000070) - ); - XORCY blk00000043 ( - .CI(sig0000004e), - .LI(sig0000006f), - .O(p[28]) - ); - MUXCY blk00000044 ( - .CI(sig0000004e), - .DI(sig00000141), - .S(sig0000006f), - .O(sig0000004f) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000045 ( - .I0(sig00000141), - .I1(sig0000011c), - .O(sig0000006f) - ); - XORCY blk00000046 ( - .CI(sig0000006c), - .LI(sig0000006e), - .O(p[27]) - ); - MUXCY blk00000047 ( - .CI(sig0000006c), - .DI(sig00000140), - .S(sig0000006e), - .O(sig0000004e) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000048 ( - .I0(sig00000140), - .I1(sig0000011b), - .O(sig0000006e) - ); - XORCY blk00000049 ( - .CI(sig0000006b), - .LI(sig0000008d), - .O(p[26]) - ); - MUXCY blk0000004a ( - .CI(sig0000006b), - .DI(sig00000156), - .S(sig0000008d), - .O(sig0000006c) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000004b ( - .I0(sig00000156), - .I1(sig00000130), - .O(sig0000008d) - ); - XORCY blk0000004c ( - .CI(sig0000006a), - .LI(sig0000008c), - .O(p[25]) - ); - MUXCY blk0000004d ( - .CI(sig0000006a), + .CI(sig00000062), .DI(sig00000155), - .S(sig0000008c), - .O(sig0000006b) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000004e ( - .I0(sig00000155), - .I1(sig0000012f), - .O(sig0000008c) - ); - XORCY blk0000004f ( - .CI(sig00000069), - .LI(sig0000008b), - .O(p[24]) - ); - MUXCY blk00000050 ( - .CI(sig00000069), - .DI(sig00000154), - .S(sig0000008b), - .O(sig0000006a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000051 ( - .I0(sig00000154), - .I1(sig0000012e), - .O(sig0000008b) - ); - XORCY blk00000052 ( - .CI(sig00000068), - .LI(sig0000008a), - .O(p[23]) - ); - MUXCY blk00000053 ( - .CI(sig00000068), - .DI(sig00000153), - .S(sig0000008a), - .O(sig00000069) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000054 ( - .I0(sig00000153), - .I1(sig0000012d), - .O(sig0000008a) - ); - XORCY blk00000055 ( - .CI(sig00000067), - .LI(sig00000089), - .O(p[22]) - ); - MUXCY blk00000056 ( - .CI(sig00000067), - .DI(sig00000152), - .S(sig00000089), - .O(sig00000068) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000057 ( - .I0(sig00000152), - .I1(sig0000012c), - .O(sig00000089) - ); - XORCY blk00000058 ( - .CI(sig00000066), - .LI(sig00000088), - .O(p[21]) - ); - MUXCY blk00000059 ( - .CI(sig00000066), - .DI(sig00000151), - .S(sig00000088), - .O(sig00000067) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000005a ( - .I0(sig00000151), - .I1(sig0000012b), - .O(sig00000088) - ); - XORCY blk0000005b ( - .CI(sig00000063), - .LI(sig00000087), - .O(p[20]) - ); - MUXCY blk0000005c ( - .CI(sig00000063), - .DI(sig00000150), - .S(sig00000087), - .O(sig00000066) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000005d ( - .I0(sig00000150), - .I1(sig0000012a), - .O(sig00000087) - ); - XORCY blk0000005e ( - .CI(sig00000058), - .LI(sig00000083), - .O(p[19]) - ); - MUXCY blk0000005f ( - .CI(sig00000058), - .DI(sig0000014f), .S(sig00000083), .O(sig00000063) ); LUT2 #( .INIT ( 4'h6 )) - blk00000060 ( - .I0(sig0000014f), - .I1(sig00000125), + blk0000003c ( + .I0(sig00000130), + .I1(sig00000155), .O(sig00000083) ); + XORCY blk0000003d ( + .CI(sig00000061), + .LI(sig00000082), + .O(sig0000017a) + ); + MUXCY blk0000003e ( + .CI(sig00000061), + .DI(sig00000154), + .S(sig00000082), + .O(sig00000062) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000003f ( + .I0(sig0000012f), + .I1(sig00000154), + .O(sig00000082) + ); + XORCY blk00000040 ( + .CI(sig00000060), + .LI(sig00000081), + .O(sig00000179) + ); + MUXCY blk00000041 ( + .CI(sig00000060), + .DI(sig00000153), + .S(sig00000081), + .O(sig00000061) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000042 ( + .I0(sig0000012e), + .I1(sig00000153), + .O(sig00000081) + ); + XORCY blk00000043 ( + .CI(sig0000005f), + .LI(sig00000080), + .O(sig00000178) + ); + MUXCY blk00000044 ( + .CI(sig0000005f), + .DI(sig00000152), + .S(sig00000080), + .O(sig00000060) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000045 ( + .I0(sig0000012d), + .I1(sig00000152), + .O(sig00000080) + ); + XORCY blk00000046 ( + .CI(sig0000007d), + .LI(sig0000007f), + .O(sig00000177) + ); + MUXCY blk00000047 ( + .CI(sig0000007d), + .DI(sig00000151), + .S(sig0000007f), + .O(sig0000005f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000048 ( + .I0(sig0000012c), + .I1(sig00000151), + .O(sig0000007f) + ); + XORCY blk00000049 ( + .CI(sig0000007c), + .LI(sig0000009e), + .O(sig00000194) + ); + MUXCY blk0000004a ( + .CI(sig0000007c), + .DI(sig00000167), + .S(sig0000009e), + .O(sig0000007d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004b ( + .I0(sig00000141), + .I1(sig00000167), + .O(sig0000009e) + ); + XORCY blk0000004c ( + .CI(sig0000007b), + .LI(sig0000009d), + .O(sig00000193) + ); + MUXCY blk0000004d ( + .CI(sig0000007b), + .DI(sig00000166), + .S(sig0000009d), + .O(sig0000007c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004e ( + .I0(sig00000140), + .I1(sig00000166), + .O(sig0000009d) + ); + XORCY blk0000004f ( + .CI(sig0000007a), + .LI(sig0000009c), + .O(sig00000192) + ); + MUXCY blk00000050 ( + .CI(sig0000007a), + .DI(sig00000165), + .S(sig0000009c), + .O(sig0000007b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000051 ( + .I0(sig0000013f), + .I1(sig00000165), + .O(sig0000009c) + ); + XORCY blk00000052 ( + .CI(sig00000079), + .LI(sig0000009b), + .O(sig00000191) + ); + MUXCY blk00000053 ( + .CI(sig00000079), + .DI(sig00000164), + .S(sig0000009b), + .O(sig0000007a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000054 ( + .I0(sig0000013e), + .I1(sig00000164), + .O(sig0000009b) + ); + XORCY blk00000055 ( + .CI(sig00000078), + .LI(sig0000009a), + .O(sig00000190) + ); + MUXCY blk00000056 ( + .CI(sig00000078), + .DI(sig00000163), + .S(sig0000009a), + .O(sig00000079) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000057 ( + .I0(sig0000013d), + .I1(sig00000163), + .O(sig0000009a) + ); + XORCY blk00000058 ( + .CI(sig00000077), + .LI(sig00000099), + .O(sig0000018e) + ); + MUXCY blk00000059 ( + .CI(sig00000077), + .DI(sig00000162), + .S(sig00000099), + .O(sig00000078) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005a ( + .I0(sig0000013c), + .I1(sig00000162), + .O(sig00000099) + ); + XORCY blk0000005b ( + .CI(sig00000074), + .LI(sig00000098), + .O(sig0000018d) + ); + MUXCY blk0000005c ( + .CI(sig00000074), + .DI(sig00000161), + .S(sig00000098), + .O(sig00000077) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005d ( + .I0(sig0000013b), + .I1(sig00000161), + .O(sig00000098) + ); + XORCY blk0000005e ( + .CI(sig00000069), + .LI(sig00000094), + .O(sig0000018c) + ); + MUXCY blk0000005f ( + .CI(sig00000069), + .DI(sig00000160), + .S(sig00000094), + .O(sig00000074) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000060 ( + .I0(sig00000136), + .I1(sig00000160), + .O(sig00000094) + ); XORCY blk00000061 ( - .CI(sig0000004d), - .LI(sig00000078), - .O(p[18]) + .CI(sig0000005e), + .LI(sig00000089), + .O(sig00000181) ); MUXCY blk00000062 ( - .CI(sig0000004d), - .DI(sig0000014a), - .S(sig00000078), - .O(sig00000058) + .CI(sig0000005e), + .DI(sig0000015b), + .S(sig00000089), + .O(sig00000069) ); LUT2 #( .INIT ( 4'h6 )) blk00000063 ( - .I0(sig0000014a), - .I1(sig0000011a), - .O(sig00000078) + .I0(sig0000012b), + .I1(sig0000015b), + .O(sig00000089) ); XORCY blk00000064 ( - .CI(sig00000001), - .LI(sig0000006d), - .O(p[17]) + .CI(sig00000012), + .LI(sig0000007e), + .O(sig00000176) ); MUXCY blk00000065 ( - .CI(sig00000001), - .DI(sig0000013f), - .S(sig0000006d), - .O(sig0000004d) + .CI(sig00000012), + .DI(sig00000150), + .S(sig0000007e), + .O(sig0000005e) ); LUT2 #( .INIT ( 4'h6 )) blk00000066 ( - .I0(sig0000013f), - .I1(sig00000119), - .O(sig0000006d) + .I0(sig0000012a), + .I1(sig00000150), + .O(sig0000007e) ); XORCY blk00000067 ( - .CI(sig00000011), - .LI(sig00000029), - .O(sig0000014e) + .CI(sig00000022), + .LI(sig0000003a), + .O(sig0000015f) ); LUT2 #( .INIT ( 4'h6 )) blk00000068 ( - .I0(sig00000100), - .I1(sig00000111), - .O(sig00000029) + .I0(sig00000111), + .I1(sig00000122), + .O(sig0000003a) ); XORCY blk00000069 ( - .CI(sig00000010), - .LI(sig00000028), - .O(sig0000014d) + .CI(sig00000021), + .LI(sig00000039), + .O(sig0000015e) ); MUXCY blk0000006a ( - .CI(sig00000010), - .DI(sig00000100), - .S(sig00000028), - .O(sig00000011) + .CI(sig00000021), + .DI(sig00000111), + .S(sig00000039), + .O(sig00000022) ); LUT2 #( .INIT ( 4'h6 )) blk0000006b ( - .I0(sig00000100), - .I1(sig00000110), - .O(sig00000028) + .I0(sig00000121), + .I1(sig00000111), + .O(sig00000039) ); XORCY blk0000006c ( - .CI(sig0000000f), - .LI(sig00000027), - .O(sig0000014c) + .CI(sig00000020), + .LI(sig00000038), + .O(sig0000015d) ); MUXCY blk0000006d ( - .CI(sig0000000f), - .DI(sig00000100), - .S(sig00000027), - .O(sig00000010) + .CI(sig00000020), + .DI(sig00000111), + .S(sig00000038), + .O(sig00000021) ); LUT2 #( .INIT ( 4'h6 )) blk0000006e ( - .I0(sig00000100), - .I1(sig0000010f), - .O(sig00000027) + .I0(sig00000120), + .I1(sig00000111), + .O(sig00000038) ); XORCY blk0000006f ( - .CI(sig0000000d), - .LI(sig00000026), - .O(sig0000014b) + .CI(sig0000001e), + .LI(sig00000037), + .O(sig0000015c) ); MUXCY blk00000070 ( - .CI(sig0000000d), - .DI(sig00000100), - .S(sig00000026), - .O(sig0000000f) + .CI(sig0000001e), + .DI(sig00000111), + .S(sig00000037), + .O(sig00000020) ); LUT2 #( .INIT ( 4'h6 )) blk00000071 ( - .I0(sig00000100), - .I1(sig0000010e), - .O(sig00000026) + .I0(sig0000011f), + .I1(sig00000111), + .O(sig00000037) ); XORCY blk00000072 ( - .CI(sig0000000c), - .LI(sig00000024), - .O(sig00000149) + .CI(sig0000001d), + .LI(sig00000035), + .O(sig0000015a) ); MUXCY blk00000073 ( - .CI(sig0000000c), - .DI(sig00000100), - .S(sig00000024), - .O(sig0000000d) + .CI(sig0000001d), + .DI(sig00000111), + .S(sig00000035), + .O(sig0000001e) ); LUT2 #( .INIT ( 4'h6 )) blk00000074 ( - .I0(sig00000100), - .I1(sig0000010c), - .O(sig00000024) + .I0(sig0000011d), + .I1(sig00000111), + .O(sig00000035) ); XORCY blk00000075 ( - .CI(sig0000000b), - .LI(sig00000023), - .O(sig00000148) + .CI(sig0000001c), + .LI(sig00000034), + .O(sig00000159) ); MUXCY blk00000076 ( - .CI(sig0000000b), - .DI(sig00000100), - .S(sig00000023), - .O(sig0000000c) + .CI(sig0000001c), + .DI(sig00000111), + .S(sig00000034), + .O(sig0000001d) ); LUT2 #( .INIT ( 4'h6 )) blk00000077 ( - .I0(sig00000100), - .I1(sig0000010b), - .O(sig00000023) + .I0(sig0000011c), + .I1(sig00000111), + .O(sig00000034) ); XORCY blk00000078 ( - .CI(sig0000000a), - .LI(sig00000022), - .O(sig00000147) + .CI(sig0000001b), + .LI(sig00000033), + .O(sig00000158) ); MUXCY blk00000079 ( - .CI(sig0000000a), - .DI(sig00000100), - .S(sig00000022), - .O(sig0000000b) + .CI(sig0000001b), + .DI(sig00000111), + .S(sig00000033), + .O(sig0000001c) ); LUT2 #( .INIT ( 4'h6 )) blk0000007a ( - .I0(sig00000100), - .I1(sig0000010a), - .O(sig00000022) + .I0(sig0000011b), + .I1(sig00000111), + .O(sig00000033) ); XORCY blk0000007b ( - .CI(sig00000009), - .LI(sig00000021), - .O(sig00000146) + .CI(sig0000001a), + .LI(sig00000032), + .O(sig00000157) ); MUXCY blk0000007c ( - .CI(sig00000009), - .DI(sig000000ff), - .S(sig00000021), - .O(sig0000000a) + .CI(sig0000001a), + .DI(sig00000110), + .S(sig00000032), + .O(sig0000001b) ); LUT2 #( .INIT ( 4'h6 )) blk0000007d ( - .I0(sig000000ff), - .I1(sig00000109), - .O(sig00000021) + .I0(sig00000110), + .I1(sig0000011a), + .O(sig00000032) ); XORCY blk0000007e ( - .CI(sig00000008), - .LI(sig00000020), - .O(sig00000145) + .CI(sig00000019), + .LI(sig00000031), + .O(sig00000156) ); MUXCY blk0000007f ( - .CI(sig00000008), - .DI(sig000000fe), - .S(sig00000020), - .O(sig00000009) + .CI(sig00000019), + .DI(sig0000010f), + .S(sig00000031), + .O(sig0000001a) ); LUT2 #( .INIT ( 4'h6 )) blk00000080 ( - .I0(sig000000fe), - .I1(sig00000108), - .O(sig00000020) + .I0(sig0000010f), + .I1(sig00000119), + .O(sig00000031) ); XORCY blk00000081 ( - .CI(sig00000007), - .LI(sig0000001f), - .O(sig00000144) + .CI(sig00000018), + .LI(sig00000030), + .O(sig00000155) ); MUXCY blk00000082 ( - .CI(sig00000007), - .DI(sig000000fd), - .S(sig0000001f), - .O(sig00000008) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000083 ( - .I0(sig000000fd), - .I1(sig00000107), - .O(sig0000001f) - ); - XORCY blk00000084 ( - .CI(sig00000006), - .LI(sig0000001e), - .O(sig00000143) - ); - MUXCY blk00000085 ( - .CI(sig00000006), - .DI(sig000000fc), - .S(sig0000001e), - .O(sig00000007) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000086 ( - .I0(sig000000fc), - .I1(sig00000106), - .O(sig0000001e) - ); - XORCY blk00000087 ( - .CI(sig00000005), - .LI(sig0000001d), - .O(sig00000142) - ); - MUXCY blk00000088 ( - .CI(sig00000005), - .DI(sig000000fb), - .S(sig0000001d), - .O(sig00000006) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000089 ( - .I0(sig000000fb), - .I1(sig00000105), - .O(sig0000001d) - ); - XORCY blk0000008a ( - .CI(sig00000004), - .LI(sig0000001c), - .O(sig00000141) - ); - MUXCY blk0000008b ( - .CI(sig00000004), - .DI(sig000000fa), - .S(sig0000001c), - .O(sig00000005) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000008c ( - .I0(sig000000fa), - .I1(sig00000104), - .O(sig0000001c) - ); - XORCY blk0000008d ( - .CI(sig00000019), - .LI(sig0000001b), - .O(sig00000140) - ); - MUXCY blk0000008e ( - .CI(sig00000019), - .DI(sig000000f9), - .S(sig0000001b), - .O(sig00000004) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000008f ( - .I0(sig000000f9), - .I1(sig00000103), - .O(sig0000001b) - ); - XORCY blk00000090 ( .CI(sig00000018), - .LI(sig00000031), - .O(sig00000156) - ); - MUXCY blk00000091 ( - .CI(sig00000018), - .DI(sig000000f8), - .S(sig00000031), + .DI(sig0000010e), + .S(sig00000030), .O(sig00000019) ); LUT2 #( .INIT ( 4'h6 )) - blk00000092 ( - .I0(sig000000f8), + blk00000083 ( + .I0(sig0000010e), .I1(sig00000118), - .O(sig00000031) + .O(sig00000030) ); - XORCY blk00000093 ( + XORCY blk00000084 ( .CI(sig00000017), - .LI(sig00000030), - .O(sig00000155) + .LI(sig0000002f), + .O(sig00000154) ); - MUXCY blk00000094 ( + MUXCY blk00000085 ( .CI(sig00000017), - .DI(sig000000f7), - .S(sig00000030), + .DI(sig0000010d), + .S(sig0000002f), .O(sig00000018) ); LUT2 #( .INIT ( 4'h6 )) - blk00000095 ( - .I0(sig000000f7), + blk00000086 ( + .I0(sig0000010d), .I1(sig00000117), - .O(sig00000030) + .O(sig0000002f) ); - XORCY blk00000096 ( + XORCY blk00000087 ( .CI(sig00000016), - .LI(sig0000002f), - .O(sig00000154) + .LI(sig0000002e), + .O(sig00000153) ); - MUXCY blk00000097 ( + MUXCY blk00000088 ( .CI(sig00000016), - .DI(sig000000f6), - .S(sig0000002f), + .DI(sig0000010c), + .S(sig0000002e), .O(sig00000017) ); LUT2 #( .INIT ( 4'h6 )) - blk00000098 ( - .I0(sig000000f6), + blk00000089 ( + .I0(sig0000010c), .I1(sig00000116), - .O(sig0000002f) + .O(sig0000002e) ); - XORCY blk00000099 ( + XORCY blk0000008a ( .CI(sig00000015), - .LI(sig0000002e), - .O(sig00000153) + .LI(sig0000002d), + .O(sig00000152) ); - MUXCY blk0000009a ( + MUXCY blk0000008b ( .CI(sig00000015), - .DI(sig000000f5), - .S(sig0000002e), + .DI(sig0000010b), + .S(sig0000002d), .O(sig00000016) ); LUT2 #( .INIT ( 4'h6 )) - blk0000009b ( - .I0(sig000000f5), + blk0000008c ( + .I0(sig0000010b), .I1(sig00000115), - .O(sig0000002e) + .O(sig0000002d) ); - XORCY blk0000009c ( - .CI(sig00000014), - .LI(sig0000002d), - .O(sig00000152) + XORCY blk0000008d ( + .CI(sig0000002a), + .LI(sig0000002c), + .O(sig00000151) ); - MUXCY blk0000009d ( - .CI(sig00000014), - .DI(sig000000f4), - .S(sig0000002d), + MUXCY blk0000008e ( + .CI(sig0000002a), + .DI(sig0000010a), + .S(sig0000002c), .O(sig00000015) ); LUT2 #( .INIT ( 4'h6 )) - blk0000009e ( - .I0(sig000000f4), + blk0000008f ( + .I0(sig0000010a), .I1(sig00000114), - .O(sig0000002d) + .O(sig0000002c) + ); + XORCY blk00000090 ( + .CI(sig00000029), + .LI(sig00000042), + .O(sig00000167) + ); + MUXCY blk00000091 ( + .CI(sig00000029), + .DI(sig00000109), + .S(sig00000042), + .O(sig0000002a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000092 ( + .I0(sig00000109), + .I1(sig00000129), + .O(sig00000042) + ); + XORCY blk00000093 ( + .CI(sig00000028), + .LI(sig00000041), + .O(sig00000166) + ); + MUXCY blk00000094 ( + .CI(sig00000028), + .DI(sig00000108), + .S(sig00000041), + .O(sig00000029) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000095 ( + .I0(sig00000108), + .I1(sig00000128), + .O(sig00000041) + ); + XORCY blk00000096 ( + .CI(sig00000027), + .LI(sig00000040), + .O(sig00000165) + ); + MUXCY blk00000097 ( + .CI(sig00000027), + .DI(sig00000107), + .S(sig00000040), + .O(sig00000028) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000098 ( + .I0(sig00000107), + .I1(sig00000127), + .O(sig00000040) + ); + XORCY blk00000099 ( + .CI(sig00000026), + .LI(sig0000003f), + .O(sig00000164) + ); + MUXCY blk0000009a ( + .CI(sig00000026), + .DI(sig00000106), + .S(sig0000003f), + .O(sig00000027) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009b ( + .I0(sig00000106), + .I1(sig00000126), + .O(sig0000003f) + ); + XORCY blk0000009c ( + .CI(sig00000025), + .LI(sig0000003e), + .O(sig00000163) + ); + MUXCY blk0000009d ( + .CI(sig00000025), + .DI(sig00000105), + .S(sig0000003e), + .O(sig00000026) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009e ( + .I0(sig00000105), + .I1(sig00000125), + .O(sig0000003e) ); XORCY blk0000009f ( - .CI(sig00000013), - .LI(sig0000002c), - .O(sig00000151) + .CI(sig00000024), + .LI(sig0000003d), + .O(sig00000162) ); MUXCY blk000000a0 ( - .CI(sig00000013), - .DI(sig000000f3), - .S(sig0000002c), - .O(sig00000014) + .CI(sig00000024), + .DI(sig00000104), + .S(sig0000003d), + .O(sig00000025) ); LUT2 #( .INIT ( 4'h6 )) blk000000a1 ( - .I0(sig000000f3), - .I1(sig00000113), - .O(sig0000002c) + .I0(sig00000104), + .I1(sig00000124), + .O(sig0000003d) ); XORCY blk000000a2 ( - .CI(sig00000012), - .LI(sig0000002b), - .O(sig00000150) + .CI(sig00000023), + .LI(sig0000003c), + .O(sig00000161) ); MUXCY blk000000a3 ( - .CI(sig00000012), - .DI(sig000000f2), - .S(sig0000002b), - .O(sig00000013) + .CI(sig00000023), + .DI(sig00000103), + .S(sig0000003c), + .O(sig00000024) ); LUT2 #( .INIT ( 4'h6 )) blk000000a4 ( - .I0(sig000000f2), - .I1(sig00000112), - .O(sig0000002b) + .I0(sig00000103), + .I1(sig00000123), + .O(sig0000003c) ); XORCY blk000000a5 ( - .CI(sig0000000e), - .LI(sig0000002a), - .O(sig0000014f) + .CI(sig0000001f), + .LI(sig0000003b), + .O(sig00000160) ); MUXCY blk000000a6 ( - .CI(sig0000000e), - .DI(sig000000f1), - .S(sig0000002a), - .O(sig00000012) + .CI(sig0000001f), + .DI(sig00000102), + .S(sig0000003b), + .O(sig00000023) ); LUT2 #( .INIT ( 4'h6 )) blk000000a7 ( - .I0(sig000000f1), - .I1(sig0000010d), - .O(sig0000002a) + .I0(sig00000102), + .I1(sig0000011e), + .O(sig0000003b) ); XORCY blk000000a8 ( - .CI(sig00000003), - .LI(sig00000025), - .O(sig0000014a) + .CI(sig00000014), + .LI(sig00000036), + .O(sig0000015b) ); MUXCY blk000000a9 ( - .CI(sig00000003), - .DI(sig000000f0), - .S(sig00000025), - .O(sig0000000e) + .CI(sig00000014), + .DI(sig00000101), + .S(sig00000036), + .O(sig0000001f) ); LUT2 #( .INIT ( 4'h6 )) blk000000aa ( - .I0(sig000000f0), - .I1(sig00000102), - .O(sig00000025) + .I0(sig00000101), + .I1(sig00000113), + .O(sig00000036) ); XORCY blk000000ab ( - .CI(sig00000001), - .LI(sig0000001a), - .O(sig0000013f) + .CI(sig00000012), + .LI(sig0000002b), + .O(sig00000150) ); MUXCY blk000000ac ( - .CI(sig00000001), - .DI(sig000000ef), - .S(sig0000001a), - .O(sig00000003) + .CI(sig00000012), + .DI(sig00000100), + .S(sig0000002b), + .O(sig00000014) ); LUT2 #( .INIT ( 4'h6 )) blk000000ad ( - .I0(sig000000ef), - .I1(sig00000101), - .O(sig0000001a) + .I0(sig00000100), + .I1(sig00000112), + .O(sig0000002b) ); XORCY blk000000ae ( - .CI(sig00000035), - .LI(sig00000043), - .O(sig0000015b) + .CI(sig00000046), + .LI(sig00000054), + .O(sig0000016c) ); LUT2 #( .INIT ( 4'h6 )) blk000000af ( - .I0(sig00000129), - .I1(sig00000136), - .O(sig00000043) + .I0(sig0000013a), + .I1(sig00000147), + .O(sig00000054) ); XORCY blk000000b0 ( - .CI(sig00000034), - .LI(sig00000042), - .O(sig0000015a) + .CI(sig00000045), + .LI(sig00000053), + .O(sig0000016b) ); MUXCY blk000000b1 ( - .CI(sig00000034), - .DI(sig00000129), - .S(sig00000042), - .O(sig00000035) + .CI(sig00000045), + .DI(sig0000013a), + .S(sig00000053), + .O(sig00000046) ); LUT2 #( .INIT ( 4'h6 )) blk000000b2 ( - .I0(sig00000129), - .I1(sig00000135), - .O(sig00000042) + .I0(sig00000146), + .I1(sig0000013a), + .O(sig00000053) ); XORCY blk000000b3 ( - .CI(sig00000033), - .LI(sig00000041), - .O(sig00000159) + .CI(sig00000044), + .LI(sig00000052), + .O(sig0000016a) ); MUXCY blk000000b4 ( - .CI(sig00000033), - .DI(sig00000129), - .S(sig00000041), - .O(sig00000034) + .CI(sig00000044), + .DI(sig0000013a), + .S(sig00000052), + .O(sig00000045) ); LUT2 #( .INIT ( 4'h6 )) blk000000b5 ( - .I0(sig00000129), - .I1(sig00000134), - .O(sig00000041) + .I0(sig00000145), + .I1(sig0000013a), + .O(sig00000052) ); XORCY blk000000b6 ( - .CI(sig0000003e), - .LI(sig00000040), - .O(sig00000158) + .CI(sig0000004f), + .LI(sig00000051), + .O(sig00000169) ); MUXCY blk000000b7 ( - .CI(sig0000003e), - .DI(sig00000129), - .S(sig00000040), - .O(sig00000033) + .CI(sig0000004f), + .DI(sig0000013a), + .S(sig00000051), + .O(sig00000044) ); LUT2 #( .INIT ( 4'h6 )) blk000000b8 ( - .I0(sig00000129), - .I1(sig00000133), - .O(sig00000040) + .I0(sig00000144), + .I1(sig0000013a), + .O(sig00000051) ); XORCY blk000000b9 ( - .CI(sig0000003d), - .LI(sig0000004c), - .O(sig00000164) + .CI(sig0000004e), + .LI(sig0000005d), + .O(sig00000175) ); MUXCY blk000000ba ( - .CI(sig0000003d), - .DI(sig00000129), - .S(sig0000004c), - .O(sig0000003e) + .CI(sig0000004e), + .DI(sig0000013a), + .S(sig0000005d), + .O(sig0000004f) ); LUT2 #( .INIT ( 4'h6 )) blk000000bb ( - .I0(sig00000129), - .I1(sig0000013e), - .O(sig0000004c) + .I0(sig0000014f), + .I1(sig0000013a), + .O(sig0000005d) ); XORCY blk000000bc ( - .CI(sig0000003c), - .LI(sig0000004b), - .O(sig00000163) + .CI(sig0000004d), + .LI(sig0000005c), + .O(sig00000174) ); MUXCY blk000000bd ( - .CI(sig0000003c), - .DI(sig00000129), - .S(sig0000004b), - .O(sig0000003d) + .CI(sig0000004d), + .DI(sig0000013a), + .S(sig0000005c), + .O(sig0000004e) ); LUT2 #( .INIT ( 4'h6 )) blk000000be ( - .I0(sig00000129), - .I1(sig0000013d), - .O(sig0000004b) + .I0(sig0000014e), + .I1(sig0000013a), + .O(sig0000005c) ); XORCY blk000000bf ( - .CI(sig0000003b), - .LI(sig0000004a), - .O(sig00000162) + .CI(sig0000004c), + .LI(sig0000005b), + .O(sig00000173) ); MUXCY blk000000c0 ( - .CI(sig0000003b), - .DI(sig00000129), - .S(sig0000004a), - .O(sig0000003c) + .CI(sig0000004c), + .DI(sig0000013a), + .S(sig0000005b), + .O(sig0000004d) ); LUT2 #( .INIT ( 4'h6 )) blk000000c1 ( - .I0(sig00000129), - .I1(sig0000013c), - .O(sig0000004a) + .I0(sig0000014d), + .I1(sig0000013a), + .O(sig0000005b) ); XORCY blk000000c2 ( - .CI(sig0000003a), - .LI(sig00000049), - .O(sig00000161) + .CI(sig0000004b), + .LI(sig0000005a), + .O(sig00000172) ); MUXCY blk000000c3 ( - .CI(sig0000003a), - .DI(sig00000129), - .S(sig00000049), - .O(sig0000003b) + .CI(sig0000004b), + .DI(sig0000013a), + .S(sig0000005a), + .O(sig0000004c) ); LUT2 #( .INIT ( 4'h6 )) blk000000c4 ( - .I0(sig00000129), - .I1(sig0000013b), - .O(sig00000049) + .I0(sig0000014c), + .I1(sig0000013a), + .O(sig0000005a) ); XORCY blk000000c5 ( - .CI(sig00000039), - .LI(sig00000048), - .O(sig00000160) + .CI(sig0000004a), + .LI(sig00000059), + .O(sig00000171) ); MUXCY blk000000c6 ( - .CI(sig00000039), - .DI(sig00000128), - .S(sig00000048), - .O(sig0000003a) + .CI(sig0000004a), + .DI(sig00000139), + .S(sig00000059), + .O(sig0000004b) ); LUT2 #( .INIT ( 4'h6 )) blk000000c7 ( - .I0(sig00000128), - .I1(sig0000013a), - .O(sig00000048) + .I0(sig00000139), + .I1(sig0000014b), + .O(sig00000059) ); XORCY blk000000c8 ( - .CI(sig00000038), - .LI(sig00000047), - .O(sig0000015f) + .CI(sig00000049), + .LI(sig00000058), + .O(sig00000170) ); MUXCY blk000000c9 ( - .CI(sig00000038), - .DI(sig00000127), - .S(sig00000047), - .O(sig00000039) + .CI(sig00000049), + .DI(sig00000138), + .S(sig00000058), + .O(sig0000004a) ); LUT2 #( .INIT ( 4'h6 )) blk000000ca ( - .I0(sig00000127), - .I1(sig00000139), - .O(sig00000047) + .I0(sig00000138), + .I1(sig0000014a), + .O(sig00000058) ); XORCY blk000000cb ( - .CI(sig00000037), - .LI(sig00000046), - .O(sig0000015e) + .CI(sig00000048), + .LI(sig00000057), + .O(sig0000016f) ); MUXCY blk000000cc ( - .CI(sig00000037), - .DI(sig00000126), - .S(sig00000046), - .O(sig00000038) + .CI(sig00000048), + .DI(sig00000137), + .S(sig00000057), + .O(sig00000049) ); LUT2 #( .INIT ( 4'h6 )) blk000000cd ( - .I0(sig00000126), - .I1(sig00000138), - .O(sig00000046) + .I0(sig00000137), + .I1(sig00000149), + .O(sig00000057) ); XORCY blk000000ce ( - .CI(sig00000036), - .LI(sig00000045), - .O(sig0000015d) + .CI(sig00000047), + .LI(sig00000056), + .O(sig0000016e) ); MUXCY blk000000cf ( - .CI(sig00000036), - .DI(sig00000124), - .S(sig00000045), - .O(sig00000037) + .CI(sig00000047), + .DI(sig00000135), + .S(sig00000056), + .O(sig00000048) ); LUT2 #( .INIT ( 4'h6 )) blk000000d0 ( - .I0(sig00000124), - .I1(sig00000137), - .O(sig00000045) + .I0(sig00000135), + .I1(sig00000148), + .O(sig00000056) ); XORCY blk000000d1 ( - .CI(sig00000032), - .LI(sig00000044), - .O(sig0000015c) + .CI(sig00000043), + .LI(sig00000055), + .O(sig0000016d) ); MUXCY blk000000d2 ( - .CI(sig00000032), - .DI(sig00000123), - .S(sig00000044), - .O(sig00000036) + .CI(sig00000043), + .DI(sig00000134), + .S(sig00000055), + .O(sig00000047) ); LUT2 #( .INIT ( 4'h6 )) blk000000d3 ( - .I0(sig00000123), - .I1(sig00000132), - .O(sig00000044) + .I0(sig00000134), + .I1(sig00000143), + .O(sig00000055) ); XORCY blk000000d4 ( - .CI(sig00000001), - .LI(sig0000003f), - .O(sig00000157) + .CI(sig00000012), + .LI(sig00000050), + .O(sig00000168) ); MUXCY blk000000d5 ( - .CI(sig00000001), - .DI(sig00000122), - .S(sig0000003f), - .O(sig00000032) + .CI(sig00000012), + .DI(sig00000133), + .S(sig00000050), + .O(sig00000043) ); LUT2 #( .INIT ( 4'h6 )) blk000000d6 ( - .I0(sig00000122), - .I1(sig00000131), - .O(sig0000003f) + .I0(sig00000133), + .I1(sig00000142), + .O(sig00000050) ); FD #( .INIT ( 1'b0 )) blk000000d7 ( .C(clk), - .D(sig000000d8), - .Q(sig00000129) + .D(sig0000018f), + .Q(p[47]) ); FD #( .INIT ( 1'b0 )) blk000000d8 ( .C(clk), - .D(sig000000d7), - .Q(sig00000128) + .D(sig0000018b), + .Q(p[46]) ); FD #( .INIT ( 1'b0 )) blk000000d9 ( .C(clk), - .D(sig000000d6), - .Q(sig00000127) + .D(sig0000018a), + .Q(p[45]) ); FD #( .INIT ( 1'b0 )) blk000000da ( .C(clk), - .D(sig000000d5), - .Q(sig00000126) + .D(sig00000189), + .Q(p[44]) ); FD #( .INIT ( 1'b0 )) blk000000db ( .C(clk), - .D(sig000000d3), - .Q(sig00000124) + .D(sig00000188), + .Q(p[43]) ); FD #( .INIT ( 1'b0 )) blk000000dc ( .C(clk), - .D(sig000000d2), - .Q(sig00000123) + .D(sig00000187), + .Q(p[42]) ); FD #( .INIT ( 1'b0 )) blk000000dd ( .C(clk), - .D(sig000000d1), - .Q(sig00000122) + .D(sig00000186), + .Q(p[41]) ); FD #( .INIT ( 1'b0 )) blk000000de ( .C(clk), - .D(sig000000d0), - .Q(sig00000121) + .D(sig00000185), + .Q(p[40]) ); FD #( .INIT ( 1'b0 )) blk000000df ( .C(clk), - .D(sig000000cf), - .Q(sig00000120) + .D(sig00000184), + .Q(p[39]) ); FD #( .INIT ( 1'b0 )) blk000000e0 ( .C(clk), - .D(sig000000ce), - .Q(sig0000011f) + .D(sig00000183), + .Q(p[38]) ); FD #( .INIT ( 1'b0 )) blk000000e1 ( .C(clk), - .D(sig000000cd), - .Q(sig0000011e) + .D(sig00000182), + .Q(p[37]) ); FD #( .INIT ( 1'b0 )) blk000000e2 ( .C(clk), - .D(sig000000cc), - .Q(sig0000011d) + .D(sig00000180), + .Q(p[36]) ); FD #( .INIT ( 1'b0 )) blk000000e3 ( .C(clk), - .D(sig000000cb), - .Q(sig0000011c) + .D(sig0000017f), + .Q(p[35]) ); FD #( .INIT ( 1'b0 )) blk000000e4 ( .C(clk), - .D(sig000000ca), - .Q(sig0000011b) + .D(sig0000017e), + .Q(p[34]) ); FD #( .INIT ( 1'b0 )) blk000000e5 ( .C(clk), - .D(sig000000e0), - .Q(sig00000130) + .D(sig0000017d), + .Q(p[33]) ); FD #( .INIT ( 1'b0 )) blk000000e6 ( .C(clk), - .D(sig000000df), - .Q(sig0000012f) + .D(sig0000017c), + .Q(p[32]) ); FD #( .INIT ( 1'b0 )) blk000000e7 ( .C(clk), - .D(sig000000de), - .Q(sig0000012e) + .D(sig0000017b), + .Q(p[31]) ); FD #( .INIT ( 1'b0 )) blk000000e8 ( .C(clk), - .D(sig000000dd), - .Q(sig0000012d) + .D(sig0000017a), + .Q(p[30]) ); FD #( .INIT ( 1'b0 )) blk000000e9 ( .C(clk), - .D(sig000000dc), - .Q(sig0000012c) + .D(sig00000179), + .Q(p[29]) ); FD #( .INIT ( 1'b0 )) blk000000ea ( .C(clk), - .D(sig000000db), - .Q(sig0000012b) + .D(sig00000178), + .Q(p[28]) ); FD #( .INIT ( 1'b0 )) blk000000eb ( .C(clk), - .D(sig000000da), - .Q(sig0000012a) + .D(sig00000177), + .Q(p[27]) ); FD #( .INIT ( 1'b0 )) blk000000ec ( .C(clk), - .D(sig000000d9), - .Q(sig00000125) + .D(sig00000194), + .Q(p[26]) ); FD #( .INIT ( 1'b0 )) blk000000ed ( .C(clk), - .D(sig000000d4), - .Q(sig0000011a) + .D(sig00000193), + .Q(p[25]) ); FD #( .INIT ( 1'b0 )) blk000000ee ( .C(clk), - .D(sig000000c9), - .Q(sig00000119) + .D(sig00000192), + .Q(p[24]) ); FD #( .INIT ( 1'b0 )) blk000000ef ( .C(clk), - .D(sig000000c0), - .Q(sig00000111) + .D(sig00000191), + .Q(p[23]) ); FD #( .INIT ( 1'b0 )) blk000000f0 ( .C(clk), - .D(sig000000bf), - .Q(sig00000110) + .D(sig00000190), + .Q(p[22]) ); FD #( .INIT ( 1'b0 )) blk000000f1 ( .C(clk), - .D(sig000000be), - .Q(sig0000010f) + .D(sig0000018e), + .Q(p[21]) ); FD #( .INIT ( 1'b0 )) blk000000f2 ( .C(clk), - .D(sig000000bd), - .Q(sig0000010e) + .D(sig0000018d), + .Q(p[20]) ); FD #( .INIT ( 1'b0 )) blk000000f3 ( .C(clk), - .D(sig000000bb), - .Q(sig0000010c) + .D(sig0000018c), + .Q(p[19]) ); FD #( .INIT ( 1'b0 )) blk000000f4 ( .C(clk), - .D(sig000000ba), - .Q(sig0000010b) + .D(sig00000181), + .Q(p[18]) ); FD #( .INIT ( 1'b0 )) blk000000f5 ( .C(clk), - .D(sig000000b9), - .Q(sig0000010a) + .D(sig00000176), + .Q(p[17]) ); FD #( .INIT ( 1'b0 )) blk000000f6 ( .C(clk), - .D(sig000000b8), - .Q(sig00000109) + .D(sig000000f6), + .Q(sig00000147) ); FD #( .INIT ( 1'b0 )) blk000000f7 ( .C(clk), - .D(sig000000b7), - .Q(sig00000108) + .D(sig000000f5), + .Q(sig00000146) ); FD #( .INIT ( 1'b0 )) blk000000f8 ( .C(clk), - .D(sig000000b6), - .Q(sig00000107) + .D(sig000000f4), + .Q(sig00000145) ); FD #( .INIT ( 1'b0 )) blk000000f9 ( .C(clk), - .D(sig000000b5), - .Q(sig00000106) + .D(sig000000f3), + .Q(sig00000144) ); FD #( .INIT ( 1'b0 )) blk000000fa ( .C(clk), - .D(sig000000b4), - .Q(sig00000105) + .D(sig000000ff), + .Q(sig0000014f) ); FD #( .INIT ( 1'b0 )) blk000000fb ( .C(clk), - .D(sig000000b3), - .Q(sig00000104) + .D(sig000000fe), + .Q(sig0000014e) ); FD #( .INIT ( 1'b0 )) blk000000fc ( .C(clk), - .D(sig000000b2), - .Q(sig00000103) + .D(sig000000fd), + .Q(sig0000014d) ); FD #( .INIT ( 1'b0 )) blk000000fd ( .C(clk), - .D(sig000000c8), - .Q(sig00000118) + .D(sig000000fc), + .Q(sig0000014c) ); FD #( .INIT ( 1'b0 )) blk000000fe ( .C(clk), - .D(sig000000c7), - .Q(sig00000117) + .D(sig000000fb), + .Q(sig0000014b) ); FD #( .INIT ( 1'b0 )) blk000000ff ( .C(clk), - .D(sig000000c6), - .Q(sig00000116) + .D(sig000000fa), + .Q(sig0000014a) ); FD #( .INIT ( 1'b0 )) blk00000100 ( .C(clk), - .D(sig000000c5), - .Q(sig00000115) + .D(sig000000f9), + .Q(sig00000149) ); FD #( .INIT ( 1'b0 )) blk00000101 ( .C(clk), - .D(sig000000c4), - .Q(sig00000114) + .D(sig000000f8), + .Q(sig00000148) ); FD #( .INIT ( 1'b0 )) blk00000102 ( .C(clk), - .D(sig000000c3), - .Q(sig00000113) + .D(sig000000f7), + .Q(sig00000143) ); FD #( .INIT ( 1'b0 )) blk00000103 ( .C(clk), - .D(sig000000c2), - .Q(sig00000112) + .D(sig000000f2), + .Q(sig00000142) ); FD #( .INIT ( 1'b0 )) blk00000104 ( .C(clk), - .D(sig000000c1), - .Q(sig0000010d) + .D(sig000000e9), + .Q(sig0000013a) ); FD #( .INIT ( 1'b0 )) blk00000105 ( .C(clk), - .D(sig000000bc), - .Q(sig00000102) + .D(sig000000e8), + .Q(sig00000139) ); FD #( .INIT ( 1'b0 )) blk00000106 ( .C(clk), - .D(sig000000b1), - .Q(sig00000101) + .D(sig000000e7), + .Q(sig00000138) ); FD #( .INIT ( 1'b0 )) blk00000107 ( .C(clk), - .D(sig000000e5), - .Q(sig00000136) + .D(sig000000e6), + .Q(sig00000137) ); FD #( .INIT ( 1'b0 )) @@ -2120,316 +2168,720 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) FD #( .INIT ( 1'b0 )) blk0000010b ( + .C(clk), + .D(sig000000e1), + .Q(sig00000132) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010c ( + .C(clk), + .D(sig000000e0), + .Q(sig00000131) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010d ( + .C(clk), + .D(sig000000df), + .Q(sig00000130) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010e ( + .C(clk), + .D(sig000000de), + .Q(sig0000012f) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010f ( + .C(clk), + .D(sig000000dd), + .Q(sig0000012e) + ); + FD #( + .INIT ( 1'b0 )) + blk00000110 ( + .C(clk), + .D(sig000000dc), + .Q(sig0000012d) + ); + FD #( + .INIT ( 1'b0 )) + blk00000111 ( + .C(clk), + .D(sig000000db), + .Q(sig0000012c) + ); + FD #( + .INIT ( 1'b0 )) + blk00000112 ( + .C(clk), + .D(sig000000f1), + .Q(sig00000141) + ); + FD #( + .INIT ( 1'b0 )) + blk00000113 ( + .C(clk), + .D(sig000000f0), + .Q(sig00000140) + ); + FD #( + .INIT ( 1'b0 )) + blk00000114 ( + .C(clk), + .D(sig000000ef), + .Q(sig0000013f) + ); + FD #( + .INIT ( 1'b0 )) + blk00000115 ( .C(clk), .D(sig000000ee), .Q(sig0000013e) ); FD #( .INIT ( 1'b0 )) - blk0000010c ( + blk00000116 ( .C(clk), .D(sig000000ed), .Q(sig0000013d) ); FD #( .INIT ( 1'b0 )) - blk0000010d ( + blk00000117 ( .C(clk), .D(sig000000ec), .Q(sig0000013c) ); FD #( .INIT ( 1'b0 )) - blk0000010e ( + blk00000118 ( .C(clk), .D(sig000000eb), .Q(sig0000013b) ); - FD #( - .INIT ( 1'b0 )) - blk0000010f ( - .C(clk), - .D(sig000000ea), - .Q(sig0000013a) - ); - FD #( - .INIT ( 1'b0 )) - blk00000110 ( - .C(clk), - .D(sig000000e9), - .Q(sig00000139) - ); - FD #( - .INIT ( 1'b0 )) - blk00000111 ( - .C(clk), - .D(sig000000e8), - .Q(sig00000138) - ); - FD #( - .INIT ( 1'b0 )) - blk00000112 ( - .C(clk), - .D(sig000000e7), - .Q(sig00000137) - ); - FD #( - .INIT ( 1'b0 )) - blk00000113 ( - .C(clk), - .D(sig000000e6), - .Q(sig00000132) - ); - FD #( - .INIT ( 1'b0 )) - blk00000114 ( - .C(clk), - .D(sig000000e1), - .Q(sig00000131) - ); - FD #( - .INIT ( 1'b0 )) - blk00000115 ( - .C(clk), - .D(sig000000a9), - .Q(sig00000100) - ); - FD #( - .INIT ( 1'b0 )) - blk00000116 ( - .C(clk), - .D(sig000000a8), - .Q(sig000000ff) - ); - FD #( - .INIT ( 1'b0 )) - blk00000117 ( - .C(clk), - .D(sig000000a7), - .Q(sig000000fe) - ); - FD #( - .INIT ( 1'b0 )) - blk00000118 ( - .C(clk), - .D(sig000000a6), - .Q(sig000000fd) - ); FD #( .INIT ( 1'b0 )) blk00000119 ( .C(clk), - .D(sig000000a5), - .Q(sig000000fc) + .D(sig000000ea), + .Q(sig00000136) ); FD #( .INIT ( 1'b0 )) blk0000011a ( .C(clk), - .D(sig000000a3), - .Q(sig000000fb) + .D(sig000000e5), + .Q(sig0000012b) ); FD #( .INIT ( 1'b0 )) blk0000011b ( .C(clk), - .D(sig000000a2), - .Q(sig000000fa) + .D(sig000000da), + .Q(sig0000012a) ); FD #( .INIT ( 1'b0 )) blk0000011c ( .C(clk), - .D(sig000000a1), - .Q(sig000000f9) + .D(sig000000d1), + .Q(sig00000122) ); FD #( .INIT ( 1'b0 )) blk0000011d ( .C(clk), - .D(sig000000a0), - .Q(sig000000f8) + .D(sig000000d0), + .Q(sig00000121) ); FD #( .INIT ( 1'b0 )) blk0000011e ( .C(clk), - .D(sig0000009f), - .Q(sig000000f7) + .D(sig000000cf), + .Q(sig00000120) ); FD #( .INIT ( 1'b0 )) blk0000011f ( .C(clk), - .D(sig0000009e), - .Q(sig000000f6) + .D(sig000000ce), + .Q(sig0000011f) ); FD #( .INIT ( 1'b0 )) blk00000120 ( .C(clk), - .D(sig0000009d), - .Q(sig000000f5) + .D(sig000000cc), + .Q(sig0000011d) ); FD #( .INIT ( 1'b0 )) blk00000121 ( .C(clk), - .D(sig0000009c), - .Q(sig000000f4) + .D(sig000000cb), + .Q(sig0000011c) ); FD #( .INIT ( 1'b0 )) blk00000122 ( .C(clk), - .D(sig0000009b), - .Q(sig000000f3) + .D(sig000000ca), + .Q(sig0000011b) ); FD #( .INIT ( 1'b0 )) blk00000123 ( .C(clk), - .D(sig0000009a), - .Q(sig000000f2) + .D(sig000000c9), + .Q(sig0000011a) ); FD #( .INIT ( 1'b0 )) blk00000124 ( .C(clk), - .D(sig00000098), - .Q(sig000000f1) + .D(sig000000c8), + .Q(sig00000119) ); FD #( .INIT ( 1'b0 )) blk00000125 ( .C(clk), - .D(sig00000097), - .Q(sig000000f0) + .D(sig000000c7), + .Q(sig00000118) ); FD #( .INIT ( 1'b0 )) blk00000126 ( .C(clk), - .D(sig00000096), - .Q(sig000000ef) + .D(sig000000c6), + .Q(sig00000117) ); FD #( .INIT ( 1'b0 )) blk00000127 ( .C(clk), - .D(sig00000095), - .Q(p[16]) + .D(sig000000c5), + .Q(sig00000116) ); FD #( .INIT ( 1'b0 )) blk00000128 ( .C(clk), - .D(sig00000094), - .Q(p[15]) + .D(sig000000c4), + .Q(sig00000115) ); FD #( .INIT ( 1'b0 )) blk00000129 ( .C(clk), - .D(sig00000093), - .Q(p[14]) + .D(sig000000c3), + .Q(sig00000114) ); FD #( .INIT ( 1'b0 )) blk0000012a ( .C(clk), - .D(sig00000092), - .Q(p[13]) + .D(sig000000d9), + .Q(sig00000129) ); FD #( .INIT ( 1'b0 )) blk0000012b ( .C(clk), - .D(sig00000091), - .Q(p[12]) + .D(sig000000d8), + .Q(sig00000128) ); FD #( .INIT ( 1'b0 )) blk0000012c ( .C(clk), - .D(sig00000090), - .Q(p[11]) + .D(sig000000d7), + .Q(sig00000127) ); FD #( .INIT ( 1'b0 )) blk0000012d ( .C(clk), - .D(sig0000008f), - .Q(p[10]) + .D(sig000000d6), + .Q(sig00000126) ); FD #( .INIT ( 1'b0 )) blk0000012e ( .C(clk), - .D(sig000000b0), - .Q(p[9]) + .D(sig000000d5), + .Q(sig00000125) ); FD #( .INIT ( 1'b0 )) blk0000012f ( .C(clk), - .D(sig000000af), - .Q(p[8]) + .D(sig000000d4), + .Q(sig00000124) ); FD #( .INIT ( 1'b0 )) blk00000130 ( .C(clk), - .D(sig000000ae), - .Q(p[7]) + .D(sig000000d3), + .Q(sig00000123) ); FD #( .INIT ( 1'b0 )) blk00000131 ( .C(clk), - .D(sig000000ad), - .Q(p[6]) + .D(sig000000d2), + .Q(sig0000011e) ); FD #( .INIT ( 1'b0 )) blk00000132 ( .C(clk), - .D(sig000000ac), - .Q(p[5]) + .D(sig000000cd), + .Q(sig00000113) ); FD #( .INIT ( 1'b0 )) blk00000133 ( .C(clk), - .D(sig000000ab), - .Q(p[4]) + .D(sig000000c2), + .Q(sig00000112) ); FD #( .INIT ( 1'b0 )) blk00000134 ( .C(clk), - .D(sig000000aa), - .Q(p[3]) + .D(sig000000ba), + .Q(sig00000111) ); FD #( .INIT ( 1'b0 )) blk00000135 ( .C(clk), - .D(sig000000a4), - .Q(p[2]) + .D(sig000000b9), + .Q(sig00000110) ); FD #( .INIT ( 1'b0 )) blk00000136 ( .C(clk), - .D(sig00000099), - .Q(p[1]) + .D(sig000000b8), + .Q(sig0000010f) ); FD #( .INIT ( 1'b0 )) blk00000137 ( .C(clk), - .D(sig0000008e), + .D(sig000000b7), + .Q(sig0000010e) + ); + FD #( + .INIT ( 1'b0 )) + blk00000138 ( + .C(clk), + .D(sig000000b6), + .Q(sig0000010d) + ); + FD #( + .INIT ( 1'b0 )) + blk00000139 ( + .C(clk), + .D(sig000000b4), + .Q(sig0000010c) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013a ( + .C(clk), + .D(sig000000b3), + .Q(sig0000010b) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013b ( + .C(clk), + .D(sig000000b2), + .Q(sig0000010a) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013c ( + .C(clk), + .D(sig000000b1), + .Q(sig00000109) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013d ( + .C(clk), + .D(sig000000b0), + .Q(sig00000108) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013e ( + .C(clk), + .D(sig000000af), + .Q(sig00000107) + ); + FD #( + .INIT ( 1'b0 )) + blk0000013f ( + .C(clk), + .D(sig000000ae), + .Q(sig00000106) + ); + FD #( + .INIT ( 1'b0 )) + blk00000140 ( + .C(clk), + .D(sig000000ad), + .Q(sig00000105) + ); + FD #( + .INIT ( 1'b0 )) + blk00000141 ( + .C(clk), + .D(sig000000ac), + .Q(sig00000104) + ); + FD #( + .INIT ( 1'b0 )) + blk00000142 ( + .C(clk), + .D(sig000000ab), + .Q(sig00000103) + ); + FD #( + .INIT ( 1'b0 )) + blk00000143 ( + .C(clk), + .D(sig000000a9), + .Q(sig00000102) + ); + FD #( + .INIT ( 1'b0 )) + blk00000144 ( + .C(clk), + .D(sig000000a8), + .Q(sig00000101) + ); + FD #( + .INIT ( 1'b0 )) + blk00000145 ( + .C(clk), + .D(sig000000a7), + .Q(sig00000100) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000146 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a4), + .Q(sig00000007) + ); + FD #( + .INIT ( 1'b0 )) + blk00000147 ( + .C(clk), + .D(sig00000007), + .Q(p[14]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000148 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a6), + .Q(sig00000009) + ); + FD #( + .INIT ( 1'b0 )) + blk00000149 ( + .C(clk), + .D(sig00000009), + .Q(p[16]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000014a ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a5), + .Q(sig00000008) + ); + FD #( + .INIT ( 1'b0 )) + blk0000014b ( + .C(clk), + .D(sig00000008), + .Q(p[15]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000014c ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a3), + .Q(sig00000006) + ); + FD #( + .INIT ( 1'b0 )) + blk0000014d ( + .C(clk), + .D(sig00000006), + .Q(p[13]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000014e ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a2), + .Q(sig00000005) + ); + FD #( + .INIT ( 1'b0 )) + blk0000014f ( + .C(clk), + .D(sig00000005), + .Q(p[12]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000150 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a1), + .Q(sig00000004) + ); + FD #( + .INIT ( 1'b0 )) + blk00000151 ( + .C(clk), + .D(sig00000004), + .Q(p[11]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000152 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000a0), + .Q(sig00000003) + ); + FD #( + .INIT ( 1'b0 )) + blk00000153 ( + .C(clk), + .D(sig00000003), + .Q(p[10]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000154 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000c1), + .Q(sig00000011) + ); + FD #( + .INIT ( 1'b0 )) + blk00000155 ( + .C(clk), + .D(sig00000011), + .Q(p[9]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000156 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000c0), + .Q(sig00000010) + ); + FD #( + .INIT ( 1'b0 )) + blk00000157 ( + .C(clk), + .D(sig00000010), + .Q(p[8]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000158 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000bf), + .Q(sig0000000f) + ); + FD #( + .INIT ( 1'b0 )) + blk00000159 ( + .C(clk), + .D(sig0000000f), + .Q(p[7]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000015a ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000be), + .Q(sig0000000e) + ); + FD #( + .INIT ( 1'b0 )) + blk0000015b ( + .C(clk), + .D(sig0000000e), + .Q(p[6]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000015c ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000bd), + .Q(sig0000000d) + ); + FD #( + .INIT ( 1'b0 )) + blk0000015d ( + .C(clk), + .D(sig0000000d), + .Q(p[5]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk0000015e ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000bc), + .Q(sig0000000c) + ); + FD #( + .INIT ( 1'b0 )) + blk0000015f ( + .C(clk), + .D(sig0000000c), + .Q(p[4]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000160 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000bb), + .Q(sig0000000b) + ); + FD #( + .INIT ( 1'b0 )) + blk00000161 ( + .C(clk), + .D(sig0000000b), + .Q(p[3]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000162 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000b5), + .Q(sig0000000a) + ); + FD #( + .INIT ( 1'b0 )) + blk00000163 ( + .C(clk), + .D(sig0000000a), + .Q(p[2]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000164 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig000000aa), + .Q(sig00000002) + ); + FD #( + .INIT ( 1'b0 )) + blk00000165 ( + .C(clk), + .D(sig00000002), + .Q(p[1]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + blk00000166 ( + .A0(sig00000012), + .A1(sig00000012), + .A2(sig00000012), + .A3(sig00000012), + .CLK(clk), + .D(sig0000009f), + .Q(sig00000001) + ); + FD #( + .INIT ( 1'b0 )) + blk00000167 ( + .C(clk), + .D(sig00000001), .Q(p[0]) ); diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco index 89401df..2273be6 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 13.2 -# Date: Fri Oct 21 20:38:07 2011 +# Date: Mon Oct 24 22:04:01 2011 # ############################################################## # @@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier CSET optgoal=Speed CSET outputwidthhigh=47 CSET outputwidthlow=0 -CSET pipestages=2 +CSET pipestages=3 CSET portatype=Signed CSET portawidth=24 CSET portbtype=Signed @@ -65,4 +65,4 @@ CSET zerodetect=false MISC pkg_timestamp=2011-06-21T06:26:54.000Z # END Extra information GENERATE -# CRC: efe4d30e +# CRC: fd22ef14 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise index 12daee6..1efcbc5 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise @@ -29,335 +29,29 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v index 88379dd..fb18653 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v @@ -83,11 +83,11 @@ output [15 : 0] doutb; .C_HAS_RSTB(0), .C_HAS_SOFTECC_INPUT_REGS_A(0), .C_HAS_SOFTECC_OUTPUT_REGS_B(0), - .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INIT_FILE_NAME("cx4_pgmrom.mif"), .C_INITA_VAL("0"), .C_INITB_VAL("0"), .C_INTERFACE_TYPE(0), - .C_LOAD_INIT_FILE(0), + .C_LOAD_INIT_FILE(1), .C_MEM_TYPE(1), .C_MUX_PIPELINE_STAGES(0), .C_PRIM_TYPE(1), diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco index 59cb743..3e5d771 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 13.2 -# Date: Tue Oct 18 18:45:53 2011 +# Date: Sun Oct 23 22:07:47 2011 # ############################################################## # @@ -46,7 +46,7 @@ CSET axi_id_width=4 CSET axi_slave_type=Memory_Slave CSET axi_type=AXI4_Full CSET byte_size=9 -CSET coe_file=no_coe_file_loaded +CSET coe_file=/home/ikari/prj/sd2snes/verilog/sd2snes_cx4/cx4_e.coe CSET collision_warnings=ALL CSET component_name=cx4_pgmrom CSET disable_collision_warnings=false @@ -58,7 +58,7 @@ CSET enable_b=Always_Enabled CSET error_injection_type=Single_Bit_Error_Injection CSET fill_remaining_memory_locations=false CSET interface_type=Native -CSET load_init_file=false +CSET load_init_file=true CSET memory_type=Simple_Dual_Port_RAM CSET operating_mode_a=WRITE_FIRST CSET operating_mode_b=WRITE_FIRST @@ -102,4 +102,4 @@ CSET write_width_b=16 MISC pkg_timestamp=2011-03-11T08:24:14.000Z # END Extra information GENERATE -# CRC: 30264765 +# CRC: a9280b11 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise index 72cb4ec..81e9188 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise @@ -50,8 +50,8 @@ - - + + diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index b8fcf11..93c69dd 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -106,6 +106,10 @@ wire [7:0] CX4_SNES_DATA_OUT; wire [23:0] MAPPED_SNES_ADDR; wire ROM_ADDR0; +wire [23:0] cx4_datrom_data; +wire [9:0] cx4_datrom_addr; +wire cx4_datrom_we; + sd_dma snes_sd_dma( .CLK(CLK2), .SD_DAT(SD_DAT), @@ -226,7 +230,11 @@ mcu_cmd snes_mcu_cmd( .mcu_rrq(MCU_RRQ), .mcu_wrq(MCU_WRQ), .mcu_rq_rdy(MCU_RDY), - .use_msu1(use_msu1) + .use_msu1(use_msu1), + .cx4_datrom_addr_out(cx4_datrom_addr), + .cx4_datrom_data_out(cx4_datrom_data), + .cx4_datrom_we_out(cx4_datrom_we), + .cx4_reset_out(cx4_reset) ); wire [7:0] DCM_STATUS; @@ -285,9 +293,9 @@ cx4 snes_cx4 ( .nRD(SNES_READ), .nWR(SNES_WRITE), .CLK(CLK2), - .DATROM_DI(DATROM_DI), - .DATROM_WE(DATROM_WE), - .DATROM_ADDR(DATROM_ADDR), + .DATROM_DI(cx4_datrom_data), + .DATROM_WE(cx4_datrom_we), + .DATROM_ADDR(cx4_datrom_addr), .BUS_DI(CX4_DINr), .BUS_ADDR(CX4_ADDR), .BUS_RRQ(CX4_RRQ), diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise index 0c67fd3..82ca3c5 100644 --- a/verilog/sd2snes_cx4/sd2snes_cx4.xise +++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise @@ -283,14 +283,14 @@ - - + + - + @@ -311,7 +311,7 @@ - + @@ -330,7 +330,7 @@ - + @@ -338,8 +338,8 @@ - - + + @@ -361,13 +361,13 @@ - + - - + + @@ -405,7 +405,7 @@ - + From 65e26cb0c30674330482c313ad75ac7b0f75639b Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 27 Oct 2011 15:37:44 +0200 Subject: [PATCH 10/66] basic build instructions --- src/README | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 src/README diff --git a/src/README b/src/README new file mode 100644 index 0000000..8829d25 --- /dev/null +++ b/src/README @@ -0,0 +1,85 @@ +How to build: + +a) Build requirements + * make + * Cortex M3 toolchain + * snescom/sneslink + * Xilinx FPGA synthesis tool (e.g. ISE WebPack) + * PIC assembler + +b) Cortex M3 toolchain + * obtain the cm3-toolchain builder: + git clone http://snowcat.de/toolchain-cm3.git/ + * build the cm3-toolchain. Some tools, libraries, and headers are required, + including but probably not limited to: + - libz-dev + - libcloog-ppl-dev + - texinfo + - libmpfr-dev + - libgmp3-dev + - gawk + - bison + - recode + - flex + - libncurses5-dev + - libexpat-dev + - make + - gcc + Newer gccs complain when compiling binutils, so you may have to add + '--disable-werror' to the compiler options for binutils in the Makefile. + The Makefile will install immediately so make sure you can write to the + installation directory. + +c) snescom/sneslink + * http://bisqwit.iki.fi/source/snescom.html + +d) ISE WebPack + * http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm + +e) PIC assembler + * e.g. GPUTILS, http://gputils.sourceforge.net/ + +f) general order of operations + 1) program the PIC (cic/supercic/supercic-key.asm) + 2) build and program the bootloader. + 3) build the firmware and copy it to the memory card + 4) build the snes menu and copy it to the memory card + 5) build and compress the FPGA configuration and copy it to the memory card + 6) insert memory card, power on; the bootloader should begin flashing the + firmware and boot it + +1) Programming the PIC +Use a PIC assembler + programmer of your choice and program a PIC12F629 with +cic/supercic/supercic-key.asm. Make sure that the clock source is set to +EC_OSC and MCLRE is disabled. +After programming you can solder the PIC to the board and short JP401. +Open JP401 in case you need to reprogram the PIC on board. + +2) Building & programming the bootloader +The Makefile is prepared for JTAG programming using OpenOCD 0.4 and an FT2232 +based USB-JTAG adapter. +Connect a JTAG cable to J401 (14-pin header). The pinout is printed on the +board. cd to src/bootldr and make && make program. + +3) Building the firmware +cd to src/utils and make. +cd to src/ and make. +You should obtain a firmware file called obj/firmware.img. Copy this file to +/sd2snes/firmware.img. + +4) Building the SNES menu +snescom is required. +cd to snes/ and make. +Copy the resulting file menu.bin to /sd2snes/menu.bin. + +5) Building the FPGA configuration +Compile the RLE compressor in utils/rle.c: + $ gcc -Wall -o rle rle.c + +Load verilog/sd2snes/sd2snes.xise in Xilinx ISE (or create your own project). +Target is a XC3S400-4PQ208. +Generate the programming file and compress it using utils/rle.c: + $ rle main.bit fpga_base.bit + +Copy fpga_base.bit to /sd2snes/fpga_base.bit + From 7643790fedd67f2ac3a126c47b2d6fb202ef9ff7 Mon Sep 17 00:00:00 2001 From: ikari Date: Sun, 30 Oct 2011 01:53:56 +0200 Subject: [PATCH 11/66] FPGA/Cx4: fully operational except reset vector area --- verilog/sd2snes_cx4/cx4.v | 212 +- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v | 3058 ++++++++----------- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco | 6 +- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise | 4 +- verilog/sd2snes_cx4/main.v | 240 +- verilog/sd2snes_cx4/sd2snes_cx4.xise | 8 +- 6 files changed, 1535 insertions(+), 1993 deletions(-) diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index 4eb055b..06d943d 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -42,28 +42,24 @@ parameter BUSY_DMA = 2'b01; parameter BUSY_CPU = 2'b10; wire datram_enable = CS & (ADDR[11:0] < 12'hc00); -wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11001); -wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11001); +wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011); +wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011); wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); -wire debug_enable = CS & (&(ADDR[12:7]) && &(ADDR[5:4])); wire [7:0] DATRAM_DO; -reg [7:0] MMIO_DOr; +reg [7:0] MMIO_DOr; wire [7:0] MMIO_DO; wire [7:0] STATUS_DO; wire [7:0] VECTOR_DO; wire [7:0] GPR_DO; -wire [7:0] DEBUG_DO; -reg [7:0] DEBUG_DOr; assign DO = datram_enable ? DATRAM_DO : mmio_enable ? MMIO_DO : status_enable ? STATUS_DO : vector_enable ? VECTOR_DO : gpr_enable ? GPR_DO - : debug_enable ? DEBUG_DO : 8'h00; /* 0x1f40 - 0x1f52: MMIO @@ -71,33 +67,37 @@ assign DO = datram_enable ? DATRAM_DO reg [23:0] cx4_mmio_dmasrc; reg [15:0] cx4_mmio_dmalen; reg [23:0] cx4_mmio_dmatgt; -reg cx4_mmio_cachepage; +reg cx4_mmio_cachepage; reg [23:0] cx4_mmio_pgmoff; -reg [1:0] cx4_mmio_r1f4c; +reg [1:0] cx4_mmio_savepage; reg [14:0] cx4_mmio_pgmpage; -reg [7:0] cx4_mmio_pc; -reg [7:0] cx4_mmio_r1f50; -reg cx4_mmio_r1f51; -reg cx4_mmio_r1f52; +reg [7:0] cx4_mmio_pc; +reg [7:0] cx4_mmio_r1f50; +reg cx4_mmio_r1f51; +reg cx4_mmio_r1f52; /* 0x1f53 - 0x1f5f: status register */ assign cx4_active = |cx4_busy; /* 0x1f60 - 0x1f7f: reset vectors */ -reg [7:0] vector [31:0]; +reg [7:0] vector [31:0]; /* 0x1f80 - 0x1faf (0x1fc0 - 0x1fef): general purpose register file SNES: 8 bits / CX4: 24 bits */ -reg [7:0] gpr [47:0]; +reg [7:0] gpr [47:0]; wire [47:0] cpu_mul_result; +reg [14:0] cx4_mmio_pagemem[1:0]; + reg [23:0] const [15:0]; -reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number +reg [14:0] cachetag [1:0]; // 14-0: bank number +reg [1:0] cachevalid; + reg [14:0] cache_pgmpage; reg [14:0] cpu_cache_pgmpage; -reg cache_cachepage; -reg cpu_cache_cachepage; -reg cpu_cache_done; -reg [7:0] cpu_pc_stack [7:0]; -reg [7:0] cpu_page_stack; +reg cache_cachepage; +reg cpu_cache_cachepage; +reg cpu_cache_done; +reg [7:0] cpu_pc_stack [7:0]; +reg [7:0] cpu_page_stack; initial begin cache_pgmpage = 15'b0; @@ -105,14 +105,16 @@ initial begin cache_cachepage = 1'b0; cpu_cache_cachepage = 1'b0; cpu_cache_done = 1'b0; - cachetag[0] = 16'h0000; - cachetag[1] = 16'h0000; + cachetag[0] = 14'h0000; + cachetag[1] = 14'h0000; + cachevalid = 2'b00; cx4_busy = 3'b000; cx4_mmio_pgmoff = 24'h000000; cx4_mmio_pgmpage = 15'h0000; cx4_mmio_dmasrc = 24'h000000; cx4_mmio_dmalen = 16'h0000; cx4_mmio_dmatgt = 24'h000000; + cx4_mmio_savepage = 2'b00; const[0] = 24'h000000; const[1] = 24'hffffff; const[2] = 24'h00ff00; @@ -144,7 +146,6 @@ assign MMIO_DO = MMIO_DOr; assign VECTOR_DO = vector [ADDR[4:0]]; assign GPR_DO = gpr [ADDR[5:0]]; assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0}; -assign DEBUG_DO = DEBUG_DOr; reg [7:0] DIr; always @(posedge CLK) DIr <= DI; @@ -198,6 +199,11 @@ assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq; reg cpu_page; reg [14:0] cpu_p; reg [7:0] cpu_pc; +reg [23:0] cpu_a; +reg fl_n; +reg fl_z; +reg fl_c; + reg cpu_go_en_r; initial cpu_go_en_r = 1'b0; @@ -222,69 +228,58 @@ always @(posedge CLK) begin 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b - 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c + 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_savepage}; // 1f4c 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51 - 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 + 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 default: MMIO_DOr <= 8'hff; endcase end -always @(posedge CLK) begin - case(ADDR[3:0]) - 4'h0: DEBUG_DOr <= cachetag[0][15:8]; // 1f40 - 4'h1: DEBUG_DOr <= cachetag[0][7:0]; // 1f41 - 4'h2: DEBUG_DOr <= cachetag[1][15:8]; // 1f42 - 4'h3: DEBUG_DOr <= cachetag[1][7:0]; // 1f43 - 4'h4: DEBUG_DOr <= cpu_page; - 4'h5: DEBUG_DOr <= cpu_p; - 4'h6: DEBUG_DOr <= cpu_pc; - 4'h7: DEBUG_DOr <= cx4_busy; - 4'h8: DEBUG_DOr <= cpu_page_stack[0]; - 4'h9: DEBUG_DOr <= cpu_pc_stack[0]; - 4'ha: DEBUG_DOr <= cpu_page_stack[1]; - 4'hb: DEBUG_DOr <= cpu_pc_stack[1]; - 4'hc: DEBUG_DOr <= cpu_page_stack[2]; - 4'hd: DEBUG_DOr <= cpu_pc_stack[2]; - 4'he: DEBUG_DOr <= cpu_page_stack[3]; - 4'hf: DEBUG_DOr <= cpu_pc_stack[3]; - endcase -end - always @(posedge CLK) begin if(MMIO_WR_EN) begin case(ADDR[4:0]) - 5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 - 5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 - 5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 - 5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 - 5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 - 5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 - 5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 + 5'h00: cx4_mmio_dmasrc[7:0] <= DIr; // 1f40 + 5'h01: cx4_mmio_dmasrc[15:8] <= DIr; // 1f41 + 5'h02: cx4_mmio_dmasrc[23:16] <= DIr; // 1f42 + 5'h03: cx4_mmio_dmalen[7:0] <= DIr; // 1f43 + 5'h04: cx4_mmio_dmalen[15:8] <= DIr; // 1f44 + 5'h05: cx4_mmio_dmatgt[7:0] <= DIr; // 1f45 + 5'h06: cx4_mmio_dmatgt[15:8] <= DIr; // 1f46 5'h07: begin - cx4_mmio_dmatgt[23:16] <= DI; // 1f47 + cx4_mmio_dmatgt[23:16] <= DIr; // 1f47 DMA_TRIG_ENr <= 1'b1; end 5'h08: begin - cx4_mmio_cachepage <= DI[0]; // 1f48 + cx4_mmio_cachepage <= DIr[0]; // 1f48 CACHE_TRIG_ENr <= 1'b1; end - 5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 - 5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a - 5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b - 5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c - 5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d - 5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e + 5'h09: cx4_mmio_pgmoff[7:0] <= DIr; // 1f49 + 5'h0a: cx4_mmio_pgmoff[15:8] <= DIr; // 1f4a + 5'h0b: cx4_mmio_pgmoff[23:16] <= DIr; // 1f4b + 5'h0c: begin + cx4_mmio_savepage <= DIr[1:0]; + if(DIr[0]) cx4_mmio_pagemem[0] <= cx4_mmio_pgmpage; + if(DIr[1]) cx4_mmio_pagemem[1] <= cx4_mmio_pgmpage; + end + 5'h0d: cx4_mmio_pgmpage[7:0] <= DIr; // 1f4d + 5'h0e: cx4_mmio_pgmpage[14:8] <= DIr[6:0]; // 1f4e 5'h0f: begin - cx4_mmio_pc <= DI; // 1f4f + cx4_mmio_pc <= DIr; // 1f4f + if(cx4_mmio_savepage[0] + && cx4_mmio_pagemem[0] == cx4_mmio_pgmpage) + cx4_mmio_cachepage <= 1'b0; + else if(cx4_mmio_savepage[1] + && cx4_mmio_pagemem[1] == cx4_mmio_pgmpage) + cx4_mmio_cachepage <= 1'b1; cpu_go_en_r <= 1'b1; end - 5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 - 5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 - 5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 + 5'h10: cx4_mmio_r1f50 <= DIr & 8'h77; // 1f50 + 5'h11: cx4_mmio_r1f51 <= DIr[0]; // 1f51 + 5'h12: cx4_mmio_r1f52 <= DIr[0]; // 1f52 endcase end else begin CACHE_TRIG_ENr <= 1'b0; @@ -294,7 +289,7 @@ always @(posedge CLK) begin end always @(posedge CLK) begin - if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI; + if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DIr; end reg [4:0] CACHE_ST; @@ -333,14 +328,14 @@ always @(posedge CLK) begin case(CACHE_ST) ST_CACHE_IDLE: begin if(CACHE_TRIG_EN - & (~cachetag[cx4_mmio_cachepage][15] - | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) begin + & (~cachevalid[cx4_mmio_cachepage] + | |(cachetag[cx4_mmio_cachepage] ^ cx4_mmio_pgmpage))) begin CACHE_ST <= ST_CACHE_START; cache_pgmpage <= cx4_mmio_pgmpage; cache_cachepage <= cx4_mmio_cachepage; end else if(cpu_cache_en - & (~cachetag[~cpu_page][15] - | |(cachetag[~cpu_page][14:0] ^ cpu_p))) begin + & (~cachevalid[~cpu_page] + | |(cachetag[~cpu_page] ^ cpu_p))) begin CACHE_ST <= ST_CACHE_START; cache_pgmpage <= cpu_p; cache_cachepage <= ~cpu_page; @@ -370,7 +365,8 @@ always @(posedge CLK) begin cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; if(cache_count == 9'h1ff) begin cx4_busy[BUSY_CACHE] <= 1'b0; - cachetag[cache_cachepage] <= {1'b1,cache_pgmpage}; + cachetag[cache_cachepage] <= cache_pgmpage; + cachevalid[cache_cachepage] <= 1'b1; CACHE_ST <= ST_CACHE_IDLE; end else begin CACHE_BUS_RRQr <= 1'b1; @@ -439,7 +435,6 @@ reg [2:0] cpu_sp; initial cpu_sp = 3'b000; wire [15:0] cpu_op_w; reg [15:0] cpu_op; -reg [23:0] cpu_a; reg [23:0] cpu_busdata; reg [23:0] cpu_romdata; reg [23:0] cpu_ramdata; @@ -455,9 +450,6 @@ reg [23:0] cpu_dummy; reg [23:0] cpu_tmp; reg [23:0] cpu_sa; // tmp register for shifted accumulator -reg fl_n; -reg fl_z; -reg fl_c; wire [9:0] cx4_datrom_addr = cpu_a[9:0]; wire [23:0] cx4_datrom_do; @@ -499,19 +491,24 @@ reg op_call; reg op_jump; reg condtrue; -/* XXX DEBUG */ -reg [23:0] dbg_cnt; -initial dbg_cnt = 24'b0; -always @(posedge CLK) dbg_cnt <= dbg_cnt + 1; -wire step_enable = 1'b1; - always @(posedge CLK) begin if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1; - else if((op == OP_HLT) && step_enable) cx4_busy[BUSY_CPU] <= 1'b0; + else if(op == OP_HLT) cx4_busy[BUSY_CPU] <= 1'b0; end always @(posedge CLK) begin -if(step_enable | cpu_go_en_r) begin + case(op_sa) + 2'b00: cpu_sa <= cpu_a; + 2'b01: cpu_sa <= cpu_a << 1; + 2'b10: cpu_sa <= cpu_a << 8; + 2'b11: cpu_sa <= cpu_a << 16; + endcase +end + +reg jp_docache; +initial jp_docache = 1'b0; + +always @(posedge CLK) begin case(CPU_STATE) ST_CPU_IDLE: begin if(cpu_go_en_r) begin @@ -537,6 +534,10 @@ if(step_enable | cpu_go_en_r) begin 2'b00: condtrue <= fl_c; 2'b01: condtrue <= fl_n; endcase + if(op_p && !jp_docache) begin + jp_docache <= 1'b1; + cpu_cache_en <= 1'b1; + end end OP_SKIP: begin case(cpu_op[9:8]) @@ -562,14 +563,6 @@ if(step_enable | cpu_go_en_r) begin gpr[op_param[3:0]*3]}; default: cpu_idb <= 24'b0; endcase - if(op==OP_ALU || op==OP_CMP) begin - case(op_sa) - 2'b00: cpu_sa <= cpu_a; - 2'b01: cpu_sa <= cpu_a << 1; - 2'b10: cpu_sa <= cpu_a << 8; - 2'b11: cpu_sa <= cpu_a << 16; - endcase - end end OP_ST: begin cpu_idb <= cpu_a; @@ -615,9 +608,12 @@ if(step_enable | cpu_go_en_r) begin end ST_CPU_1: begin CPU_STATE <= ST_CPU_2; + condtrue <= 1'b0; case(op) OP_JP: begin - if(!cx4_busy[BUSY_CACHE]) begin + cpu_cache_en <= 1'b0; + if(!cpu_cache_en && !cx4_busy[BUSY_CACHE]) begin + jp_docache <= 1'b0; if(condtrue) begin if(op_call) begin cpu_page_stack[cpu_sp] <= cpu_page; @@ -659,10 +655,8 @@ if(step_enable | cpu_go_en_r) begin end OP_ST, OP_SWP: begin casex(op_param) -// 8'h00: cpu_a <= cpu_idb; 8'h01: cpu_acch <= cpu_idb; 8'h02: cpu_accl <= cpu_idb; -// 8'h03: cpu_busdata <= cpu_idb; 8'h08: cpu_romdata <= cpu_idb; 8'h0c: cpu_ramdata <= cpu_idb; 8'h13: cpu_busaddr <= cpu_idb; @@ -707,8 +701,8 @@ if(step_enable | cpu_go_en_r) begin 5'b10110: cpu_alu_res <= cpu_sa & cpu_idb; 5'b10111: cpu_alu_res <= cpu_sa | cpu_idb; 5'b11000: cpu_alu_res <= cpu_a >> cpu_idb; - 5'b11001: cpu_alu_res <= $signed(cpu_a) >>> cpu_idb; - 5'b11010: {cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb; + 5'b11001: cpu_alu_res <= ($signed(cpu_a)) >>> cpu_idb; + 5'b11010: {cpu_dummy, cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb; 5'b11011: cpu_alu_res <= cpu_a << cpu_idb; endcase end @@ -717,12 +711,6 @@ if(step_enable | cpu_go_en_r) begin ST_CPU_3: begin CPU_STATE <= ST_CPU_0; case(op) - OP_LD: begin - casex(cpu_op[11:8]) - 4'b0x11: cpu_cache_en <= 1'b1; - 4'b1100: cpu_cache_en <= 1'b1; - endcase - end OP_BUS: cpu_busaddr <= cpu_busaddr + 1; OP_WRRAM: cx4_cpu_datram_we <= 1'b0; OP_CMP: begin @@ -803,12 +791,14 @@ if(step_enable | cpu_go_en_r) begin end endcase end -end reg[2:0] BUSRD_STATE; -parameter ST_BUSRD_IDLE = 2'b01; -parameter ST_BUSRD_WAIT = 2'b10; +parameter ST_BUSRD_IDLE = 3'b001; +parameter ST_BUSRD_WAIT = 3'b010; +parameter ST_BUSRD_END = 3'b100; initial BUSRD_STATE = ST_BUSRD_IDLE; +reg cpu_bus_rq2; +always @(posedge CLK) cpu_bus_rq2 <= cpu_bus_rq; always @(posedge CLK) begin if(CPU_STATE == ST_CPU_2 @@ -818,13 +808,15 @@ always @(posedge CLK) begin else begin case(BUSRD_STATE) ST_BUSRD_IDLE: begin - if(cpu_bus_rq) begin + if(cpu_bus_rq2) begin BUSRD_STATE <= ST_BUSRD_WAIT; end end ST_BUSRD_WAIT: begin - if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_IDLE; + if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_END; else BUSRD_STATE <= ST_BUSRD_WAIT; + end + ST_BUSRD_END: begin if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI; else cpu_busdata <= 8'h00; end @@ -841,7 +833,7 @@ always @(posedge CLK) begin gpr[op_param[3:0]*3+1] <= cpu_idb[15:8]; gpr[op_param[3:0]*3] <= cpu_idb[7:0]; end - else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; + else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DIr; end /*************************** @@ -861,7 +853,7 @@ cx4_datram cx4_datram ( .clka(CLK), // input clka .wea(DATRAM_WR_EN), // input [0 : 0] wea .addra(ADDR[11:0]), // input [11 : 0] addra - .dina(DI), // input [7 : 0] dina + .dina(DIr), // input [7 : 0] dina .douta(DATRAM_DO), // output [7 : 0] douta .clkb(CLK), // input clkb .web(cx4_datram_we), // input [0 : 0] web diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v index ebb89bc..da8b924 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v @@ -7,7 +7,7 @@ // \ \ \/ Version: O.61xd // \ \ Application: netgen // / / Filename: cx4_mul.v -// /___/ /\ Timestamp: Tue Oct 25 00:04:23 2011 +// /___/ /\ Timestamp: Fri Oct 28 10:30:51 2011 // \ \ / \ // \___\/\___\ // @@ -399,54 +399,6 @@ module cx4_mul ( wire sig00000162; wire sig00000163; wire sig00000164; - wire sig00000165; - wire sig00000166; - wire sig00000167; - wire sig00000168; - wire sig00000169; - wire sig0000016a; - wire sig0000016b; - wire sig0000016c; - wire sig0000016d; - wire sig0000016e; - wire sig0000016f; - wire sig00000170; - wire sig00000171; - wire sig00000172; - wire sig00000173; - wire sig00000174; - wire sig00000175; - wire sig00000176; - wire sig00000177; - wire sig00000178; - wire sig00000179; - wire sig0000017a; - wire sig0000017b; - wire sig0000017c; - wire sig0000017d; - wire sig0000017e; - wire sig0000017f; - wire sig00000180; - wire sig00000181; - wire sig00000182; - wire sig00000183; - wire sig00000184; - wire sig00000185; - wire sig00000186; - wire sig00000187; - wire sig00000188; - wire sig00000189; - wire sig0000018a; - wire sig0000018b; - wire sig0000018c; - wire sig0000018d; - wire sig0000018e; - wire sig0000018f; - wire sig00000190; - wire sig00000191; - wire sig00000192; - wire sig00000193; - wire sig00000194; wire \NLW_blk00000003_P<35>_UNCONNECTED ; wire \NLW_blk00000003_P<34>_UNCONNECTED ; wire \NLW_blk00000003_P<33>_UNCONNECTED ; @@ -495,15 +447,15 @@ module cx4_mul ( wire \NLW_blk00000005_P<24>_UNCONNECTED ; wire \NLW_blk00000006_P<35>_UNCONNECTED ; GND blk00000001 ( - .G(sig00000012) + .G(sig00000001) ); VCC blk00000002 ( - .P(sig00000013) + .P(sig00000002) ); MULT18X18S blk00000003 ( .C(clk), - .CE(sig00000013), - .R(sig00000012), + .CE(sig00000002), + .R(sig00000001), .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , @@ -511,1638 +463,1638 @@ module cx4_mul ( \NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , \NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , \NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , -\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000f6, sig000000f5, sig000000f4, -sig000000f3, sig000000ff, sig000000fe, sig000000fd, sig000000fc, sig000000fb, sig000000fa, sig000000f9, sig000000f8, sig000000f7, sig000000f2}) +\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, +sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1}) ); MULT18X18S blk00000004 ( .C(clk), - .CE(sig00000013), - .R(sig00000012), + .CE(sig00000002), + .R(sig00000001), .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), - .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , \NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , \NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , -\NLW_blk00000004_P<24>_UNCONNECTED , sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e4, sig000000e3, sig000000e2, sig000000e1, -sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, sig000000db, sig000000f1, sig000000f0, sig000000ef, sig000000ee, sig000000ed, -sig000000ec, sig000000eb, sig000000ea, sig000000e5, sig000000da}) +\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, +sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, +sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9}) ); MULT18X18S blk00000005 ( .C(clk), - .CE(sig00000013), - .R(sig00000012), - .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , \NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , \NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , -\NLW_blk00000005_P<24>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf, sig000000ce, sig000000cc, sig000000cb, sig000000ca, sig000000c9, -sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, sig000000c3, sig000000d9, sig000000d8, sig000000d7, sig000000d6, sig000000d5, -sig000000d4, sig000000d3, sig000000d2, sig000000cd, sig000000c2}) +\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, +sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, +sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1}) ); MULT18X18S blk00000006 ( .C(clk), - .CE(sig00000013), - .R(sig00000012), - .A({sig00000012, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), - .B({sig00000012, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), - .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000ba, sig000000b9, sig000000b8, sig000000b7, sig000000b6, sig000000b4, sig000000b3, sig000000b2, -sig000000b1, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, sig000000ab, sig000000a9, sig000000a8, sig000000a7, sig000000a6, -sig000000a5, sig000000a4, sig000000a3, sig000000a2, sig000000a1, sig000000a0, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, -sig000000bc, sig000000bb, sig000000b5, sig000000aa, sig0000009f}) + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, +sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, +sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, +sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); XORCY blk00000007 ( - .CI(sig00000076), - .LI(sig00000097), - .O(sig0000018f) + .CI(sig00000065), + .LI(sig00000086), + .O(p[47]) ); LUT2 #( .INIT ( 4'h6 )) blk00000008 ( - .I0(sig0000016c), - .I1(sig0000015f), - .O(sig00000097) - ); - MUXCY blk00000009 ( - .CI(sig00000075), - .DI(sig0000015f), - .S(sig00000096), - .O(sig00000076) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000000a ( - .I0(sig0000016c), - .I1(sig0000015f), - .O(sig00000096) - ); - MUXCY blk0000000b ( - .CI(sig00000073), - .DI(sig0000015f), - .S(sig00000095), - .O(sig00000075) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000000c ( - .I0(sig0000016c), - .I1(sig0000015f), - .O(sig00000095) - ); - XORCY blk0000000d ( - .CI(sig00000072), - .LI(sig00000093), - .O(sig0000018b) - ); - MUXCY blk0000000e ( - .CI(sig00000072), - .DI(sig0000015f), - .S(sig00000093), - .O(sig00000073) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000000f ( - .I0(sig0000016b), - .I1(sig0000015f), - .O(sig00000093) - ); - XORCY blk00000010 ( - .CI(sig00000071), - .LI(sig00000092), - .O(sig0000018a) - ); - MUXCY blk00000011 ( - .CI(sig00000071), - .DI(sig0000015f), - .S(sig00000092), - .O(sig00000072) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000012 ( - .I0(sig0000016a), - .I1(sig0000015f), - .O(sig00000092) - ); - XORCY blk00000013 ( - .CI(sig00000070), - .LI(sig00000091), - .O(sig00000189) - ); - MUXCY blk00000014 ( - .CI(sig00000070), - .DI(sig0000015f), - .S(sig00000091), - .O(sig00000071) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000015 ( - .I0(sig00000169), - .I1(sig0000015f), - .O(sig00000091) - ); - XORCY blk00000016 ( - .CI(sig0000006f), - .LI(sig00000090), - .O(sig00000188) - ); - MUXCY blk00000017 ( - .CI(sig0000006f), - .DI(sig0000015f), - .S(sig00000090), - .O(sig00000070) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000018 ( - .I0(sig00000175), - .I1(sig0000015f), - .O(sig00000090) - ); - XORCY blk00000019 ( - .CI(sig0000006e), - .LI(sig0000008f), - .O(sig00000187) - ); - MUXCY blk0000001a ( - .CI(sig0000006e), - .DI(sig0000015f), - .S(sig0000008f), - .O(sig0000006f) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000001b ( - .I0(sig00000174), - .I1(sig0000015f), - .O(sig0000008f) - ); - XORCY blk0000001c ( - .CI(sig0000006d), - .LI(sig0000008e), - .O(sig00000186) - ); - MUXCY blk0000001d ( - .CI(sig0000006d), - .DI(sig0000015f), - .S(sig0000008e), - .O(sig0000006e) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000001e ( - .I0(sig00000173), - .I1(sig0000015f), - .O(sig0000008e) - ); - XORCY blk0000001f ( - .CI(sig0000006c), - .LI(sig0000008d), - .O(sig00000185) - ); - MUXCY blk00000020 ( - .CI(sig0000006c), - .DI(sig0000015f), - .S(sig0000008d), - .O(sig0000006d) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000021 ( - .I0(sig00000172), - .I1(sig0000015f), - .O(sig0000008d) - ); - XORCY blk00000022 ( - .CI(sig0000006b), - .LI(sig0000008c), - .O(sig00000184) - ); - MUXCY blk00000023 ( - .CI(sig0000006b), - .DI(sig0000015e), - .S(sig0000008c), - .O(sig0000006c) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000024 ( - .I0(sig00000171), - .I1(sig0000015e), - .O(sig0000008c) - ); - XORCY blk00000025 ( - .CI(sig0000006a), - .LI(sig0000008b), - .O(sig00000183) - ); - MUXCY blk00000026 ( - .CI(sig0000006a), - .DI(sig0000015d), - .S(sig0000008b), - .O(sig0000006b) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000027 ( - .I0(sig00000170), - .I1(sig0000015d), - .O(sig0000008b) - ); - XORCY blk00000028 ( - .CI(sig00000068), - .LI(sig0000008a), - .O(sig00000182) - ); - MUXCY blk00000029 ( - .CI(sig00000068), - .DI(sig0000015c), - .S(sig0000008a), - .O(sig0000006a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000002a ( - .I0(sig0000016f), - .I1(sig0000015c), - .O(sig0000008a) - ); - XORCY blk0000002b ( - .CI(sig00000067), - .LI(sig00000088), - .O(sig00000180) - ); - MUXCY blk0000002c ( - .CI(sig00000067), - .DI(sig0000015a), - .S(sig00000088), - .O(sig00000068) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000002d ( - .I0(sig0000016e), - .I1(sig0000015a), - .O(sig00000088) - ); - XORCY blk0000002e ( - .CI(sig00000066), - .LI(sig00000087), - .O(sig0000017f) - ); - MUXCY blk0000002f ( - .CI(sig00000066), - .DI(sig00000159), - .S(sig00000087), - .O(sig00000067) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000030 ( - .I0(sig0000016d), - .I1(sig00000159), - .O(sig00000087) - ); - XORCY blk00000031 ( - .CI(sig00000065), - .LI(sig00000086), - .O(sig0000017e) - ); - MUXCY blk00000032 ( - .CI(sig00000065), - .DI(sig00000158), - .S(sig00000086), - .O(sig00000066) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000033 ( - .I0(sig00000168), - .I1(sig00000158), + .I0(sig0000014e), + .I1(sig0000015b), .O(sig00000086) ); - XORCY blk00000034 ( + MUXCY blk00000009 ( .CI(sig00000064), - .LI(sig00000085), - .O(sig0000017d) - ); - MUXCY blk00000035 ( - .CI(sig00000064), - .DI(sig00000157), + .DI(sig0000014e), .S(sig00000085), .O(sig00000065) ); LUT2 #( .INIT ( 4'h6 )) - blk00000036 ( - .I0(sig00000132), - .I1(sig00000157), + blk0000000a ( + .I0(sig0000014e), + .I1(sig0000015b), .O(sig00000085) ); - XORCY blk00000037 ( - .CI(sig00000063), - .LI(sig00000084), - .O(sig0000017c) - ); - MUXCY blk00000038 ( - .CI(sig00000063), - .DI(sig00000156), + MUXCY blk0000000b ( + .CI(sig00000062), + .DI(sig0000014e), .S(sig00000084), .O(sig00000064) ); LUT2 #( .INIT ( 4'h6 )) - blk00000039 ( - .I0(sig00000131), - .I1(sig00000156), + blk0000000c ( + .I0(sig0000014e), + .I1(sig0000015b), .O(sig00000084) ); - XORCY blk0000003a ( - .CI(sig00000062), - .LI(sig00000083), - .O(sig0000017b) - ); - MUXCY blk0000003b ( - .CI(sig00000062), - .DI(sig00000155), - .S(sig00000083), - .O(sig00000063) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000003c ( - .I0(sig00000130), - .I1(sig00000155), - .O(sig00000083) - ); - XORCY blk0000003d ( + XORCY blk0000000d ( .CI(sig00000061), .LI(sig00000082), - .O(sig0000017a) + .O(p[46]) ); - MUXCY blk0000003e ( + MUXCY blk0000000e ( .CI(sig00000061), - .DI(sig00000154), + .DI(sig0000014e), .S(sig00000082), .O(sig00000062) ); LUT2 #( .INIT ( 4'h6 )) - blk0000003f ( - .I0(sig0000012f), - .I1(sig00000154), + blk0000000f ( + .I0(sig0000014e), + .I1(sig0000015a), .O(sig00000082) ); - XORCY blk00000040 ( + XORCY blk00000010 ( .CI(sig00000060), .LI(sig00000081), - .O(sig00000179) + .O(p[45]) ); - MUXCY blk00000041 ( + MUXCY blk00000011 ( .CI(sig00000060), - .DI(sig00000153), + .DI(sig0000014e), .S(sig00000081), .O(sig00000061) ); LUT2 #( .INIT ( 4'h6 )) - blk00000042 ( - .I0(sig0000012e), - .I1(sig00000153), + blk00000012 ( + .I0(sig0000014e), + .I1(sig00000159), .O(sig00000081) ); - XORCY blk00000043 ( + XORCY blk00000013 ( .CI(sig0000005f), .LI(sig00000080), - .O(sig00000178) + .O(p[44]) ); - MUXCY blk00000044 ( + MUXCY blk00000014 ( .CI(sig0000005f), - .DI(sig00000152), + .DI(sig0000014e), .S(sig00000080), .O(sig00000060) ); LUT2 #( .INIT ( 4'h6 )) - blk00000045 ( - .I0(sig0000012d), - .I1(sig00000152), + blk00000015 ( + .I0(sig0000014e), + .I1(sig00000158), .O(sig00000080) ); - XORCY blk00000046 ( - .CI(sig0000007d), + XORCY blk00000016 ( + .CI(sig0000005e), .LI(sig0000007f), - .O(sig00000177) + .O(p[43]) ); - MUXCY blk00000047 ( - .CI(sig0000007d), - .DI(sig00000151), + MUXCY blk00000017 ( + .CI(sig0000005e), + .DI(sig0000014e), .S(sig0000007f), .O(sig0000005f) ); LUT2 #( .INIT ( 4'h6 )) - blk00000048 ( - .I0(sig0000012c), - .I1(sig00000151), + blk00000018 ( + .I0(sig0000014e), + .I1(sig00000164), .O(sig0000007f) ); - XORCY blk00000049 ( - .CI(sig0000007c), - .LI(sig0000009e), - .O(sig00000194) - ); - MUXCY blk0000004a ( - .CI(sig0000007c), - .DI(sig00000167), - .S(sig0000009e), - .O(sig0000007d) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000004b ( - .I0(sig00000141), - .I1(sig00000167), - .O(sig0000009e) - ); - XORCY blk0000004c ( - .CI(sig0000007b), - .LI(sig0000009d), - .O(sig00000193) - ); - MUXCY blk0000004d ( - .CI(sig0000007b), - .DI(sig00000166), - .S(sig0000009d), - .O(sig0000007c) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000004e ( - .I0(sig00000140), - .I1(sig00000166), - .O(sig0000009d) - ); - XORCY blk0000004f ( - .CI(sig0000007a), - .LI(sig0000009c), - .O(sig00000192) - ); - MUXCY blk00000050 ( - .CI(sig0000007a), - .DI(sig00000165), - .S(sig0000009c), - .O(sig0000007b) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000051 ( - .I0(sig0000013f), - .I1(sig00000165), - .O(sig0000009c) - ); - XORCY blk00000052 ( - .CI(sig00000079), - .LI(sig0000009b), - .O(sig00000191) - ); - MUXCY blk00000053 ( - .CI(sig00000079), - .DI(sig00000164), - .S(sig0000009b), - .O(sig0000007a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000054 ( - .I0(sig0000013e), - .I1(sig00000164), - .O(sig0000009b) - ); - XORCY blk00000055 ( - .CI(sig00000078), - .LI(sig0000009a), - .O(sig00000190) - ); - MUXCY blk00000056 ( - .CI(sig00000078), - .DI(sig00000163), - .S(sig0000009a), - .O(sig00000079) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000057 ( - .I0(sig0000013d), - .I1(sig00000163), - .O(sig0000009a) - ); - XORCY blk00000058 ( - .CI(sig00000077), - .LI(sig00000099), - .O(sig0000018e) - ); - MUXCY blk00000059 ( - .CI(sig00000077), - .DI(sig00000162), - .S(sig00000099), - .O(sig00000078) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000005a ( - .I0(sig0000013c), - .I1(sig00000162), - .O(sig00000099) - ); - XORCY blk0000005b ( - .CI(sig00000074), - .LI(sig00000098), - .O(sig0000018d) - ); - MUXCY blk0000005c ( - .CI(sig00000074), - .DI(sig00000161), - .S(sig00000098), - .O(sig00000077) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000005d ( - .I0(sig0000013b), - .I1(sig00000161), - .O(sig00000098) - ); - XORCY blk0000005e ( - .CI(sig00000069), - .LI(sig00000094), - .O(sig0000018c) - ); - MUXCY blk0000005f ( - .CI(sig00000069), - .DI(sig00000160), - .S(sig00000094), - .O(sig00000074) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000060 ( - .I0(sig00000136), - .I1(sig00000160), - .O(sig00000094) - ); - XORCY blk00000061 ( - .CI(sig0000005e), - .LI(sig00000089), - .O(sig00000181) - ); - MUXCY blk00000062 ( - .CI(sig0000005e), - .DI(sig0000015b), - .S(sig00000089), - .O(sig00000069) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000063 ( - .I0(sig0000012b), - .I1(sig0000015b), - .O(sig00000089) - ); - XORCY blk00000064 ( - .CI(sig00000012), + XORCY blk00000019 ( + .CI(sig0000005d), .LI(sig0000007e), - .O(sig00000176) + .O(p[42]) ); - MUXCY blk00000065 ( - .CI(sig00000012), - .DI(sig00000150), + MUXCY blk0000001a ( + .CI(sig0000005d), + .DI(sig0000014e), .S(sig0000007e), .O(sig0000005e) ); LUT2 #( .INIT ( 4'h6 )) - blk00000066 ( - .I0(sig0000012a), - .I1(sig00000150), + blk0000001b ( + .I0(sig0000014e), + .I1(sig00000163), .O(sig0000007e) ); - XORCY blk00000067 ( - .CI(sig00000022), - .LI(sig0000003a), - .O(sig0000015f) + XORCY blk0000001c ( + .CI(sig0000005c), + .LI(sig0000007d), + .O(p[41]) + ); + MUXCY blk0000001d ( + .CI(sig0000005c), + .DI(sig0000014e), + .S(sig0000007d), + .O(sig0000005d) ); LUT2 #( .INIT ( 4'h6 )) - blk00000068 ( - .I0(sig00000111), - .I1(sig00000122), - .O(sig0000003a) + blk0000001e ( + .I0(sig0000014e), + .I1(sig00000162), + .O(sig0000007d) ); - XORCY blk00000069 ( - .CI(sig00000021), - .LI(sig00000039), - .O(sig0000015e) + XORCY blk0000001f ( + .CI(sig0000005b), + .LI(sig0000007c), + .O(p[40]) ); - MUXCY blk0000006a ( - .CI(sig00000021), - .DI(sig00000111), - .S(sig00000039), - .O(sig00000022) + MUXCY blk00000020 ( + .CI(sig0000005b), + .DI(sig0000014e), + .S(sig0000007c), + .O(sig0000005c) ); LUT2 #( .INIT ( 4'h6 )) - blk0000006b ( - .I0(sig00000121), - .I1(sig00000111), - .O(sig00000039) + blk00000021 ( + .I0(sig0000014e), + .I1(sig00000161), + .O(sig0000007c) ); - XORCY blk0000006c ( - .CI(sig00000020), - .LI(sig00000038), - .O(sig0000015d) + XORCY blk00000022 ( + .CI(sig0000005a), + .LI(sig0000007b), + .O(p[39]) ); - MUXCY blk0000006d ( - .CI(sig00000020), - .DI(sig00000111), - .S(sig00000038), - .O(sig00000021) + MUXCY blk00000023 ( + .CI(sig0000005a), + .DI(sig0000014d), + .S(sig0000007b), + .O(sig0000005b) ); LUT2 #( .INIT ( 4'h6 )) - blk0000006e ( - .I0(sig00000120), - .I1(sig00000111), - .O(sig00000038) + blk00000024 ( + .I0(sig0000014d), + .I1(sig00000160), + .O(sig0000007b) ); - XORCY blk0000006f ( - .CI(sig0000001e), - .LI(sig00000037), - .O(sig0000015c) + XORCY blk00000025 ( + .CI(sig00000059), + .LI(sig0000007a), + .O(p[38]) ); - MUXCY blk00000070 ( - .CI(sig0000001e), - .DI(sig00000111), - .S(sig00000037), - .O(sig00000020) + MUXCY blk00000026 ( + .CI(sig00000059), + .DI(sig0000014c), + .S(sig0000007a), + .O(sig0000005a) ); LUT2 #( .INIT ( 4'h6 )) - blk00000071 ( - .I0(sig0000011f), - .I1(sig00000111), - .O(sig00000037) + blk00000027 ( + .I0(sig0000014c), + .I1(sig0000015f), + .O(sig0000007a) ); - XORCY blk00000072 ( - .CI(sig0000001d), - .LI(sig00000035), - .O(sig0000015a) + XORCY blk00000028 ( + .CI(sig00000057), + .LI(sig00000079), + .O(p[37]) ); - MUXCY blk00000073 ( - .CI(sig0000001d), - .DI(sig00000111), - .S(sig00000035), - .O(sig0000001e) + MUXCY blk00000029 ( + .CI(sig00000057), + .DI(sig0000014b), + .S(sig00000079), + .O(sig00000059) ); LUT2 #( .INIT ( 4'h6 )) - blk00000074 ( - .I0(sig0000011d), - .I1(sig00000111), - .O(sig00000035) + blk0000002a ( + .I0(sig0000014b), + .I1(sig0000015e), + .O(sig00000079) ); - XORCY blk00000075 ( - .CI(sig0000001c), - .LI(sig00000034), - .O(sig00000159) + XORCY blk0000002b ( + .CI(sig00000056), + .LI(sig00000077), + .O(p[36]) ); - MUXCY blk00000076 ( - .CI(sig0000001c), - .DI(sig00000111), - .S(sig00000034), - .O(sig0000001d) + MUXCY blk0000002c ( + .CI(sig00000056), + .DI(sig00000149), + .S(sig00000077), + .O(sig00000057) ); LUT2 #( .INIT ( 4'h6 )) - blk00000077 ( - .I0(sig0000011c), - .I1(sig00000111), - .O(sig00000034) + blk0000002d ( + .I0(sig00000149), + .I1(sig0000015d), + .O(sig00000077) ); - XORCY blk00000078 ( - .CI(sig0000001b), - .LI(sig00000033), - .O(sig00000158) + XORCY blk0000002e ( + .CI(sig00000055), + .LI(sig00000076), + .O(p[35]) ); - MUXCY blk00000079 ( - .CI(sig0000001b), - .DI(sig00000111), - .S(sig00000033), - .O(sig0000001c) + MUXCY blk0000002f ( + .CI(sig00000055), + .DI(sig00000148), + .S(sig00000076), + .O(sig00000056) ); LUT2 #( .INIT ( 4'h6 )) - blk0000007a ( - .I0(sig0000011b), - .I1(sig00000111), - .O(sig00000033) + blk00000030 ( + .I0(sig00000148), + .I1(sig0000015c), + .O(sig00000076) ); - XORCY blk0000007b ( - .CI(sig0000001a), - .LI(sig00000032), - .O(sig00000157) + XORCY blk00000031 ( + .CI(sig00000054), + .LI(sig00000075), + .O(p[34]) ); - MUXCY blk0000007c ( - .CI(sig0000001a), - .DI(sig00000110), - .S(sig00000032), - .O(sig0000001b) + MUXCY blk00000032 ( + .CI(sig00000054), + .DI(sig00000147), + .S(sig00000075), + .O(sig00000055) ); LUT2 #( .INIT ( 4'h6 )) - blk0000007d ( - .I0(sig00000110), - .I1(sig0000011a), - .O(sig00000032) + blk00000033 ( + .I0(sig00000147), + .I1(sig00000157), + .O(sig00000075) ); - XORCY blk0000007e ( - .CI(sig00000019), - .LI(sig00000031), - .O(sig00000156) + XORCY blk00000034 ( + .CI(sig00000053), + .LI(sig00000074), + .O(p[33]) ); - MUXCY blk0000007f ( - .CI(sig00000019), - .DI(sig0000010f), - .S(sig00000031), - .O(sig0000001a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000080 ( - .I0(sig0000010f), - .I1(sig00000119), - .O(sig00000031) - ); - XORCY blk00000081 ( - .CI(sig00000018), - .LI(sig00000030), - .O(sig00000155) - ); - MUXCY blk00000082 ( - .CI(sig00000018), - .DI(sig0000010e), - .S(sig00000030), - .O(sig00000019) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000083 ( - .I0(sig0000010e), - .I1(sig00000118), - .O(sig00000030) - ); - XORCY blk00000084 ( - .CI(sig00000017), - .LI(sig0000002f), - .O(sig00000154) - ); - MUXCY blk00000085 ( - .CI(sig00000017), - .DI(sig0000010d), - .S(sig0000002f), - .O(sig00000018) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000086 ( - .I0(sig0000010d), - .I1(sig00000117), - .O(sig0000002f) - ); - XORCY blk00000087 ( - .CI(sig00000016), - .LI(sig0000002e), - .O(sig00000153) - ); - MUXCY blk00000088 ( - .CI(sig00000016), - .DI(sig0000010c), - .S(sig0000002e), - .O(sig00000017) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000089 ( - .I0(sig0000010c), - .I1(sig00000116), - .O(sig0000002e) - ); - XORCY blk0000008a ( - .CI(sig00000015), - .LI(sig0000002d), - .O(sig00000152) - ); - MUXCY blk0000008b ( - .CI(sig00000015), - .DI(sig0000010b), - .S(sig0000002d), - .O(sig00000016) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000008c ( - .I0(sig0000010b), - .I1(sig00000115), - .O(sig0000002d) - ); - XORCY blk0000008d ( - .CI(sig0000002a), - .LI(sig0000002c), - .O(sig00000151) - ); - MUXCY blk0000008e ( - .CI(sig0000002a), - .DI(sig0000010a), - .S(sig0000002c), - .O(sig00000015) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000008f ( - .I0(sig0000010a), - .I1(sig00000114), - .O(sig0000002c) - ); - XORCY blk00000090 ( - .CI(sig00000029), - .LI(sig00000042), - .O(sig00000167) - ); - MUXCY blk00000091 ( - .CI(sig00000029), - .DI(sig00000109), - .S(sig00000042), - .O(sig0000002a) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000092 ( - .I0(sig00000109), - .I1(sig00000129), - .O(sig00000042) - ); - XORCY blk00000093 ( - .CI(sig00000028), - .LI(sig00000041), - .O(sig00000166) - ); - MUXCY blk00000094 ( - .CI(sig00000028), - .DI(sig00000108), - .S(sig00000041), - .O(sig00000029) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000095 ( - .I0(sig00000108), - .I1(sig00000128), - .O(sig00000041) - ); - XORCY blk00000096 ( - .CI(sig00000027), - .LI(sig00000040), - .O(sig00000165) - ); - MUXCY blk00000097 ( - .CI(sig00000027), - .DI(sig00000107), - .S(sig00000040), - .O(sig00000028) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000098 ( - .I0(sig00000107), - .I1(sig00000127), - .O(sig00000040) - ); - XORCY blk00000099 ( - .CI(sig00000026), - .LI(sig0000003f), - .O(sig00000164) - ); - MUXCY blk0000009a ( - .CI(sig00000026), - .DI(sig00000106), - .S(sig0000003f), - .O(sig00000027) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000009b ( - .I0(sig00000106), - .I1(sig00000126), - .O(sig0000003f) - ); - XORCY blk0000009c ( - .CI(sig00000025), - .LI(sig0000003e), - .O(sig00000163) - ); - MUXCY blk0000009d ( - .CI(sig00000025), - .DI(sig00000105), - .S(sig0000003e), - .O(sig00000026) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000009e ( - .I0(sig00000105), - .I1(sig00000125), - .O(sig0000003e) - ); - XORCY blk0000009f ( - .CI(sig00000024), - .LI(sig0000003d), - .O(sig00000162) - ); - MUXCY blk000000a0 ( - .CI(sig00000024), - .DI(sig00000104), - .S(sig0000003d), - .O(sig00000025) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000a1 ( - .I0(sig00000104), - .I1(sig00000124), - .O(sig0000003d) - ); - XORCY blk000000a2 ( - .CI(sig00000023), - .LI(sig0000003c), - .O(sig00000161) - ); - MUXCY blk000000a3 ( - .CI(sig00000023), - .DI(sig00000103), - .S(sig0000003c), - .O(sig00000024) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000a4 ( - .I0(sig00000103), - .I1(sig00000123), - .O(sig0000003c) - ); - XORCY blk000000a5 ( - .CI(sig0000001f), - .LI(sig0000003b), - .O(sig00000160) - ); - MUXCY blk000000a6 ( - .CI(sig0000001f), - .DI(sig00000102), - .S(sig0000003b), - .O(sig00000023) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000a7 ( - .I0(sig00000102), - .I1(sig0000011e), - .O(sig0000003b) - ); - XORCY blk000000a8 ( - .CI(sig00000014), - .LI(sig00000036), - .O(sig0000015b) - ); - MUXCY blk000000a9 ( - .CI(sig00000014), - .DI(sig00000101), - .S(sig00000036), - .O(sig0000001f) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000aa ( - .I0(sig00000101), - .I1(sig00000113), - .O(sig00000036) - ); - XORCY blk000000ab ( - .CI(sig00000012), - .LI(sig0000002b), - .O(sig00000150) - ); - MUXCY blk000000ac ( - .CI(sig00000012), - .DI(sig00000100), - .S(sig0000002b), - .O(sig00000014) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000ad ( - .I0(sig00000100), - .I1(sig00000112), - .O(sig0000002b) - ); - XORCY blk000000ae ( - .CI(sig00000046), - .LI(sig00000054), - .O(sig0000016c) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk000000af ( - .I0(sig0000013a), - .I1(sig00000147), + MUXCY blk00000035 ( + .CI(sig00000053), + .DI(sig00000146), + .S(sig00000074), .O(sig00000054) ); - XORCY blk000000b0 ( - .CI(sig00000045), - .LI(sig00000053), - .O(sig0000016b) - ); - MUXCY blk000000b1 ( - .CI(sig00000045), - .DI(sig0000013a), - .S(sig00000053), - .O(sig00000046) - ); LUT2 #( .INIT ( 4'h6 )) - blk000000b2 ( + blk00000036 ( .I0(sig00000146), - .I1(sig0000013a), + .I1(sig00000121), + .O(sig00000074) + ); + XORCY blk00000037 ( + .CI(sig00000052), + .LI(sig00000073), + .O(p[32]) + ); + MUXCY blk00000038 ( + .CI(sig00000052), + .DI(sig00000145), + .S(sig00000073), .O(sig00000053) ); - XORCY blk000000b3 ( - .CI(sig00000044), - .LI(sig00000052), - .O(sig0000016a) - ); - MUXCY blk000000b4 ( - .CI(sig00000044), - .DI(sig0000013a), - .S(sig00000052), - .O(sig00000045) - ); LUT2 #( .INIT ( 4'h6 )) - blk000000b5 ( + blk00000039 ( .I0(sig00000145), - .I1(sig0000013a), + .I1(sig00000120), + .O(sig00000073) + ); + XORCY blk0000003a ( + .CI(sig00000051), + .LI(sig00000072), + .O(p[31]) + ); + MUXCY blk0000003b ( + .CI(sig00000051), + .DI(sig00000144), + .S(sig00000072), .O(sig00000052) ); - XORCY blk000000b6 ( - .CI(sig0000004f), - .LI(sig00000051), - .O(sig00000169) + LUT2 #( + .INIT ( 4'h6 )) + blk0000003c ( + .I0(sig00000144), + .I1(sig0000011f), + .O(sig00000072) ); - MUXCY blk000000b7 ( - .CI(sig0000004f), - .DI(sig0000013a), - .S(sig00000051), - .O(sig00000044) + XORCY blk0000003d ( + .CI(sig00000050), + .LI(sig00000071), + .O(p[30]) + ); + MUXCY blk0000003e ( + .CI(sig00000050), + .DI(sig00000143), + .S(sig00000071), + .O(sig00000051) ); LUT2 #( .INIT ( 4'h6 )) - blk000000b8 ( - .I0(sig00000144), - .I1(sig0000013a), - .O(sig00000051) + blk0000003f ( + .I0(sig00000143), + .I1(sig0000011e), + .O(sig00000071) ); - XORCY blk000000b9 ( - .CI(sig0000004e), - .LI(sig0000005d), - .O(sig00000175) + XORCY blk00000040 ( + .CI(sig0000004f), + .LI(sig00000070), + .O(p[29]) ); - MUXCY blk000000ba ( + MUXCY blk00000041 ( + .CI(sig0000004f), + .DI(sig00000142), + .S(sig00000070), + .O(sig00000050) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000042 ( + .I0(sig00000142), + .I1(sig0000011d), + .O(sig00000070) + ); + XORCY blk00000043 ( .CI(sig0000004e), - .DI(sig0000013a), - .S(sig0000005d), + .LI(sig0000006f), + .O(p[28]) + ); + MUXCY blk00000044 ( + .CI(sig0000004e), + .DI(sig00000141), + .S(sig0000006f), .O(sig0000004f) ); LUT2 #( .INIT ( 4'h6 )) - blk000000bb ( - .I0(sig0000014f), - .I1(sig0000013a), - .O(sig0000005d) + blk00000045 ( + .I0(sig00000141), + .I1(sig0000011c), + .O(sig0000006f) ); - XORCY blk000000bc ( - .CI(sig0000004d), - .LI(sig0000005c), - .O(sig00000174) + XORCY blk00000046 ( + .CI(sig0000006c), + .LI(sig0000006e), + .O(p[27]) ); - MUXCY blk000000bd ( - .CI(sig0000004d), - .DI(sig0000013a), - .S(sig0000005c), + MUXCY blk00000047 ( + .CI(sig0000006c), + .DI(sig00000140), + .S(sig0000006e), .O(sig0000004e) ); LUT2 #( .INIT ( 4'h6 )) - blk000000be ( - .I0(sig0000014e), - .I1(sig0000013a), - .O(sig0000005c) + blk00000048 ( + .I0(sig00000140), + .I1(sig0000011b), + .O(sig0000006e) ); - XORCY blk000000bf ( - .CI(sig0000004c), - .LI(sig0000005b), - .O(sig00000173) + XORCY blk00000049 ( + .CI(sig0000006b), + .LI(sig0000008d), + .O(p[26]) ); - MUXCY blk000000c0 ( - .CI(sig0000004c), - .DI(sig0000013a), - .S(sig0000005b), + MUXCY blk0000004a ( + .CI(sig0000006b), + .DI(sig00000156), + .S(sig0000008d), + .O(sig0000006c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004b ( + .I0(sig00000156), + .I1(sig00000130), + .O(sig0000008d) + ); + XORCY blk0000004c ( + .CI(sig0000006a), + .LI(sig0000008c), + .O(p[25]) + ); + MUXCY blk0000004d ( + .CI(sig0000006a), + .DI(sig00000155), + .S(sig0000008c), + .O(sig0000006b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004e ( + .I0(sig00000155), + .I1(sig0000012f), + .O(sig0000008c) + ); + XORCY blk0000004f ( + .CI(sig00000069), + .LI(sig0000008b), + .O(p[24]) + ); + MUXCY blk00000050 ( + .CI(sig00000069), + .DI(sig00000154), + .S(sig0000008b), + .O(sig0000006a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000051 ( + .I0(sig00000154), + .I1(sig0000012e), + .O(sig0000008b) + ); + XORCY blk00000052 ( + .CI(sig00000068), + .LI(sig0000008a), + .O(p[23]) + ); + MUXCY blk00000053 ( + .CI(sig00000068), + .DI(sig00000153), + .S(sig0000008a), + .O(sig00000069) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000054 ( + .I0(sig00000153), + .I1(sig0000012d), + .O(sig0000008a) + ); + XORCY blk00000055 ( + .CI(sig00000067), + .LI(sig00000089), + .O(p[22]) + ); + MUXCY blk00000056 ( + .CI(sig00000067), + .DI(sig00000152), + .S(sig00000089), + .O(sig00000068) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000057 ( + .I0(sig00000152), + .I1(sig0000012c), + .O(sig00000089) + ); + XORCY blk00000058 ( + .CI(sig00000066), + .LI(sig00000088), + .O(p[21]) + ); + MUXCY blk00000059 ( + .CI(sig00000066), + .DI(sig00000151), + .S(sig00000088), + .O(sig00000067) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005a ( + .I0(sig00000151), + .I1(sig0000012b), + .O(sig00000088) + ); + XORCY blk0000005b ( + .CI(sig00000063), + .LI(sig00000087), + .O(p[20]) + ); + MUXCY blk0000005c ( + .CI(sig00000063), + .DI(sig00000150), + .S(sig00000087), + .O(sig00000066) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005d ( + .I0(sig00000150), + .I1(sig0000012a), + .O(sig00000087) + ); + XORCY blk0000005e ( + .CI(sig00000058), + .LI(sig00000083), + .O(p[19]) + ); + MUXCY blk0000005f ( + .CI(sig00000058), + .DI(sig0000014f), + .S(sig00000083), + .O(sig00000063) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000060 ( + .I0(sig0000014f), + .I1(sig00000125), + .O(sig00000083) + ); + XORCY blk00000061 ( + .CI(sig0000004d), + .LI(sig00000078), + .O(p[18]) + ); + MUXCY blk00000062 ( + .CI(sig0000004d), + .DI(sig0000014a), + .S(sig00000078), + .O(sig00000058) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000063 ( + .I0(sig0000014a), + .I1(sig0000011a), + .O(sig00000078) + ); + XORCY blk00000064 ( + .CI(sig00000001), + .LI(sig0000006d), + .O(p[17]) + ); + MUXCY blk00000065 ( + .CI(sig00000001), + .DI(sig0000013f), + .S(sig0000006d), .O(sig0000004d) ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000066 ( + .I0(sig0000013f), + .I1(sig00000119), + .O(sig0000006d) + ); + XORCY blk00000067 ( + .CI(sig00000011), + .LI(sig00000029), + .O(sig0000014e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000068 ( + .I0(sig00000100), + .I1(sig00000111), + .O(sig00000029) + ); + XORCY blk00000069 ( + .CI(sig00000010), + .LI(sig00000028), + .O(sig0000014d) + ); + MUXCY blk0000006a ( + .CI(sig00000010), + .DI(sig00000100), + .S(sig00000028), + .O(sig00000011) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006b ( + .I0(sig00000100), + .I1(sig00000110), + .O(sig00000028) + ); + XORCY blk0000006c ( + .CI(sig0000000f), + .LI(sig00000027), + .O(sig0000014c) + ); + MUXCY blk0000006d ( + .CI(sig0000000f), + .DI(sig00000100), + .S(sig00000027), + .O(sig00000010) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006e ( + .I0(sig00000100), + .I1(sig0000010f), + .O(sig00000027) + ); + XORCY blk0000006f ( + .CI(sig0000000d), + .LI(sig00000026), + .O(sig0000014b) + ); + MUXCY blk00000070 ( + .CI(sig0000000d), + .DI(sig00000100), + .S(sig00000026), + .O(sig0000000f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000071 ( + .I0(sig00000100), + .I1(sig0000010e), + .O(sig00000026) + ); + XORCY blk00000072 ( + .CI(sig0000000c), + .LI(sig00000024), + .O(sig00000149) + ); + MUXCY blk00000073 ( + .CI(sig0000000c), + .DI(sig00000100), + .S(sig00000024), + .O(sig0000000d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000074 ( + .I0(sig00000100), + .I1(sig0000010c), + .O(sig00000024) + ); + XORCY blk00000075 ( + .CI(sig0000000b), + .LI(sig00000023), + .O(sig00000148) + ); + MUXCY blk00000076 ( + .CI(sig0000000b), + .DI(sig00000100), + .S(sig00000023), + .O(sig0000000c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000077 ( + .I0(sig00000100), + .I1(sig0000010b), + .O(sig00000023) + ); + XORCY blk00000078 ( + .CI(sig0000000a), + .LI(sig00000022), + .O(sig00000147) + ); + MUXCY blk00000079 ( + .CI(sig0000000a), + .DI(sig00000100), + .S(sig00000022), + .O(sig0000000b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007a ( + .I0(sig00000100), + .I1(sig0000010a), + .O(sig00000022) + ); + XORCY blk0000007b ( + .CI(sig00000009), + .LI(sig00000021), + .O(sig00000146) + ); + MUXCY blk0000007c ( + .CI(sig00000009), + .DI(sig000000ff), + .S(sig00000021), + .O(sig0000000a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007d ( + .I0(sig000000ff), + .I1(sig00000109), + .O(sig00000021) + ); + XORCY blk0000007e ( + .CI(sig00000008), + .LI(sig00000020), + .O(sig00000145) + ); + MUXCY blk0000007f ( + .CI(sig00000008), + .DI(sig000000fe), + .S(sig00000020), + .O(sig00000009) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000080 ( + .I0(sig000000fe), + .I1(sig00000108), + .O(sig00000020) + ); + XORCY blk00000081 ( + .CI(sig00000007), + .LI(sig0000001f), + .O(sig00000144) + ); + MUXCY blk00000082 ( + .CI(sig00000007), + .DI(sig000000fd), + .S(sig0000001f), + .O(sig00000008) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000083 ( + .I0(sig000000fd), + .I1(sig00000107), + .O(sig0000001f) + ); + XORCY blk00000084 ( + .CI(sig00000006), + .LI(sig0000001e), + .O(sig00000143) + ); + MUXCY blk00000085 ( + .CI(sig00000006), + .DI(sig000000fc), + .S(sig0000001e), + .O(sig00000007) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000086 ( + .I0(sig000000fc), + .I1(sig00000106), + .O(sig0000001e) + ); + XORCY blk00000087 ( + .CI(sig00000005), + .LI(sig0000001d), + .O(sig00000142) + ); + MUXCY blk00000088 ( + .CI(sig00000005), + .DI(sig000000fb), + .S(sig0000001d), + .O(sig00000006) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000089 ( + .I0(sig000000fb), + .I1(sig00000105), + .O(sig0000001d) + ); + XORCY blk0000008a ( + .CI(sig00000004), + .LI(sig0000001c), + .O(sig00000141) + ); + MUXCY blk0000008b ( + .CI(sig00000004), + .DI(sig000000fa), + .S(sig0000001c), + .O(sig00000005) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008c ( + .I0(sig000000fa), + .I1(sig00000104), + .O(sig0000001c) + ); + XORCY blk0000008d ( + .CI(sig00000019), + .LI(sig0000001b), + .O(sig00000140) + ); + MUXCY blk0000008e ( + .CI(sig00000019), + .DI(sig000000f9), + .S(sig0000001b), + .O(sig00000004) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008f ( + .I0(sig000000f9), + .I1(sig00000103), + .O(sig0000001b) + ); + XORCY blk00000090 ( + .CI(sig00000018), + .LI(sig00000031), + .O(sig00000156) + ); + MUXCY blk00000091 ( + .CI(sig00000018), + .DI(sig000000f8), + .S(sig00000031), + .O(sig00000019) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000092 ( + .I0(sig000000f8), + .I1(sig00000118), + .O(sig00000031) + ); + XORCY blk00000093 ( + .CI(sig00000017), + .LI(sig00000030), + .O(sig00000155) + ); + MUXCY blk00000094 ( + .CI(sig00000017), + .DI(sig000000f7), + .S(sig00000030), + .O(sig00000018) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000095 ( + .I0(sig000000f7), + .I1(sig00000117), + .O(sig00000030) + ); + XORCY blk00000096 ( + .CI(sig00000016), + .LI(sig0000002f), + .O(sig00000154) + ); + MUXCY blk00000097 ( + .CI(sig00000016), + .DI(sig000000f6), + .S(sig0000002f), + .O(sig00000017) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000098 ( + .I0(sig000000f6), + .I1(sig00000116), + .O(sig0000002f) + ); + XORCY blk00000099 ( + .CI(sig00000015), + .LI(sig0000002e), + .O(sig00000153) + ); + MUXCY blk0000009a ( + .CI(sig00000015), + .DI(sig000000f5), + .S(sig0000002e), + .O(sig00000016) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009b ( + .I0(sig000000f5), + .I1(sig00000115), + .O(sig0000002e) + ); + XORCY blk0000009c ( + .CI(sig00000014), + .LI(sig0000002d), + .O(sig00000152) + ); + MUXCY blk0000009d ( + .CI(sig00000014), + .DI(sig000000f4), + .S(sig0000002d), + .O(sig00000015) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009e ( + .I0(sig000000f4), + .I1(sig00000114), + .O(sig0000002d) + ); + XORCY blk0000009f ( + .CI(sig00000013), + .LI(sig0000002c), + .O(sig00000151) + ); + MUXCY blk000000a0 ( + .CI(sig00000013), + .DI(sig000000f3), + .S(sig0000002c), + .O(sig00000014) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a1 ( + .I0(sig000000f3), + .I1(sig00000113), + .O(sig0000002c) + ); + XORCY blk000000a2 ( + .CI(sig00000012), + .LI(sig0000002b), + .O(sig00000150) + ); + MUXCY blk000000a3 ( + .CI(sig00000012), + .DI(sig000000f2), + .S(sig0000002b), + .O(sig00000013) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a4 ( + .I0(sig000000f2), + .I1(sig00000112), + .O(sig0000002b) + ); + XORCY blk000000a5 ( + .CI(sig0000000e), + .LI(sig0000002a), + .O(sig0000014f) + ); + MUXCY blk000000a6 ( + .CI(sig0000000e), + .DI(sig000000f1), + .S(sig0000002a), + .O(sig00000012) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a7 ( + .I0(sig000000f1), + .I1(sig0000010d), + .O(sig0000002a) + ); + XORCY blk000000a8 ( + .CI(sig00000003), + .LI(sig00000025), + .O(sig0000014a) + ); + MUXCY blk000000a9 ( + .CI(sig00000003), + .DI(sig000000f0), + .S(sig00000025), + .O(sig0000000e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000aa ( + .I0(sig000000f0), + .I1(sig00000102), + .O(sig00000025) + ); + XORCY blk000000ab ( + .CI(sig00000001), + .LI(sig0000001a), + .O(sig0000013f) + ); + MUXCY blk000000ac ( + .CI(sig00000001), + .DI(sig000000ef), + .S(sig0000001a), + .O(sig00000003) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000ad ( + .I0(sig000000ef), + .I1(sig00000101), + .O(sig0000001a) + ); + XORCY blk000000ae ( + .CI(sig00000035), + .LI(sig00000043), + .O(sig0000015b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000af ( + .I0(sig00000129), + .I1(sig00000136), + .O(sig00000043) + ); + XORCY blk000000b0 ( + .CI(sig00000034), + .LI(sig00000042), + .O(sig0000015a) + ); + MUXCY blk000000b1 ( + .CI(sig00000034), + .DI(sig00000129), + .S(sig00000042), + .O(sig00000035) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b2 ( + .I0(sig00000129), + .I1(sig00000135), + .O(sig00000042) + ); + XORCY blk000000b3 ( + .CI(sig00000033), + .LI(sig00000041), + .O(sig00000159) + ); + MUXCY blk000000b4 ( + .CI(sig00000033), + .DI(sig00000129), + .S(sig00000041), + .O(sig00000034) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b5 ( + .I0(sig00000129), + .I1(sig00000134), + .O(sig00000041) + ); + XORCY blk000000b6 ( + .CI(sig0000003e), + .LI(sig00000040), + .O(sig00000158) + ); + MUXCY blk000000b7 ( + .CI(sig0000003e), + .DI(sig00000129), + .S(sig00000040), + .O(sig00000033) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b8 ( + .I0(sig00000129), + .I1(sig00000133), + .O(sig00000040) + ); + XORCY blk000000b9 ( + .CI(sig0000003d), + .LI(sig0000004c), + .O(sig00000164) + ); + MUXCY blk000000ba ( + .CI(sig0000003d), + .DI(sig00000129), + .S(sig0000004c), + .O(sig0000003e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000bb ( + .I0(sig00000129), + .I1(sig0000013e), + .O(sig0000004c) + ); + XORCY blk000000bc ( + .CI(sig0000003c), + .LI(sig0000004b), + .O(sig00000163) + ); + MUXCY blk000000bd ( + .CI(sig0000003c), + .DI(sig00000129), + .S(sig0000004b), + .O(sig0000003d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000be ( + .I0(sig00000129), + .I1(sig0000013d), + .O(sig0000004b) + ); + XORCY blk000000bf ( + .CI(sig0000003b), + .LI(sig0000004a), + .O(sig00000162) + ); + MUXCY blk000000c0 ( + .CI(sig0000003b), + .DI(sig00000129), + .S(sig0000004a), + .O(sig0000003c) + ); LUT2 #( .INIT ( 4'h6 )) blk000000c1 ( - .I0(sig0000014d), - .I1(sig0000013a), - .O(sig0000005b) + .I0(sig00000129), + .I1(sig0000013c), + .O(sig0000004a) ); XORCY blk000000c2 ( - .CI(sig0000004b), - .LI(sig0000005a), - .O(sig00000172) + .CI(sig0000003a), + .LI(sig00000049), + .O(sig00000161) ); MUXCY blk000000c3 ( - .CI(sig0000004b), - .DI(sig0000013a), - .S(sig0000005a), - .O(sig0000004c) + .CI(sig0000003a), + .DI(sig00000129), + .S(sig00000049), + .O(sig0000003b) ); LUT2 #( .INIT ( 4'h6 )) blk000000c4 ( - .I0(sig0000014c), - .I1(sig0000013a), - .O(sig0000005a) + .I0(sig00000129), + .I1(sig0000013b), + .O(sig00000049) ); XORCY blk000000c5 ( - .CI(sig0000004a), - .LI(sig00000059), - .O(sig00000171) + .CI(sig00000039), + .LI(sig00000048), + .O(sig00000160) ); MUXCY blk000000c6 ( - .CI(sig0000004a), - .DI(sig00000139), - .S(sig00000059), - .O(sig0000004b) + .CI(sig00000039), + .DI(sig00000128), + .S(sig00000048), + .O(sig0000003a) ); LUT2 #( .INIT ( 4'h6 )) blk000000c7 ( - .I0(sig00000139), - .I1(sig0000014b), - .O(sig00000059) + .I0(sig00000128), + .I1(sig0000013a), + .O(sig00000048) ); XORCY blk000000c8 ( - .CI(sig00000049), - .LI(sig00000058), - .O(sig00000170) + .CI(sig00000038), + .LI(sig00000047), + .O(sig0000015f) ); MUXCY blk000000c9 ( - .CI(sig00000049), - .DI(sig00000138), - .S(sig00000058), - .O(sig0000004a) + .CI(sig00000038), + .DI(sig00000127), + .S(sig00000047), + .O(sig00000039) ); LUT2 #( .INIT ( 4'h6 )) blk000000ca ( - .I0(sig00000138), - .I1(sig0000014a), - .O(sig00000058) + .I0(sig00000127), + .I1(sig00000139), + .O(sig00000047) ); XORCY blk000000cb ( - .CI(sig00000048), - .LI(sig00000057), - .O(sig0000016f) + .CI(sig00000037), + .LI(sig00000046), + .O(sig0000015e) ); MUXCY blk000000cc ( - .CI(sig00000048), - .DI(sig00000137), - .S(sig00000057), - .O(sig00000049) + .CI(sig00000037), + .DI(sig00000126), + .S(sig00000046), + .O(sig00000038) ); LUT2 #( .INIT ( 4'h6 )) blk000000cd ( - .I0(sig00000137), - .I1(sig00000149), - .O(sig00000057) + .I0(sig00000126), + .I1(sig00000138), + .O(sig00000046) ); XORCY blk000000ce ( - .CI(sig00000047), - .LI(sig00000056), - .O(sig0000016e) + .CI(sig00000036), + .LI(sig00000045), + .O(sig0000015d) ); MUXCY blk000000cf ( - .CI(sig00000047), - .DI(sig00000135), - .S(sig00000056), - .O(sig00000048) + .CI(sig00000036), + .DI(sig00000124), + .S(sig00000045), + .O(sig00000037) ); LUT2 #( .INIT ( 4'h6 )) blk000000d0 ( - .I0(sig00000135), - .I1(sig00000148), - .O(sig00000056) + .I0(sig00000124), + .I1(sig00000137), + .O(sig00000045) ); XORCY blk000000d1 ( - .CI(sig00000043), - .LI(sig00000055), - .O(sig0000016d) + .CI(sig00000032), + .LI(sig00000044), + .O(sig0000015c) ); MUXCY blk000000d2 ( - .CI(sig00000043), - .DI(sig00000134), - .S(sig00000055), - .O(sig00000047) + .CI(sig00000032), + .DI(sig00000123), + .S(sig00000044), + .O(sig00000036) ); LUT2 #( .INIT ( 4'h6 )) blk000000d3 ( - .I0(sig00000134), - .I1(sig00000143), - .O(sig00000055) + .I0(sig00000123), + .I1(sig00000132), + .O(sig00000044) ); XORCY blk000000d4 ( - .CI(sig00000012), - .LI(sig00000050), - .O(sig00000168) + .CI(sig00000001), + .LI(sig0000003f), + .O(sig00000157) ); MUXCY blk000000d5 ( - .CI(sig00000012), - .DI(sig00000133), - .S(sig00000050), - .O(sig00000043) + .CI(sig00000001), + .DI(sig00000122), + .S(sig0000003f), + .O(sig00000032) ); LUT2 #( .INIT ( 4'h6 )) blk000000d6 ( - .I0(sig00000133), - .I1(sig00000142), - .O(sig00000050) + .I0(sig00000122), + .I1(sig00000131), + .O(sig0000003f) ); FD #( .INIT ( 1'b0 )) blk000000d7 ( .C(clk), - .D(sig0000018f), - .Q(p[47]) + .D(sig000000d8), + .Q(sig00000129) ); FD #( .INIT ( 1'b0 )) blk000000d8 ( .C(clk), - .D(sig0000018b), - .Q(p[46]) + .D(sig000000d7), + .Q(sig00000128) ); FD #( .INIT ( 1'b0 )) blk000000d9 ( .C(clk), - .D(sig0000018a), - .Q(p[45]) + .D(sig000000d6), + .Q(sig00000127) ); FD #( .INIT ( 1'b0 )) blk000000da ( .C(clk), - .D(sig00000189), - .Q(p[44]) + .D(sig000000d5), + .Q(sig00000126) ); FD #( .INIT ( 1'b0 )) blk000000db ( .C(clk), - .D(sig00000188), - .Q(p[43]) + .D(sig000000d3), + .Q(sig00000124) ); FD #( .INIT ( 1'b0 )) blk000000dc ( .C(clk), - .D(sig00000187), - .Q(p[42]) + .D(sig000000d2), + .Q(sig00000123) ); FD #( .INIT ( 1'b0 )) blk000000dd ( .C(clk), - .D(sig00000186), - .Q(p[41]) + .D(sig000000d1), + .Q(sig00000122) ); FD #( .INIT ( 1'b0 )) blk000000de ( .C(clk), - .D(sig00000185), - .Q(p[40]) + .D(sig000000d0), + .Q(sig00000121) ); FD #( .INIT ( 1'b0 )) blk000000df ( .C(clk), - .D(sig00000184), - .Q(p[39]) + .D(sig000000cf), + .Q(sig00000120) ); FD #( .INIT ( 1'b0 )) blk000000e0 ( .C(clk), - .D(sig00000183), - .Q(p[38]) + .D(sig000000ce), + .Q(sig0000011f) ); FD #( .INIT ( 1'b0 )) blk000000e1 ( .C(clk), - .D(sig00000182), - .Q(p[37]) + .D(sig000000cd), + .Q(sig0000011e) ); FD #( .INIT ( 1'b0 )) blk000000e2 ( .C(clk), - .D(sig00000180), - .Q(p[36]) + .D(sig000000cc), + .Q(sig0000011d) ); FD #( .INIT ( 1'b0 )) blk000000e3 ( .C(clk), - .D(sig0000017f), - .Q(p[35]) + .D(sig000000cb), + .Q(sig0000011c) ); FD #( .INIT ( 1'b0 )) blk000000e4 ( .C(clk), - .D(sig0000017e), - .Q(p[34]) + .D(sig000000ca), + .Q(sig0000011b) ); FD #( .INIT ( 1'b0 )) blk000000e5 ( .C(clk), - .D(sig0000017d), - .Q(p[33]) + .D(sig000000e0), + .Q(sig00000130) ); FD #( .INIT ( 1'b0 )) blk000000e6 ( .C(clk), - .D(sig0000017c), - .Q(p[32]) + .D(sig000000df), + .Q(sig0000012f) ); FD #( .INIT ( 1'b0 )) blk000000e7 ( .C(clk), - .D(sig0000017b), - .Q(p[31]) + .D(sig000000de), + .Q(sig0000012e) ); FD #( .INIT ( 1'b0 )) blk000000e8 ( .C(clk), - .D(sig0000017a), - .Q(p[30]) + .D(sig000000dd), + .Q(sig0000012d) ); FD #( .INIT ( 1'b0 )) blk000000e9 ( .C(clk), - .D(sig00000179), - .Q(p[29]) + .D(sig000000dc), + .Q(sig0000012c) ); FD #( .INIT ( 1'b0 )) blk000000ea ( .C(clk), - .D(sig00000178), - .Q(p[28]) + .D(sig000000db), + .Q(sig0000012b) ); FD #( .INIT ( 1'b0 )) blk000000eb ( .C(clk), - .D(sig00000177), - .Q(p[27]) + .D(sig000000da), + .Q(sig0000012a) ); FD #( .INIT ( 1'b0 )) blk000000ec ( .C(clk), - .D(sig00000194), - .Q(p[26]) + .D(sig000000d9), + .Q(sig00000125) ); FD #( .INIT ( 1'b0 )) blk000000ed ( .C(clk), - .D(sig00000193), - .Q(p[25]) + .D(sig000000d4), + .Q(sig0000011a) ); FD #( .INIT ( 1'b0 )) blk000000ee ( .C(clk), - .D(sig00000192), - .Q(p[24]) + .D(sig000000c9), + .Q(sig00000119) ); FD #( .INIT ( 1'b0 )) blk000000ef ( .C(clk), - .D(sig00000191), - .Q(p[23]) + .D(sig000000c0), + .Q(sig00000111) ); FD #( .INIT ( 1'b0 )) blk000000f0 ( .C(clk), - .D(sig00000190), - .Q(p[22]) + .D(sig000000bf), + .Q(sig00000110) ); FD #( .INIT ( 1'b0 )) blk000000f1 ( .C(clk), - .D(sig0000018e), - .Q(p[21]) + .D(sig000000be), + .Q(sig0000010f) ); FD #( .INIT ( 1'b0 )) blk000000f2 ( .C(clk), - .D(sig0000018d), - .Q(p[20]) + .D(sig000000bd), + .Q(sig0000010e) ); FD #( .INIT ( 1'b0 )) blk000000f3 ( .C(clk), - .D(sig0000018c), - .Q(p[19]) + .D(sig000000bb), + .Q(sig0000010c) ); FD #( .INIT ( 1'b0 )) blk000000f4 ( .C(clk), - .D(sig00000181), - .Q(p[18]) + .D(sig000000ba), + .Q(sig0000010b) ); FD #( .INIT ( 1'b0 )) blk000000f5 ( .C(clk), - .D(sig00000176), - .Q(p[17]) + .D(sig000000b9), + .Q(sig0000010a) ); FD #( .INIT ( 1'b0 )) blk000000f6 ( .C(clk), - .D(sig000000f6), - .Q(sig00000147) + .D(sig000000b8), + .Q(sig00000109) ); FD #( .INIT ( 1'b0 )) blk000000f7 ( .C(clk), - .D(sig000000f5), - .Q(sig00000146) + .D(sig000000b7), + .Q(sig00000108) ); FD #( .INIT ( 1'b0 )) blk000000f8 ( .C(clk), - .D(sig000000f4), - .Q(sig00000145) + .D(sig000000b6), + .Q(sig00000107) ); FD #( .INIT ( 1'b0 )) blk000000f9 ( .C(clk), - .D(sig000000f3), - .Q(sig00000144) + .D(sig000000b5), + .Q(sig00000106) ); FD #( .INIT ( 1'b0 )) blk000000fa ( .C(clk), - .D(sig000000ff), - .Q(sig0000014f) + .D(sig000000b4), + .Q(sig00000105) ); FD #( .INIT ( 1'b0 )) blk000000fb ( .C(clk), - .D(sig000000fe), - .Q(sig0000014e) + .D(sig000000b3), + .Q(sig00000104) ); FD #( .INIT ( 1'b0 )) blk000000fc ( .C(clk), - .D(sig000000fd), - .Q(sig0000014d) + .D(sig000000b2), + .Q(sig00000103) ); FD #( .INIT ( 1'b0 )) blk000000fd ( .C(clk), - .D(sig000000fc), - .Q(sig0000014c) + .D(sig000000c8), + .Q(sig00000118) ); FD #( .INIT ( 1'b0 )) blk000000fe ( .C(clk), - .D(sig000000fb), - .Q(sig0000014b) + .D(sig000000c7), + .Q(sig00000117) ); FD #( .INIT ( 1'b0 )) blk000000ff ( .C(clk), - .D(sig000000fa), - .Q(sig0000014a) + .D(sig000000c6), + .Q(sig00000116) ); FD #( .INIT ( 1'b0 )) blk00000100 ( .C(clk), - .D(sig000000f9), - .Q(sig00000149) + .D(sig000000c5), + .Q(sig00000115) ); FD #( .INIT ( 1'b0 )) blk00000101 ( .C(clk), - .D(sig000000f8), - .Q(sig00000148) + .D(sig000000c4), + .Q(sig00000114) ); FD #( .INIT ( 1'b0 )) blk00000102 ( .C(clk), - .D(sig000000f7), - .Q(sig00000143) + .D(sig000000c3), + .Q(sig00000113) ); FD #( .INIT ( 1'b0 )) blk00000103 ( .C(clk), - .D(sig000000f2), - .Q(sig00000142) + .D(sig000000c2), + .Q(sig00000112) ); FD #( .INIT ( 1'b0 )) blk00000104 ( .C(clk), - .D(sig000000e9), - .Q(sig0000013a) + .D(sig000000c1), + .Q(sig0000010d) ); FD #( .INIT ( 1'b0 )) blk00000105 ( .C(clk), - .D(sig000000e8), - .Q(sig00000139) + .D(sig000000bc), + .Q(sig00000102) ); FD #( .INIT ( 1'b0 )) blk00000106 ( .C(clk), - .D(sig000000e7), - .Q(sig00000138) + .D(sig000000b1), + .Q(sig00000101) ); FD #( .INIT ( 1'b0 )) blk00000107 ( .C(clk), - .D(sig000000e6), - .Q(sig00000137) + .D(sig000000e5), + .Q(sig00000136) ); FD #( .INIT ( 1'b0 )) @@ -2168,720 +2120,316 @@ sig000000bc, sig000000bb, sig000000b5, sig000000aa, sig0000009f}) FD #( .INIT ( 1'b0 )) blk0000010b ( - .C(clk), - .D(sig000000e1), - .Q(sig00000132) - ); - FD #( - .INIT ( 1'b0 )) - blk0000010c ( - .C(clk), - .D(sig000000e0), - .Q(sig00000131) - ); - FD #( - .INIT ( 1'b0 )) - blk0000010d ( - .C(clk), - .D(sig000000df), - .Q(sig00000130) - ); - FD #( - .INIT ( 1'b0 )) - blk0000010e ( - .C(clk), - .D(sig000000de), - .Q(sig0000012f) - ); - FD #( - .INIT ( 1'b0 )) - blk0000010f ( - .C(clk), - .D(sig000000dd), - .Q(sig0000012e) - ); - FD #( - .INIT ( 1'b0 )) - blk00000110 ( - .C(clk), - .D(sig000000dc), - .Q(sig0000012d) - ); - FD #( - .INIT ( 1'b0 )) - blk00000111 ( - .C(clk), - .D(sig000000db), - .Q(sig0000012c) - ); - FD #( - .INIT ( 1'b0 )) - blk00000112 ( - .C(clk), - .D(sig000000f1), - .Q(sig00000141) - ); - FD #( - .INIT ( 1'b0 )) - blk00000113 ( - .C(clk), - .D(sig000000f0), - .Q(sig00000140) - ); - FD #( - .INIT ( 1'b0 )) - blk00000114 ( - .C(clk), - .D(sig000000ef), - .Q(sig0000013f) - ); - FD #( - .INIT ( 1'b0 )) - blk00000115 ( .C(clk), .D(sig000000ee), .Q(sig0000013e) ); FD #( .INIT ( 1'b0 )) - blk00000116 ( + blk0000010c ( .C(clk), .D(sig000000ed), .Q(sig0000013d) ); FD #( .INIT ( 1'b0 )) - blk00000117 ( + blk0000010d ( .C(clk), .D(sig000000ec), .Q(sig0000013c) ); FD #( .INIT ( 1'b0 )) - blk00000118 ( + blk0000010e ( .C(clk), .D(sig000000eb), .Q(sig0000013b) ); FD #( .INIT ( 1'b0 )) - blk00000119 ( + blk0000010f ( .C(clk), .D(sig000000ea), - .Q(sig00000136) + .Q(sig0000013a) + ); + FD #( + .INIT ( 1'b0 )) + blk00000110 ( + .C(clk), + .D(sig000000e9), + .Q(sig00000139) + ); + FD #( + .INIT ( 1'b0 )) + blk00000111 ( + .C(clk), + .D(sig000000e8), + .Q(sig00000138) + ); + FD #( + .INIT ( 1'b0 )) + blk00000112 ( + .C(clk), + .D(sig000000e7), + .Q(sig00000137) + ); + FD #( + .INIT ( 1'b0 )) + blk00000113 ( + .C(clk), + .D(sig000000e6), + .Q(sig00000132) + ); + FD #( + .INIT ( 1'b0 )) + blk00000114 ( + .C(clk), + .D(sig000000e1), + .Q(sig00000131) + ); + FD #( + .INIT ( 1'b0 )) + blk00000115 ( + .C(clk), + .D(sig000000a9), + .Q(sig00000100) + ); + FD #( + .INIT ( 1'b0 )) + blk00000116 ( + .C(clk), + .D(sig000000a8), + .Q(sig000000ff) + ); + FD #( + .INIT ( 1'b0 )) + blk00000117 ( + .C(clk), + .D(sig000000a7), + .Q(sig000000fe) + ); + FD #( + .INIT ( 1'b0 )) + blk00000118 ( + .C(clk), + .D(sig000000a6), + .Q(sig000000fd) + ); + FD #( + .INIT ( 1'b0 )) + blk00000119 ( + .C(clk), + .D(sig000000a5), + .Q(sig000000fc) ); FD #( .INIT ( 1'b0 )) blk0000011a ( .C(clk), - .D(sig000000e5), - .Q(sig0000012b) + .D(sig000000a3), + .Q(sig000000fb) ); FD #( .INIT ( 1'b0 )) blk0000011b ( .C(clk), - .D(sig000000da), - .Q(sig0000012a) + .D(sig000000a2), + .Q(sig000000fa) ); FD #( .INIT ( 1'b0 )) blk0000011c ( .C(clk), - .D(sig000000d1), - .Q(sig00000122) + .D(sig000000a1), + .Q(sig000000f9) ); FD #( .INIT ( 1'b0 )) blk0000011d ( .C(clk), - .D(sig000000d0), - .Q(sig00000121) + .D(sig000000a0), + .Q(sig000000f8) ); FD #( .INIT ( 1'b0 )) blk0000011e ( .C(clk), - .D(sig000000cf), - .Q(sig00000120) + .D(sig0000009f), + .Q(sig000000f7) ); FD #( .INIT ( 1'b0 )) blk0000011f ( .C(clk), - .D(sig000000ce), - .Q(sig0000011f) + .D(sig0000009e), + .Q(sig000000f6) ); FD #( .INIT ( 1'b0 )) blk00000120 ( .C(clk), - .D(sig000000cc), - .Q(sig0000011d) + .D(sig0000009d), + .Q(sig000000f5) ); FD #( .INIT ( 1'b0 )) blk00000121 ( .C(clk), - .D(sig000000cb), - .Q(sig0000011c) + .D(sig0000009c), + .Q(sig000000f4) ); FD #( .INIT ( 1'b0 )) blk00000122 ( .C(clk), - .D(sig000000ca), - .Q(sig0000011b) + .D(sig0000009b), + .Q(sig000000f3) ); FD #( .INIT ( 1'b0 )) blk00000123 ( .C(clk), - .D(sig000000c9), - .Q(sig0000011a) + .D(sig0000009a), + .Q(sig000000f2) ); FD #( .INIT ( 1'b0 )) blk00000124 ( .C(clk), - .D(sig000000c8), - .Q(sig00000119) + .D(sig00000098), + .Q(sig000000f1) ); FD #( .INIT ( 1'b0 )) blk00000125 ( .C(clk), - .D(sig000000c7), - .Q(sig00000118) + .D(sig00000097), + .Q(sig000000f0) ); FD #( .INIT ( 1'b0 )) blk00000126 ( .C(clk), - .D(sig000000c6), - .Q(sig00000117) + .D(sig00000096), + .Q(sig000000ef) ); FD #( .INIT ( 1'b0 )) blk00000127 ( .C(clk), - .D(sig000000c5), - .Q(sig00000116) + .D(sig00000095), + .Q(p[16]) ); FD #( .INIT ( 1'b0 )) blk00000128 ( .C(clk), - .D(sig000000c4), - .Q(sig00000115) + .D(sig00000094), + .Q(p[15]) ); FD #( .INIT ( 1'b0 )) blk00000129 ( .C(clk), - .D(sig000000c3), - .Q(sig00000114) + .D(sig00000093), + .Q(p[14]) ); FD #( .INIT ( 1'b0 )) blk0000012a ( .C(clk), - .D(sig000000d9), - .Q(sig00000129) + .D(sig00000092), + .Q(p[13]) ); FD #( .INIT ( 1'b0 )) blk0000012b ( .C(clk), - .D(sig000000d8), - .Q(sig00000128) + .D(sig00000091), + .Q(p[12]) ); FD #( .INIT ( 1'b0 )) blk0000012c ( .C(clk), - .D(sig000000d7), - .Q(sig00000127) + .D(sig00000090), + .Q(p[11]) ); FD #( .INIT ( 1'b0 )) blk0000012d ( .C(clk), - .D(sig000000d6), - .Q(sig00000126) + .D(sig0000008f), + .Q(p[10]) ); FD #( .INIT ( 1'b0 )) blk0000012e ( .C(clk), - .D(sig000000d5), - .Q(sig00000125) + .D(sig000000b0), + .Q(p[9]) ); FD #( .INIT ( 1'b0 )) blk0000012f ( .C(clk), - .D(sig000000d4), - .Q(sig00000124) + .D(sig000000af), + .Q(p[8]) ); FD #( .INIT ( 1'b0 )) blk00000130 ( .C(clk), - .D(sig000000d3), - .Q(sig00000123) + .D(sig000000ae), + .Q(p[7]) ); FD #( .INIT ( 1'b0 )) blk00000131 ( .C(clk), - .D(sig000000d2), - .Q(sig0000011e) + .D(sig000000ad), + .Q(p[6]) ); FD #( .INIT ( 1'b0 )) blk00000132 ( .C(clk), - .D(sig000000cd), - .Q(sig00000113) + .D(sig000000ac), + .Q(p[5]) ); FD #( .INIT ( 1'b0 )) blk00000133 ( .C(clk), - .D(sig000000c2), - .Q(sig00000112) + .D(sig000000ab), + .Q(p[4]) ); FD #( .INIT ( 1'b0 )) blk00000134 ( .C(clk), - .D(sig000000ba), - .Q(sig00000111) + .D(sig000000aa), + .Q(p[3]) ); FD #( .INIT ( 1'b0 )) blk00000135 ( .C(clk), - .D(sig000000b9), - .Q(sig00000110) + .D(sig000000a4), + .Q(p[2]) ); FD #( .INIT ( 1'b0 )) blk00000136 ( .C(clk), - .D(sig000000b8), - .Q(sig0000010f) + .D(sig00000099), + .Q(p[1]) ); FD #( .INIT ( 1'b0 )) blk00000137 ( .C(clk), - .D(sig000000b7), - .Q(sig0000010e) - ); - FD #( - .INIT ( 1'b0 )) - blk00000138 ( - .C(clk), - .D(sig000000b6), - .Q(sig0000010d) - ); - FD #( - .INIT ( 1'b0 )) - blk00000139 ( - .C(clk), - .D(sig000000b4), - .Q(sig0000010c) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013a ( - .C(clk), - .D(sig000000b3), - .Q(sig0000010b) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013b ( - .C(clk), - .D(sig000000b2), - .Q(sig0000010a) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013c ( - .C(clk), - .D(sig000000b1), - .Q(sig00000109) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013d ( - .C(clk), - .D(sig000000b0), - .Q(sig00000108) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013e ( - .C(clk), - .D(sig000000af), - .Q(sig00000107) - ); - FD #( - .INIT ( 1'b0 )) - blk0000013f ( - .C(clk), - .D(sig000000ae), - .Q(sig00000106) - ); - FD #( - .INIT ( 1'b0 )) - blk00000140 ( - .C(clk), - .D(sig000000ad), - .Q(sig00000105) - ); - FD #( - .INIT ( 1'b0 )) - blk00000141 ( - .C(clk), - .D(sig000000ac), - .Q(sig00000104) - ); - FD #( - .INIT ( 1'b0 )) - blk00000142 ( - .C(clk), - .D(sig000000ab), - .Q(sig00000103) - ); - FD #( - .INIT ( 1'b0 )) - blk00000143 ( - .C(clk), - .D(sig000000a9), - .Q(sig00000102) - ); - FD #( - .INIT ( 1'b0 )) - blk00000144 ( - .C(clk), - .D(sig000000a8), - .Q(sig00000101) - ); - FD #( - .INIT ( 1'b0 )) - blk00000145 ( - .C(clk), - .D(sig000000a7), - .Q(sig00000100) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000146 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a4), - .Q(sig00000007) - ); - FD #( - .INIT ( 1'b0 )) - blk00000147 ( - .C(clk), - .D(sig00000007), - .Q(p[14]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000148 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a6), - .Q(sig00000009) - ); - FD #( - .INIT ( 1'b0 )) - blk00000149 ( - .C(clk), - .D(sig00000009), - .Q(p[16]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000014a ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a5), - .Q(sig00000008) - ); - FD #( - .INIT ( 1'b0 )) - blk0000014b ( - .C(clk), - .D(sig00000008), - .Q(p[15]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000014c ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a3), - .Q(sig00000006) - ); - FD #( - .INIT ( 1'b0 )) - blk0000014d ( - .C(clk), - .D(sig00000006), - .Q(p[13]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000014e ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a2), - .Q(sig00000005) - ); - FD #( - .INIT ( 1'b0 )) - blk0000014f ( - .C(clk), - .D(sig00000005), - .Q(p[12]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000150 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a1), - .Q(sig00000004) - ); - FD #( - .INIT ( 1'b0 )) - blk00000151 ( - .C(clk), - .D(sig00000004), - .Q(p[11]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000152 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000a0), - .Q(sig00000003) - ); - FD #( - .INIT ( 1'b0 )) - blk00000153 ( - .C(clk), - .D(sig00000003), - .Q(p[10]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000154 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000c1), - .Q(sig00000011) - ); - FD #( - .INIT ( 1'b0 )) - blk00000155 ( - .C(clk), - .D(sig00000011), - .Q(p[9]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000156 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000c0), - .Q(sig00000010) - ); - FD #( - .INIT ( 1'b0 )) - blk00000157 ( - .C(clk), - .D(sig00000010), - .Q(p[8]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000158 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000bf), - .Q(sig0000000f) - ); - FD #( - .INIT ( 1'b0 )) - blk00000159 ( - .C(clk), - .D(sig0000000f), - .Q(p[7]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000015a ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000be), - .Q(sig0000000e) - ); - FD #( - .INIT ( 1'b0 )) - blk0000015b ( - .C(clk), - .D(sig0000000e), - .Q(p[6]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000015c ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000bd), - .Q(sig0000000d) - ); - FD #( - .INIT ( 1'b0 )) - blk0000015d ( - .C(clk), - .D(sig0000000d), - .Q(p[5]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk0000015e ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000bc), - .Q(sig0000000c) - ); - FD #( - .INIT ( 1'b0 )) - blk0000015f ( - .C(clk), - .D(sig0000000c), - .Q(p[4]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000160 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000bb), - .Q(sig0000000b) - ); - FD #( - .INIT ( 1'b0 )) - blk00000161 ( - .C(clk), - .D(sig0000000b), - .Q(p[3]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000162 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000b5), - .Q(sig0000000a) - ); - FD #( - .INIT ( 1'b0 )) - blk00000163 ( - .C(clk), - .D(sig0000000a), - .Q(p[2]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000164 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig000000aa), - .Q(sig00000002) - ); - FD #( - .INIT ( 1'b0 )) - blk00000165 ( - .C(clk), - .D(sig00000002), - .Q(p[1]) - ); - SRL16 #( - .INIT ( 16'h0000 )) - blk00000166 ( - .A0(sig00000012), - .A1(sig00000012), - .A2(sig00000012), - .A3(sig00000012), - .CLK(clk), - .D(sig0000009f), - .Q(sig00000001) - ); - FD #( - .INIT ( 1'b0 )) - blk00000167 ( - .C(clk), - .D(sig00000001), + .D(sig0000008e), .Q(p[0]) ); diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco index 2273be6..13cf374 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 13.2 -# Date: Mon Oct 24 22:04:01 2011 +# Date: Fri Oct 28 08:30:26 2011 # ############################################################## # @@ -49,7 +49,7 @@ CSET multtype=Parallel_Multiplier CSET optgoal=Speed CSET outputwidthhigh=47 CSET outputwidthlow=0 -CSET pipestages=3 +CSET pipestages=2 CSET portatype=Signed CSET portawidth=24 CSET portbtype=Signed @@ -65,4 +65,4 @@ CSET zerodetect=false MISC pkg_timestamp=2011-06-21T06:26:54.000Z # END Extra information GENERATE -# CRC: fd22ef14 +# CRC: efe4d30e diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise index 1efcbc5..60829e7 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise @@ -50,8 +50,8 @@ - - + + diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index 93c69dd..182b861 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -299,7 +299,8 @@ cx4 snes_cx4 ( .BUS_DI(CX4_DINr), .BUS_ADDR(CX4_ADDR), .BUS_RRQ(CX4_RRQ), - .BUS_RDY(CX4_RDY) + .BUS_RDY(CX4_RDY), + .cx4_active(cx4_active) ); parameter MODE_SNES = 1'b0; @@ -359,7 +360,7 @@ always @(posedge CLK2) begin end wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE; -wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART; +wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART & ~cx4_active; assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1]; assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0]; @@ -374,14 +375,14 @@ assign MCU_RDY = RQ_MCU_RDYr; always @(posedge CLK2) begin if(MCU_RRQ) begin MCU_RD_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(MCU_WRQ) begin MCU_WR_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin MCU_RD_PENDr <= 1'b0; - MCU_WR_PENDr <= 1'b0; - RQ_MCU_RDYr <= 1'b1; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; end end @@ -392,143 +393,144 @@ assign CX4_RDY = RQ_CX4_RDYr; always @(posedge CLK2) begin if(CX4_RRQ) begin CX4_RD_PENDr <= 1'b1; - RQ_CX4_RDYr <= 1'b0; - end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin + RQ_CX4_RDYr <= 1'b0; + end else if(STATE == ST_CX4_RD_END) begin CX4_RD_PENDr <= 1'b0; - RQ_CX4_RDYr <= 1'b1; + RQ_CX4_RDYr <= 1'b1; end end reg snes_wr_cycle; always @(posedge CLK2) begin - if(SNES_cycle_start & IS_CART) begin + if(SNES_cycle_start & IS_CART & ~cx4_active) begin STATE <= ST_SNES_RD_ADDR; - end else if(SNES_WR_start & IS_CART) begin + end else if(SNES_WR_start & IS_CART & ~cx4_active) begin STATE <= ST_SNES_WR_ADDR; end else begin case(STATE) - ST_IDLE: begin - ROM_ADDRr <= MAPPED_SNES_ADDR; - if(CX4_RRQ | CX4_RD_PENDr) begin - ROM_ADDRr <= CX4_ADDR; - STATE <= ST_CX4_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + ST_IDLE: begin + ROM_ADDRr <= MAPPED_SNES_ADDR; + if(CX4_RD_PENDr) begin + STATE <= ST_CX4_RD_WAIT; + ROM_ADDRr <= CX4_ADDR; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + else if(~cx4_active) begin + if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; + else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; + else STATE <= ST_IDLE; end - else if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; - else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; else STATE <= ST_IDLE; - end - ST_SNES_RD_ADDR: begin - STATE <= ST_SNES_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT; - end - ST_SNES_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; - else STATE <= ST_SNES_RD_WAIT; - if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; - else SNES_DINr <= ROM_DATA[15:8]; - end - ST_SNES_RD_END: begin - STATE <= ST_IDLE; - if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; - else SNES_DINr <= ROM_DATA[15:8]; - end + end + ST_SNES_RD_ADDR: begin + STATE <= ST_SNES_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT; + end + ST_SNES_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; + else STATE <= ST_SNES_RD_WAIT; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_RD_END: begin + STATE <= ST_IDLE; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end ST_SNES_WR_ADDR: begin ROM_WEr <= (!IS_WRITABLE); snes_wr_cycle <= 1'b1; - STATE <= ST_SNES_WR_WAIT1; - ST_MEM_DELAYr <= ROM_WR_WAIT1; - end - ST_SNES_WR_WAIT1: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; - else STATE <= ST_SNES_WR_WAIT1; - end - ST_SNES_WR_DATA: begin + STATE <= ST_SNES_WR_WAIT1; + ST_MEM_DELAYr <= ROM_WR_WAIT1; + end + ST_SNES_WR_WAIT1: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; + else STATE <= ST_SNES_WR_WAIT1; + end + ST_SNES_WR_DATA: begin ROM_DOUTr <= SNES_DATA; - ST_MEM_DELAYr <= ROM_WR_WAIT2; - STATE <= ST_SNES_WR_WAIT2; - end + ST_MEM_DELAYr <= ROM_WR_WAIT2; + STATE <= ST_SNES_WR_WAIT2; + end ST_SNES_WR_WAIT2: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; - else STATE <= ST_SNES_WR_WAIT2; - end - ST_SNES_WR_END: begin - STATE <= ST_IDLE; - ROM_WEr <= 1'b1; - snes_wr_cycle <= 1'b0; - end - ST_MCU_RD_ADDR: begin - ROM_ADDRr <= MCU_ADDR; - STATE <= ST_MCU_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; - end - ST_MCU_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - STATE <= ST_MCU_RD_WAIT2; - ST_MEM_DELAYr <= 4'h2; + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; + else STATE <= ST_SNES_WR_WAIT2; end - else STATE <= ST_MCU_RD_WAIT; - if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; - else MCU_DINr <= ROM_DATA[15:8]; - end - ST_MCU_RD_WAIT2: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - STATE <= ST_MCU_RD_END; - end else STATE <= ST_MCU_RD_WAIT2; - end - ST_MCU_RD_END: begin - STATE <= ST_IDLE; - end - ST_MCU_WR_ADDR: begin - ROM_ADDRr <= MCU_ADDR; - STATE <= ST_MCU_WR_WAIT; - ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; - ROM_DOUTr <= MCU_DOUT; - ROM_WEr <= 1'b0; - end - ST_MCU_WR_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - ROM_WEr <= 1'b1; - STATE <= ST_MCU_WR_WAIT2; - ST_MEM_DELAYr <= 4'h2; + ST_SNES_WR_END: begin + STATE <= ST_IDLE; + ROM_WEr <= 1'b1; + snes_wr_cycle <= 1'b0; end - else STATE <= ST_MCU_WR_WAIT; + ST_MCU_RD_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; + end + ST_MCU_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_RD_WAIT; + if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; + else MCU_DINr <= ROM_DATA[15:8]; end - ST_MCU_WR_WAIT2: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - STATE <= ST_MCU_WR_END; - end else STATE <= ST_MCU_WR_WAIT2; - end - ST_MCU_WR_END: begin - STATE <= ST_IDLE; - end - - ST_CX4_RD_ADDR: begin - ROM_ADDRr <= CX4_ADDR; - STATE <= ST_CX4_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; - end - ST_CX4_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin + ST_MCU_RD_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_END; + end else STATE <= ST_MCU_RD_WAIT2; + end + ST_MCU_RD_END: begin STATE <= ST_IDLE; end - else STATE <= ST_CX4_RD_WAIT; - if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; - else CX4_DINr <= ROM_DATA[15:8]; + ST_MCU_WR_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_WR_WAIT; + ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; + ROM_DOUTr <= MCU_DOUT; + ROM_WEr <= 1'b0; + end + ST_MCU_WR_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + ROM_WEr <= 1'b1; + STATE <= ST_MCU_WR_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_WR_WAIT; end - ST_CX4_RD_END: begin - STATE <= ST_IDLE; - end - endcase + ST_MCU_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_WR_END; + end else STATE <= ST_MCU_WR_WAIT2; + end + ST_MCU_WR_END: begin + STATE <= ST_IDLE; + end + + ST_CX4_RD_ADDR: begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + ST_CX4_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_CX4_RD_END; + else STATE <= ST_CX4_RD_WAIT; + if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; + else CX4_DINr <= ROM_DATA[15:8]; + end + ST_CX4_RD_END: begin + STATE <= ST_IDLE; + end + endcase end end diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise index 82ca3c5..a182ee5 100644 --- a/verilog/sd2snes_cx4/sd2snes_cx4.xise +++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise @@ -238,7 +238,7 @@ - + @@ -320,7 +320,7 @@ - + @@ -366,8 +366,8 @@ - - + + From 314da586a40a3454a81e8331c24d37c7e34acd85 Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 1 Nov 2011 20:54:07 +0100 Subject: [PATCH 12/66] FPGA/cx4: implement reset vector access --- verilog/sd2snes_cx4/address.v | 7 +++++-- verilog/sd2snes_cx4/cx4.v | 3 ++- verilog/sd2snes_cx4/main.v | 16 +++++++++++----- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v index e62071d..c2502d3 100644 --- a/verilog/sd2snes_cx4/address.v +++ b/verilog/sd2snes_cx4/address.v @@ -21,6 +21,7 @@ module address( input CLK, input [2:0] MAPPER, // MCU detected mapper input [23:0] SNES_ADDR, // requested address from SNES + input SNES_CS, // SNES ROMSEL signal output [23:0] ROM_ADDR, // Address to request from SRAM0 output ROM_SEL, // enable SRAM0 (active low) output IS_SAVERAM, // address/CS mapped as SRAM? @@ -30,7 +31,8 @@ module address( input [23:0] ROM_MASK, input use_msu1, output msu_enable, - output cx4_enable + output cx4_enable, + output cx4_vect_enable ); wire [23:0] SRAM_SNES_ADDR; @@ -40,7 +42,7 @@ wire [23:0] SRAM_SNES_ADDR; - MMIO @ 6000-7fff */ -assign IS_ROM = (SNES_ADDR[15]); +assign IS_ROM = SNES_ADDR[15] & ~SNES_CS; assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK); @@ -61,4 +63,5 @@ initial cx4_enable_r = 6'b000000; always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w}; assign cx4_enable = &cx4_enable_r[5:2]; +assign cx4_vect_enable = &SNES_ADDR[15:5]; endmodule diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index 06d943d..6afdbea 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -23,6 +23,7 @@ module cx4( output [7:0] DO, input [12:0] ADDR, input CS, + input SNES_VECT_EN, input nRD, input nWR, input CLK, @@ -44,7 +45,7 @@ parameter BUSY_CPU = 2'b10; wire datram_enable = CS & (ADDR[11:0] < 12'hc00); wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011); wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011); -wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); +wire vector_enable = (CS & (ADDR[12:5] == 8'b11111011)) | (cx4_active & SNES_VECT_EN); wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index 182b861..ff82ab7 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -268,6 +268,7 @@ address snes_addr( .CLK(CLK2), .MAPPER(MAPPER), .SNES_ADDR(SNES_ADDR), // requested address from SNES + .SNES_CS(SNES_CS), .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) .ROM_SEL(ROM_SEL), // which SRAM unit to access .IS_SAVERAM(IS_SAVERAM), @@ -279,7 +280,8 @@ address snes_addr( //MSU-1 .msu_enable(msu_enable), //CX4 - .cx4_enable(cx4_enable) + .cx4_enable(cx4_enable), + .cx4_vect_enable(cx4_vect_enable) ); reg [7:0] CX4_DINr; @@ -290,6 +292,7 @@ cx4 snes_cx4 ( .DO(CX4_SNES_DATA_OUT), .ADDR(SNES_ADDR[12:0]), .CS(cx4_enable), + .SNES_VECT_EN(cx4_vect_enable), .nRD(SNES_READ), .nWR(SNES_WRITE), .CLK(CLK2), @@ -344,9 +347,12 @@ assign CX4_SNES_DATA_IN = SNES_DATA; reg [7:0] SNES_DINr; reg [7:0] ROM_DOUTr; -assign SNES_DATA = (!SNES_READ) ? (msu_enable ? MSU_SNES_DATA_OUT +assign SNES_DATA = (!SNES_READ) + ? (msu_enable ? MSU_SNES_DATA_OUT :cx4_enable ? CX4_SNES_DATA_OUT - :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ; + :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT + : SNES_DINr) + : 8'bZ; reg [3:0] ST_MEM_DELAYr; reg MCU_RD_PENDr; @@ -559,8 +565,8 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; assign SNES_DATABUS_OE = msu_enable ? 1'b0 : cx4_enable ? 1'b0 : - ((IS_ROM & SNES_CS) - |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE) + (cx4_active & cx4_vect_enable) ? 1'b0 : + ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE) |(SNES_READ & SNES_WRITE) ); From ecd75210a903526250097712da5b43bc559c5dfb Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 1 Nov 2011 20:55:59 +0100 Subject: [PATCH 13/66] FPGA/cx4: fix memory sharing --- verilog/sd2snes_cx4/main.v | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index ff82ab7..de849b4 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -400,7 +400,7 @@ always @(posedge CLK2) begin if(CX4_RRQ) begin CX4_RD_PENDr <= 1'b1; RQ_CX4_RDYr <= 1'b0; - end else if(STATE == ST_CX4_RD_END) begin + end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin CX4_RD_PENDr <= 1'b0; RQ_CX4_RDYr <= 1'b1; end @@ -421,8 +421,7 @@ always @(posedge CLK2) begin STATE <= ST_CX4_RD_WAIT; ROM_ADDRr <= CX4_ADDR; ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; - end - else if(~cx4_active) begin + end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; else STATE <= ST_IDLE; @@ -481,10 +480,10 @@ always @(posedge CLK2) begin if(ST_MEM_DELAYr == 4'h0) begin STATE <= ST_MCU_RD_WAIT2; ST_MEM_DELAYr <= 4'h2; + if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; + else MCU_DINr <= ROM_DATA[15:8]; end else STATE <= ST_MCU_RD_WAIT; - if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; - else MCU_DINr <= ROM_DATA[15:8]; end ST_MCU_RD_WAIT2: begin ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; @@ -528,7 +527,7 @@ always @(posedge CLK2) begin end ST_CX4_RD_WAIT: begin ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_CX4_RD_END; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE; else STATE <= ST_CX4_RD_WAIT; if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; else CX4_DINr <= ROM_DATA[15:8]; From 3dd64cb98fedf3a46c6a7123c978b8e42d2d8733 Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 1 Nov 2011 20:56:30 +0100 Subject: [PATCH 14/66] FPGA/cx4: timing closure --- verilog/sd2snes_cx4/cx4.v | 2 +- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v | 1716 ++++++++++--------- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco | 6 +- verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise | 314 +++- verilog/sd2snes_cx4/sd2snes_cx4.xise | 14 +- 5 files changed, 1226 insertions(+), 826 deletions(-) diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index 6afdbea..54173f8 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -89,7 +89,7 @@ reg [14:0] cx4_mmio_pagemem[1:0]; reg [23:0] const [15:0]; -reg [14:0] cachetag [1:0]; // 14-0: bank number +reg [14:0] cachetag [1:0]; reg [1:0] cachevalid; reg [14:0] cache_pgmpage; diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v index da8b924..a2c52a6 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v @@ -7,7 +7,7 @@ // \ \ \/ Version: O.61xd // \ \ Application: netgen // / / Filename: cx4_mul.v -// /___/ /\ Timestamp: Fri Oct 28 10:30:51 2011 +// /___/ /\ Timestamp: Sun Oct 30 21:22:41 2011 // \ \ / \ // \___\/\___\ // @@ -34,9 +34,10 @@ `timescale 1 ns/1 ps module cx4_mul ( - clk, p, a, b + clk, ce, p, a, b )/* synthesis syn_black_box syn_noprune=1 */; input clk; + input ce; output [47 : 0] p; input [23 : 0] a; input [23 : 0] b; @@ -398,7 +399,28 @@ module cx4_mul ( wire sig00000161; wire sig00000162; wire sig00000163; - wire sig00000164; + wire \NLW_blk00000002_P<35>_UNCONNECTED ; + wire \NLW_blk00000002_P<34>_UNCONNECTED ; + wire \NLW_blk00000002_P<33>_UNCONNECTED ; + wire \NLW_blk00000002_P<32>_UNCONNECTED ; + wire \NLW_blk00000002_P<31>_UNCONNECTED ; + wire \NLW_blk00000002_P<30>_UNCONNECTED ; + wire \NLW_blk00000002_P<29>_UNCONNECTED ; + wire \NLW_blk00000002_P<28>_UNCONNECTED ; + wire \NLW_blk00000002_P<27>_UNCONNECTED ; + wire \NLW_blk00000002_P<26>_UNCONNECTED ; + wire \NLW_blk00000002_P<25>_UNCONNECTED ; + wire \NLW_blk00000002_P<24>_UNCONNECTED ; + wire \NLW_blk00000002_P<23>_UNCONNECTED ; + wire \NLW_blk00000002_P<22>_UNCONNECTED ; + wire \NLW_blk00000002_P<21>_UNCONNECTED ; + wire \NLW_blk00000002_P<20>_UNCONNECTED ; + wire \NLW_blk00000002_P<19>_UNCONNECTED ; + wire \NLW_blk00000002_P<18>_UNCONNECTED ; + wire \NLW_blk00000002_P<17>_UNCONNECTED ; + wire \NLW_blk00000002_P<16>_UNCONNECTED ; + wire \NLW_blk00000002_P<15>_UNCONNECTED ; + wire \NLW_blk00000002_P<14>_UNCONNECTED ; wire \NLW_blk00000003_P<35>_UNCONNECTED ; wire \NLW_blk00000003_P<34>_UNCONNECTED ; wire \NLW_blk00000003_P<33>_UNCONNECTED ; @@ -411,16 +433,6 @@ module cx4_mul ( wire \NLW_blk00000003_P<26>_UNCONNECTED ; wire \NLW_blk00000003_P<25>_UNCONNECTED ; wire \NLW_blk00000003_P<24>_UNCONNECTED ; - wire \NLW_blk00000003_P<23>_UNCONNECTED ; - wire \NLW_blk00000003_P<22>_UNCONNECTED ; - wire \NLW_blk00000003_P<21>_UNCONNECTED ; - wire \NLW_blk00000003_P<20>_UNCONNECTED ; - wire \NLW_blk00000003_P<19>_UNCONNECTED ; - wire \NLW_blk00000003_P<18>_UNCONNECTED ; - wire \NLW_blk00000003_P<17>_UNCONNECTED ; - wire \NLW_blk00000003_P<16>_UNCONNECTED ; - wire \NLW_blk00000003_P<15>_UNCONNECTED ; - wire \NLW_blk00000003_P<14>_UNCONNECTED ; wire \NLW_blk00000004_P<35>_UNCONNECTED ; wire \NLW_blk00000004_P<34>_UNCONNECTED ; wire \NLW_blk00000004_P<33>_UNCONNECTED ; @@ -434,245 +446,212 @@ module cx4_mul ( wire \NLW_blk00000004_P<25>_UNCONNECTED ; wire \NLW_blk00000004_P<24>_UNCONNECTED ; wire \NLW_blk00000005_P<35>_UNCONNECTED ; - wire \NLW_blk00000005_P<34>_UNCONNECTED ; - wire \NLW_blk00000005_P<33>_UNCONNECTED ; - wire \NLW_blk00000005_P<32>_UNCONNECTED ; - wire \NLW_blk00000005_P<31>_UNCONNECTED ; - wire \NLW_blk00000005_P<30>_UNCONNECTED ; - wire \NLW_blk00000005_P<29>_UNCONNECTED ; - wire \NLW_blk00000005_P<28>_UNCONNECTED ; - wire \NLW_blk00000005_P<27>_UNCONNECTED ; - wire \NLW_blk00000005_P<26>_UNCONNECTED ; - wire \NLW_blk00000005_P<25>_UNCONNECTED ; - wire \NLW_blk00000005_P<24>_UNCONNECTED ; - wire \NLW_blk00000006_P<35>_UNCONNECTED ; GND blk00000001 ( .G(sig00000001) ); - VCC blk00000002 ( - .P(sig00000002) + MULT18X18S blk00000002 ( + .C(clk), + .CE(ce), + .R(sig00000001), + .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), + .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .P({\NLW_blk00000002_P<35>_UNCONNECTED , \NLW_blk00000002_P<34>_UNCONNECTED , \NLW_blk00000002_P<33>_UNCONNECTED , +\NLW_blk00000002_P<32>_UNCONNECTED , \NLW_blk00000002_P<31>_UNCONNECTED , \NLW_blk00000002_P<30>_UNCONNECTED , \NLW_blk00000002_P<29>_UNCONNECTED , +\NLW_blk00000002_P<28>_UNCONNECTED , \NLW_blk00000002_P<27>_UNCONNECTED , \NLW_blk00000002_P<26>_UNCONNECTED , \NLW_blk00000002_P<25>_UNCONNECTED , +\NLW_blk00000002_P<24>_UNCONNECTED , \NLW_blk00000002_P<23>_UNCONNECTED , \NLW_blk00000002_P<22>_UNCONNECTED , \NLW_blk00000002_P<21>_UNCONNECTED , +\NLW_blk00000002_P<20>_UNCONNECTED , \NLW_blk00000002_P<19>_UNCONNECTED , \NLW_blk00000002_P<18>_UNCONNECTED , \NLW_blk00000002_P<17>_UNCONNECTED , +\NLW_blk00000002_P<16>_UNCONNECTED , \NLW_blk00000002_P<15>_UNCONNECTED , \NLW_blk00000002_P<14>_UNCONNECTED , sig000000e4, sig000000e3, sig000000e2, +sig000000e1, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e5, sig000000e0}) ); MULT18X18S blk00000003 ( .C(clk), - .CE(sig00000002), + .CE(ce), .R(sig00000001), .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), - .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , \NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED , \NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , -\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , -\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , -\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, -sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1}) +\NLW_blk00000003_P<24>_UNCONNECTED , sig000000d7, sig000000d6, sig000000d5, sig000000d4, sig000000d2, sig000000d1, sig000000d0, sig000000cf, +sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000c9, sig000000df, sig000000de, sig000000dd, sig000000dc, sig000000db, +sig000000da, sig000000d9, sig000000d8, sig000000d3, sig000000c8}) ); MULT18X18S blk00000004 ( .C(clk), - .CE(sig00000002), - .R(sig00000001), - .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), - .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), - .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , -\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , -\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , -\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, -sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, -sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9}) - ); - MULT18X18S blk00000005 ( - .C(clk), - .CE(sig00000002), + .CE(ce), .R(sig00000001), .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), - .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , -\NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , -\NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , -\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, -sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, -sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1}) + .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , +\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , +\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , +\NLW_blk00000004_P<24>_UNCONNECTED , sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000ba, sig000000b9, sig000000b8, sig000000b7, +sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000b1, sig000000c7, sig000000c6, sig000000c5, sig000000c4, sig000000c3, +sig000000c2, sig000000c1, sig000000c0, sig000000bb, sig000000b0}) ); - MULT18X18S blk00000006 ( + MULT18X18S blk00000005 ( .C(clk), - .CE(sig00000002), + .CE(ce), .R(sig00000001), .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), - .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, -sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, -sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, -sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) + .P({\NLW_blk00000005_P<35>_UNCONNECTED , sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a4, sig000000a2, sig000000a1, sig000000a0, +sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000099, sig00000097, sig00000096, sig00000095, sig00000094, +sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig0000008e, sig000000af, sig000000ae, sig000000ad, sig000000ac, sig000000ab, +sig000000aa, sig000000a9, sig000000a3, sig00000098, sig0000008d}) ); - XORCY blk00000007 ( - .CI(sig00000065), - .LI(sig00000086), + XORCY blk00000006 ( + .CI(sig00000064), + .LI(sig00000085), .O(p[47]) ); LUT2 #( .INIT ( 4'h6 )) - blk00000008 ( - .I0(sig0000014e), - .I1(sig0000015b), - .O(sig00000086) - ); - MUXCY blk00000009 ( - .CI(sig00000064), - .DI(sig0000014e), - .S(sig00000085), - .O(sig00000065) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk0000000a ( - .I0(sig0000014e), - .I1(sig0000015b), + blk00000007 ( + .I0(sig0000014d), + .I1(sig0000015a), .O(sig00000085) ); - MUXCY blk0000000b ( - .CI(sig00000062), - .DI(sig0000014e), + MUXCY blk00000008 ( + .CI(sig00000063), + .DI(sig0000014d), .S(sig00000084), .O(sig00000064) ); LUT2 #( .INIT ( 4'h6 )) - blk0000000c ( - .I0(sig0000014e), - .I1(sig0000015b), + blk00000009 ( + .I0(sig0000014d), + .I1(sig0000015a), .O(sig00000084) ); - XORCY blk0000000d ( + MUXCY blk0000000a ( .CI(sig00000061), - .LI(sig00000082), - .O(p[46]) - ); - MUXCY blk0000000e ( - .CI(sig00000061), - .DI(sig0000014e), - .S(sig00000082), - .O(sig00000062) + .DI(sig0000014d), + .S(sig00000083), + .O(sig00000063) ); LUT2 #( .INIT ( 4'h6 )) - blk0000000f ( - .I0(sig0000014e), + blk0000000b ( + .I0(sig0000014d), .I1(sig0000015a), - .O(sig00000082) + .O(sig00000083) ); - XORCY blk00000010 ( + XORCY blk0000000c ( .CI(sig00000060), .LI(sig00000081), - .O(p[45]) + .O(p[46]) ); - MUXCY blk00000011 ( + MUXCY blk0000000d ( .CI(sig00000060), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig00000081), .O(sig00000061) ); LUT2 #( .INIT ( 4'h6 )) - blk00000012 ( - .I0(sig0000014e), + blk0000000e ( + .I0(sig0000014d), .I1(sig00000159), .O(sig00000081) ); - XORCY blk00000013 ( + XORCY blk0000000f ( .CI(sig0000005f), .LI(sig00000080), - .O(p[44]) + .O(p[45]) ); - MUXCY blk00000014 ( + MUXCY blk00000010 ( .CI(sig0000005f), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig00000080), .O(sig00000060) ); LUT2 #( .INIT ( 4'h6 )) - blk00000015 ( - .I0(sig0000014e), + blk00000011 ( + .I0(sig0000014d), .I1(sig00000158), .O(sig00000080) ); - XORCY blk00000016 ( + XORCY blk00000012 ( .CI(sig0000005e), .LI(sig0000007f), - .O(p[43]) + .O(p[44]) ); - MUXCY blk00000017 ( + MUXCY blk00000013 ( .CI(sig0000005e), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig0000007f), .O(sig0000005f) ); LUT2 #( .INIT ( 4'h6 )) - blk00000018 ( - .I0(sig0000014e), - .I1(sig00000164), + blk00000014 ( + .I0(sig0000014d), + .I1(sig00000157), .O(sig0000007f) ); - XORCY blk00000019 ( + XORCY blk00000015 ( .CI(sig0000005d), .LI(sig0000007e), - .O(p[42]) + .O(p[43]) ); - MUXCY blk0000001a ( + MUXCY blk00000016 ( .CI(sig0000005d), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig0000007e), .O(sig0000005e) ); LUT2 #( .INIT ( 4'h6 )) - blk0000001b ( - .I0(sig0000014e), + blk00000017 ( + .I0(sig0000014d), .I1(sig00000163), .O(sig0000007e) ); - XORCY blk0000001c ( + XORCY blk00000018 ( .CI(sig0000005c), .LI(sig0000007d), - .O(p[41]) + .O(p[42]) ); - MUXCY blk0000001d ( + MUXCY blk00000019 ( .CI(sig0000005c), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig0000007d), .O(sig0000005d) ); LUT2 #( .INIT ( 4'h6 )) - blk0000001e ( - .I0(sig0000014e), + blk0000001a ( + .I0(sig0000014d), .I1(sig00000162), .O(sig0000007d) ); - XORCY blk0000001f ( + XORCY blk0000001b ( .CI(sig0000005b), .LI(sig0000007c), - .O(p[40]) + .O(p[41]) ); - MUXCY blk00000020 ( + MUXCY blk0000001c ( .CI(sig0000005b), - .DI(sig0000014e), + .DI(sig0000014d), .S(sig0000007c), .O(sig0000005c) ); LUT2 #( .INIT ( 4'h6 )) - blk00000021 ( - .I0(sig0000014e), + blk0000001d ( + .I0(sig0000014d), .I1(sig00000161), .O(sig0000007c) ); - XORCY blk00000022 ( + XORCY blk0000001e ( .CI(sig0000005a), .LI(sig0000007b), - .O(p[39]) + .O(p[40]) ); - MUXCY blk00000023 ( + MUXCY blk0000001f ( .CI(sig0000005a), .DI(sig0000014d), .S(sig0000007b), @@ -680,17 +659,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000024 ( + blk00000020 ( .I0(sig0000014d), .I1(sig00000160), .O(sig0000007b) ); - XORCY blk00000025 ( + XORCY blk00000021 ( .CI(sig00000059), .LI(sig0000007a), - .O(p[38]) + .O(p[39]) ); - MUXCY blk00000026 ( + MUXCY blk00000022 ( .CI(sig00000059), .DI(sig0000014c), .S(sig0000007a), @@ -698,53 +677,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000027 ( + blk00000023 ( .I0(sig0000014c), .I1(sig0000015f), .O(sig0000007a) ); - XORCY blk00000028 ( - .CI(sig00000057), + XORCY blk00000024 ( + .CI(sig00000058), .LI(sig00000079), - .O(p[37]) + .O(p[38]) ); - MUXCY blk00000029 ( - .CI(sig00000057), + MUXCY blk00000025 ( + .CI(sig00000058), .DI(sig0000014b), .S(sig00000079), .O(sig00000059) ); LUT2 #( .INIT ( 4'h6 )) - blk0000002a ( + blk00000026 ( .I0(sig0000014b), .I1(sig0000015e), .O(sig00000079) ); - XORCY blk0000002b ( + XORCY blk00000027 ( .CI(sig00000056), - .LI(sig00000077), - .O(p[36]) + .LI(sig00000078), + .O(p[37]) ); - MUXCY blk0000002c ( + MUXCY blk00000028 ( .CI(sig00000056), - .DI(sig00000149), - .S(sig00000077), - .O(sig00000057) + .DI(sig0000014a), + .S(sig00000078), + .O(sig00000058) ); LUT2 #( .INIT ( 4'h6 )) - blk0000002d ( - .I0(sig00000149), + blk00000029 ( + .I0(sig0000014a), .I1(sig0000015d), - .O(sig00000077) + .O(sig00000078) ); - XORCY blk0000002e ( + XORCY blk0000002a ( .CI(sig00000055), .LI(sig00000076), - .O(p[35]) + .O(p[36]) ); - MUXCY blk0000002f ( + MUXCY blk0000002b ( .CI(sig00000055), .DI(sig00000148), .S(sig00000076), @@ -752,17 +731,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000030 ( + blk0000002c ( .I0(sig00000148), .I1(sig0000015c), .O(sig00000076) ); - XORCY blk00000031 ( + XORCY blk0000002d ( .CI(sig00000054), .LI(sig00000075), - .O(p[34]) + .O(p[35]) ); - MUXCY blk00000032 ( + MUXCY blk0000002e ( .CI(sig00000054), .DI(sig00000147), .S(sig00000075), @@ -770,17 +749,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000033 ( + blk0000002f ( .I0(sig00000147), - .I1(sig00000157), + .I1(sig0000015b), .O(sig00000075) ); - XORCY blk00000034 ( + XORCY blk00000030 ( .CI(sig00000053), .LI(sig00000074), - .O(p[33]) + .O(p[34]) ); - MUXCY blk00000035 ( + MUXCY blk00000031 ( .CI(sig00000053), .DI(sig00000146), .S(sig00000074), @@ -788,17 +767,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000036 ( + blk00000032 ( .I0(sig00000146), - .I1(sig00000121), + .I1(sig00000156), .O(sig00000074) ); - XORCY blk00000037 ( + XORCY blk00000033 ( .CI(sig00000052), .LI(sig00000073), - .O(p[32]) + .O(p[33]) ); - MUXCY blk00000038 ( + MUXCY blk00000034 ( .CI(sig00000052), .DI(sig00000145), .S(sig00000073), @@ -806,17 +785,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000039 ( + blk00000035 ( .I0(sig00000145), .I1(sig00000120), .O(sig00000073) ); - XORCY blk0000003a ( + XORCY blk00000036 ( .CI(sig00000051), .LI(sig00000072), - .O(p[31]) + .O(p[32]) ); - MUXCY blk0000003b ( + MUXCY blk00000037 ( .CI(sig00000051), .DI(sig00000144), .S(sig00000072), @@ -824,17 +803,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000003c ( + blk00000038 ( .I0(sig00000144), .I1(sig0000011f), .O(sig00000072) ); - XORCY blk0000003d ( + XORCY blk00000039 ( .CI(sig00000050), .LI(sig00000071), - .O(p[30]) + .O(p[31]) ); - MUXCY blk0000003e ( + MUXCY blk0000003a ( .CI(sig00000050), .DI(sig00000143), .S(sig00000071), @@ -842,17 +821,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000003f ( + blk0000003b ( .I0(sig00000143), .I1(sig0000011e), .O(sig00000071) ); - XORCY blk00000040 ( + XORCY blk0000003c ( .CI(sig0000004f), .LI(sig00000070), - .O(p[29]) + .O(p[30]) ); - MUXCY blk00000041 ( + MUXCY blk0000003d ( .CI(sig0000004f), .DI(sig00000142), .S(sig00000070), @@ -860,17 +839,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000042 ( + blk0000003e ( .I0(sig00000142), .I1(sig0000011d), .O(sig00000070) ); - XORCY blk00000043 ( + XORCY blk0000003f ( .CI(sig0000004e), .LI(sig0000006f), - .O(p[28]) + .O(p[29]) ); - MUXCY blk00000044 ( + MUXCY blk00000040 ( .CI(sig0000004e), .DI(sig00000141), .S(sig0000006f), @@ -878,53 +857,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000045 ( + blk00000041 ( .I0(sig00000141), .I1(sig0000011c), .O(sig0000006f) ); - XORCY blk00000046 ( - .CI(sig0000006c), + XORCY blk00000042 ( + .CI(sig0000004d), .LI(sig0000006e), - .O(p[27]) + .O(p[28]) ); - MUXCY blk00000047 ( - .CI(sig0000006c), + MUXCY blk00000043 ( + .CI(sig0000004d), .DI(sig00000140), .S(sig0000006e), .O(sig0000004e) ); LUT2 #( .INIT ( 4'h6 )) - blk00000048 ( + blk00000044 ( .I0(sig00000140), .I1(sig0000011b), .O(sig0000006e) ); - XORCY blk00000049 ( + XORCY blk00000045 ( .CI(sig0000006b), - .LI(sig0000008d), - .O(p[26]) + .LI(sig0000006d), + .O(p[27]) ); - MUXCY blk0000004a ( + MUXCY blk00000046 ( .CI(sig0000006b), - .DI(sig00000156), - .S(sig0000008d), - .O(sig0000006c) + .DI(sig0000013f), + .S(sig0000006d), + .O(sig0000004d) ); LUT2 #( .INIT ( 4'h6 )) - blk0000004b ( - .I0(sig00000156), - .I1(sig00000130), - .O(sig0000008d) + blk00000047 ( + .I0(sig0000013f), + .I1(sig0000011a), + .O(sig0000006d) ); - XORCY blk0000004c ( + XORCY blk00000048 ( .CI(sig0000006a), .LI(sig0000008c), - .O(p[25]) + .O(p[26]) ); - MUXCY blk0000004d ( + MUXCY blk00000049 ( .CI(sig0000006a), .DI(sig00000155), .S(sig0000008c), @@ -932,17 +911,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000004e ( + blk0000004a ( .I0(sig00000155), .I1(sig0000012f), .O(sig0000008c) ); - XORCY blk0000004f ( + XORCY blk0000004b ( .CI(sig00000069), .LI(sig0000008b), - .O(p[24]) + .O(p[25]) ); - MUXCY blk00000050 ( + MUXCY blk0000004c ( .CI(sig00000069), .DI(sig00000154), .S(sig0000008b), @@ -950,17 +929,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000051 ( + blk0000004d ( .I0(sig00000154), .I1(sig0000012e), .O(sig0000008b) ); - XORCY blk00000052 ( + XORCY blk0000004e ( .CI(sig00000068), .LI(sig0000008a), - .O(p[23]) + .O(p[24]) ); - MUXCY blk00000053 ( + MUXCY blk0000004f ( .CI(sig00000068), .DI(sig00000153), .S(sig0000008a), @@ -968,17 +947,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000054 ( + blk00000050 ( .I0(sig00000153), .I1(sig0000012d), .O(sig0000008a) ); - XORCY blk00000055 ( + XORCY blk00000051 ( .CI(sig00000067), .LI(sig00000089), - .O(p[22]) + .O(p[23]) ); - MUXCY blk00000056 ( + MUXCY blk00000052 ( .CI(sig00000067), .DI(sig00000152), .S(sig00000089), @@ -986,17 +965,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000057 ( + blk00000053 ( .I0(sig00000152), .I1(sig0000012c), .O(sig00000089) ); - XORCY blk00000058 ( + XORCY blk00000054 ( .CI(sig00000066), .LI(sig00000088), - .O(p[21]) + .O(p[22]) ); - MUXCY blk00000059 ( + MUXCY blk00000055 ( .CI(sig00000066), .DI(sig00000151), .S(sig00000088), @@ -1004,209 +983,209 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000005a ( + blk00000056 ( .I0(sig00000151), .I1(sig0000012b), .O(sig00000088) ); - XORCY blk0000005b ( - .CI(sig00000063), + XORCY blk00000057 ( + .CI(sig00000065), .LI(sig00000087), - .O(p[20]) + .O(p[21]) ); - MUXCY blk0000005c ( - .CI(sig00000063), + MUXCY blk00000058 ( + .CI(sig00000065), .DI(sig00000150), .S(sig00000087), .O(sig00000066) ); LUT2 #( .INIT ( 4'h6 )) - blk0000005d ( + blk00000059 ( .I0(sig00000150), .I1(sig0000012a), .O(sig00000087) ); - XORCY blk0000005e ( - .CI(sig00000058), - .LI(sig00000083), + XORCY blk0000005a ( + .CI(sig00000062), + .LI(sig00000086), + .O(p[20]) + ); + MUXCY blk0000005b ( + .CI(sig00000062), + .DI(sig0000014f), + .S(sig00000086), + .O(sig00000065) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005c ( + .I0(sig0000014f), + .I1(sig00000129), + .O(sig00000086) + ); + XORCY blk0000005d ( + .CI(sig00000057), + .LI(sig00000082), .O(p[19]) ); - MUXCY blk0000005f ( - .CI(sig00000058), - .DI(sig0000014f), - .S(sig00000083), - .O(sig00000063) + MUXCY blk0000005e ( + .CI(sig00000057), + .DI(sig0000014e), + .S(sig00000082), + .O(sig00000062) ); LUT2 #( .INIT ( 4'h6 )) - blk00000060 ( - .I0(sig0000014f), - .I1(sig00000125), - .O(sig00000083) + blk0000005f ( + .I0(sig0000014e), + .I1(sig00000124), + .O(sig00000082) ); - XORCY blk00000061 ( - .CI(sig0000004d), - .LI(sig00000078), + XORCY blk00000060 ( + .CI(sig0000004c), + .LI(sig00000077), .O(p[18]) ); - MUXCY blk00000062 ( - .CI(sig0000004d), - .DI(sig0000014a), - .S(sig00000078), - .O(sig00000058) + MUXCY blk00000061 ( + .CI(sig0000004c), + .DI(sig00000149), + .S(sig00000077), + .O(sig00000057) ); LUT2 #( .INIT ( 4'h6 )) - blk00000063 ( - .I0(sig0000014a), - .I1(sig0000011a), - .O(sig00000078) + blk00000062 ( + .I0(sig00000149), + .I1(sig00000119), + .O(sig00000077) ); - XORCY blk00000064 ( + XORCY blk00000063 ( .CI(sig00000001), - .LI(sig0000006d), + .LI(sig0000006c), .O(p[17]) ); - MUXCY blk00000065 ( + MUXCY blk00000064 ( .CI(sig00000001), - .DI(sig0000013f), - .S(sig0000006d), - .O(sig0000004d) + .DI(sig0000013e), + .S(sig0000006c), + .O(sig0000004c) ); LUT2 #( .INIT ( 4'h6 )) - blk00000066 ( - .I0(sig0000013f), - .I1(sig00000119), - .O(sig0000006d) + blk00000065 ( + .I0(sig0000013e), + .I1(sig00000118), + .O(sig0000006c) ); - XORCY blk00000067 ( - .CI(sig00000011), - .LI(sig00000029), - .O(sig0000014e) - ); - LUT2 #( - .INIT ( 4'h6 )) - blk00000068 ( - .I0(sig00000100), - .I1(sig00000111), - .O(sig00000029) - ); - XORCY blk00000069 ( + XORCY blk00000066 ( .CI(sig00000010), .LI(sig00000028), .O(sig0000014d) ); - MUXCY blk0000006a ( - .CI(sig00000010), - .DI(sig00000100), - .S(sig00000028), - .O(sig00000011) - ); LUT2 #( .INIT ( 4'h6 )) - blk0000006b ( - .I0(sig00000100), + blk00000067 ( + .I0(sig000000ff), .I1(sig00000110), .O(sig00000028) ); - XORCY blk0000006c ( + XORCY blk00000068 ( .CI(sig0000000f), .LI(sig00000027), .O(sig0000014c) ); - MUXCY blk0000006d ( + MUXCY blk00000069 ( .CI(sig0000000f), - .DI(sig00000100), + .DI(sig000000ff), .S(sig00000027), .O(sig00000010) ); LUT2 #( .INIT ( 4'h6 )) - blk0000006e ( - .I0(sig00000100), + blk0000006a ( + .I0(sig000000ff), .I1(sig0000010f), .O(sig00000027) ); - XORCY blk0000006f ( - .CI(sig0000000d), + XORCY blk0000006b ( + .CI(sig0000000e), .LI(sig00000026), .O(sig0000014b) ); - MUXCY blk00000070 ( - .CI(sig0000000d), - .DI(sig00000100), + MUXCY blk0000006c ( + .CI(sig0000000e), + .DI(sig000000ff), .S(sig00000026), .O(sig0000000f) ); LUT2 #( .INIT ( 4'h6 )) - blk00000071 ( - .I0(sig00000100), + blk0000006d ( + .I0(sig000000ff), .I1(sig0000010e), .O(sig00000026) ); - XORCY blk00000072 ( + XORCY blk0000006e ( .CI(sig0000000c), - .LI(sig00000024), - .O(sig00000149) + .LI(sig00000025), + .O(sig0000014a) ); - MUXCY blk00000073 ( + MUXCY blk0000006f ( .CI(sig0000000c), - .DI(sig00000100), - .S(sig00000024), - .O(sig0000000d) + .DI(sig000000ff), + .S(sig00000025), + .O(sig0000000e) ); LUT2 #( .INIT ( 4'h6 )) - blk00000074 ( - .I0(sig00000100), - .I1(sig0000010c), - .O(sig00000024) + blk00000070 ( + .I0(sig000000ff), + .I1(sig0000010d), + .O(sig00000025) ); - XORCY blk00000075 ( + XORCY blk00000071 ( .CI(sig0000000b), .LI(sig00000023), .O(sig00000148) ); - MUXCY blk00000076 ( + MUXCY blk00000072 ( .CI(sig0000000b), - .DI(sig00000100), + .DI(sig000000ff), .S(sig00000023), .O(sig0000000c) ); LUT2 #( .INIT ( 4'h6 )) - blk00000077 ( - .I0(sig00000100), + blk00000073 ( + .I0(sig000000ff), .I1(sig0000010b), .O(sig00000023) ); - XORCY blk00000078 ( + XORCY blk00000074 ( .CI(sig0000000a), .LI(sig00000022), .O(sig00000147) ); - MUXCY blk00000079 ( + MUXCY blk00000075 ( .CI(sig0000000a), - .DI(sig00000100), + .DI(sig000000ff), .S(sig00000022), .O(sig0000000b) ); LUT2 #( .INIT ( 4'h6 )) - blk0000007a ( - .I0(sig00000100), + blk00000076 ( + .I0(sig000000ff), .I1(sig0000010a), .O(sig00000022) ); - XORCY blk0000007b ( + XORCY blk00000077 ( .CI(sig00000009), .LI(sig00000021), .O(sig00000146) ); - MUXCY blk0000007c ( + MUXCY blk00000078 ( .CI(sig00000009), .DI(sig000000ff), .S(sig00000021), @@ -1214,17 +1193,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000007d ( + blk00000079 ( .I0(sig000000ff), .I1(sig00000109), .O(sig00000021) ); - XORCY blk0000007e ( + XORCY blk0000007a ( .CI(sig00000008), .LI(sig00000020), .O(sig00000145) ); - MUXCY blk0000007f ( + MUXCY blk0000007b ( .CI(sig00000008), .DI(sig000000fe), .S(sig00000020), @@ -1232,17 +1211,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000080 ( + blk0000007c ( .I0(sig000000fe), .I1(sig00000108), .O(sig00000020) ); - XORCY blk00000081 ( + XORCY blk0000007d ( .CI(sig00000007), .LI(sig0000001f), .O(sig00000144) ); - MUXCY blk00000082 ( + MUXCY blk0000007e ( .CI(sig00000007), .DI(sig000000fd), .S(sig0000001f), @@ -1250,17 +1229,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000083 ( + blk0000007f ( .I0(sig000000fd), .I1(sig00000107), .O(sig0000001f) ); - XORCY blk00000084 ( + XORCY blk00000080 ( .CI(sig00000006), .LI(sig0000001e), .O(sig00000143) ); - MUXCY blk00000085 ( + MUXCY blk00000081 ( .CI(sig00000006), .DI(sig000000fc), .S(sig0000001e), @@ -1268,17 +1247,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000086 ( + blk00000082 ( .I0(sig000000fc), .I1(sig00000106), .O(sig0000001e) ); - XORCY blk00000087 ( + XORCY blk00000083 ( .CI(sig00000005), .LI(sig0000001d), .O(sig00000142) ); - MUXCY blk00000088 ( + MUXCY blk00000084 ( .CI(sig00000005), .DI(sig000000fb), .S(sig0000001d), @@ -1286,17 +1265,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000089 ( + blk00000085 ( .I0(sig000000fb), .I1(sig00000105), .O(sig0000001d) ); - XORCY blk0000008a ( + XORCY blk00000086 ( .CI(sig00000004), .LI(sig0000001c), .O(sig00000141) ); - MUXCY blk0000008b ( + MUXCY blk00000087 ( .CI(sig00000004), .DI(sig000000fa), .S(sig0000001c), @@ -1304,53 +1283,53 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000008c ( + blk00000088 ( .I0(sig000000fa), .I1(sig00000104), .O(sig0000001c) ); - XORCY blk0000008d ( - .CI(sig00000019), + XORCY blk00000089 ( + .CI(sig00000003), .LI(sig0000001b), .O(sig00000140) ); - MUXCY blk0000008e ( - .CI(sig00000019), + MUXCY blk0000008a ( + .CI(sig00000003), .DI(sig000000f9), .S(sig0000001b), .O(sig00000004) ); LUT2 #( .INIT ( 4'h6 )) - blk0000008f ( + blk0000008b ( .I0(sig000000f9), .I1(sig00000103), .O(sig0000001b) ); - XORCY blk00000090 ( + XORCY blk0000008c ( .CI(sig00000018), - .LI(sig00000031), - .O(sig00000156) + .LI(sig0000001a), + .O(sig0000013f) ); - MUXCY blk00000091 ( + MUXCY blk0000008d ( .CI(sig00000018), .DI(sig000000f8), - .S(sig00000031), - .O(sig00000019) + .S(sig0000001a), + .O(sig00000003) ); LUT2 #( .INIT ( 4'h6 )) - blk00000092 ( + blk0000008e ( .I0(sig000000f8), - .I1(sig00000118), - .O(sig00000031) + .I1(sig00000102), + .O(sig0000001a) ); - XORCY blk00000093 ( + XORCY blk0000008f ( .CI(sig00000017), .LI(sig00000030), .O(sig00000155) ); - MUXCY blk00000094 ( + MUXCY blk00000090 ( .CI(sig00000017), .DI(sig000000f7), .S(sig00000030), @@ -1358,17 +1337,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000095 ( + blk00000091 ( .I0(sig000000f7), .I1(sig00000117), .O(sig00000030) ); - XORCY blk00000096 ( + XORCY blk00000092 ( .CI(sig00000016), .LI(sig0000002f), .O(sig00000154) ); - MUXCY blk00000097 ( + MUXCY blk00000093 ( .CI(sig00000016), .DI(sig000000f6), .S(sig0000002f), @@ -1376,17 +1355,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk00000098 ( + blk00000094 ( .I0(sig000000f6), .I1(sig00000116), .O(sig0000002f) ); - XORCY blk00000099 ( + XORCY blk00000095 ( .CI(sig00000015), .LI(sig0000002e), .O(sig00000153) ); - MUXCY blk0000009a ( + MUXCY blk00000096 ( .CI(sig00000015), .DI(sig000000f5), .S(sig0000002e), @@ -1394,17 +1373,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000009b ( + blk00000097 ( .I0(sig000000f5), .I1(sig00000115), .O(sig0000002e) ); - XORCY blk0000009c ( + XORCY blk00000098 ( .CI(sig00000014), .LI(sig0000002d), .O(sig00000152) ); - MUXCY blk0000009d ( + MUXCY blk00000099 ( .CI(sig00000014), .DI(sig000000f4), .S(sig0000002d), @@ -1412,17 +1391,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk0000009e ( + blk0000009a ( .I0(sig000000f4), .I1(sig00000114), .O(sig0000002d) ); - XORCY blk0000009f ( + XORCY blk0000009b ( .CI(sig00000013), .LI(sig0000002c), .O(sig00000151) ); - MUXCY blk000000a0 ( + MUXCY blk0000009c ( .CI(sig00000013), .DI(sig000000f3), .S(sig0000002c), @@ -1430,17 +1409,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk000000a1 ( + blk0000009d ( .I0(sig000000f3), .I1(sig00000113), .O(sig0000002c) ); - XORCY blk000000a2 ( + XORCY blk0000009e ( .CI(sig00000012), .LI(sig0000002b), .O(sig00000150) ); - MUXCY blk000000a3 ( + MUXCY blk0000009f ( .CI(sig00000012), .DI(sig000000f2), .S(sig0000002b), @@ -1448,209 +1427,209 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk000000a4 ( + blk000000a0 ( .I0(sig000000f2), .I1(sig00000112), .O(sig0000002b) ); - XORCY blk000000a5 ( - .CI(sig0000000e), + XORCY blk000000a1 ( + .CI(sig00000011), .LI(sig0000002a), .O(sig0000014f) ); - MUXCY blk000000a6 ( - .CI(sig0000000e), + MUXCY blk000000a2 ( + .CI(sig00000011), .DI(sig000000f1), .S(sig0000002a), .O(sig00000012) ); LUT2 #( .INIT ( 4'h6 )) - blk000000a7 ( + blk000000a3 ( .I0(sig000000f1), - .I1(sig0000010d), + .I1(sig00000111), .O(sig0000002a) ); - XORCY blk000000a8 ( - .CI(sig00000003), - .LI(sig00000025), - .O(sig0000014a) + XORCY blk000000a4 ( + .CI(sig0000000d), + .LI(sig00000029), + .O(sig0000014e) ); - MUXCY blk000000a9 ( - .CI(sig00000003), + MUXCY blk000000a5 ( + .CI(sig0000000d), .DI(sig000000f0), - .S(sig00000025), - .O(sig0000000e) + .S(sig00000029), + .O(sig00000011) ); LUT2 #( .INIT ( 4'h6 )) - blk000000aa ( + blk000000a6 ( .I0(sig000000f0), - .I1(sig00000102), - .O(sig00000025) + .I1(sig0000010c), + .O(sig00000029) ); - XORCY blk000000ab ( - .CI(sig00000001), - .LI(sig0000001a), - .O(sig0000013f) + XORCY blk000000a7 ( + .CI(sig00000002), + .LI(sig00000024), + .O(sig00000149) ); - MUXCY blk000000ac ( - .CI(sig00000001), + MUXCY blk000000a8 ( + .CI(sig00000002), .DI(sig000000ef), - .S(sig0000001a), - .O(sig00000003) + .S(sig00000024), + .O(sig0000000d) ); LUT2 #( .INIT ( 4'h6 )) - blk000000ad ( + blk000000a9 ( .I0(sig000000ef), .I1(sig00000101), - .O(sig0000001a) + .O(sig00000024) ); - XORCY blk000000ae ( - .CI(sig00000035), - .LI(sig00000043), - .O(sig0000015b) + XORCY blk000000aa ( + .CI(sig00000001), + .LI(sig00000019), + .O(sig0000013e) + ); + MUXCY blk000000ab ( + .CI(sig00000001), + .DI(sig000000ee), + .S(sig00000019), + .O(sig00000002) ); LUT2 #( .INIT ( 4'h6 )) - blk000000af ( - .I0(sig00000129), - .I1(sig00000136), - .O(sig00000043) + blk000000ac ( + .I0(sig000000ee), + .I1(sig00000100), + .O(sig00000019) ); - XORCY blk000000b0 ( + XORCY blk000000ad ( .CI(sig00000034), .LI(sig00000042), .O(sig0000015a) ); - MUXCY blk000000b1 ( - .CI(sig00000034), - .DI(sig00000129), - .S(sig00000042), - .O(sig00000035) - ); LUT2 #( .INIT ( 4'h6 )) - blk000000b2 ( - .I0(sig00000129), + blk000000ae ( + .I0(sig00000128), .I1(sig00000135), .O(sig00000042) ); - XORCY blk000000b3 ( + XORCY blk000000af ( .CI(sig00000033), .LI(sig00000041), .O(sig00000159) ); - MUXCY blk000000b4 ( + MUXCY blk000000b0 ( .CI(sig00000033), - .DI(sig00000129), + .DI(sig00000128), .S(sig00000041), .O(sig00000034) ); LUT2 #( .INIT ( 4'h6 )) - blk000000b5 ( - .I0(sig00000129), + blk000000b1 ( + .I0(sig00000128), .I1(sig00000134), .O(sig00000041) ); - XORCY blk000000b6 ( - .CI(sig0000003e), + XORCY blk000000b2 ( + .CI(sig00000032), .LI(sig00000040), .O(sig00000158) ); - MUXCY blk000000b7 ( - .CI(sig0000003e), - .DI(sig00000129), + MUXCY blk000000b3 ( + .CI(sig00000032), + .DI(sig00000128), .S(sig00000040), .O(sig00000033) ); LUT2 #( .INIT ( 4'h6 )) - blk000000b8 ( - .I0(sig00000129), + blk000000b4 ( + .I0(sig00000128), .I1(sig00000133), .O(sig00000040) ); - XORCY blk000000b9 ( + XORCY blk000000b5 ( .CI(sig0000003d), - .LI(sig0000004c), - .O(sig00000164) + .LI(sig0000003f), + .O(sig00000157) ); - MUXCY blk000000ba ( + MUXCY blk000000b6 ( .CI(sig0000003d), - .DI(sig00000129), - .S(sig0000004c), - .O(sig0000003e) + .DI(sig00000128), + .S(sig0000003f), + .O(sig00000032) ); LUT2 #( .INIT ( 4'h6 )) - blk000000bb ( - .I0(sig00000129), - .I1(sig0000013e), - .O(sig0000004c) + blk000000b7 ( + .I0(sig00000128), + .I1(sig00000132), + .O(sig0000003f) ); - XORCY blk000000bc ( + XORCY blk000000b8 ( .CI(sig0000003c), .LI(sig0000004b), .O(sig00000163) ); - MUXCY blk000000bd ( + MUXCY blk000000b9 ( .CI(sig0000003c), - .DI(sig00000129), + .DI(sig00000128), .S(sig0000004b), .O(sig0000003d) ); LUT2 #( .INIT ( 4'h6 )) - blk000000be ( - .I0(sig00000129), + blk000000ba ( + .I0(sig00000128), .I1(sig0000013d), .O(sig0000004b) ); - XORCY blk000000bf ( + XORCY blk000000bb ( .CI(sig0000003b), .LI(sig0000004a), .O(sig00000162) ); - MUXCY blk000000c0 ( + MUXCY blk000000bc ( .CI(sig0000003b), - .DI(sig00000129), + .DI(sig00000128), .S(sig0000004a), .O(sig0000003c) ); LUT2 #( .INIT ( 4'h6 )) - blk000000c1 ( - .I0(sig00000129), + blk000000bd ( + .I0(sig00000128), .I1(sig0000013c), .O(sig0000004a) ); - XORCY blk000000c2 ( + XORCY blk000000be ( .CI(sig0000003a), .LI(sig00000049), .O(sig00000161) ); - MUXCY blk000000c3 ( + MUXCY blk000000bf ( .CI(sig0000003a), - .DI(sig00000129), + .DI(sig00000128), .S(sig00000049), .O(sig0000003b) ); LUT2 #( .INIT ( 4'h6 )) - blk000000c4 ( - .I0(sig00000129), + blk000000c0 ( + .I0(sig00000128), .I1(sig0000013b), .O(sig00000049) ); - XORCY blk000000c5 ( + XORCY blk000000c1 ( .CI(sig00000039), .LI(sig00000048), .O(sig00000160) ); - MUXCY blk000000c6 ( + MUXCY blk000000c2 ( .CI(sig00000039), .DI(sig00000128), .S(sig00000048), @@ -1658,17 +1637,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk000000c7 ( + blk000000c3 ( .I0(sig00000128), .I1(sig0000013a), .O(sig00000048) ); - XORCY blk000000c8 ( + XORCY blk000000c4 ( .CI(sig00000038), .LI(sig00000047), .O(sig0000015f) ); - MUXCY blk000000c9 ( + MUXCY blk000000c5 ( .CI(sig00000038), .DI(sig00000127), .S(sig00000047), @@ -1676,17 +1655,17 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk000000ca ( + blk000000c6 ( .I0(sig00000127), .I1(sig00000139), .O(sig00000047) ); - XORCY blk000000cb ( + XORCY blk000000c7 ( .CI(sig00000037), .LI(sig00000046), .O(sig0000015e) ); - MUXCY blk000000cc ( + MUXCY blk000000c8 ( .CI(sig00000037), .DI(sig00000126), .S(sig00000046), @@ -1694,742 +1673,857 @@ sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) ); LUT2 #( .INIT ( 4'h6 )) - blk000000cd ( + blk000000c9 ( .I0(sig00000126), .I1(sig00000138), .O(sig00000046) ); - XORCY blk000000ce ( + XORCY blk000000ca ( .CI(sig00000036), .LI(sig00000045), .O(sig0000015d) ); - MUXCY blk000000cf ( + MUXCY blk000000cb ( .CI(sig00000036), - .DI(sig00000124), + .DI(sig00000125), .S(sig00000045), .O(sig00000037) ); LUT2 #( .INIT ( 4'h6 )) - blk000000d0 ( - .I0(sig00000124), + blk000000cc ( + .I0(sig00000125), .I1(sig00000137), .O(sig00000045) ); - XORCY blk000000d1 ( - .CI(sig00000032), + XORCY blk000000cd ( + .CI(sig00000035), .LI(sig00000044), .O(sig0000015c) ); - MUXCY blk000000d2 ( - .CI(sig00000032), + MUXCY blk000000ce ( + .CI(sig00000035), .DI(sig00000123), .S(sig00000044), .O(sig00000036) ); LUT2 #( .INIT ( 4'h6 )) - blk000000d3 ( + blk000000cf ( .I0(sig00000123), - .I1(sig00000132), + .I1(sig00000136), .O(sig00000044) ); - XORCY blk000000d4 ( - .CI(sig00000001), - .LI(sig0000003f), - .O(sig00000157) + XORCY blk000000d0 ( + .CI(sig00000031), + .LI(sig00000043), + .O(sig0000015b) ); - MUXCY blk000000d5 ( - .CI(sig00000001), + MUXCY blk000000d1 ( + .CI(sig00000031), .DI(sig00000122), - .S(sig0000003f), - .O(sig00000032) + .S(sig00000043), + .O(sig00000035) ); LUT2 #( .INIT ( 4'h6 )) - blk000000d6 ( + blk000000d2 ( .I0(sig00000122), .I1(sig00000131), - .O(sig0000003f) + .O(sig00000043) ); - FD #( - .INIT ( 1'b0 )) - blk000000d7 ( - .C(clk), - .D(sig000000d8), - .Q(sig00000129) + XORCY blk000000d3 ( + .CI(sig00000001), + .LI(sig0000003e), + .O(sig00000156) ); - FD #( + MUXCY blk000000d4 ( + .CI(sig00000001), + .DI(sig00000121), + .S(sig0000003e), + .O(sig00000031) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d5 ( + .I0(sig00000121), + .I1(sig00000130), + .O(sig0000003e) + ); + FDE #( .INIT ( 1'b0 )) - blk000000d8 ( + blk000000d6 ( .C(clk), + .CE(ce), .D(sig000000d7), .Q(sig00000128) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000d9 ( + blk000000d7 ( .C(clk), + .CE(ce), .D(sig000000d6), .Q(sig00000127) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000da ( + blk000000d8 ( .C(clk), + .CE(ce), .D(sig000000d5), .Q(sig00000126) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000db ( + blk000000d9 ( .C(clk), - .D(sig000000d3), - .Q(sig00000124) + .CE(ce), + .D(sig000000d4), + .Q(sig00000125) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000dc ( + blk000000da ( .C(clk), + .CE(ce), .D(sig000000d2), .Q(sig00000123) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000dd ( + blk000000db ( .C(clk), + .CE(ce), .D(sig000000d1), .Q(sig00000122) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000de ( + blk000000dc ( .C(clk), + .CE(ce), .D(sig000000d0), .Q(sig00000121) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000df ( + blk000000dd ( .C(clk), + .CE(ce), .D(sig000000cf), .Q(sig00000120) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e0 ( + blk000000de ( .C(clk), + .CE(ce), .D(sig000000ce), .Q(sig0000011f) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e1 ( + blk000000df ( .C(clk), + .CE(ce), .D(sig000000cd), .Q(sig0000011e) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e2 ( + blk000000e0 ( .C(clk), + .CE(ce), .D(sig000000cc), .Q(sig0000011d) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e3 ( + blk000000e1 ( .C(clk), + .CE(ce), .D(sig000000cb), .Q(sig0000011c) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e4 ( + blk000000e2 ( .C(clk), + .CE(ce), .D(sig000000ca), .Q(sig0000011b) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e5 ( + blk000000e3 ( .C(clk), - .D(sig000000e0), - .Q(sig00000130) + .CE(ce), + .D(sig000000c9), + .Q(sig0000011a) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e6 ( + blk000000e4 ( .C(clk), + .CE(ce), .D(sig000000df), .Q(sig0000012f) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e7 ( + blk000000e5 ( .C(clk), + .CE(ce), .D(sig000000de), .Q(sig0000012e) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e8 ( + blk000000e6 ( .C(clk), + .CE(ce), .D(sig000000dd), .Q(sig0000012d) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000e9 ( + blk000000e7 ( .C(clk), + .CE(ce), .D(sig000000dc), .Q(sig0000012c) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000ea ( + blk000000e8 ( .C(clk), + .CE(ce), .D(sig000000db), .Q(sig0000012b) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000eb ( + blk000000e9 ( .C(clk), + .CE(ce), .D(sig000000da), .Q(sig0000012a) ); - FD #( + FDE #( + .INIT ( 1'b0 )) + blk000000ea ( + .C(clk), + .CE(ce), + .D(sig000000d9), + .Q(sig00000129) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000eb ( + .C(clk), + .CE(ce), + .D(sig000000d8), + .Q(sig00000124) + ); + FDE #( .INIT ( 1'b0 )) blk000000ec ( .C(clk), - .D(sig000000d9), - .Q(sig00000125) + .CE(ce), + .D(sig000000d3), + .Q(sig00000119) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk000000ed ( .C(clk), - .D(sig000000d4), - .Q(sig0000011a) - ); - FD #( - .INIT ( 1'b0 )) - blk000000ee ( - .C(clk), - .D(sig000000c9), - .Q(sig00000119) - ); - FD #( - .INIT ( 1'b0 )) - blk000000ef ( - .C(clk), - .D(sig000000c0), - .Q(sig00000111) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f0 ( - .C(clk), - .D(sig000000bf), - .Q(sig00000110) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f1 ( - .C(clk), - .D(sig000000be), - .Q(sig0000010f) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f2 ( - .C(clk), - .D(sig000000bd), - .Q(sig0000010e) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f3 ( - .C(clk), - .D(sig000000bb), - .Q(sig0000010c) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f4 ( - .C(clk), - .D(sig000000ba), - .Q(sig0000010b) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f5 ( - .C(clk), - .D(sig000000b9), - .Q(sig0000010a) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f6 ( - .C(clk), - .D(sig000000b8), - .Q(sig00000109) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f7 ( - .C(clk), - .D(sig000000b7), - .Q(sig00000108) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f8 ( - .C(clk), - .D(sig000000b6), - .Q(sig00000107) - ); - FD #( - .INIT ( 1'b0 )) - blk000000f9 ( - .C(clk), - .D(sig000000b5), - .Q(sig00000106) - ); - FD #( - .INIT ( 1'b0 )) - blk000000fa ( - .C(clk), - .D(sig000000b4), - .Q(sig00000105) - ); - FD #( - .INIT ( 1'b0 )) - blk000000fb ( - .C(clk), - .D(sig000000b3), - .Q(sig00000104) - ); - FD #( - .INIT ( 1'b0 )) - blk000000fc ( - .C(clk), - .D(sig000000b2), - .Q(sig00000103) - ); - FD #( - .INIT ( 1'b0 )) - blk000000fd ( - .C(clk), + .CE(ce), .D(sig000000c8), .Q(sig00000118) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000fe ( + blk000000ee ( .C(clk), + .CE(ce), + .D(sig000000bf), + .Q(sig00000110) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000ef ( + .C(clk), + .CE(ce), + .D(sig000000be), + .Q(sig0000010f) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f0 ( + .C(clk), + .CE(ce), + .D(sig000000bd), + .Q(sig0000010e) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f1 ( + .C(clk), + .CE(ce), + .D(sig000000bc), + .Q(sig0000010d) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f2 ( + .C(clk), + .CE(ce), + .D(sig000000ba), + .Q(sig0000010b) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f3 ( + .C(clk), + .CE(ce), + .D(sig000000b9), + .Q(sig0000010a) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f4 ( + .C(clk), + .CE(ce), + .D(sig000000b8), + .Q(sig00000109) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f5 ( + .C(clk), + .CE(ce), + .D(sig000000b7), + .Q(sig00000108) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f6 ( + .C(clk), + .CE(ce), + .D(sig000000b6), + .Q(sig00000107) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f7 ( + .C(clk), + .CE(ce), + .D(sig000000b5), + .Q(sig00000106) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f8 ( + .C(clk), + .CE(ce), + .D(sig000000b4), + .Q(sig00000105) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000f9 ( + .C(clk), + .CE(ce), + .D(sig000000b3), + .Q(sig00000104) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000fa ( + .C(clk), + .CE(ce), + .D(sig000000b2), + .Q(sig00000103) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000fb ( + .C(clk), + .CE(ce), + .D(sig000000b1), + .Q(sig00000102) + ); + FDE #( + .INIT ( 1'b0 )) + blk000000fc ( + .C(clk), + .CE(ce), .D(sig000000c7), .Q(sig00000117) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk000000ff ( + blk000000fd ( .C(clk), + .CE(ce), .D(sig000000c6), .Q(sig00000116) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000100 ( + blk000000fe ( .C(clk), + .CE(ce), .D(sig000000c5), .Q(sig00000115) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000101 ( + blk000000ff ( .C(clk), + .CE(ce), .D(sig000000c4), .Q(sig00000114) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000102 ( + blk00000100 ( .C(clk), + .CE(ce), .D(sig000000c3), .Q(sig00000113) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000103 ( + blk00000101 ( .C(clk), + .CE(ce), .D(sig000000c2), .Q(sig00000112) ); - FD #( + FDE #( + .INIT ( 1'b0 )) + blk00000102 ( + .C(clk), + .CE(ce), + .D(sig000000c1), + .Q(sig00000111) + ); + FDE #( + .INIT ( 1'b0 )) + blk00000103 ( + .C(clk), + .CE(ce), + .D(sig000000c0), + .Q(sig0000010c) + ); + FDE #( .INIT ( 1'b0 )) blk00000104 ( .C(clk), - .D(sig000000c1), - .Q(sig0000010d) + .CE(ce), + .D(sig000000bb), + .Q(sig00000101) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000105 ( .C(clk), - .D(sig000000bc), - .Q(sig00000102) + .CE(ce), + .D(sig000000b0), + .Q(sig00000100) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000106 ( .C(clk), - .D(sig000000b1), - .Q(sig00000101) - ); - FD #( - .INIT ( 1'b0 )) - blk00000107 ( - .C(clk), - .D(sig000000e5), - .Q(sig00000136) - ); - FD #( - .INIT ( 1'b0 )) - blk00000108 ( - .C(clk), + .CE(ce), .D(sig000000e4), .Q(sig00000135) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000109 ( + blk00000107 ( .C(clk), + .CE(ce), .D(sig000000e3), .Q(sig00000134) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010a ( + blk00000108 ( .C(clk), + .CE(ce), .D(sig000000e2), .Q(sig00000133) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010b ( + blk00000109 ( .C(clk), - .D(sig000000ee), - .Q(sig0000013e) + .CE(ce), + .D(sig000000e1), + .Q(sig00000132) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010c ( + blk0000010a ( .C(clk), + .CE(ce), .D(sig000000ed), .Q(sig0000013d) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010d ( + blk0000010b ( .C(clk), + .CE(ce), .D(sig000000ec), .Q(sig0000013c) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010e ( + blk0000010c ( .C(clk), + .CE(ce), .D(sig000000eb), .Q(sig0000013b) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000010f ( + blk0000010d ( .C(clk), + .CE(ce), .D(sig000000ea), .Q(sig0000013a) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000110 ( + blk0000010e ( .C(clk), + .CE(ce), .D(sig000000e9), .Q(sig00000139) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000111 ( + blk0000010f ( .C(clk), + .CE(ce), .D(sig000000e8), .Q(sig00000138) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000112 ( + blk00000110 ( .C(clk), + .CE(ce), .D(sig000000e7), .Q(sig00000137) ); - FD #( + FDE #( + .INIT ( 1'b0 )) + blk00000111 ( + .C(clk), + .CE(ce), + .D(sig000000e6), + .Q(sig00000136) + ); + FDE #( + .INIT ( 1'b0 )) + blk00000112 ( + .C(clk), + .CE(ce), + .D(sig000000e5), + .Q(sig00000131) + ); + FDE #( .INIT ( 1'b0 )) blk00000113 ( .C(clk), - .D(sig000000e6), - .Q(sig00000132) + .CE(ce), + .D(sig000000e0), + .Q(sig00000130) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000114 ( .C(clk), - .D(sig000000e1), - .Q(sig00000131) - ); - FD #( - .INIT ( 1'b0 )) - blk00000115 ( - .C(clk), - .D(sig000000a9), - .Q(sig00000100) - ); - FD #( - .INIT ( 1'b0 )) - blk00000116 ( - .C(clk), + .CE(ce), .D(sig000000a8), .Q(sig000000ff) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000117 ( + blk00000115 ( .C(clk), + .CE(ce), .D(sig000000a7), .Q(sig000000fe) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000118 ( + blk00000116 ( .C(clk), + .CE(ce), .D(sig000000a6), .Q(sig000000fd) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000119 ( + blk00000117 ( .C(clk), + .CE(ce), .D(sig000000a5), .Q(sig000000fc) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011a ( + blk00000118 ( .C(clk), - .D(sig000000a3), + .CE(ce), + .D(sig000000a4), .Q(sig000000fb) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011b ( + blk00000119 ( .C(clk), + .CE(ce), .D(sig000000a2), .Q(sig000000fa) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011c ( + blk0000011a ( .C(clk), + .CE(ce), .D(sig000000a1), .Q(sig000000f9) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011d ( + blk0000011b ( .C(clk), + .CE(ce), .D(sig000000a0), .Q(sig000000f8) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011e ( + blk0000011c ( .C(clk), + .CE(ce), .D(sig0000009f), .Q(sig000000f7) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk0000011f ( + blk0000011d ( .C(clk), + .CE(ce), .D(sig0000009e), .Q(sig000000f6) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000120 ( + blk0000011e ( .C(clk), + .CE(ce), .D(sig0000009d), .Q(sig000000f5) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000121 ( + blk0000011f ( .C(clk), + .CE(ce), .D(sig0000009c), .Q(sig000000f4) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000122 ( + blk00000120 ( .C(clk), + .CE(ce), .D(sig0000009b), .Q(sig000000f3) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000123 ( + blk00000121 ( .C(clk), + .CE(ce), .D(sig0000009a), .Q(sig000000f2) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000124 ( + blk00000122 ( .C(clk), - .D(sig00000098), + .CE(ce), + .D(sig00000099), .Q(sig000000f1) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000125 ( + blk00000123 ( .C(clk), + .CE(ce), .D(sig00000097), .Q(sig000000f0) ); - FD #( + FDE #( .INIT ( 1'b0 )) - blk00000126 ( + blk00000124 ( .C(clk), + .CE(ce), .D(sig00000096), .Q(sig000000ef) ); - FD #( + FDE #( + .INIT ( 1'b0 )) + blk00000125 ( + .C(clk), + .CE(ce), + .D(sig00000095), + .Q(sig000000ee) + ); + FDE #( + .INIT ( 1'b0 )) + blk00000126 ( + .C(clk), + .CE(ce), + .D(sig00000094), + .Q(p[16]) + ); + FDE #( .INIT ( 1'b0 )) blk00000127 ( .C(clk), - .D(sig00000095), - .Q(p[16]) + .CE(ce), + .D(sig00000093), + .Q(p[15]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000128 ( .C(clk), - .D(sig00000094), - .Q(p[15]) + .CE(ce), + .D(sig00000092), + .Q(p[14]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000129 ( .C(clk), - .D(sig00000093), - .Q(p[14]) + .CE(ce), + .D(sig00000091), + .Q(p[13]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012a ( .C(clk), - .D(sig00000092), - .Q(p[13]) + .CE(ce), + .D(sig00000090), + .Q(p[12]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012b ( .C(clk), - .D(sig00000091), - .Q(p[12]) + .CE(ce), + .D(sig0000008f), + .Q(p[11]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012c ( .C(clk), - .D(sig00000090), - .Q(p[11]) + .CE(ce), + .D(sig0000008e), + .Q(p[10]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012d ( .C(clk), - .D(sig0000008f), - .Q(p[10]) + .CE(ce), + .D(sig000000af), + .Q(p[9]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012e ( .C(clk), - .D(sig000000b0), - .Q(p[9]) + .CE(ce), + .D(sig000000ae), + .Q(p[8]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk0000012f ( .C(clk), - .D(sig000000af), - .Q(p[8]) + .CE(ce), + .D(sig000000ad), + .Q(p[7]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000130 ( .C(clk), - .D(sig000000ae), - .Q(p[7]) + .CE(ce), + .D(sig000000ac), + .Q(p[6]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000131 ( .C(clk), - .D(sig000000ad), - .Q(p[6]) + .CE(ce), + .D(sig000000ab), + .Q(p[5]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000132 ( .C(clk), - .D(sig000000ac), - .Q(p[5]) + .CE(ce), + .D(sig000000aa), + .Q(p[4]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000133 ( .C(clk), - .D(sig000000ab), - .Q(p[4]) + .CE(ce), + .D(sig000000a9), + .Q(p[3]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000134 ( .C(clk), - .D(sig000000aa), - .Q(p[3]) + .CE(ce), + .D(sig000000a3), + .Q(p[2]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000135 ( .C(clk), - .D(sig000000a4), - .Q(p[2]) + .CE(ce), + .D(sig00000098), + .Q(p[1]) ); - FD #( + FDE #( .INIT ( 1'b0 )) blk00000136 ( .C(clk), - .D(sig00000099), - .Q(p[1]) - ); - FD #( - .INIT ( 1'b0 )) - blk00000137 ( - .C(clk), - .D(sig0000008e), + .CE(ce), + .D(sig0000008d), .Q(p[0]) ); diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco index 13cf374..0935e67 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 13.2 -# Date: Fri Oct 28 08:30:26 2011 +# Date: Sun Oct 30 20:22:20 2011 # ############################################################## # @@ -40,7 +40,7 @@ SELECT Multiplier xilinx.com:ip:mult_gen:11.2 # END Select # BEGIN Parameters CSET ccmimp=Distributed_Memory -CSET clockenable=false +CSET clockenable=true CSET component_name=cx4_mul CSET constvalue=129 CSET internaluser=0 @@ -65,4 +65,4 @@ CSET zerodetect=false MISC pkg_timestamp=2011-06-21T06:26:54.000Z # END Extra information GENERATE -# CRC: efe4d30e +# CRC: 4f144c3 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise index 60829e7..ed5595c 100644 --- a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise @@ -29,29 +29,335 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise index a182ee5..ca19fae 100644 --- a/verilog/sd2snes_cx4/sd2snes_cx4.xise +++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise @@ -238,7 +238,7 @@ - + @@ -253,7 +253,7 @@ - + @@ -290,7 +290,7 @@ - + @@ -321,7 +321,7 @@ - + @@ -330,7 +330,7 @@ - + @@ -366,8 +366,8 @@ - - + + From 1987968db27c53eeb2b273a5556abcb24eb8fe5d Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 1 Nov 2011 21:09:31 +0100 Subject: [PATCH 15/66] FPGA/cx4: clean up tab/whitespace mix --- verilog/sd2snes_cx4/address.v | 4 +- verilog/sd2snes_cx4/main.v | 208 +++++++++++++++++----------------- verilog/sd2snes_cx4/spi.v | 2 +- 3 files changed, 107 insertions(+), 107 deletions(-) diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v index c2502d3..1ec0902 100644 --- a/verilog/sd2snes_cx4/address.v +++ b/verilog/sd2snes_cx4/address.v @@ -38,8 +38,8 @@ module address( wire [23:0] SRAM_SNES_ADDR; /* Cx4 mapper: - - LoROM (extended to 00-7d, 80-ff) - - MMIO @ 6000-7fff + - LoROM (extended to 00-7d, 80-ff) + - MMIO @ 6000-7fff */ assign IS_ROM = SNES_ADDR[15] & ~SNES_CS; diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index de849b4..9e564dc 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -305,7 +305,7 @@ cx4 snes_cx4 ( .BUS_RDY(CX4_RDY), .cx4_active(cx4_active) ); - + parameter MODE_SNES = 1'b0; parameter MODE_MCU = 1'b1; @@ -349,7 +349,7 @@ reg [7:0] ROM_DOUTr; assign SNES_DATA = (!SNES_READ) ? (msu_enable ? MSU_SNES_DATA_OUT - :cx4_enable ? CX4_SNES_DATA_OUT + :cx4_enable ? CX4_SNES_DATA_OUT :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT : SNES_DINr) : 8'bZ; @@ -381,14 +381,14 @@ assign MCU_RDY = RQ_MCU_RDYr; always @(posedge CLK2) begin if(MCU_RRQ) begin MCU_RD_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(MCU_WRQ) begin MCU_WR_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin MCU_RD_PENDr <= 1'b0; - MCU_WR_PENDr <= 1'b0; - RQ_MCU_RDYr <= 1'b1; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; end end @@ -399,10 +399,10 @@ assign CX4_RDY = RQ_CX4_RDYr; always @(posedge CLK2) begin if(CX4_RRQ) begin CX4_RD_PENDr <= 1'b1; - RQ_CX4_RDYr <= 1'b0; + RQ_CX4_RDYr <= 1'b0; end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin CX4_RD_PENDr <= 1'b0; - RQ_CX4_RDYr <= 1'b1; + RQ_CX4_RDYr <= 1'b1; end end @@ -416,126 +416,126 @@ always @(posedge CLK2) begin end else begin case(STATE) ST_IDLE: begin - ROM_ADDRr <= MAPPED_SNES_ADDR; + ROM_ADDRr <= MAPPED_SNES_ADDR; if(CX4_RD_PENDr) begin STATE <= ST_CX4_RD_WAIT; ROM_ADDRr <= CX4_ADDR; ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; end else if(~cx4_active && ~ASSERT_SNES_ADDR) begin - if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; - else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; + if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; + else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; else STATE <= ST_IDLE; end else STATE <= ST_IDLE; - end - ST_SNES_RD_ADDR: begin - STATE <= ST_SNES_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT; - end - ST_SNES_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; - else STATE <= ST_SNES_RD_WAIT; - if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; - else SNES_DINr <= ROM_DATA[15:8]; - end - ST_SNES_RD_END: begin - STATE <= ST_IDLE; - if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; - else SNES_DINr <= ROM_DATA[15:8]; - end + end + ST_SNES_RD_ADDR: begin + STATE <= ST_SNES_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT; + end + ST_SNES_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; + else STATE <= ST_SNES_RD_WAIT; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_RD_END: begin + STATE <= ST_IDLE; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end ST_SNES_WR_ADDR: begin ROM_WEr <= (!IS_WRITABLE); snes_wr_cycle <= 1'b1; - STATE <= ST_SNES_WR_WAIT1; - ST_MEM_DELAYr <= ROM_WR_WAIT1; - end - ST_SNES_WR_WAIT1: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; - else STATE <= ST_SNES_WR_WAIT1; - end - ST_SNES_WR_DATA: begin + STATE <= ST_SNES_WR_WAIT1; + ST_MEM_DELAYr <= ROM_WR_WAIT1; + end + ST_SNES_WR_WAIT1: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; + else STATE <= ST_SNES_WR_WAIT1; + end + ST_SNES_WR_DATA: begin ROM_DOUTr <= SNES_DATA; - ST_MEM_DELAYr <= ROM_WR_WAIT2; - STATE <= ST_SNES_WR_WAIT2; - end + ST_MEM_DELAYr <= ROM_WR_WAIT2; + STATE <= ST_SNES_WR_WAIT2; + end ST_SNES_WR_WAIT2: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; - else STATE <= ST_SNES_WR_WAIT2; - end - ST_SNES_WR_END: begin - STATE <= ST_IDLE; - ROM_WEr <= 1'b1; - snes_wr_cycle <= 1'b0; - end - ST_MCU_RD_ADDR: begin - ROM_ADDRr <= MCU_ADDR; - STATE <= ST_MCU_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; - end - ST_MCU_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - STATE <= ST_MCU_RD_WAIT2; + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; + else STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_END: begin + STATE <= ST_IDLE; + ROM_WEr <= 1'b1; + snes_wr_cycle <= 1'b0; + end + ST_MCU_RD_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; + end + ST_MCU_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_WAIT2; ST_MEM_DELAYr <= 4'h2; if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; else MCU_DINr <= ROM_DATA[15:8]; - end - else STATE <= ST_MCU_RD_WAIT; + end + else STATE <= ST_MCU_RD_WAIT; end - ST_MCU_RD_WAIT2: begin + ST_MCU_RD_WAIT2: begin ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin - STATE <= ST_MCU_RD_END; - end else STATE <= ST_MCU_RD_WAIT2; - end - ST_MCU_RD_END: begin - STATE <= ST_IDLE; - end - ST_MCU_WR_ADDR: begin - ROM_ADDRr <= MCU_ADDR; - STATE <= ST_MCU_WR_WAIT; - ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; - ROM_DOUTr <= MCU_DOUT; - ROM_WEr <= 1'b0; - end - ST_MCU_WR_WAIT: begin + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_END; + end else STATE <= ST_MCU_RD_WAIT2; + end + ST_MCU_RD_END: begin + STATE <= ST_IDLE; + end + ST_MCU_WR_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_WR_WAIT; + ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; + ROM_DOUTr <= MCU_DOUT; + ROM_WEr <= 1'b0; + end + ST_MCU_WR_WAIT: begin ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin + if(ST_MEM_DELAYr == 4'h0) begin ROM_WEr <= 1'b1; - STATE <= ST_MCU_WR_WAIT2; - ST_MEM_DELAYr <= 4'h2; - end - else STATE <= ST_MCU_WR_WAIT; + STATE <= ST_MCU_WR_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_WR_WAIT; end - ST_MCU_WR_WAIT2: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) begin + ST_MCU_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin STATE <= ST_MCU_WR_END; end else STATE <= ST_MCU_WR_WAIT2; - end - ST_MCU_WR_END: begin - STATE <= ST_IDLE; - end - - ST_CX4_RD_ADDR: begin - ROM_ADDRr <= CX4_ADDR; - STATE <= ST_CX4_RD_WAIT; - ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; - end - ST_CX4_RD_WAIT: begin - ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; - if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE; - else STATE <= ST_CX4_RD_WAIT; - if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; - else CX4_DINr <= ROM_DATA[15:8]; end - ST_CX4_RD_END: begin - STATE <= ST_IDLE; - end - endcase + ST_MCU_WR_END: begin + STATE <= ST_IDLE; + end + + ST_CX4_RD_ADDR: begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + ST_CX4_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_IDLE; + else STATE <= ST_CX4_RD_WAIT; + if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; + else CX4_DINr <= ROM_DATA[15:8]; + end + ST_CX4_RD_END: begin + STATE <= ST_IDLE; + end + endcase end end diff --git a/verilog/sd2snes_cx4/spi.v b/verilog/sd2snes_cx4/spi.v index cb6bf79..8b9b0fd 100644 --- a/verilog/sd2snes_cx4/spi.v +++ b/verilog/sd2snes_cx4/spi.v @@ -59,7 +59,7 @@ always @(posedge SCK) begin if(SSEL) bitcnt <= 3'b000; else begin bitcnt <= bitcnt + 3'b001; - byte_data_received <= {byte_data_received[6:0], MOSI}; + byte_data_received <= {byte_data_received[6:0], MOSI}; end if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1; else byte_received <= 1'b0; From 6a17ffe1521dfe7f1609608a33a928be6b135e56 Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 1 Nov 2011 22:01:14 +0100 Subject: [PATCH 16/66] Firmware: cx4 support --- src/memory.c | 8 +++++++- src/smc.c | 2 ++ src/smc.h | 3 +++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/memory.c b/src/memory.c index 3797114..d276178 100644 --- a/src/memory.c +++ b/src/memory.c @@ -191,7 +191,14 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) { } filesize = file_handle.fsize; smc_id(&romprops); + file_close(); + /* reconfigure FPGA if necessary */ + if(romprops.fpga_conf) { + printf("reconfigure FPGA with %s...\n", romprops.fpga_conf); + fpga_pgm((uint8_t*)romprops.fpga_conf); + } set_mcu_addr(base_addr); + file_open(filename, FA_READ); f_lseek(&file_handle, romprops.offset); for(;;) { ff_sd_offload=1; @@ -226,7 +233,6 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) { sram_writebyte(0xfc, rombase+0xd5); set_fpga_time(0x0220110301180530LL); } -fpga_pgm((uint8_t*)"/sd2snes/cx4.bit"); if(romprops.has_dspx || romprops.has_cx4) { printf("DSPx game. Loading firmware image %s...\n", romprops.dsp_fw); load_dspx(romprops.dsp_fw, romprops.fpga_features); diff --git a/src/smc.c b/src/smc.c index 202c2ff..3a07223 100644 --- a/src/smc.c +++ b/src/smc.c @@ -85,6 +85,7 @@ void smc_id(snes_romprops_t* props) { props->has_st0010 = 0; props->has_cx4 = 0; props->fpga_features = 0; + props->fpga_conf = NULL; for(uint8_t num = 0; num < 6; num++) { if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t)) || file_res) { @@ -155,6 +156,7 @@ void smc_id(snes_romprops_t* props) { if (header->map == 0x20 && header->carttype == 0xf3) { props->has_cx4 = 1; props->dsp_fw = CX4FW; + props->fpga_conf = FPGA_CX4; props->fpga_features |= FEAT_CX4; } else if ((header->map == 0x20 && header->carttype == 0x03) || diff --git a/src/smc.h b/src/smc.h index 561078f..8e77b7c 100644 --- a/src/smc.h +++ b/src/smc.h @@ -35,6 +35,8 @@ #define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin") #define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin") +#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit") + typedef struct _snes_header { uint8_t maker[2]; /* 0xB0 */ uint8_t gamecode[4]; /* 0xB2 */ @@ -62,6 +64,7 @@ typedef struct _snes_romprops { uint32_t ramsize_bytes; /* CartRAM size in bytes */ uint32_t romsize_bytes; /* ROM size in bytes (rounded up) */ const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */ + const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */ uint8_t has_dspx; /* DSP[1-4] presence flag */ uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/ uint8_t has_msu1; /* MSU1 presence flag */ From 3fda86125c1eda0dc6610564c3c7b00eda3fe2d8 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 15:31:58 +0100 Subject: [PATCH 17/66] firmware: speed up directory scanning --- src/ff.c | 61 ++++++++++++++++++++++++++++++++----------------- src/ff.h | 1 + src/fileops.c | 4 ++++ src/fileops.h | 1 + src/filetypes.c | 10 +++++--- src/filetypes.h | 2 +- src/main.c | 4 ++-- 7 files changed, 56 insertions(+), 27 deletions(-) diff --git a/src/ff.c b/src/ff.c index 4f9e0cd..2d7862a 100644 --- a/src/ff.c +++ b/src/ff.c @@ -2822,6 +2822,46 @@ FRESULT f_readdir ( } +FRESULT l_opendirbycluster ( + FATFS *fs, + DIR *dj, + const TCHAR *path, + DWORD clust +) +{ + FRESULT res; + res = chk_mounted(&path, &fs, 0); + DEF_NAMEBUF; + INIT_BUF(*dj); + dj->sclust = clust; + dj->fs = fs; + dj->id = fs->id; + dj->dir = 0; + res = dir_sdi(dj, 0); + FREE_BUF(); + return res; +} + +FRESULT l_openfilebycluster ( + FATFS *fs, /* Pointer to file system object */ + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, + DWORD clust, /* Cluster number to be opened */ + DWORD fsize /* File size to be assumed */ +) +{ + chk_mounted(&path, &fs, 0); + fp->flag = FA_READ; + fp->org_clust = clust; + fp->fsize = fsize; + fp->fptr = 0; + fp->dsect = 0; + fp->fs = fs; + + return FR_OK; +} + + #if _FS_MINIMIZE == 0 /*-----------------------------------------------------------------------*/ @@ -2854,27 +2894,6 @@ FRESULT f_stat ( LEAVE_FF(dj.fs, res); } - -FRESULT l_openfilebycluster ( - FATFS *fs, /* Pointer to file system object */ - FIL *fp, /* Pointer to the blank file object */ - const TCHAR *path, - DWORD clust, /* Cluster number to be opened */ - DWORD fsize /* File size to be assumed */ -) -{ - chk_mounted(&path, &fs, 0); - fp->flag = FA_READ; - fp->org_clust = clust; - fp->fsize = fsize; - fp->fptr = 0; - fp->dsect = 0; - fp->fs = fs; - - return FR_OK; -} - - #if !_FS_READONLY /*-----------------------------------------------------------------------*/ /* Get Number of Free Clusters */ diff --git a/src/ff.h b/src/ff.h index 438fa14..55abce9 100644 --- a/src/ff.h +++ b/src/ff.h @@ -398,6 +398,7 @@ typedef enum { /* Low Level functions */ FRESULT l_openfilebycluster(FATFS *fs, FIL *fp, const TCHAR *path, DWORD clust, DWORD fsize); /* Open a file by its start cluster using supplied file size */ +FRESULT l_opendirbycluster (FATFS *fs, DIR *dj, const TCHAR *path, DWORD clust); /* application level functions */ FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ diff --git a/src/fileops.c b/src/fileops.c index f211992..4e681d1 100644 --- a/src/fileops.c +++ b/src/fileops.c @@ -47,6 +47,10 @@ void file_reinit(void) { file_init(); } +FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno) { + return l_opendirbycluster(&fatfs, dir, (TCHAR*)"", fno->clust); +} + void file_open_by_filinfo(FILINFO* fno) { file_res = l_openfilebycluster(&fatfs, &file_handle, (TCHAR*)"", fno->clust, fno->fsize); } diff --git a/src/fileops.h b/src/fileops.h index b866b65..633ee25 100644 --- a/src/fileops.h +++ b/src/fileops.h @@ -41,6 +41,7 @@ enum filestates file_status; void file_init(void); void file_open(uint8_t* filename, BYTE flags); +FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno_param); void file_open_by_filinfo(FILINFO* fno); void file_close(void); void file_seek(uint32_t offset); diff --git a/src/filetypes.c b/src/filetypes.c index d333369..7e05851 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -53,7 +53,7 @@ uint16_t scan_flat(const char* path) { return numentries; } -uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { +uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_tgt) { DIR dir; FILINFO fno; FRESULT res; @@ -103,7 +103,11 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { sram_writelong(0L, next_subdir_tgt - 4); } } - res = f_opendir(&dir, (TCHAR*)path); + if(fno_param) { + res = dir_open_by_filinfo(&dir, fno_param); + } else { + res = f_opendir(&dir, path); + } if (res == FR_OK) { if(pass && parent_tgt && mkdb) { /* write backlink to parent dir @@ -162,7 +166,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { db_tgt += sizeof(next_subdir_tgt) + sizeof(len) + pathlen + 2; } parent_tgt = this_dir_tgt; - scan_dir(path, mkdb, next_subdir_tgt); + scan_dir(path, &fno, mkdb, next_subdir_tgt); dir_tgt += 4; was_empty = 0; } diff --git a/src/filetypes.h b/src/filetypes.h index d50ff42..d42546a 100644 --- a/src/filetypes.h +++ b/src/filetypes.h @@ -50,7 +50,7 @@ char fs_path[256]; SNES_FTYPE determine_filetype(char* filename); //uint32_t scan_fs(); uint16_t scan_flat(const char* path); -uint32_t scan_dir(char* path, char mkdb, uint32_t this_subdir_tgt); +uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_subdir_tgt); FRESULT get_db_id(uint32_t*); int get_num_dirent(uint32_t addr); void sort_all_dir(uint32_t endaddr); diff --git a/src/main.c b/src/main.c index 366072c..8f961ce 100644 --- a/src/main.c +++ b/src/main.c @@ -145,7 +145,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) { newcard = 0; /* generate fs footprint (interesting files only) */ - uint32_t curr_dir_id = scan_dir(fs_path, 0, 0); + uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0); printf("curr dir id = %lx\n", curr_dir_id); /* files changed or no database found? */ if((get_db_id(&saved_dir_id) != FR_OK) @@ -154,7 +154,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); printf("saved dir id = %lx\n", saved_dir_id); printf("rebuilding database..."); snes_bootprint(" rebuilding database ... \0"); - curr_dir_id = scan_dir(fs_path, 1, 0); + curr_dir_id = scan_dir(fs_path, NULL, 1, 0); sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4); uint32_t endaddr, direndaddr; sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4); From 68f255d75b804e30184f61c6b0cabb3f30508ee6 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 17:54:52 +0100 Subject: [PATCH 18/66] firmware, FPGA: fix for some SD cards --- src/sdnative.c | 3 +++ verilog/sd2snes/sd_dma.v | 6 +++--- verilog/sd2snes_cx4/sd_dma.v | 6 +++--- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/sdnative.c b/src/sdnative.c index 95abd93..76218b9 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -867,6 +867,9 @@ DRESULT sdn_initialize(BYTE drv) { if(rsp[1]&0x80) break; } + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + ccs = (rsp[1]>>6) & 1; /* SDHC/XC */ cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp); diff --git a/verilog/sd2snes/sd_dma.v b/verilog/sd2snes/sd_dma.v index 0d7d2c8..2137370 100644 --- a/verilog/sd2snes/sd_dma.v +++ b/verilog/sd2snes/sd_dma.v @@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; // we have 4 internal cycles per SD clock, 8 per RAM byte write reg [2:0] clkcnt; initial clkcnt = 3'b000; -reg SD_CLKr; -always @(posedge CLK) SD_CLKr <= clkcnt[1]; -assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; +reg [1:0] SD_CLKr; +always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]}; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ; always @(posedge CLK) begin if(SD_DMA_EN_rising) begin diff --git a/verilog/sd2snes_cx4/sd_dma.v b/verilog/sd2snes_cx4/sd_dma.v index 0d7d2c8..2137370 100644 --- a/verilog/sd2snes_cx4/sd_dma.v +++ b/verilog/sd2snes_cx4/sd_dma.v @@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; // we have 4 internal cycles per SD clock, 8 per RAM byte write reg [2:0] clkcnt; initial clkcnt = 3'b000; -reg SD_CLKr; -always @(posedge CLK) SD_CLKr <= clkcnt[1]; -assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; +reg [1:0] SD_CLKr; +always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]}; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ; always @(posedge CLK) begin if(SD_DMA_EN_rising) begin From 08cace5c12a651f386bbb35993b8111b4eef3094 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 18:06:22 +0100 Subject: [PATCH 19/66] firmware: increase qsort entry limit to 2048 --- src/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/config.h b/src/config.h index 7ff8965..6900ac2 100644 --- a/src/config.h +++ b/src/config.h @@ -65,7 +65,7 @@ #define FPGA_MCU_RDY_REG LPC_GPIO2 #define FPGA_MCU_RDY_BIT 9 -#define QSORT_MAXELEM 1024 +#define QSORT_MAXELEM 2048 #define SSP_REGS LPC_SSP0 #define SSP_PCLKREG PCLKSEL1 From bd1f5215db163639ca51cdb7e745d0b6880085fa Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 18:10:26 +0100 Subject: [PATCH 20/66] firmware: fix db entry linking on bank switch --- src/filetypes.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/filetypes.c b/src/filetypes.c index 7e05851..8c03d05 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -146,9 +146,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len); if(mkdb) { uint16_t pathlen = strlen(path); - /* write element pointer to current dir structure */ - printf("d=%d Saving %lx to Address %lx [dir]\n", depth, db_tgt, dir_tgt); - sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt); +// printf("d=%d Saving %lx to Address %lx [dir]\n", depth, db_tgt, dir_tgt); /* save element: - path name - pointer to sub dir structure */ @@ -158,7 +156,12 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t db_tgt += 0x00010000; printf("new=%lx\n", db_tgt); } - printf(" Saving dir descriptor to %lx tgt=%lx, path=%s\n", db_tgt, next_subdir_tgt, path); +// printf(" Saving dir descriptor to %lx tgt=%lx, path=%s\n", db_tgt, next_subdir_tgt, path); + /* write element pointer to current dir structure */ + sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt); + /* save element: + - path name + - pointer to sub dir structure */ sram_writelong((next_subdir_tgt-SRAM_MENU_ADDR), db_tgt); sram_writebyte(len+1, db_tgt+sizeof(next_subdir_tgt)); sram_writeblock(path, db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen); From 93a12f3ca1d740fc3063c10dcbb481ff528d6da0 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 23:41:33 +0100 Subject: [PATCH 21/66] FPGA: fix occasional erroneous write inhibit --- verilog/sd2snes/main.v | 4 ++-- verilog/sd2snes/sd2snes.xise | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 4199373..7d3fc6b 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -460,7 +460,7 @@ end reg snes_wr_cycle; always @(posedge CLK2) begin - if(SNES_cycle_start) begin + if(SNES_cycle_start & ~SNES_WR_start) begin STATE <= ST_SNES_RD_ADDR; end else if(SNES_WR_start) begin STATE <= ST_SNES_WR_ADDR; @@ -605,6 +605,6 @@ assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; assign IRQ_DIR = 1'b0; assign SNES_IRQ = 1'bZ; -assign p113_out = ROM_WE; +assign p113_out = 1'b0; endmodule diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index 2923d2b..f432d1f 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -377,8 +377,8 @@ - - + + From d94b4355112f3f9504062522b4cf2a1dea50f734 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 11 Nov 2011 00:23:07 +0100 Subject: [PATCH 22/66] PCB Rev.E: add BOM --- pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods | Bin 0 -> 21435 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods diff --git a/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods b/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods new file mode 100644 index 0000000000000000000000000000000000000000..219763411a49c2ededb7834e828f88bd2e12b9b2 GIT binary patch literal 21435 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zSV4G)imR(Du!yi?5O@KcViRv<1kS7mD?y`xVR|yKl?ODdsfkIDfdhEww?Y0r8`*}_ zf_JZ9U(QsZ`Res+V9o@EDzKacw&8#PSgZgS`h5eA#B_FUe8=`<|K+P!uU@<;$k%=z zcu4_pA_v$s0^S`bCL#h{JKK4<6|~?Ns6Hw^{rUX;-oS|fpaCsT3!gkmDTKPB;WKEc z_vTGWzV_X_cK!R4;iVx0yhXCIuyCVA%n9Hq;HuTDtE;L&62K`NFE6jGtX0~c4FC9n zg&we~>g($RhW-DayIp`KK5%_-Wo0GsGI+ZKPYuv^=yE&=vW9saOgAvFp&c;C$b+_J zmq`L`YcLCjsR`(tdJibT25caE?J OSq@KEKbLh*2~7a|TIxXn literal 0 HcmV?d00001 From d1919c5f14524170ec29d0dab7178346ff87bc69 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 2 Dec 2011 10:01:37 +0100 Subject: [PATCH 24/66] PCB/Rev.E: update schematic, PCB and component diagram with recent changes --- pcb/kicad/RevE/fpga.sch | 4 +- pcb/kicad/RevE/mcu.sch | 8 +- pcb/kicad/RevE/memory.sch | 4 +- pcb/kicad/RevE/pwr_misc.sch | 8 +- pcb/kicad/RevE/sd2snes-components-back.png | Bin 783897 -> 359324 bytes pcb/kicad/RevE/sd2snes-components-front.png | Bin 881107 -> 457959 bytes pcb/kicad/RevE/sd2snes.brd | 2040 ++++++------------- pcb/kicad/RevE/sd2snes.net | 1698 +++++++-------- pcb/kicad/RevE/sd2snes.sch | 4 +- pcb/kicad/RevE/snesslot.sch | 32 +- 10 files changed, 1498 insertions(+), 2300 deletions(-) diff --git a/pcb/kicad/RevE/fpga.sch b/pcb/kicad/RevE/fpga.sch index bd9198d..4cb6667 100644 --- a/pcb/kicad/RevE/fpga.sch +++ b/pcb/kicad/RevE/fpga.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A3 16535 11700 encoding utf-8 Sheet 6 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/mcu.sch b/pcb/kicad/RevE/mcu.sch index f26e126..d1b28ad 100644 --- a/pcb/kicad/RevE/mcu.sch +++ b/pcb/kicad/RevE/mcu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 4 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" @@ -1034,7 +1034,7 @@ L C C409 U 1 1 4BEECBD1 P 3100 6600 F 0 "C409" H 3150 6700 50 0000 L CNN -F 1 "22p" H 3150 6500 50 0000 L CNN +F 1 "10p" H 3150 6500 50 0000 L CNN F 2 "SM0805_FIXEDMASK" H 3100 6600 60 0001 C CNN 1 3100 6600 1 0 0 -1 @@ -1044,7 +1044,7 @@ L C C408 U 1 1 4BEECBCD P 2500 6600 F 0 "C408" H 2550 6700 50 0000 L CNN -F 1 "22p" H 2550 6500 50 0000 L CNN +F 1 "10p" H 2550 6500 50 0000 L CNN F 2 "SM0805_FIXEDMASK" H 2500 6600 60 0001 C CNN 1 2500 6600 1 0 0 -1 diff --git a/pcb/kicad/RevE/memory.sch b/pcb/kicad/RevE/memory.sch index 2924b7c..664ae4d 100644 --- a/pcb/kicad/RevE/memory.sch +++ b/pcb/kicad/RevE/memory.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 3 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/pwr_misc.sch b/pcb/kicad/RevE/pwr_misc.sch index eb1687f..babba70 100644 --- a/pcb/kicad/RevE/pwr_misc.sch +++ b/pcb/kicad/RevE/pwr_misc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 5 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" @@ -55,6 +55,8 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text Notes 4900 5900 0 50 ~ 0 +Stuff with 0603 ferrite bead Wire Wire Line 5750 5500 5900 5500 Wire Wire Line @@ -334,7 +336,7 @@ L JUMPER JP341 U 1 1 4DB35D41 P 5450 5500 F 0 "JP341" H 5450 5650 60 0000 C CNN -F 1 "JUMPER" H 5450 5420 40 0000 C CNN +F 1 "FB 0603" H 5450 5420 40 0000 C CNN 1 5450 5500 1 0 0 -1 $EndComp diff --git a/pcb/kicad/RevE/sd2snes-components-back.png b/pcb/kicad/RevE/sd2snes-components-back.png index cdfb93b3cce418583013e842a6da6920ffc25b1d..6ad957fbe79bcb076b0986d3e7295dcb307108cf 100644 GIT binary patch literal 359324 zcmdpeWmJ@17w7;IqJk)$N(u-_H#15}D@Y3{C=4y#p@>K$2uKgzATs0-DlIj13?bd! zeV;-7UiE!{-23;smdmxCIcN9YXYYOX(f@(6>=k@Ud=Ln9Mee?oDhPBP0s>tH;b8$^ zzA}}(2L8dYQ*l9G~d7Z=x^J9oIbxp{baczJpG`1ttw`2_?71O)|!goK2Jg+)X}L`6l# z#KgqK#U&&pz+f;00=awl?!9~WBqb%Kq@<*!rDbGfWMyUV-@h*>Cnqm2ub`lysHmu< zq@=8@tfHdw;K7534V{2<`XJ=<`Z|~sX;OOY+lq= z?fvrQ%U7>n`S|#}e*N0l*Z0kvH-3J8Z{NQ4_xBG72nY-e3ua&mHWbMx}@^7Hcx3JMAf3qOARSX5N>>C>m; z;$k=)UQ$w0T3T9GR#skKUQtm|Sy_odAgZdWs;jGOYHDh0Yd?Sf{N>A+uV25`)z#J4 z*EcjYG&VLiH8nLiH@CF3eEasTwY9aat*yPiy`!U}v$GS4M0Ry`b$567^z`)h_V)Gl z_4oG=3=9ko4h{_s4G#~aP^giSk+IAq2;(hdAjMkYu7{EtddpRX( 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zSV4G)imR(Du!yi?5O@KcViRv<1kS7mD?y`xVR|yKl?ODdsfkIDfdhEww?Y0r8`*}_ zf_JZ9U(QsZ`Res+V9o@EDzKacw&8#PSgZgS`h5eA#B_FUe8=`<|K+P!uU@<;$k%=z zcu4_pA_v$s0^S`bCL#h{JKK4<6|~?Ns6Hw^{rUX;-oS|fpaCsT3!gkmDTKPB;WKEc z_vTGWzV_X_cK!R4;iVx0yhXCIuyCVA%n9Hq;HuTDtE;L&62K`NFE6jGtX0~c4FC9n zg&we~>g($RhW-DayIp`KK5%_-Wo0GsGI+ZKPYuv^=yE&=vW9saOgAvFp&c;C$b+_J zmq`L`YcLCjsR`(tdJibT25caE?J OSq@KEKbLh*2~7a|TIxXn diff --git a/pcb/kicad/RevE/sd2snes.brd b/pcb/kicad/RevE/sd2snes.brd index 54dbbc8..00cff02 100644 --- a/pcb/kicad/RevE/sd2snes.brd +++ b/pcb/kicad/RevE/sd2snes.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Mon 25 Jul 2011 02:18:48 PM CEST +PCBNEW-BOARD Version 1 date Sat 12 Nov 2011 04:56:02 PM CET # Created by Pcbnew(2011-07-02 BZR 2664)-stable @@ -9,7 +9,7 @@ Ly 1FFF8001 EnabledLayers 1FFF8001 Links 668 NoConn 0 -Di 36521 16630 77260 64790 +Di 36595 16630 77260 64790 Ndraw 239 Ntrack 4007 Nzone 0 @@ -21,7 +21,7 @@ $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "sd2snes Mark II" -Date "25 jul 2011" +Date "12 nov 2011" Rev "C2" Comp "Maximilian Rehkopf" Comment1 "" @@ -35,7 +35,7 @@ InternalUnit 0.000100 INCH Layers 2 Layer[0] Copper signal Layer[15] Component signal -TrackWidth 80 +TrackWidth 60 TrackWidthList 59 TrackWidthList 60 TrackWidthList 80 @@ -64,14 +64,14 @@ MicroViaMinSize 8 MicroViaMinDrill 50 TextPcbWidth 120 TextPcbSize 600 800 -EdgeModWidth 80 +EdgeModWidth 39 TextModSize 600 600 TextModWidth 120 -PadSize 600 600 -PadDrill 320 +PadSize 79 690 +PadDrill 0 Pad2MaskClearance 40 AuxiliaryAxisOrg 0 0 -PcbPlotParams (pcbplotparams (layerselection 15761409) (usegerberextensions true) (excludeedgelayer true) (linewidth 79) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue false) (plotothertext false) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk true) (outputformat 1) (mirror false) (drillshape 2) (scaleselection 1) (outputdirectory "")) +PcbPlotParams (pcbplotparams (layerselection 2097152) (usegerberextensions true) (excludeedgelayer false) (linewidth 79) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext true) (padsonsilk false) (subtractmaskfromsilk true) (outputformat 2) (mirror false) (drillshape 2) (scaleselection 1) (outputdirectory "")) $EndSETUP $EQUIPOT @@ -463,151 +463,151 @@ Na 96 "N-000013" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "N-000037" +Na 97 "N-000036" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "N-000038" +Na 98 "N-000037" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "N-000039" +Na 99 "N-000038" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "N-000040" +Na 100 "N-000039" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "N-000041" +Na 101 "N-000040" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "N-000042" +Na 102 "N-000041" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "N-000045" +Na 103 "N-000042" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "N-000047" +Na 104 "N-000045" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "N-000048" +Na 105 "N-000047" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "N-000050" +Na 106 "N-000049" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "N-000051" +Na 107 "N-000050" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "N-000054" +Na 108 "N-000053" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "N-000071" +Na 109 "N-000056" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "N-000072" +Na 110 "N-000071" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "N-000073" +Na 111 "N-000072" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "N-000074" +Na 112 "N-000073" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "N-000075" +Na 113 "N-000074" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "N-000077" +Na 114 "N-000075" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "N-000081" +Na 115 "N-000076" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "N-000082" +Na 116 "N-000078" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "N-000083" +Na 117 "N-000082" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "N-000084" +Na 118 "N-000083" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "N-000086" +Na 119 "N-000084" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "N-000087" +Na 120 "N-000086" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "N-000091" +Na 121 "N-000087" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "N-000092" +Na 122 "N-000091" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "N-000093" +Na 123 "N-000092" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "N-000097" +Na 124 "N-000095" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "N-000102" +Na 125 "N-000100" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "N-000104" +Na 126 "N-000102" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "N-000105" +Na 127 "N-000103" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "N-000106" +Na 128 "N-000104" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "N-000107" +Na 129 "N-000105" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "N-000108" +Na 130 "N-000106" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "N-000109" +Na 131 "N-000107" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "N-000110" +Na 132 "N-000108" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "N-000111" +Na 133 "N-000120" St ~ $EndEQUIPOT $EQUIPOT @@ -615,71 +615,71 @@ Na 134 "N-000125" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "N-000126" +Na 135 "N-000127" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "N-000127" +Na 136 "N-000137" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "N-000128" +Na 137 "N-000143" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "N-000146" +Na 138 "N-000144" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "N-000147" +Na 139 "N-000145" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "N-000148" +Na 140 "N-000146" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "N-000149" +Na 141 "N-000147" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "N-000153" +Na 142 "N-000151" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "N-000154" +Na 143 "N-000152" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "N-000155" +Na 144 "N-000153" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "N-000156" +Na 145 "N-000154" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "N-000157" +Na 146 "N-000156" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "N-000158" +Na 147 "N-000157" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "N-000159" +Na 148 "N-000158" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "N-000160" +Na 149 "N-000159" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "N-000161" +Na 150 "N-000160" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "N-000162" +Na 151 "N-000161" St ~ $EndEQUIPOT $EQUIPOT @@ -687,7 +687,7 @@ Na 152 "N-000193" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "N-000276" +Na 153 "N-000273" St ~ $EndEQUIPOT $EQUIPOT @@ -759,31 +759,31 @@ Na 170 "N-000315" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "N-000318" +Na 171 "N-000316" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "N-000319" +Na 172 "N-000318" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "N-000323" +Na 173 "N-000322" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "N-000324" +Na 174 "N-000323" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "N-000325" +Na 175 "N-000324" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "N-000326" +Na 176 "N-000327" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "N-000327" +Na 177 "N-000328" St ~ $EndEQUIPOT $EQUIPOT @@ -1484,6 +1484,7 @@ AddNet "MCU_SPI_SCK" AddNet "MCU_SPI_SS" AddNet "N-000012" AddNet "N-000013" +AddNet "N-000036" AddNet "N-000037" AddNet "N-000038" AddNet "N-000039" @@ -1492,17 +1493,17 @@ AddNet "N-000041" AddNet "N-000042" AddNet "N-000045" AddNet "N-000047" -AddNet "N-000048" +AddNet "N-000049" AddNet "N-000050" -AddNet "N-000051" -AddNet "N-000054" +AddNet "N-000053" +AddNet "N-000056" AddNet "N-000071" AddNet "N-000072" AddNet "N-000073" AddNet "N-000074" AddNet "N-000075" -AddNet "N-000077" -AddNet "N-000081" +AddNet "N-000076" +AddNet "N-000078" AddNet "N-000082" AddNet "N-000083" AddNet "N-000084" @@ -1510,37 +1511,36 @@ AddNet "N-000086" AddNet "N-000087" AddNet "N-000091" AddNet "N-000092" -AddNet "N-000093" -AddNet "N-000097" +AddNet "N-000095" +AddNet "N-000100" AddNet "N-000102" +AddNet "N-000103" AddNet "N-000104" AddNet "N-000105" AddNet "N-000106" AddNet "N-000107" AddNet "N-000108" -AddNet "N-000109" -AddNet "N-000110" -AddNet "N-000111" +AddNet "N-000120" AddNet "N-000125" -AddNet "N-000126" AddNet "N-000127" -AddNet "N-000128" +AddNet "N-000137" +AddNet "N-000143" +AddNet "N-000144" +AddNet "N-000145" AddNet "N-000146" AddNet "N-000147" -AddNet "N-000148" -AddNet "N-000149" +AddNet "N-000151" +AddNet "N-000152" AddNet "N-000153" AddNet "N-000154" -AddNet "N-000155" AddNet "N-000156" AddNet "N-000157" AddNet "N-000158" AddNet "N-000159" AddNet "N-000160" AddNet "N-000161" -AddNet "N-000162" AddNet "N-000193" -AddNet "N-000276" +AddNet "N-000273" AddNet "N-000277" AddNet "N-000278" AddNet "N-000279" @@ -1558,13 +1558,13 @@ AddNet "N-000311" AddNet "N-000313" AddNet "N-000314" AddNet "N-000315" +AddNet "N-000316" AddNet "N-000318" -AddNet "N-000319" +AddNet "N-000322" AddNet "N-000323" AddNet "N-000324" -AddNet "N-000325" -AddNet "N-000326" AddNet "N-000327" +AddNet "N-000328" AddNet "N-000337" AddNet "N-000338" AddNet "N-000339" @@ -1761,7 +1761,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 64 "/USEBATT" Po 0 250 -Le -131587 $EndPAD $EndMODULE GS2 $MODULE SOT23-5_LARGEPADS @@ -1784,7 +1783,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 500 -Le 69 $EndPAD $PAD Sh "3" R 272 390 0 0 900 @@ -1792,7 +1790,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 375 500 -Le 126 $EndPAD $PAD Sh "5" R 272 390 0 0 900 @@ -1800,7 +1797,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -375 -500 -Le 126 $EndPAD $PAD Sh "2" R 272 390 0 0 900 @@ -1808,7 +1804,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 0 500 -Le 46978608 $EndPAD $PAD Sh "4" R 272 390 0 0 900 @@ -1844,7 +1839,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 500 -Le 69 $EndPAD $PAD Sh "3" R 272 390 0 0 0 @@ -1852,7 +1846,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 375 500 -Le 126 $EndPAD $PAD Sh "5" R 272 390 0 0 0 @@ -1860,7 +1853,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 2 "+1.8V" Po -375 -500 -Le 126 $EndPAD $PAD Sh "2" R 272 390 0 0 0 @@ -1868,7 +1860,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 0 500 -Le 46978608 $EndPAD $PAD Sh "4" R 272 390 0 0 0 @@ -1876,7 +1867,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 375 -500 -Le 368 $EndPAD $SHAPE3D Na "smd/SOT23_5.wrl" @@ -1910,7 +1900,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 184 "P1_D0" Po -1000 500 -Le 168 $EndPAD $PAD Sh "2" C 600 600 0 0 0 @@ -1918,7 +1907,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 183 "P1_CLK" Po -1000 -500 -Le 5376 $EndPAD $PAD Sh "3" C 600 600 0 0 0 @@ -1926,7 +1914,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 189 "P_LATCH" Po 0 500 -Le 504107287 $EndPAD $PAD Sh "4" C 600 600 0 0 0 @@ -1934,7 +1921,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 90 "MCU_SPARE" Po 0 -500 -Le 48 $EndPAD $PAD Sh "5" C 600 600 0 0 0 @@ -1942,7 +1928,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 186 "P2_CLK" Po 1000 500 -Le 168 $EndPAD $PAD Sh "6" C 600 600 0 0 0 @@ -1977,20 +1962,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2263 1535 -Le 166 $EndPAD $PAD Sh "2" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000104" +Ne 126 "N-000102" Po -2066 1535 $EndPAD $PAD Sh "3" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000105" +Ne 123 "N-000092" Po -1870 1535 $EndPAD $PAD @@ -1999,21 +1983,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1673 1535 -Le 2035555993 $EndPAD $PAD Sh "5" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000106" +Ne 127 "N-000103" Po -1476 1535 -Le 1 $EndPAD $PAD Sh "6" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000107" +Ne 128 "N-000104" Po -1279 1535 $EndPAD $PAD @@ -2027,16 +2009,15 @@ $PAD Sh "8" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000108" +Ne 129 "N-000105" Po -885 1535 $EndPAD $PAD Sh "9" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000109" +Ne 130 "N-000106" Po -688 1535 -Le 166 $EndPAD $PAD Sh "10" R 118 472 0 0 1800 @@ -2056,22 +2037,21 @@ $PAD Sh "12" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000147" +Ne 138 "N-000144" Po -98 1535 -Le 40174704 $EndPAD $PAD Sh "13" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 111 "N-000073" +Ne 113 "N-000074" Po 98 1535 $EndPAD $PAD Sh "14" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 114 "N-000077" +Ne 116 "N-000078" Po 295 1535 $EndPAD $PAD @@ -2085,16 +2065,15 @@ $PAD Sh "16" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 116 "N-000082" +Ne 110 "N-000071" Po 688 1535 $EndPAD $PAD Sh "17" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000086" +Ne 120 "N-000086" Po 885 1535 -Le 1579 $EndPAD $PAD Sh "18" R 118 472 0 0 1800 @@ -2102,23 +2081,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po 1082 1535 -Le 1579 $EndPAD $PAD Sh "19" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000091" +Ne 122 "N-000091" Po 1279 1535 -Le 33 $EndPAD $PAD Sh "20" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000110" +Ne 131 "N-000107" Po 1476 1535 -Le 76 $EndPAD $PAD Sh "21" R 118 472 0 0 1800 @@ -2126,21 +2102,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1673 1535 -Le 1579 $EndPAD $PAD Sh "22" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 109 "N-000071" +Ne 111 "N-000072" Po 1870 1535 -Le 93136432 $EndPAD $PAD Sh "23" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 112 "N-000074" +Ne 114 "N-000075" Po 2066 1535 $EndPAD $PAD @@ -2149,7 +2123,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 80 "DATABUS_DIR" Po 2263 1535 -Le 1961268560 $EndPAD $PAD Sh "25" R 118 472 0 0 0 @@ -2157,23 +2130,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 79 "DATABUS_/OE" Po 2263 -1535 -Le 92391432 $EndPAD $PAD Sh "26" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "N-000083" +Ne 118 "N-000083" Po 2066 -1535 -Le 93141952 $EndPAD $PAD Sh "27" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000087" +Ne 121 "N-000087" Po 1870 -1535 -Le 65 $EndPAD $PAD Sh "28" R 118 472 0 0 0 @@ -2181,20 +2151,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1673 -1535 -Le 105 $EndPAD $PAD Sh "29" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000092" +Ne 139 "N-000145" Po 1476 -1535 $EndPAD $PAD Sh "30" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000111" +Ne 132 "N-000108" Po 1279 -1535 $EndPAD $PAD @@ -2208,16 +2177,15 @@ $PAD Sh "32" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "N-000072" +Ne 112 "N-000073" Po 885 -1535 $EndPAD $PAD Sh "33" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "N-000075" +Ne 115 "N-000076" Po 688 -1535 -Le 91 $EndPAD $PAD Sh "34" R 118 472 0 0 0 @@ -2225,23 +2193,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 492 -1535 -Le 92761888 $EndPAD $PAD Sh "35" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "N-000081" +Ne 117 "N-000082" Po 295 -1535 -Le 1961267920 $EndPAD $PAD Sh "36" R 118 472 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000084" +Ne 119 "N-000084" Po 98 -1535 -Le 14554736 $EndPAD $PAD Sh "37" R 118 472 0 0 0 @@ -2249,7 +2214,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 301 "SNES_CPU_CLK" Po -98 -1535 -Le 280 $EndPAD $PAD Sh "38" R 118 472 0 0 0 @@ -2257,7 +2221,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 276 "SNES_/WR" Po -295 -1535 -Le -557404128 $EndPAD $PAD Sh "39" R 118 472 0 0 0 @@ -2265,7 +2228,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -492 -1535 -Le 640 $EndPAD $PAD Sh "40" R 118 472 0 0 0 @@ -2280,7 +2242,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 311 "SNES_PA0" Po -885 -1535 -Le 929 $EndPAD $PAD Sh "42" R 118 472 0 0 0 @@ -2288,7 +2249,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -1082 -1535 -Le 241 $EndPAD $PAD Sh "43" R 118 472 0 0 0 @@ -2303,7 +2263,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 313 "SNES_PA2" Po -1476 -1535 -Le 64 $EndPAD $PAD Sh "45" R 118 472 0 0 0 @@ -2325,7 +2284,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 315 "SNES_PA4" Po -2066 -1535 -Le 186 $EndPAD $PAD Sh "48" R 118 472 0 0 0 @@ -2333,7 +2291,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2263 -1535 -Le 48 $EndPAD $EndMODULE TSSOP48 $MODULE TSSOP48 @@ -2362,15 +2319,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 134 "N-000125" Po -2066 1535 -Le 112 $EndPAD $PAD Sh "3" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000126" +Ne 133 "N-000120" Po -1870 1535 -Le 92684544 $EndPAD $PAD Sh "4" R 118 472 0 0 1800 @@ -2378,23 +2333,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1673 1535 -Le 1961267920 $EndPAD $PAD Sh "5" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000127" +Ne 135 "N-000127" Po -1476 1535 -Le 2035556120 $EndPAD $PAD Sh "6" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000128" +Ne 136 "N-000137" Po -1279 1535 -Le 36 $EndPAD $PAD Sh "7" R 118 472 0 0 1800 @@ -2402,20 +2354,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po -1082 1535 -Le 102 $EndPAD $PAD Sh "8" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000162" +Ne 151 "N-000161" Po -885 1535 $EndPAD $PAD Sh "9" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 150 "N-000161" +Ne 150 "N-000160" Po -688 1535 $EndPAD $PAD @@ -2424,37 +2375,34 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -492 1535 -Le 49 $EndPAD $PAD Sh "11" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 149 "N-000160" +Ne 149 "N-000159" Po -295 1535 -Le 168 $EndPAD $PAD Sh "12" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000148" +Ne 140 "N-000146" Po -98 1535 $EndPAD $PAD Sh "13" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 148 "N-000159" +Ne 148 "N-000158" Po 98 1535 $EndPAD $PAD Sh "14" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 147 "N-000158" +Ne 147 "N-000157" Po 295 1535 -Le 40095568 $EndPAD $PAD Sh "15" R 118 472 0 0 1800 @@ -2462,21 +2410,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 492 1535 -Le 41042640 $EndPAD $PAD Sh "16" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 146 "N-000157" +Ne 146 "N-000156" Po 688 1535 -Le 42077552 $EndPAD $PAD Sh "17" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 142 "N-000153" +Ne 142 "N-000151" Po 885 1535 $EndPAD $PAD @@ -2485,23 +2431,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po 1082 1535 -Le 42077728 $EndPAD $PAD Sh "19" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 143 "N-000154" +Ne 143 "N-000152" Po 1279 1535 -Le 42078432 $EndPAD $PAD Sh "20" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 144 "N-000155" +Ne 144 "N-000153" Po 1476 1535 -Le 41498848 $EndPAD $PAD Sh "21" R 118 472 0 0 1800 @@ -2509,15 +2452,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1673 1535 -Le 641 $EndPAD $PAD Sh "22" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 145 "N-000156" +Ne 145 "N-000154" Po 1870 1535 -Le 41157456 $EndPAD $PAD Sh "23" R 118 472 0 0 1800 @@ -2525,7 +2466,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" Po 2066 1535 -Le 65 $EndPAD $PAD Sh "24" R 118 472 0 0 1800 @@ -2533,7 +2473,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2263 1535 -Le 80 $EndPAD $PAD Sh "25" R 118 472 0 0 0 @@ -2541,7 +2480,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2263 -1535 -Le 1579 $EndPAD $PAD Sh "26" R 118 472 0 0 0 @@ -2549,7 +2487,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 320 "SNES_SYS_CLK" Po 2066 -1535 -Le 1454 $EndPAD $PAD Sh "27" R 118 472 0 0 0 @@ -2557,7 +2494,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 319 "SNES_REFRESH" Po 1870 -1535 -Le 1433 $EndPAD $PAD Sh "28" R 118 472 0 0 0 @@ -2565,7 +2501,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1673 -1535 -Le 48 $EndPAD $PAD Sh "29" R 118 472 0 0 0 @@ -2573,7 +2508,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 318 "SNES_PA7" Po 1476 -1535 -Le 1663071336 $EndPAD $PAD Sh "30" R 118 472 0 0 0 @@ -2581,7 +2515,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 317 "SNES_PA6" Po 1279 -1535 -Le 48 $EndPAD $PAD Sh "31" R 118 472 0 0 0 @@ -2589,7 +2522,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 1082 -1535 -Le 81 $EndPAD $PAD Sh "32" R 118 472 0 0 0 @@ -2597,7 +2529,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 272 "SNES_/PAWR" Po 885 -1535 -Le 92655264 $EndPAD $PAD Sh "33" R 118 472 0 0 0 @@ -2605,7 +2536,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 271 "SNES_/PARD" Po 688 -1535 -Le 65 $EndPAD $PAD Sh "34" R 118 472 0 0 0 @@ -2613,7 +2543,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 492 -1535 -Le 4 $EndPAD $PAD Sh "35" R 118 472 0 0 0 @@ -2635,7 +2564,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 279 "SNES_A10" Po -98 -1535 -Le 55973368 $EndPAD $PAD Sh "38" R 118 472 0 0 0 @@ -2643,7 +2571,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 282 "SNES_A13" Po -295 -1535 -Le 95 $EndPAD $PAD Sh "39" R 118 472 0 0 0 @@ -2651,7 +2578,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -492 -1535 -Le 25 $EndPAD $PAD Sh "40" R 118 472 0 0 0 @@ -2659,7 +2585,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 300 "SNES_A9" Po -688 -1535 -Le 401 $EndPAD $PAD Sh "41" R 118 472 0 0 0 @@ -2667,7 +2592,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 283 "SNES_A14" Po -885 -1535 -Le -557405504 $EndPAD $PAD Sh "42" R 118 472 0 0 0 @@ -2675,7 +2599,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -1082 -1535 -Le 141 $EndPAD $PAD Sh "43" R 118 472 0 0 0 @@ -2683,7 +2606,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 299 "SNES_A8" Po -1279 -1535 -Le 92992888 $EndPAD $PAD Sh "44" R 118 472 0 0 0 @@ -2691,7 +2613,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 284 "SNES_A15" Po -1476 -1535 -Le 1579 $EndPAD $PAD Sh "45" R 118 472 0 0 0 @@ -2699,7 +2620,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1673 -1535 -Le 1454 $EndPAD $PAD Sh "46" R 118 472 0 0 0 @@ -2707,7 +2627,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 298 "SNES_A7" Po -1870 -1535 -Le 1433 $EndPAD $PAD Sh "47" R 118 472 0 0 0 @@ -2715,7 +2634,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 285 "SNES_A16" Po -2066 -1535 -Le 112 $EndPAD $PAD Sh "48" R 118 472 0 0 0 @@ -2723,7 +2641,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2263 -1535 -Le 48 $EndPAD $EndMODULE TSSOP48 $MODULE TSSOP48 @@ -2752,15 +2669,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 95 "N-000012" Po -2066 1535 -Le 801 $EndPAD $PAD Sh "3" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000146" +Ne 137 "N-000143" Po -1870 1535 -Le 92705440 $EndPAD $PAD Sh "4" R 118 472 0 0 1800 @@ -2768,23 +2683,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1673 1535 -Le 97 $EndPAD $PAD Sh "5" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 98 "N-000038" +Ne 99 "N-000038" Po -1476 1535 -Le 75354 $EndPAD $PAD Sh "6" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 99 "N-000039" +Ne 100 "N-000039" Po -1279 1535 -Le 43500 $EndPAD $PAD Sh "7" R 118 472 0 0 1800 @@ -2792,23 +2704,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po -1082 1535 -Le 67700 $EndPAD $PAD Sh "8" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 100 "N-000040" +Ne 101 "N-000040" Po -885 1535 -Le 67975 $EndPAD $PAD Sh "9" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000041" +Ne 102 "N-000041" Po -688 1535 -Le 50075 $EndPAD $PAD Sh "10" R 118 472 0 0 1800 @@ -2816,39 +2725,34 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -492 1535 -Le 75354 $EndPAD $PAD Sh "11" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000045" +Ne 104 "N-000045" Po -295 1535 -Le 43500 $EndPAD $PAD Sh "12" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 104 "N-000047" +Ne 105 "N-000047" Po -98 1535 -Le 67700 $EndPAD $PAD Sh "13" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000050" +Ne 106 "N-000049" Po 98 1535 -Le 67975 $EndPAD $PAD Sh "14" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000054" +Ne 108 "N-000053" Po 295 1535 -Le 50075 $EndPAD $PAD Sh "15" R 118 472 0 0 1800 @@ -2856,20 +2760,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 492 1535 -Le 1041 $EndPAD $PAD Sh "16" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000093" +Ne 109 "N-000056" Po 688 1535 $EndPAD $PAD Sh "17" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000097" +Ne 124 "N-000095" Po 885 1535 $EndPAD $PAD @@ -2878,21 +2781,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po 1082 1535 -Le 846737440 $EndPAD $PAD Sh "19" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000102" +Ne 125 "N-000100" Po 1279 1535 -Le -1851454231 $EndPAD $PAD Sh "20" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000042" +Ne 103 "N-000042" Po 1476 1535 $EndPAD $PAD @@ -2901,21 +2802,19 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1673 1535 -Le 48 $EndPAD $PAD Sh "22" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000048" +Ne 98 "N-000037" Po 1870 1535 -Le 97 $EndPAD $PAD Sh "23" R 118 472 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 107 "N-000051" +Ne 107 "N-000050" Po 2066 1535 $EndPAD $PAD @@ -2924,7 +2823,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2263 1535 -Le 753 $EndPAD $PAD Sh "25" R 118 472 0 0 0 @@ -2932,7 +2830,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2263 -1535 -Le 33 $EndPAD $PAD Sh "26" R 118 472 0 0 0 @@ -2947,7 +2844,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 286 "SNES_A17" Po 1870 -1535 -Le 14554736 $EndPAD $PAD Sh "28" R 118 472 0 0 0 @@ -2962,7 +2858,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 296 "SNES_A5" Po 1476 -1535 -Le 1121 $EndPAD $PAD Sh "30" R 118 472 0 0 0 @@ -2970,7 +2865,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 287 "SNES_A18" Po 1279 -1535 -Le 10 $EndPAD $PAD Sh "31" R 118 472 0 0 0 @@ -2985,7 +2879,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 295 "SNES_A4" Po 885 -1535 -Le 40414896 $EndPAD $PAD Sh "33" R 118 472 0 0 0 @@ -3000,7 +2893,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 492 -1535 -Le 5120 $EndPAD $PAD Sh "35" R 118 472 0 0 0 @@ -3008,7 +2900,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 294 "SNES_A3" Po 295 -1535 -Le -16314833 $EndPAD $PAD Sh "36" R 118 472 0 0 0 @@ -3023,7 +2914,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 289 "SNES_A2" Po -98 -1535 -Le 7168 $EndPAD $PAD Sh "38" R 118 472 0 0 0 @@ -3031,7 +2921,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 291 "SNES_A21" Po -295 -1535 -Le 48 $EndPAD $PAD Sh "39" R 118 472 0 0 0 @@ -3039,7 +2928,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -492 -1535 -Le 65 $EndPAD $PAD Sh "40" R 118 472 0 0 0 @@ -3047,7 +2935,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 278 "SNES_A1" Po -688 -1535 -Le 44708800 $EndPAD $PAD Sh "41" R 118 472 0 0 0 @@ -3055,7 +2942,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 292 "SNES_A22" Po -885 -1535 -Le 92690448 $EndPAD $PAD Sh "42" R 118 472 0 0 0 @@ -3063,7 +2949,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -1082 -1535 -Le 301 $EndPAD $PAD Sh "43" R 118 472 0 0 0 @@ -3071,7 +2956,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 277 "SNES_A0" Po -1279 -1535 -Le 80 $EndPAD $PAD Sh "44" R 118 472 0 0 0 @@ -3079,7 +2963,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 293 "SNES_A23" Po -1476 -1535 -Le 69 $EndPAD $PAD Sh "45" R 118 472 0 0 0 @@ -3087,7 +2970,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1673 -1535 -Le 1953185812 $EndPAD $PAD Sh "46" R 118 472 0 0 0 @@ -3102,7 +2984,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 273 "SNES_/RD" Po -2066 -1535 -Le 19 $EndPAD $PAD Sh "48" R 118 472 0 0 0 @@ -3110,7 +2991,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2263 -1535 -Le 64 $EndPAD $EndMODULE TSSOP48 $MODULE LQFP80-.5 @@ -3132,7 +3012,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 86 "EXT_TDO" Po -1870 2755 -Le 64944048 $EndPAD $PAD Sh "2" R 98 590 0 0 900 @@ -3140,7 +3019,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 85 "EXT_TDI" Po -1673 2755 -Le 92947776 $EndPAD $PAD Sh "3" R 98 590 0 0 900 @@ -3148,7 +3026,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 322 "TMS" Po -1476 2755 -Le 93143152 $EndPAD $PAD Sh "4" R 98 590 0 0 900 @@ -3156,7 +3033,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 63 "/TRST" Po -1279 2755 -Le 40617200 $EndPAD $PAD Sh "5" R 98 590 0 0 900 @@ -3164,7 +3040,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 321 "TCK" Po -1082 2755 -Le 70 $EndPAD $PAD Sh "6" R 98 590 0 0 900 @@ -3172,7 +3047,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 264 "RX3" Po -885 2755 -Le 16 $EndPAD $PAD Sh "7" R 98 590 0 0 900 @@ -3180,7 +3054,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 324 "TX3" Po -688 2755 -Le -557404736 $EndPAD $PAD Sh "8" R 98 590 0 0 900 @@ -3188,7 +3061,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -492 2755 -Le 963 $EndPAD $PAD Sh "9" R 98 590 0 0 900 @@ -3196,7 +3068,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -295 2755 -Le 6 $EndPAD $PAD Sh "10" R 98 590 0 0 900 @@ -3204,7 +3075,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -98 2755 -Le 93123504 $EndPAD $PAD Sh "11" R 98 590 0 0 900 @@ -3212,7 +3082,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 98 2755 -Le 65535 $EndPAD $PAD Sh "12" R 98 590 0 0 900 @@ -3220,15 +3089,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 295 2755 -Le 60395 $EndPAD $PAD Sh "13" R 98 590 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 181 "N-000340" +Ne 178 "N-000337" Po 492 2755 -Le 37830688 $EndPAD $PAD Sh "14" R 98 590 0 0 900 @@ -3236,15 +3103,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 13 "/RESET" Po 688 2755 -Le -1111638594 $EndPAD $PAD Sh "15" R 98 590 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 178 "N-000337" +Ne 179 "N-000338" Po 885 2755 -Le 1356091604 $EndPAD $PAD Sh "16" R 98 590 0 0 900 @@ -3252,7 +3117,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 8 "+BATT" Po 1082 2755 -Le 2022419540 $EndPAD $PAD Sh "17" R 98 590 0 0 900 @@ -3260,31 +3124,27 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1279 2755 -Le 343647 $EndPAD $PAD Sh "18" R 98 590 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 176 "N-000326" +Ne 177 "N-000328" Po 1476 2755 -Le 344003 $EndPAD $PAD Sh "19" R 98 590 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 179 "N-000338" +Ne 180 "N-000339" Po 1673 2755 -Le 343811 $EndPAD $PAD Sh "20" R 98 590 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 180 "N-000339" +Ne 181 "N-000340" Po 1870 2755 -Le 343402 $EndPAD $PAD Sh "21" R 98 590 0 0 1800 @@ -3292,7 +3152,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 2755 1870 -Le 340352 $EndPAD $PAD Sh "22" R 98 590 0 0 1800 @@ -3300,7 +3159,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 165 "N-000309" Po 2755 1673 -Le 40496576 $EndPAD $PAD Sh "23" R 98 590 0 0 1800 @@ -3308,7 +3166,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 169 "N-000314" Po 2755 1476 -Le 40496352 $EndPAD $PAD Sh "24" R 98 590 0 0 1800 @@ -3316,7 +3173,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2755 1279 -Le 156 $EndPAD $PAD Sh "25" R 98 590 0 0 1800 @@ -3324,7 +3180,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 168 "N-000313" Po 2755 1082 -Le 156 $EndPAD $PAD Sh "26" R 98 590 0 0 1800 @@ -3339,7 +3194,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2755 688 -Le 5888 $EndPAD $PAD Sh "28" R 98 590 0 0 1800 @@ -3347,15 +3201,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2755 492 -Le 350208 $EndPAD $PAD Sh "29" R 98 590 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 174 "N-000324" +Ne 174 "N-000323" Po 2755 295 -Le 360448 $EndPAD $PAD Sh "30" R 98 590 0 0 1800 @@ -3370,7 +3222,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 163 "N-000300" Po 2755 -98 -Le 6784 $EndPAD $PAD Sh "32" R 98 590 0 0 1800 @@ -3378,7 +3229,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 274 "SNES_/RESET" Po 2755 -295 -Le 8585216 $EndPAD $PAD Sh "33" R 98 590 0 0 1800 @@ -3386,7 +3236,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 2755 -492 -Le 93421568 $EndPAD $PAD Sh "34" R 98 590 0 0 1800 @@ -3394,7 +3243,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 2755 -688 -Le 93391360 $EndPAD $PAD Sh "35" R 98 590 0 0 1800 @@ -3402,7 +3250,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2755 -885 -Le 97 $EndPAD $PAD Sh "36" R 98 590 0 0 1800 @@ -3410,7 +3257,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 74 "CIC_STATUS" Po 2755 -1082 -Le 1432 $EndPAD $PAD Sh "37" R 98 590 0 0 1800 @@ -3418,7 +3264,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 71 "CIC_DATA1" Po 2755 -1279 -Le 1578 $EndPAD $PAD Sh "38" R 98 590 0 0 1800 @@ -3426,7 +3271,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 70 "CIC_DATA0" Po 2755 -1476 -Le 1547 $EndPAD $PAD Sh "39" R 98 590 0 0 1800 @@ -3434,15 +3278,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 87 "FPGA_CLK" Po 2755 -1673 -Le 1453 $EndPAD $PAD Sh "40" R 98 590 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 177 "N-000327" +Ne 176 "N-000327" Po 2755 -1870 -Le 1453 $EndPAD $PAD Sh "41" R 98 590 0 0 2700 @@ -3450,7 +3292,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 185 "P2.10" Po 1870 -2755 -Le 1578 $EndPAD $PAD Sh "42" R 98 590 0 0 2700 @@ -3458,7 +3299,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 1673 -2755 -Le 1540 $EndPAD $PAD Sh "43" R 98 590 0 0 2700 @@ -3466,7 +3306,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1476 -2755 -Le 1494 $EndPAD $PAD Sh "44" R 98 590 0 0 2700 @@ -3474,7 +3313,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 82 "DONE" Po 1279 -2755 -Le 1543 $EndPAD $PAD Sh "45" R 98 590 0 0 2700 @@ -3482,7 +3320,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 92 "MCU_SPI_MOSI" Po 1082 -2755 -Le 40622608 $EndPAD $PAD Sh "46" R 98 590 0 0 2700 @@ -3490,7 +3327,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 91 "MCU_SPI_MISO" Po 885 -2755 -Le 156 $EndPAD $PAD Sh "47" R 98 590 0 0 2700 @@ -3498,7 +3334,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 93 "MCU_SPI_SCK" Po 688 -2755 -Le 31 $EndPAD $PAD Sh "48" R 98 590 0 0 2700 @@ -3506,7 +3341,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 94 "MCU_SPI_SS" Po 492 -2755 -Le 10 $EndPAD $PAD Sh "49" R 98 590 0 0 2700 @@ -3514,7 +3348,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 89 "INIT_B+MCU_IRQ" Po 295 -2755 -Le 156 $EndPAD $PAD Sh "50" R 98 590 0 0 2700 @@ -3522,7 +3355,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 81 "DIN+MCU_/OVR" Po 98 -2755 -Le 122 $EndPAD $PAD Sh "51" R 98 590 0 0 2700 @@ -3530,7 +3362,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -98 -2755 -Le 156 $EndPAD $PAD Sh "52" R 98 590 0 0 2700 @@ -3538,23 +3369,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -295 -2755 -Le 31 $EndPAD $PAD Sh "53" R 98 590 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000323" +Ne 173 "N-000322" Po -492 -2755 -Le 156 $EndPAD $PAD Sh "54" R 98 590 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 162 "N-000295" +Ne 161 "N-000294" Po -688 -2755 -Le 156 $EndPAD $PAD Sh "55" R 98 590 0 0 2700 @@ -3562,7 +3390,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 270 "SD_DAT3" Po -885 -2755 -Le -921361 $EndPAD $PAD Sh "56" R 98 590 0 0 2700 @@ -3570,7 +3397,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -1082 -2755 -Le 31 $EndPAD $PAD Sh "57" R 98 590 0 0 2700 @@ -3578,7 +3404,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1279 -2755 -Le 31 $EndPAD $PAD Sh "58" R 98 590 0 0 2700 @@ -3586,7 +3411,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 269 "SD_DAT2" Po -1476 -2755 -Le 156 $EndPAD $PAD Sh "59" R 98 590 0 0 2700 @@ -3594,7 +3418,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 268 "SD_DAT1" Po -1673 -2755 -Le 117 $EndPAD $PAD Sh "60" R 98 590 0 0 2700 @@ -3602,7 +3425,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 267 "SD_DAT0" Po -1870 -2755 -Le 122 $EndPAD $PAD Sh "61" R 98 590 0 0 0 @@ -3610,15 +3432,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 266 "SD_CMD" Po -2755 -1870 -Le 119 $EndPAD $PAD Sh "62" R 98 590 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000319" +Ne 172 "N-000318" Po -2755 -1673 -Le 156 $EndPAD $PAD Sh "63" R 98 590 0 0 0 @@ -3626,15 +3446,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 265 "SD_CLK" Po -2755 -1476 -Le 156 $EndPAD $PAD Sh "64" R 98 590 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "N-000294" +Ne 162 "N-000295" Po -2755 -1279 -Le 156 $EndPAD $PAD Sh "65" R 98 590 0 0 0 @@ -3642,7 +3460,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 325 "USB_SWCONN" Po -2755 -1082 -Le 40678896 $EndPAD $PAD Sh "66" R 98 590 0 0 0 @@ -3650,7 +3467,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2755 -885 -Le 31 $EndPAD $PAD Sh "67" R 98 590 0 0 0 @@ -3658,7 +3474,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -2755 -688 -Le 31 $EndPAD $PAD Sh "68" R 98 590 0 0 0 @@ -3666,15 +3481,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -2755 -492 -Le 156 $EndPAD $PAD Sh "69" R 98 590 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "N-000325" +Ne 175 "N-000324" Po -2755 -295 -Le 156 $EndPAD $PAD Sh "70" R 98 590 0 0 0 @@ -3682,7 +3495,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 64 "/USEBATT" Po -2755 -98 -Le 31 $EndPAD $PAD Sh "71" R 98 590 0 0 0 @@ -3690,7 +3502,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 187 "P2_D0" Po -2755 98 -Le 156 $EndPAD $PAD Sh "72" R 98 590 0 0 0 @@ -3698,7 +3509,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 186 "P2_CLK" Po -2755 295 -Le 106 $EndPAD $PAD Sh "73" R 98 590 0 0 0 @@ -3706,7 +3516,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 90 "MCU_SPARE" Po -2755 492 -Le 72 $EndPAD $PAD Sh "74" R 98 590 0 0 0 @@ -3714,7 +3523,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 189 "P_LATCH" Po -2755 688 -Le 72 $EndPAD $PAD Sh "75" R 98 590 0 0 0 @@ -3722,7 +3530,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 183 "P1_CLK" Po -2755 885 -Le 76 $EndPAD $PAD Sh "76" R 98 590 0 0 0 @@ -3730,7 +3537,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 184 "P1_D0" Po -2755 1082 -Le 2035548277 $EndPAD $PAD Sh "77" R 98 590 0 0 0 @@ -3738,7 +3544,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -2755 1279 -Le 1453 $EndPAD $PAD Sh "78" R 98 590 0 0 0 @@ -3746,7 +3551,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2755 1476 -Le 1453 $EndPAD $PAD Sh "79" R 98 590 0 0 0 @@ -3754,7 +3558,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 323 "TX0" Po -2755 1673 -Le 1578 $EndPAD $PAD Sh "80" R 98 590 0 0 0 @@ -3762,7 +3565,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 263 "RX0" Po -2755 1870 -Le 1539 $EndPAD $EndMODULE LQFP80-.5 $MODULE PQFP208 @@ -3792,7 +3594,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 5023 -6100 -Le 1536 $EndPAD $PAD Sh "2" R 1000 100 0 0 900 @@ -3800,7 +3601,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 228 "ROM_A12" Po 4826 -6100 -Le 1578 $EndPAD $PAD Sh "3" R 1000 100 0 0 900 @@ -3808,7 +3608,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 234 "ROM_A18" Po 4629 -6100 -Le 1578 $EndPAD $PAD Sh "4" R 1000 100 0 0 900 @@ -3816,7 +3615,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 235 "ROM_A19" Po 4432 -6100 -Le 1578 $EndPAD $PAD Sh "5" R 1000 100 0 0 900 @@ -3824,7 +3622,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 254 "ROM_DQ15" Po 4235 -6100 -Le 1453 $EndPAD $PAD Sh "6" R 1000 100 0 0 900 @@ -3832,7 +3629,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 4038 -6100 -Le -1 $EndPAD $PAD Sh "7" R 1000 100 0 0 900 @@ -3847,7 +3643,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 3644 -6100 -Le 13947601 $EndPAD $PAD Sh "9" R 1000 100 0 0 900 @@ -3855,7 +3650,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 253 "ROM_DQ14" Po 3447 -6100 -Le 37823264 $EndPAD $PAD Sh "10" R 1000 100 0 0 900 @@ -3870,7 +3664,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 233 "ROM_A17" Po 3053 -6100 -Le 1409045500 $EndPAD $PAD Sh "12" R 1000 100 0 0 900 @@ -3878,7 +3671,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 250 "ROM_DQ11" Po 2856 -6100 -Le 973195443 $EndPAD $PAD Sh "13" R 1000 100 0 0 900 @@ -3886,7 +3678,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 262 "ROM_DQ9" Po 2659 -6100 -Le 688 $EndPAD $PAD Sh "14" R 1000 100 0 0 900 @@ -3901,7 +3692,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 249 "ROM_DQ10" Po 2265 -6100 -Le 40149968 $EndPAD $PAD Sh "16" R 1000 100 0 0 900 @@ -3916,7 +3706,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po 1871 -6100 -Le 48 $EndPAD $PAD Sh "18" R 1000 100 0 0 900 @@ -3945,7 +3734,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 215 "RAM_DQ4" Po 1083 -6100 -Le 8825817 $EndPAD $PAD Sh "22" R 1000 100 0 0 900 @@ -3953,7 +3741,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 212 "RAM_DQ1" Po 886 -6100 -Le 2107014748 $EndPAD $PAD Sh "23" R 1000 100 0 0 900 @@ -3961,7 +3748,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 689 -6100 -Le 37823744 $EndPAD $PAD Sh "24" R 1000 100 0 0 900 @@ -3969,7 +3755,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 216 "RAM_DQ5" Po 492 -6100 -Le -398792645 $EndPAD $PAD Sh "25" R 1000 100 0 0 900 @@ -3977,7 +3762,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 295 -6100 -Le 437918234 $EndPAD $PAD Sh "26" R 1000 100 0 0 900 @@ -3985,7 +3769,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 211 "RAM_DQ0" Po 98 -6100 -Le -1601468752 $EndPAD $PAD Sh "27" R 1000 100 0 0 900 @@ -3993,7 +3776,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 217 "RAM_DQ6" Po -99 -6100 -Le 465 $EndPAD $PAD Sh "28" R 1000 100 0 0 900 @@ -4001,7 +3783,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 192 "RAM_A0" Po -296 -6100 -Le 41026544 $EndPAD $PAD Sh "29" R 1000 100 0 0 900 @@ -4009,7 +3790,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 218 "RAM_DQ7" Po -493 -6100 -Le 65535 $EndPAD $PAD Sh "30" R 1000 100 0 0 900 @@ -4017,7 +3797,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -690 -6100 -Le 37822784 $EndPAD $PAD Sh "31" R 1000 100 0 0 900 @@ -4032,7 +3811,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -1084 -6100 -Le 993737531 $EndPAD $PAD Sh "33" R 1000 100 0 0 900 @@ -4040,7 +3818,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 203 "RAM_A2" Po -1281 -6100 -Le 1356091604 $EndPAD $PAD Sh "34" R 1000 100 0 0 900 @@ -4048,7 +3825,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 194 "RAM_A10" Po -1478 -6100 -Le 2022419540 $EndPAD $PAD Sh "35" R 1000 100 0 0 900 @@ -4077,7 +3853,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -2266 -6100 -Le -791621632 $EndPAD $PAD Sh "39" R 1000 100 0 0 900 @@ -4085,7 +3860,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 195 "RAM_A11" Po -2463 -6100 -Le 7716352 $EndPAD $PAD Sh "40" R 1000 100 0 0 900 @@ -4093,7 +3867,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 206 "RAM_A5" Po -2660 -6100 -Le 94400256 $EndPAD $PAD Sh "41" R 1000 100 0 0 900 @@ -4101,7 +3874,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2857 -6100 -Le 94311424 $EndPAD $PAD Sh "42" R 1000 100 0 0 900 @@ -4109,7 +3881,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 210 "RAM_A9" Po -3054 -6100 -Le 94351104 $EndPAD $PAD Sh "43" R 1000 100 0 0 900 @@ -4117,7 +3888,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 207 "RAM_A6" Po -3251 -6100 -Le 94227968 $EndPAD $PAD Sh "44" R 1000 100 0 0 900 @@ -4125,7 +3895,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 209 "RAM_A8" Po -3448 -6100 -Le 8486912 $EndPAD $PAD Sh "45" R 1000 100 0 0 900 @@ -4133,7 +3902,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 208 "RAM_A7" Po -3645 -6100 -Le 93317888 $EndPAD $PAD Sh "46" R 1000 100 0 0 900 @@ -4141,7 +3909,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 197 "RAM_A13" Po -3842 -6100 -Le 93433856 $EndPAD $PAD Sh "47" R 1000 100 0 0 900 @@ -4149,7 +3916,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -4039 -6100 -Le 93368320 $EndPAD $PAD Sh "48" R 1000 100 0 0 900 @@ -4157,7 +3923,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 196 "RAM_A12" Po -4236 -6100 -Le 93285120 $EndPAD $PAD Sh "49" R 1000 100 0 0 900 @@ -4165,7 +3930,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -4433 -6100 -Le 7888640 $EndPAD $PAD Sh "50" R 1000 100 0 0 900 @@ -4173,7 +3937,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 191 "RAM_/WE" Po -4630 -6100 -Le 49 $EndPAD $PAD Sh "51" R 1000 100 0 0 900 @@ -4181,7 +3944,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 198 "RAM_A14" Po -4827 -6100 -Le 172 $EndPAD $PAD Sh "52" R 1000 100 0 0 900 @@ -4196,7 +3958,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 -5023 -Le -398792645 $EndPAD $PAD Sh "54" R 1000 100 0 0 0 @@ -4204,7 +3965,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -6130 -4826 -Le 54867 $EndPAD $PAD Sh "55" R 1000 100 0 0 0 @@ -4212,7 +3972,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -6130 -4629 -Le 3 $EndPAD $PAD Sh "56" R 1000 100 0 0 0 @@ -4220,7 +3979,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -6130 -4432 -Le 37823264 $EndPAD $PAD Sh "57" R 1000 100 0 0 0 @@ -4235,7 +3993,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 199 "RAM_A15" Po -6130 -4038 -Le 1409045500 $EndPAD $PAD Sh "59" R 1000 100 0 0 0 @@ -4243,7 +4000,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 -3841 -Le 614718611 $EndPAD $PAD Sh "60" R 1000 100 0 0 0 @@ -4251,7 +4007,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -6130 -3644 -Le 80 $EndPAD $PAD Sh "61" R 1000 100 0 0 0 @@ -4259,7 +4014,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 201 "RAM_A17" Po -6130 -3447 -Le 48 $EndPAD $PAD Sh "62" R 1000 100 0 0 0 @@ -4267,7 +4021,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 269 "SD_DAT2" Po -6130 -3250 -Le 34406400 $EndPAD $PAD Sh "63" R 1000 100 0 0 0 @@ -4275,7 +4028,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 270 "SD_DAT3" Po -6130 -3053 -Le 34421760 $EndPAD $PAD Sh "64" R 1000 100 0 0 0 @@ -4283,7 +4035,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 265 "SD_CLK" Po -6130 -2856 -Le 47448064 $EndPAD $PAD Sh "65" R 1000 100 0 0 0 @@ -4291,7 +4042,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 267 "SD_DAT0" Po -6130 -2659 -Le 47416064 $EndPAD $PAD Sh "66" R 1000 100 0 0 0 @@ -4299,7 +4049,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 -2462 -Le 47218688 $EndPAD $PAD Sh "67" R 1000 100 0 0 0 @@ -4307,7 +4056,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 266 "SD_CMD" Po -6130 -2265 -Le 42074112 $EndPAD $PAD Sh "68" R 1000 100 0 0 0 @@ -4315,7 +4063,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 94 "MCU_SPI_SS" Po -6130 -2068 -Le 36164608 $EndPAD $PAD Sh "69" R 1000 100 0 0 0 @@ -4323,7 +4070,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -6130 -1871 -Le 42237952 $EndPAD $PAD Sh "70" R 1000 100 0 0 0 @@ -4331,7 +4077,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -6130 -1674 -Le 42115328 $EndPAD $PAD Sh "71" R 1000 100 0 0 0 @@ -4339,7 +4084,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 93 "MCU_SPI_SCK" Po -6130 -1477 -Le 42237952 $EndPAD $PAD Sh "72" R 1000 100 0 0 0 @@ -4347,7 +4091,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 91 "MCU_SPI_MISO" Po -6130 -1280 -Le 85760 $EndPAD $PAD Sh "73" R 1000 100 0 0 0 @@ -4355,7 +4098,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -6130 -1083 -Le 48 $EndPAD $PAD Sh "74" R 1000 100 0 0 0 @@ -4363,7 +4105,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 92 "MCU_SPI_MOSI" Po -6130 -886 -Le -161024276 $EndPAD $PAD Sh "75" R 1000 100 0 0 0 @@ -4371,7 +4112,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 -689 -Le 60395 $EndPAD $PAD Sh "76" R 1000 100 0 0 0 @@ -4379,7 +4119,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 77 "DAC_MCLK" Po -6130 -492 -Le 37830688 $EndPAD $PAD Sh "77" R 1000 100 0 0 0 @@ -4387,7 +4126,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 76 "DAC_LRCK" Po -6130 -295 -Le -576791137 $EndPAD $PAD Sh "78" R 1000 100 0 0 0 @@ -4402,7 +4140,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 268 "SD_DAT1" Po -6130 99 -Le -1439190392 $EndPAD $PAD Sh "80" R 1000 100 0 0 0 @@ -4410,7 +4147,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 87 "FPGA_CLK" Po -6130 296 -Le 161 $EndPAD $PAD Sh "81" R 1000 100 0 0 0 @@ -4432,7 +4168,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 89 "INIT_B+MCU_IRQ" Po -6130 887 -Le 34 $EndPAD $PAD Sh "84" R 1000 100 0 0 0 @@ -4440,7 +4175,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -6130 1084 -Le 209 $EndPAD $PAD Sh "85" R 1000 100 0 0 0 @@ -4448,7 +4182,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 316 "SNES_PA5" Po -6130 1281 -Le 168 $EndPAD $PAD Sh "86" R 1000 100 0 0 0 @@ -4470,7 +4203,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -6130 1872 -Le 9473161 $EndPAD $PAD Sh "89" R 1000 100 0 0 0 @@ -4478,7 +4210,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -6130 2069 -Le 37823104 $EndPAD $PAD Sh "90" R 1000 100 0 0 0 @@ -4493,7 +4224,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 2463 -Le -1111638594 $EndPAD $PAD Sh "92" R 1000 100 0 0 0 @@ -4515,7 +4245,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 276 "SNES_/WR" Po -6130 3054 -Le 34 $EndPAD $PAD Sh "95" R 1000 100 0 0 0 @@ -4530,7 +4259,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 305 "SNES_D3" Po -6130 3448 -Le 1579 $EndPAD $PAD Sh "97" R 1000 100 0 0 0 @@ -4538,7 +4266,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 309 "SNES_D7" Po -6130 3645 -Le 1454 $EndPAD $PAD Sh "98" R 1000 100 0 0 0 @@ -4546,7 +4273,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -6130 3842 -Le 1433 $EndPAD $PAD Sh "99" R 1000 100 0 0 0 @@ -4554,7 +4280,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -6130 4039 -Le 1579 $EndPAD $PAD Sh "100" R 1000 100 0 0 0 @@ -4562,7 +4287,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 304 "SNES_D2" Po -6130 4236 -Le 1537 $EndPAD $PAD Sh "101" R 1000 100 0 0 0 @@ -4570,7 +4294,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 308 "SNES_D6" Po -6130 4433 -Le 1454 $EndPAD $PAD Sh "102" R 1000 100 0 0 0 @@ -4578,7 +4301,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 303 "SNES_D1" Po -6130 4630 -Le 1454 $EndPAD $PAD Sh "103" R 1000 100 0 0 0 @@ -4586,7 +4308,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 82 "DONE" Po -6130 4827 -Le 1579 $EndPAD $PAD Sh "104" R 1000 100 0 0 0 @@ -4594,7 +4315,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 68 "CCLK" Po -6130 5024 -Le 1544 $EndPAD $PAD Sh "105" R 1000 100 0 0 900 @@ -4602,7 +4322,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -5023 6180 -Le 41025232 $EndPAD $PAD Sh "106" R 1000 100 0 0 900 @@ -4610,7 +4329,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 307 "SNES_D5" Po -4826 6180 -Le 112 $EndPAD $PAD Sh "107" R 1000 100 0 0 900 @@ -4618,7 +4336,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 302 "SNES_D0" Po -4629 6180 -Le 32 $EndPAD $PAD Sh "108" R 1000 100 0 0 900 @@ -4626,7 +4343,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 306 "SNES_D4" Po -4432 6180 -Le 1513 $EndPAD $PAD Sh "109" R 1000 100 0 0 900 @@ -4634,7 +4350,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 79 "DATABUS_/OE" Po -4235 6180 -Le 1551 $EndPAD $PAD Sh "110" R 1000 100 0 0 900 @@ -4642,7 +4357,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -4038 6180 -Le 1454 $EndPAD $PAD Sh "111" R 1000 100 0 0 900 @@ -4650,7 +4364,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 80 "DATABUS_DIR" Po -3841 6180 -Le 1454 $EndPAD $PAD Sh "112" R 1000 100 0 0 900 @@ -4658,7 +4371,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -3644 6180 -Le 1579 $EndPAD $PAD Sh "113" R 1000 100 0 0 900 @@ -4666,7 +4378,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 152 "N-000193" Po -3447 6180 -Le 1529 $EndPAD $PAD Sh "114" R 1000 100 0 0 900 @@ -4674,7 +4385,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 310 "SNES_IRQ_EN" Po -3250 6180 -Le 1495 $EndPAD $PAD Sh "115" R 1000 100 0 0 900 @@ -4682,7 +4392,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 273 "SNES_/RD" Po -3053 6180 -Le 37562 $EndPAD $PAD Sh "116" R 1000 100 0 0 900 @@ -4690,7 +4399,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 275 "SNES_/ROMSEL" Po -2856 6180 -Le 8216064 $EndPAD $PAD Sh "117" R 1000 100 0 0 900 @@ -4698,7 +4406,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 293 "SNES_A23" Po -2659 6180 -Le 128 $EndPAD $PAD Sh "118" R 1000 100 0 0 900 @@ -4706,7 +4413,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -2462 6180 -Le 1547 $EndPAD $PAD Sh "119" R 1000 100 0 0 900 @@ -4714,7 +4420,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 277 "SNES_A0" Po -2265 6180 -Le 397824 $EndPAD $PAD Sh "120" R 1000 100 0 0 900 @@ -4722,7 +4427,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 292 "SNES_A22" Po -2068 6180 -Le 366848 $EndPAD $PAD Sh "121" R 1000 100 0 0 900 @@ -4730,7 +4434,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -1871 6180 -Le 397824 $EndPAD $PAD Sh "122" R 1000 100 0 0 900 @@ -4738,7 +4441,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 278 "SNES_A1" Po -1674 6180 -Le 366848 $EndPAD $PAD Sh "123" R 1000 100 0 0 900 @@ -4746,7 +4448,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 291 "SNES_A21" Po -1477 6180 -Le 397824 $EndPAD $PAD Sh "124" R 1000 100 0 0 900 @@ -4754,7 +4455,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 289 "SNES_A2" Po -1280 6180 -Le 1579 $EndPAD $PAD Sh "125" R 1000 100 0 0 900 @@ -4762,7 +4462,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 290 "SNES_A20" Po -1083 6180 -Le 1454 $EndPAD $PAD Sh "126" R 1000 100 0 0 900 @@ -4770,7 +4469,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 294 "SNES_A3" Po -886 6180 -Le 67800 $EndPAD $PAD Sh "127" R 1000 100 0 0 900 @@ -4778,7 +4476,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -689 6180 -Le 67800 $EndPAD $PAD Sh "128" R 1000 100 0 0 900 @@ -4786,7 +4483,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 288 "SNES_A19" Po -492 6180 -Le 75985 $EndPAD $PAD Sh "129" R 1000 100 0 0 900 @@ -4794,7 +4490,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -295 6180 -Le 75233 $EndPAD $PAD Sh "130" R 1000 100 0 0 900 @@ -4809,7 +4504,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 287 "SNES_A18" Po 99 6180 -Le 13947601 $EndPAD $PAD Sh "132" R 1000 100 0 0 900 @@ -4817,7 +4511,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 296 "SNES_A5" Po 296 6180 -Le 39799648 $EndPAD $PAD Sh "133" R 1000 100 0 0 900 @@ -4832,7 +4525,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 690 6180 -Le 1409045500 $EndPAD $PAD Sh "135" R 1000 100 0 0 900 @@ -4840,7 +4532,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 297 "SNES_A6" Po 887 6180 -Le 614718611 $EndPAD $PAD Sh "136" R 1000 100 0 0 900 @@ -4848,7 +4539,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 1084 6180 -Le 1041 $EndPAD $PAD Sh "137" R 1000 100 0 0 900 @@ -4870,7 +4560,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 284 "SNES_A15" Po 1675 6180 -Le 73 $EndPAD $PAD Sh "140" R 1000 100 0 0 900 @@ -4878,7 +4567,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 299 "SNES_A8" Po 1872 6180 -Le 48 $EndPAD $PAD Sh "141" R 1000 100 0 0 900 @@ -4886,7 +4574,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 283 "SNES_A14" Po 2069 6180 -Le 2035556056 $EndPAD $PAD Sh "142" R 1000 100 0 0 900 @@ -4894,7 +4581,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po 2266 6180 -Le 209 $EndPAD $PAD Sh "143" R 1000 100 0 0 900 @@ -4902,7 +4588,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 300 "SNES_A9" Po 2463 6180 -Le 65535 $EndPAD $PAD Sh "144" R 1000 100 0 0 900 @@ -4910,7 +4595,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 282 "SNES_A13" Po 2660 6180 -Le 37822784 $EndPAD $PAD Sh "145" R 1000 100 0 0 900 @@ -4925,7 +4609,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 279 "SNES_A10" Po 3054 6180 -Le 993737531 $EndPAD $PAD Sh "147" R 1000 100 0 0 900 @@ -4933,7 +4616,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 281 "SNES_A12" Po 3251 6180 -Le 1356091604 $EndPAD $PAD Sh "148" R 1000 100 0 0 900 @@ -4941,7 +4623,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 280 "SNES_A11" Po 3448 6180 -Le 2022419540 $EndPAD $PAD Sh "149" R 1000 100 0 0 900 @@ -4949,7 +4630,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 271 "SNES_/PARD" Po 3645 6180 -Le 2097 $EndPAD $PAD Sh "150" R 1000 100 0 0 900 @@ -4957,7 +4637,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 272 "SNES_/PAWR" Po 3842 6180 -Le 1579 $EndPAD $PAD Sh "151" R 1000 100 0 0 900 @@ -4965,7 +4644,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 4039 6180 -Le 1579 $EndPAD $PAD Sh "152" R 1000 100 0 0 900 @@ -4973,7 +4651,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 317 "SNES_PA6" Po 4236 6180 -Le 1579 $EndPAD $PAD Sh "153" R 1000 100 0 0 900 @@ -4981,7 +4658,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 4433 6180 -Le 1454 $EndPAD $PAD Sh "154" R 1000 100 0 0 900 @@ -4989,7 +4665,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 318 "SNES_PA7" Po 4630 6180 -Le 1433 $EndPAD $PAD Sh "155" R 1000 100 0 0 900 @@ -5011,7 +4686,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 6150 5023 -Le -161024276 $EndPAD $PAD Sh "158" R 1000 100 0 0 0 @@ -5019,7 +4693,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 6150 4826 -Le 60395 $EndPAD $PAD Sh "159" R 1000 100 0 0 0 @@ -5027,7 +4700,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 6150 4629 -Le 39800608 $EndPAD $PAD Sh "160" R 1000 100 0 0 0 @@ -5042,7 +4714,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 222 "ROM_/UB" Po 6150 4235 -Le -1140933633 $EndPAD $PAD Sh "162" R 1000 100 0 0 0 @@ -5078,7 +4749,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 224 "ROM_A0" Po 6150 3250 -Le 337 $EndPAD $PAD Sh "167" R 1000 100 0 0 0 @@ -5086,7 +4756,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 244 "ROM_A7" Po 6150 3053 -Le 65535 $EndPAD $PAD Sh "168" R 1000 100 0 0 0 @@ -5094,7 +4763,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 225 "ROM_A1" Po 6150 2856 -Le 37822784 $EndPAD $PAD Sh "169" R 1000 100 0 0 0 @@ -5109,7 +4777,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 6150 2462 -Le 993737531 $EndPAD $PAD Sh "171" R 1000 100 0 0 0 @@ -5117,7 +4784,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 236 "ROM_A2" Po 6150 2265 -Le 1356091604 $EndPAD $PAD Sh "172" R 1000 100 0 0 0 @@ -5125,7 +4791,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 219 "ROM_/CE" Po 6150 2068 -Le 2022419540 $EndPAD $PAD Sh "173" R 1000 100 0 0 0 @@ -5140,7 +4805,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po 6150 1674 -Le 37251232 $EndPAD $PAD Sh "175" R 1000 100 0 0 0 @@ -5148,7 +4812,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 243 "ROM_A6" Po 6150 1477 -Le 1489 $EndPAD $PAD Sh "176" R 1000 100 0 0 0 @@ -5156,7 +4819,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 247 "ROM_DQ0" Po 6150 1280 -Le 1454 $EndPAD $PAD Sh "177" R 1000 100 0 0 0 @@ -5164,7 +4826,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 6150 1083 -Le 1433 $EndPAD $PAD Sh "178" R 1000 100 0 0 0 @@ -5172,7 +4833,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 248 "ROM_DQ1" Po 6150 886 -Le 39940128 $EndPAD $PAD Sh "179" R 1000 100 0 0 0 @@ -5180,7 +4840,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 6150 689 -Le 39944160 $EndPAD $PAD Sh "180" R 1000 100 0 0 0 @@ -5188,7 +4847,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 320 "SNES_SYS_CLK" Po 6150 492 -Le 1579 $EndPAD $PAD Sh "181" R 1000 100 0 0 0 @@ -5210,7 +4868,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 257 "ROM_DQ4" Po 6150 -99 -Le 36937968 $EndPAD $PAD Sh "184" R 1000 100 0 0 0 @@ -5232,7 +4889,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 6150 -690 -Le 36937968 $EndPAD $PAD Sh "187" R 1000 100 0 0 0 @@ -5254,7 +4910,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 260 "ROM_DQ7" Po 6150 -1281 -Le 36937968 $EndPAD $PAD Sh "190" R 1000 100 0 0 0 @@ -5269,7 +4924,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 237 "ROM_A20" Po 6150 -1675 -Le 368973 $EndPAD $PAD Sh "192" R 1000 100 0 0 0 @@ -5284,7 +4938,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po 6150 -2069 -Le 1701866599 $EndPAD $PAD Sh "194" R 1000 100 0 0 0 @@ -5292,7 +4945,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 229 "ROM_A13" Po 6150 -2266 -Le 102 $EndPAD $PAD Sh "195" R 1000 100 0 0 0 @@ -5307,7 +4959,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 227 "ROM_A11" Po 6150 -2660 -Le 993737473 $EndPAD $PAD Sh "197" R 1000 100 0 0 0 @@ -5315,7 +4966,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 226 "ROM_A10" Po 6150 -2857 -Le 1547 $EndPAD $PAD Sh "198" R 1000 100 0 0 0 @@ -5323,7 +4973,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 239 "ROM_A22" Po 6150 -3054 -Le 1513 $EndPAD $PAD Sh "199" R 1000 100 0 0 0 @@ -5331,7 +4980,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 232 "ROM_A16" Po 6150 -3251 -Le 1579 $EndPAD $PAD Sh "200" R 1000 100 0 0 0 @@ -5339,7 +4987,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 230 "ROM_A14" Po 6150 -3448 -Le 1579 $EndPAD $PAD Sh "201" R 1000 100 0 0 0 @@ -5347,7 +4994,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 6150 -3645 -Le 1579 $EndPAD $PAD Sh "202" R 1000 100 0 0 0 @@ -5355,7 +5001,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 6150 -3842 -Le 1454 $EndPAD $PAD Sh "203" R 1000 100 0 0 0 @@ -5363,7 +5008,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 238 "ROM_A21" Po 6150 -4039 -Le 1433 $EndPAD $PAD Sh "204" R 1000 100 0 0 0 @@ -5371,7 +5015,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 246 "ROM_A9" Po 6150 -4236 -Le 1579 $EndPAD $PAD Sh "205" R 1000 100 0 0 0 @@ -5379,7 +5022,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 245 "ROM_A8" Po 6150 -4433 -Le 1495 $EndPAD $PAD Sh "206" R 1000 100 0 0 0 @@ -5394,7 +5036,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 188 "PROG_B" Po 6150 -4827 -Le 3 $EndPAD $PAD Sh "208" R 1000 100 0 0 0 @@ -5402,7 +5043,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 6150 -5024 -Le 110 $EndPAD $SHAPE3D Na "smd/pqfp208.wrl" @@ -5446,7 +5086,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 10 "/Memory/SRAM_Vcc" Po 0 400 -Le 14554736 $EndPAD $SHAPE3D Na "smd/cms_sot23.wrl" @@ -5471,17 +5110,15 @@ $PAD Sh "1" R 512 866 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 181 "N-000340" +Ne 178 "N-000337" Po -827 0 -Le 31 $EndPAD $PAD Sh "2" R 512 866 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 178 "N-000337" +Ne 179 "N-000338" Po 827 0 -Le 156 $EndPAD $EndMODULE XTAL_SMD_05019 $MODULE PIN_ARRAY_2X1 @@ -5504,7 +5141,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 88 "GND" Po -500 0 -Le 335 $EndPAD $PAD Sh "2" C 600 600 0 0 900 @@ -5512,7 +5148,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 13 "/RESET" Po 500 0 -Le 40681 $EndPAD $SHAPE3D Na "pin_array/pins_array_2x1.wrl" @@ -5597,7 +5232,6 @@ Dr 276 0 0 At STD N 00D0FFFF Ne 166 "N-000310" Po -236 315 -Le 437918234 $EndPAD $PAD Sh "3" C 394 394 0 0 2700 @@ -5605,7 +5239,6 @@ Dr 276 0 0 At STD N 00D0FFFF Ne 170 "N-000315" Po 236 0 -Le -1238971745 $EndPAD $PAD Sh "4" C 394 394 0 0 2700 @@ -5613,7 +5246,6 @@ Dr 276 0 0 At STD N 00D0FFFF Ne 0 "" Po -236 -315 -Le 54068 $EndPAD $PAD Sh "5" C 394 394 0 0 2700 @@ -5621,15 +5253,13 @@ Dr 276 0 0 At STD N 00D0FFFF Ne 88 "GND" Po 236 -630 -Le 65535 $EndPAD $PAD Sh "1" C 394 394 0 0 2700 Dr 276 0 0 At STD N 00D0FFFF -Ne 176 "N-000326" +Ne 177 "N-000328" Po 236 630 -Le 37823264 $EndPAD $PAD Sh "6" O 866 394 0 0 2700 @@ -5644,7 +5274,6 @@ Dr 748 0 0 O 748 276 At STD N 00D0FFFF Ne 88 "GND" Po -1772 -1437 -Le -791621423 $EndPAD $EndMODULE USB-MINIB-THT $MODULE SOT23EBC @@ -5668,7 +5297,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -350 -400 -Le 41415008 $EndPAD $PAD Sh "2" R 360 360 0 0 1800 @@ -5676,7 +5304,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 182 "N-000344" Po 350 -400 -Le 41417248 $EndPAD $PAD Sh "3" R 360 360 0 0 1800 @@ -5684,7 +5311,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 9 "/Memory/RAM_/CE" Po 0 400 -Le 15 $EndPAD $SHAPE3D Na "smd/cms_sot23.wrl" @@ -5713,7 +5339,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 88 "GND" Po -500 0 -Le 9 $EndPAD $PAD Sh "2" C 600 600 0 0 2700 @@ -5721,7 +5346,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 168 "N-000313" Po 500 0 -Le 9 $EndPAD $SHAPE3D Na "pin_array/pins_array_2x1.wrl" @@ -5763,7 +5387,6 @@ Dr 400 0 0 At STD N 00F0FFFF Ne 88 "GND" Po -5300 0 -Le 41807728 $EndPAD $PAD Sh "1" C 600 600 0 0 900 @@ -5778,7 +5401,6 @@ Dr 400 0 0 At STD N 00F0FFFF Ne 8 "+BATT" Po 5300 -500 -Le 109 $EndPAD $EndMODULE BT_KEYSTONE_1059_20MM $MODULE VFBGA54 @@ -5814,7 +5436,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 262 "ROM_DQ9" Po -590 738 -Le 37834800 $EndPAD $PAD Sh "D1" O 114 114 0 0 1800 @@ -5822,7 +5443,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -295 738 -Le 1830776095 $EndPAD $PAD Sh "E1" O 114 114 0 0 1800 @@ -5837,7 +5457,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 253 "ROM_DQ14" Po 295 738 -Le -1908344698 $EndPAD $PAD Sh "G1" O 114 114 0 0 1800 @@ -5845,7 +5464,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 254 "ROM_DQ15" Po 590 738 -Le 1547 $EndPAD $PAD Sh "H1" O 114 114 0 0 1800 @@ -5853,7 +5471,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 234 "ROM_A18" Po 885 738 -Le 1579 $EndPAD $PAD Sh "J1" O 114 114 0 0 1800 @@ -5861,7 +5478,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1181 738 -Le 1579 $EndPAD $PAD Sh "A2" O 114 114 0 0 1800 @@ -5869,7 +5485,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 221 "ROM_/OE" Po -1181 442 -Le 1454 $EndPAD $PAD Sh "B2" O 114 114 0 0 1800 @@ -5877,7 +5492,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 222 "ROM_/UB" Po -885 442 -Le 1454 $EndPAD $PAD Sh "C2" O 114 114 0 0 1800 @@ -5885,7 +5499,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 249 "ROM_DQ10" Po -590 442 -Le 1542 $EndPAD $PAD Sh "D2" O 114 114 0 0 1800 @@ -5893,7 +5506,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 250 "ROM_DQ11" Po -295 442 -Le 1579 $EndPAD $PAD Sh "E2" O 114 114 0 0 1800 @@ -5901,7 +5513,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 251 "ROM_DQ12" Po 0 442 -Le 40193136 $EndPAD $PAD Sh "F2" O 114 114 0 0 1800 @@ -5909,7 +5520,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 252 "ROM_DQ13" Po 295 442 -Le 38167024 $EndPAD $PAD Sh "G2" O 114 114 0 0 1800 @@ -5917,7 +5527,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 235 "ROM_A19" Po 590 442 -Le 6593040 $EndPAD $PAD Sh "H2" O 114 114 0 0 1800 @@ -5932,7 +5541,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1181 442 -Le 40709040 $EndPAD $PAD Sh "A3" O 114 114 0 0 1800 @@ -5940,7 +5548,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 224 "ROM_A0" Po -1181 147 -Le 458760 $EndPAD $PAD Sh "B3" O 114 114 0 0 1800 @@ -5948,7 +5555,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 240 "ROM_A3" Po -885 147 -Le 9 $EndPAD $PAD Sh "C3" O 114 114 0 0 1800 @@ -5956,7 +5562,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 242 "ROM_A5" Po -590 147 -Le 14614744 $EndPAD $PAD Sh "D3" O 114 114 0 0 1800 @@ -5964,7 +5569,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 233 "ROM_A17" Po -295 147 -Le 993 $EndPAD $PAD Sh "E3" O 114 114 0 0 1800 @@ -5972,7 +5576,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 238 "ROM_A21" Po 0 147 -Le 15074816 $EndPAD $PAD Sh "F3" O 114 114 0 0 1800 @@ -5980,7 +5583,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 230 "ROM_A14" Po 295 147 -Le 16712960 $EndPAD $PAD Sh "G3" O 114 114 0 0 1800 @@ -5988,7 +5590,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 228 "ROM_A12" Po 590 147 -Le 919040 $EndPAD $PAD Sh "H3" O 114 114 0 0 1800 @@ -5996,7 +5597,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 246 "ROM_A9" Po 885 147 -Le 16647424 $EndPAD $PAD Sh "J3" O 114 114 0 0 1800 @@ -6004,7 +5604,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 1181 147 -Le 1181184 $EndPAD $PAD Sh "A4" O 114 114 0 0 1800 @@ -6012,7 +5611,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 225 "ROM_A1" Po -1181 -147 -Le 16712960 $EndPAD $PAD Sh "B4" O 114 114 0 0 1800 @@ -6020,7 +5618,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 241 "ROM_A4" Po -885 -147 -Le 41341072 $EndPAD $PAD Sh "C4" O 114 114 0 0 1800 @@ -6028,7 +5625,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 243 "ROM_A6" Po -590 -147 -Le 41278912 $EndPAD $PAD Sh "D4" O 114 114 0 0 1800 @@ -6036,7 +5632,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 244 "ROM_A7" Po -295 -147 -Le 41363712 $EndPAD $PAD Sh "E4" O 114 114 0 0 1800 @@ -6044,7 +5639,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 232 "ROM_A16" Po 0 -147 -Le 41269760 $EndPAD $PAD Sh "F4" O 114 114 0 0 1800 @@ -6052,7 +5646,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 231 "ROM_A15" Po 295 -147 -Le 41332752 $EndPAD $PAD Sh "G4" O 114 114 0 0 1800 @@ -6060,7 +5653,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 229 "ROM_A13" Po 590 -147 -Le 41261440 $EndPAD $PAD Sh "H4" O 114 114 0 0 1800 @@ -6068,7 +5660,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 226 "ROM_A10" Po 885 -147 -Le 41327824 $EndPAD $PAD Sh "J4" O 114 114 0 0 1800 @@ -6076,7 +5667,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 239 "ROM_A22" Po 1181 -147 -Le 41256512 $EndPAD $PAD Sh "A5" O 114 114 0 0 1800 @@ -6084,7 +5674,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 236 "ROM_A2" Po -1181 -442 -Le 41323248 $EndPAD $PAD Sh "B5" O 114 114 0 0 1800 @@ -6092,7 +5681,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 219 "ROM_/CE" Po -885 -442 -Le 41382352 $EndPAD $PAD Sh "C5" O 114 114 0 0 1800 @@ -6100,7 +5688,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 248 "ROM_DQ1" Po -590 -442 -Le 41446560 $EndPAD $PAD Sh "D5" O 114 114 0 0 1800 @@ -6108,7 +5695,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 256 "ROM_DQ3" Po -295 -442 -Le 41451600 $EndPAD $PAD Sh "E5" O 114 114 0 0 1800 @@ -6116,7 +5702,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 257 "ROM_DQ4" Po 0 -442 -Le 41662464 $EndPAD $PAD Sh "F5" O 114 114 0 0 1800 @@ -6124,7 +5709,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 258 "ROM_DQ5" Po 295 -442 -Le 37575 $EndPAD $PAD Sh "G5" O 114 114 0 0 1800 @@ -6132,7 +5716,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 223 "ROM_/WE" Po 590 -442 -Le 37575 $EndPAD $PAD Sh "H5" O 114 114 0 0 1800 @@ -6140,7 +5723,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 227 "ROM_A11" Po 885 -442 -Le 40091696 $EndPAD $PAD Sh "J5" O 114 114 0 0 1800 @@ -6148,7 +5730,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1181 -442 -Le 407552 $EndPAD $PAD Sh "A6" O 114 114 0 0 1800 @@ -6156,7 +5737,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po -1181 -738 -Le 43338 $EndPAD $PAD Sh "B6" O 114 114 0 0 1800 @@ -6164,7 +5744,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 247 "ROM_DQ0" Po -885 -738 -Le 1 $EndPAD $PAD Sh "C6" O 114 114 0 0 1800 @@ -6179,7 +5758,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 2 "+1.8V" Po -295 -738 -Le 38160 $EndPAD $PAD Sh "E6" O 114 114 0 0 1800 @@ -6187,7 +5765,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 0 -738 -Le 43750 $EndPAD $PAD Sh "F6" O 114 114 0 0 1800 @@ -6195,7 +5772,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 259 "ROM_DQ6" Po 295 -738 -Le 40093040 $EndPAD $PAD Sh "G6" O 114 114 0 0 1800 @@ -6203,7 +5779,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 260 "ROM_DQ7" Po 590 -738 -Le 350208 $EndPAD $PAD Sh "H6" O 114 114 0 0 1800 @@ -6211,7 +5786,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 237 "ROM_A20" Po 885 -738 -Le 43700 $EndPAD $PAD Sh "J6" O 114 114 0 0 1800 @@ -6219,7 +5793,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1181 -738 -Le 1 $EndPAD $EndMODULE VFBGA54 $MODULE TSSOP10 @@ -6241,7 +5814,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 78 "DAC_SDIN" Po -393 885 -Le 1 $EndPAD $PAD Sh "2" R 118 393 0 0 0 @@ -6249,7 +5821,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 75 "DAC_/DEM" Po -196 885 -Le 43048376 $EndPAD $PAD Sh "3" R 118 393 0 0 0 @@ -6257,7 +5828,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 76 "DAC_LRCK" Po 0 885 -Le 43052128 $EndPAD $PAD Sh "4" R 118 393 0 0 0 @@ -6265,7 +5835,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 77 "DAC_MCLK" Po 196 885 -Le 43054032 $EndPAD $PAD Sh "5" R 118 393 0 0 0 @@ -6273,7 +5842,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 158 "N-000284" Po 393 885 -Le 16777985 $EndPAD $PAD Sh "6" R 118 393 0 0 1800 @@ -6281,7 +5849,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 156 "N-000279" Po 393 -885 -Le 371968 $EndPAD $PAD Sh "7" R 118 393 0 0 1800 @@ -6289,7 +5856,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 157 "N-000281" Po 196 -885 -Le 395264 $EndPAD $PAD Sh "8" R 118 393 0 0 1800 @@ -6297,7 +5863,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 0 -885 -Le 366592 $EndPAD $PAD Sh "9" R 118 393 0 0 1800 @@ -6305,7 +5870,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 5 "+3.3VDAC" Po -196 -885 -Le 391168 $EndPAD $PAD Sh "10" R 118 393 0 0 1800 @@ -6313,7 +5877,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 155 "N-000278" Po -393 -885 -Le 403968 $EndPAD $EndMODULE TSSOP10 $MODULE pin_array_7x2 @@ -6344,7 +5907,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 4 "+3.3V" Po -3000 500 -Le 42764800 $EndPAD $PAD Sh "2" C 600 600 0 0 900 @@ -6352,7 +5914,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 6 "+5V" Po -3000 -500 -Le 42764800 $EndPAD $PAD Sh "3" C 600 600 0 0 900 @@ -6360,7 +5921,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 88 "GND" Po -2000 500 -Le 42764800 $EndPAD $PAD Sh "4" C 600 600 0 0 900 @@ -6368,7 +5928,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 185 "P2.10" Po -2000 -500 -Le 42764800 $EndPAD $PAD Sh "5" C 600 600 0 0 900 @@ -6376,7 +5935,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 13 "/RESET" Po -1000 500 -Le 42764800 $EndPAD $PAD Sh "6" C 600 600 0 0 900 @@ -6384,7 +5942,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 324 "TX3" Po -1000 -500 -Le 8216064 $EndPAD $PAD Sh "7" C 600 600 0 0 900 @@ -6392,7 +5949,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 264 "RX3" Po 0 500 -Le 257 $EndPAD $PAD Sh "8" C 600 600 0 0 900 @@ -6407,7 +5963,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 63 "/TRST" Po 1000 500 -Le 1454 $EndPAD $PAD Sh "10" C 600 600 0 0 900 @@ -6422,7 +5977,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 85 "EXT_TDI" Po 2000 500 -Le 38153 $EndPAD $PAD Sh "12" C 600 600 0 0 900 @@ -6430,7 +5984,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 86 "EXT_TDO" Po 2000 -500 -Le 16 $EndPAD $PAD Sh "13" C 600 600 0 0 900 @@ -6438,7 +5991,6 @@ Dr 400 0 0 At STD N 00E0FFFF Ne 263 "RX0" Po 3000 500 -Le 42746368 $EndPAD $PAD Sh "14" C 600 600 0 0 900 @@ -6467,9 +6019,8 @@ $PAD Sh "1" R 350 550 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 153 "N-000276" +Ne 154 "N-000277" Po -375 0 -Le 42745984 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -6477,7 +6028,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 69 "CIC_CLK" Po 375 0 -Le 41044112 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6514,7 +6064,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 375 0 -Le 41146848 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6544,7 +6093,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le -8355685 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -6552,7 +6100,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 1 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6580,9 +6127,8 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 174 "N-000324" +Ne 174 "N-000323" Po -375 0 -Le 6400 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -6590,7 +6136,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 167 "N-000311" Po 375 0 -Le -34816 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6620,7 +6165,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 13 "/RESET" Po -375 0 -Le 689 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -6628,7 +6172,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 687 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6658,7 +6201,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 13 "/RESET" Po -375 0 -Le 487 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -6666,7 +6208,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 375 0 -Le 480 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6696,7 +6237,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po -375 0 -Le 639 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -6704,7 +6244,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 675 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6734,7 +6273,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -6742,7 +6280,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6772,7 +6309,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -6780,7 +6316,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6810,7 +6345,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -6818,7 +6352,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6855,7 +6388,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 325 "USB_SWCONN" Po 375 0 -Le 397824 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6885,7 +6417,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -375 0 -Le 403968 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -6893,7 +6424,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 371968 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -6923,7 +6453,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 2 "+1.8V" Po -375 0 -Le 92599920 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -6960,7 +6489,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 0 -Le 36775 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -6968,7 +6496,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 42875 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7034,7 +6561,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 2 "+1.8V" Po -375 0 -Le 176 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7042,7 +6568,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 176 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7072,7 +6597,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 10 "/Memory/SRAM_Vcc" Po -375 0 -Le 75334 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7080,7 +6604,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 69649 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7146,7 +6669,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 92887984 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -7154,7 +6676,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 93106272 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7191,7 +6712,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 2949844 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7221,7 +6741,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 105 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -7229,7 +6748,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 5440256 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7259,7 +6777,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 92941296 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7267,7 +6784,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 470 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7297,7 +6813,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 65536 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7305,7 +6820,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 42079312 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7335,7 +6849,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 42082480 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7343,7 +6856,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 41384576 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7409,7 +6921,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 9 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7417,7 +6928,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 9 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7447,7 +6957,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 1 "+1.2V" Po -375 0 -Le 366848 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -7484,7 +6993,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -375 0 -Le 366848 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7521,7 +7029,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 3 "+2.5V" Po -375 0 -Le 372224 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7565,7 +7072,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 77079392 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7595,7 +7101,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -375 0 -Le 1 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -7632,7 +7137,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -375 0 -Le 41459104 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -7640,7 +7144,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 41394544 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7670,7 +7173,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 41879248 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -7678,7 +7180,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 41440704 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7708,7 +7209,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 647 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -7716,7 +7216,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 634 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7746,7 +7245,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 498 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7754,7 +7252,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 480 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7784,7 +7281,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 179 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7792,7 +7288,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 370 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7858,7 +7353,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 0 -Le 36 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -7866,7 +7360,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le -2 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7896,7 +7389,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 694 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7904,7 +7396,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 693 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7934,7 +7425,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 673 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -7942,7 +7432,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 677 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -7979,7 +7468,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" Po 375 0 -Le 847 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8007,9 +7495,8 @@ $PAD Sh "1" R 350 550 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 181 "N-000340" +Ne 178 "N-000337" Po -375 0 -Le 57050 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -8017,7 +7504,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 111 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8045,9 +7531,8 @@ $PAD Sh "1" R 350 550 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 180 "N-000339" +Ne 181 "N-000340" Po -375 0 -Le 105 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8082,9 +7567,8 @@ $PAD Sh "1" R 350 550 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "N-000338" +Ne 180 "N-000339" Po -375 0 -Le 37562 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8092,7 +7576,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 417 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8129,7 +7612,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po 375 0 -Le 68 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8195,7 +7677,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 10 "/Memory/SRAM_Vcc" Po -375 0 -Le 5177476 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -8232,7 +7713,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 1 "+1.2V" Po -375 0 -Le 955 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8240,7 +7720,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 984 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8270,7 +7749,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 1 "+1.2V" Po -375 0 -Le 92518288 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8307,7 +7785,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 23 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8315,7 +7792,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 80 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8345,7 +7821,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 44 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8382,7 +7857,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 543 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -8390,7 +7864,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 384 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8420,7 +7893,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 646 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8428,7 +7900,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 597 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8458,7 +7929,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 707 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -8466,7 +7936,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 681 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8494,16 +7963,15 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 162 "N-000295" +Ne 161 "N-000294" Po -375 0 $EndPAD $PAD Sh "2" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000318" +Ne 171 "N-000316" Po 375 0 -Le 584 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8531,9 +7999,8 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000323" +Ne 173 "N-000322" Po -375 0 -Le 658 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -8541,7 +8008,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 164 "N-000305" Po 375 0 -Le 499 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8569,9 +8035,8 @@ $PAD Sh "1" R 350 550 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "N-000325" +Ne 175 "N-000324" Po -375 0 -Le 92505040 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8613,9 +8078,8 @@ $PAD Sh "2" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 177 "N-000327" +Ne 176 "N-000327" Po 375 0 -Le 15 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8645,7 +8109,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 158 "N-000284" Po -375 0 -Le 42372176 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8653,7 +8116,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 375 0 -Le 42372528 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8755,7 +8217,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 67 "AUDIO_R" Po -375 0 -Le 801 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8763,7 +8224,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 375 0 -Le 782 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8793,7 +8253,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 66 "AUDIO_L" Po -375 0 -Le 607 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8801,7 +8260,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 159 "N-000292" Po 375 0 -Le 569 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8831,7 +8289,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 159 "N-000292" Po -375 0 -Le 252 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8839,7 +8296,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 375 0 -Le 114 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8869,7 +8325,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 159 "N-000292" Po -375 0 -Le 92824656 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -8906,7 +8361,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 160 "N-000293" Po -375 0 -Le -16777216 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -8914,7 +8368,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 155 "N-000278" Po 375 0 -Le 353 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -8980,7 +8433,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 160 "N-000293" Po -375 0 -Le 92604552 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -9017,7 +8469,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 67 "AUDIO_R" Po -375 0 -Le 14554736 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -9025,7 +8476,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 160 "N-000293" Po 375 0 -Le 91 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9091,7 +8541,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9099,7 +8548,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9129,7 +8577,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9137,7 +8584,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9167,7 +8613,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 42796288 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -9175,7 +8620,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 42796288 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9205,7 +8649,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 73800 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -9213,7 +8656,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 45875 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9243,7 +8685,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -375 0 -Le 44895 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -9251,7 +8692,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 50250 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9279,7 +8719,7 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 178 "N-000337" +Ne 179 "N-000338" Po -375 0 $EndPAD $PAD @@ -9288,7 +8728,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 48 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9326,7 +8765,6 @@ Dr 512 0 0 At STD N 00D0FFFF Ne 0 "" Po -4686 4999 -Le 41207216 $EndPAD $PAD Sh "~" C 512 512 0 0 0 @@ -9334,7 +8772,6 @@ Dr 512 0 0 At STD N 00D0FFFF Ne 0 "" Po 4133 4999 -Le 41207760 $EndPAD $PAD Sh "1" R 433 787 0 0 0 @@ -9342,7 +8779,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 270 "SD_DAT3" Po 2391 5865 -Le 41207216 $EndPAD $PAD Sh "2" R 433 787 0 0 0 @@ -9357,7 +8793,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 422 5865 -Le 7585 $EndPAD $PAD Sh "4" R 433 787 0 0 0 @@ -9365,7 +8800,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -562 5865 -Le 41209056 $EndPAD $PAD Sh "5" R 433 787 0 0 0 @@ -9380,7 +8814,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -2530 5865 -Le 48 $EndPAD $PAD Sh "7" R 433 787 0 0 0 @@ -9388,7 +8821,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 267 "SD_DAT0" Po -3485 5865 -Le 41210112 $EndPAD $PAD Sh "8" R 433 787 0 0 0 @@ -9396,7 +8828,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 268 "SD_DAT1" Po -4155 5865 -Le 41210544 $EndPAD $PAD Sh "9" R 433 787 0 0 0 @@ -9404,7 +8835,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 269 "SD_DAT2" Po 3375 5865 -Le 48 $EndPAD $PAD Sh "GND1" R 787 787 0 0 0 @@ -9412,7 +8842,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 5708 3208 -Le 41211168 $EndPAD $PAD Sh "GND1" R 787 787 0 0 0 @@ -9420,7 +8849,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 5708 -4135 -Le 41211600 $EndPAD $PAD Sh "GND1" R 787 787 0 0 0 @@ -9428,7 +8856,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -5710 3208 -Le 48 $EndPAD $PAD Sh "GND1" R 787 787 0 0 0 @@ -9436,22 +8863,20 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -5710 -4135 -Le 41211824 $EndPAD $PAD Sh "DT" R 787 394 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 172 "N-000319" +Ne 172 "N-000318" Po -5552 1377 $EndPAD $PAD Sh "WP" R 787 394 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 161 "N-000294" +Ne 162 "N-000295" Po -5552 -2147 -Le 3361 $EndPAD $PAD Sh "GND2" R 787 394 0 0 0 @@ -9459,7 +8884,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -5552 -3170 -Le 41210240 $EndPAD $EndMODULE HRS-DM1AA $MODULE SM0805_FIXEDMASK @@ -9483,7 +8907,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 170 "N-000315" Po -375 0 -Le 41216208 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9491,7 +8914,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 165 "N-000309" Po 375 0 -Le 108 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9521,7 +8943,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 166 "N-000310" Po -375 0 -Le 42406672 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9529,7 +8950,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 169 "N-000314" Po 375 0 -Le 42399104 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9559,23 +8979,20 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -350 400 -Le 67651760 $EndPAD $PAD Sh "2" R 360 360 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 97 "N-000037" +Ne 97 "N-000036" Po 350 400 -Le 91495728 $EndPAD $PAD Sh "3" R 360 360 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 141 "N-000149" +Ne 141 "N-000147" Po 0 -400 -Le 42314272 $EndPAD $SHAPE3D Na "smd/cms_sot23.wrl" @@ -9603,9 +9020,8 @@ $PAD Sh "1" R 350 550 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 97 "N-000037" +Ne 97 "N-000036" Po -375 0 -Le 42372880 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9613,7 +9029,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 42334512 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9643,15 +9058,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 310 "SNES_IRQ_EN" Po -375 0 -Le 92555072 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 97 "N-000037" +Ne 97 "N-000036" Po 375 0 -Le 3072 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9708,7 +9121,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po 375 0 -Le 4 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9744,7 +9156,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 72 "CIC_MCLR" Po 0 250 -Le 92612160 $EndPAD $EndMODULE GS2 $MODULE DIP-8__300 @@ -9770,15 +9181,13 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 6 "+5V" Po -1500 1500 -Le 49 $EndPAD $PAD Sh "2" C 550 550 0 0 1800 Dr 320 0 0 At STD N 00E0FFFF -Ne 153 "N-000276" +Ne 154 "N-000277" Po -500 1500 -Le 609 $EndPAD $PAD Sh "3" C 550 550 0 0 1800 @@ -9786,7 +9195,6 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 74 "CIC_STATUS" Po 500 1500 -Le 93155248 $EndPAD $PAD Sh "4" C 550 550 0 0 1800 @@ -9801,7 +9209,6 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 73 "CIC_RESET" Po 1500 -1500 -Le 12 $EndPAD $PAD Sh "6" C 550 550 0 0 1800 @@ -9809,7 +9216,6 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 71 "CIC_DATA1" Po 500 -1500 -Le 92631536 $EndPAD $PAD Sh "7" C 550 550 0 0 1800 @@ -9817,7 +9223,6 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 70 "CIC_DATA0" Po -500 -1500 -Le 92627904 $EndPAD $PAD Sh "8" C 550 550 0 0 1800 @@ -9825,7 +9230,6 @@ Dr 320 0 0 At STD N 00E0FFFF Ne 88 "GND" Po -1500 -1500 -Le 161 $EndPAD $SHAPE3D Na "dil/dil_8.wrl" @@ -9855,7 +9259,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 70 "CIC_DATA0" Po -375 0 -Le 69649 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -9863,7 +9266,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 83 "EXT_CIC_DATA0" Po 375 0 -Le 69649 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -9900,7 +9302,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 71 "CIC_DATA1" Po 375 0 -Le 65536 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10000,9 +9401,8 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 146 "N-000157" +Ne 146 "N-000156" Po -375 0 -Le 9 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10010,7 +9410,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 9 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10038,9 +9437,8 @@ $PAD Sh "1" R 350 550 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "N-000153" +Ne 142 "N-000151" Po -375 0 -Le 29902 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -10048,7 +9446,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 29883 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10085,7 +9482,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 375 0 -Le 37061 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10115,7 +9511,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 95 "N-000012" Po -375 0 -Le 58450 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10123,7 +9518,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 57122 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10153,7 +9547,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 96 "N-000013" Po -375 0 -Le 92845984 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10161,7 +9554,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 92842848 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10189,9 +9581,8 @@ $PAD Sh "1" R 350 550 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 141 "N-000149" +Ne 141 "N-000147" Po -375 0 -Le 14554736 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -10199,7 +9590,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 33 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10227,9 +9617,8 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 138 "N-000146" +Ne 137 "N-000143" Po -375 0 -Le 273 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10264,9 +9653,8 @@ $PAD Sh "1" R 350 550 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "N-000147" +Ne 138 "N-000144" Po -375 0 -Le 2035557928 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10341,7 +9729,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -700 0 -Le 327 $EndPAD $PAD Sh "2" R 700 1100 0 0 2700 @@ -10349,7 +9736,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 11 "/Power_Supply_/_Misc./REG_SW1" Po 700 0 -Le 257 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10378,7 +9764,6 @@ Dr 400 0 0 At STD N 00D4FFFF Ne 4 "+3.3V" Po -500 0 -Le 206 $EndPAD $PAD Sh "2" C 660 660 0 0 0 @@ -10386,7 +9771,6 @@ Dr 400 0 0 At STD N 00D4FFFF Ne 164 "N-000305" Po 500 0 -Le 293 $EndPAD $SHAPE3D Na "discret/leds/led3_vertical_amarelo.wrl" @@ -10420,7 +9804,7 @@ $PAD Sh "2" C 660 660 0 0 0 Dr 400 0 0 At STD N 00D4FFFF -Ne 171 "N-000318" +Ne 171 "N-000316" Po 500 0 $EndPAD $SHAPE3D @@ -10450,7 +9834,6 @@ Dr 400 0 0 At STD N 00D4FFFF Ne 4 "+3.3V" Po -500 0 -Le -1 $EndPAD $PAD Sh "2" C 660 660 0 0 0 @@ -10487,7 +9870,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -375 0 -Le 363 $EndPAD $PAD Sh "2" R 350 550 0 0 0 @@ -10495,7 +9877,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 847 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10526,17 +9907,15 @@ $PAD Sh "1" R 2166 787 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "N-000338" +Ne 180 "N-000339" Po -1673 0 -Le 633 $EndPAD $PAD Sh "2" R 2166 787 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "N-000339" +Ne 181 "N-000340" Po 1673 0 -Le 584 $EndPAD $EndMODULE HC49US $MODULE SM0805_FIXEDMASK @@ -10560,7 +9939,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 429 $EndPAD $PAD Sh "2" R 350 550 0 0 900 @@ -10568,7 +9946,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 428 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10598,7 +9975,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 860 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -10606,7 +9982,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 21299727 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10636,7 +10011,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -375 0 -Le 25690271 $EndPAD $PAD Sh "2" R 350 550 0 0 2700 @@ -10644,7 +10018,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 31457394 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10674,7 +10047,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 758 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -10682,7 +10054,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 665 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10712,7 +10083,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -375 0 -Le 431 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -10720,7 +10090,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po 375 0 -Le 421 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -10784,7 +10153,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 201 "RAM_A17" Po -3749 2249 -Le 786 $EndPAD $PAD Sh "2" R 295 499 0 0 1800 @@ -10792,7 +10160,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 200 "RAM_A16" Po -3249 2249 -Le 750 $EndPAD $PAD Sh "3" R 295 499 0 0 1800 @@ -10800,7 +10167,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 198 "RAM_A14" Po -2749 2249 -Le 701 $EndPAD $PAD Sh "4" R 295 499 0 0 1800 @@ -10808,7 +10174,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 196 "RAM_A12" Po -2249 2249 -Le 634 $EndPAD $PAD Sh "5" R 295 499 0 0 1800 @@ -10816,7 +10181,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 208 "RAM_A7" Po -1749 2249 -Le 587 $EndPAD $PAD Sh "6" R 295 499 0 0 1800 @@ -10824,7 +10188,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 207 "RAM_A6" Po -1249 2249 -Le 557 $EndPAD $PAD Sh "7" R 295 499 0 0 1800 @@ -10832,7 +10195,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 206 "RAM_A5" Po -749 2249 -Le 557 $EndPAD $PAD Sh "8" R 295 499 0 0 1800 @@ -10840,7 +10202,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 205 "RAM_A4" Po -249 2249 -Le 567 $EndPAD $PAD Sh "9" R 295 499 0 0 1800 @@ -10848,7 +10209,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 204 "RAM_A3" Po 249 2249 -Le 556 $EndPAD $PAD Sh "10" R 295 499 0 0 1800 @@ -10856,7 +10216,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 203 "RAM_A2" Po 749 2249 -Le 639 $EndPAD $PAD Sh "11" R 295 499 0 0 1800 @@ -10864,7 +10223,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 193 "RAM_A1" Po 1249 2249 -Le 598 $EndPAD $PAD Sh "12" R 295 499 0 0 1800 @@ -10872,7 +10230,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 192 "RAM_A0" Po 1749 2249 -Le 585 $EndPAD $PAD Sh "13" R 295 499 0 0 1800 @@ -10880,7 +10237,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 211 "RAM_DQ0" Po 2249 2249 -Le 633 $EndPAD $PAD Sh "14" R 295 499 0 0 1800 @@ -10888,7 +10244,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 212 "RAM_DQ1" Po 2749 2249 -Le 677 $EndPAD $PAD Sh "15" R 295 499 0 0 1800 @@ -10896,7 +10251,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 213 "RAM_DQ2" Po 3249 2249 -Le 722 $EndPAD $PAD Sh "16" R 295 499 0 0 1800 @@ -10904,7 +10258,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 3749 2249 -Le 763 $EndPAD $PAD Sh "17" R 295 499 0 0 0 @@ -10912,7 +10265,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 214 "RAM_DQ3" Po 3749 -2249 -Le 817 $EndPAD $PAD Sh "18" R 295 499 0 0 0 @@ -10920,7 +10272,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 215 "RAM_DQ4" Po 3249 -2249 -Le 859 $EndPAD $PAD Sh "19" R 295 499 0 0 0 @@ -10928,7 +10279,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 216 "RAM_DQ5" Po 2749 -2249 -Le 863 $EndPAD $PAD Sh "20" R 295 499 0 0 0 @@ -10936,7 +10286,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 217 "RAM_DQ6" Po 2249 -2249 -Le 64 $EndPAD $PAD Sh "21" R 295 499 0 0 0 @@ -10951,7 +10300,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 9 "/Memory/RAM_/CE" Po 1249 -2249 -Le 1 $EndPAD $PAD Sh "23" R 295 499 0 0 0 @@ -10959,7 +10307,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 194 "RAM_A10" Po 749 -2249 -Le 32776 $EndPAD $PAD Sh "24" R 295 499 0 0 0 @@ -10967,7 +10314,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 190 "RAM_/OE" Po 249 -2249 -Le 115 $EndPAD $PAD Sh "25" R 295 499 0 0 0 @@ -10982,7 +10328,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 210 "RAM_A9" Po -749 -2249 -Le 33792 $EndPAD $PAD Sh "27" R 295 499 0 0 0 @@ -10990,7 +10335,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 209 "RAM_A8" Po -1249 -2249 -Le 66340624 $EndPAD $PAD Sh "28" R 295 499 0 0 0 @@ -11005,7 +10349,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 191 "RAM_/WE" Po -2249 -2249 -Le 66340624 $EndPAD $PAD Sh "30" R 295 499 0 0 0 @@ -11013,7 +10356,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 202 "RAM_A18" Po -2749 -2249 -Le 2816 $EndPAD $PAD Sh "31" R 295 499 0 0 0 @@ -11021,7 +10363,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 199 "RAM_A15" Po -3249 -2249 -Le 43307344 $EndPAD $PAD Sh "32" R 295 499 0 0 0 @@ -11029,7 +10370,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 10 "/Memory/SRAM_Vcc" Po -3749 -2249 -Le 23040 $EndPAD $EndMODULE TSOPII-32 $MODULE SOT23GDS @@ -11053,15 +10393,13 @@ Dr 0 0 0 At SMD N 00440001 Ne 6 "+5V" Po -350 400 -Le 92344576 $EndPAD $PAD Sh "G" R 360 360 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000277" +Ne 153 "N-000273" Po 350 400 -Le 1 $EndPAD $PAD Sh "D" R 360 360 0 0 1800 @@ -11069,7 +10407,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 7 "+5VL" Po 0 -400 -Le 93124416 $EndPAD $SHAPE3D Na "smd/cms_sot23.wrl" @@ -11099,15 +10436,13 @@ Dr 0 0 0 At SMD N 00440001 Ne 88 "GND" Po -375 0 -Le 1 $EndPAD $PAD Sh "2" R 350 550 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000277" +Ne 153 "N-000273" Po 375 0 -Le 40440768 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -11123,7 +10458,7 @@ Sc 4D96383B AR /4B6E16F2/4D9630F0 Op 0 0 0 T0 875 -25 320 320 3600 70 N V 21 N "RA101" -T1 0 0 320 320 2700 70 N V 21 N "220" +T1 0 0 320 320 2700 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11132,15 +10467,14 @@ $PAD Sh "7" R 118 197 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000105" +Ne 123 "N-000092" Po -98 -197 -Le 92321184 $EndPAD $PAD Sh "6" R 118 197 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000106" +Ne 127 "N-000103" Po 98 -197 $EndPAD $PAD @@ -11149,7 +10483,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 58 "/SNES_Slot/SNES_EXT_PA5" Po -98 197 -Le 92321184 $EndPAD $PAD Sh "3" R 118 197 0 0 2700 @@ -11157,22 +10490,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 55 "/SNES_Slot/SNES_EXT_PA2" Po 98 197 -Le 31232 $EndPAD $PAD Sh "8" R 197 197 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000104" +Ne 126 "N-000102" Po -335 -197 $EndPAD $PAD Sh "5" R 197 197 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000107" +Ne 128 "N-000104" Po 335 -197 -Le 92344576 $EndPAD $PAD Sh "4" R 197 197 0 0 2700 @@ -11180,7 +10511,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 56 "/SNES_Slot/SNES_EXT_PA3" Po 335 197 -Le 1 $EndPAD $PAD Sh "1" R 197 197 0 0 2700 @@ -11188,7 +10518,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 57 "/SNES_Slot/SNES_EXT_PA4" Po -335 197 -Le 43320208 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11198,7 +10527,7 @@ Sc 4D963839 AR /4B6E16F2/4D9630F4 Op 0 0 0 T0 -475 750 320 320 0 70 N V 21 N "RA102" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11207,9 +10536,8 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000109" +Ne 130 "N-000106" Po -98 -197 -Le 43322896 $EndPAD $PAD Sh "6" R 118 197 0 0 0 @@ -11231,23 +10559,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 19 "/SNES_Slot/SNES_EXT_/WR" Po 98 197 -Le 92321184 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000108" +Ne 129 "N-000105" Po -335 -197 -Le 8192 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000147" +Ne 138 "N-000144" Po 335 -197 -Le 43325264 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11255,7 +10580,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 44 "/SNES_Slot/SNES_EXT_CPU_CLK" Po 335 197 -Le 7936 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11263,7 +10587,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 53 "/SNES_Slot/SNES_EXT_PA0" Po -335 197 -Le 1 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11273,7 +10596,7 @@ Sc 4D963837 AR /4B6E16F2/4D96310E Op 0 0 0 T0 325 750 320 320 0 70 N V 21 N "RA105" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11284,15 +10607,13 @@ Dr 0 0 0 At SMD N 00888000 Ne 95 "N-000012" Po -98 -197 -Le 1 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000146" +Ne 137 "N-000143" Po 98 -197 -Le 65820928 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11307,23 +10628,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 18 "/SNES_Slot/SNES_EXT_/ROMSEL" Po 98 197 -Le 42618928 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000149" +Ne 141 "N-000147" Po -335 -197 -Le 42630544 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "N-000038" +Ne 99 "N-000038" Po 335 -197 -Le 42638288 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11331,7 +10649,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 36 "/SNES_Slot/SNES_EXT_A23" Po 335 197 -Le 42646032 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11339,7 +10656,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 14 "/SNES_Slot/SNES_EXT_/IRQ" Po -335 197 -Le 42657648 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11349,7 +10665,7 @@ Sc 4D963835 AR /4B6E16F2/4D963115 Op 0 0 0 T0 0 -675 320 320 0 70 N V 21 N "RA106" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11358,17 +10674,15 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "N-000040" +Ne 101 "N-000040" Po -98 -197 -Le 42716784 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000041" +Ne 102 "N-000041" Po 98 -197 -Le 42724528 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11376,7 +10690,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 35 "/SNES_Slot/SNES_EXT_A22" Po -98 197 -Le 42732272 $EndPAD $PAD Sh "3" R 118 197 0 0 0 @@ -11384,23 +10697,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 21 "/SNES_Slot/SNES_EXT_A1" Po 98 197 -Le 42743888 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "N-000039" +Ne 100 "N-000039" Po -335 -197 -Le 42085296 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000045" +Ne 104 "N-000045" Po 335 -197 -Le 42093040 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11408,7 +10718,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 34 "/SNES_Slot/SNES_EXT_A21" Po 335 197 -Le 42100784 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11416,7 +10725,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 20 "/SNES_Slot/SNES_EXT_A0" Po -335 197 -Le 42112400 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11426,7 +10734,7 @@ Sc 4D963833 AR /4B6E16F2/4D963117 Op 0 0 0 T0 0 750 320 320 0 70 N V 21 N "RA107" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11435,14 +10743,14 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000050" +Ne 106 "N-000049" Po -98 -197 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000054" +Ne 108 "N-000053" Po 98 -197 $EndPAD $PAD @@ -11463,14 +10771,14 @@ $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "N-000047" +Ne 105 "N-000047" Po -335 -197 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000093" +Ne 109 "N-000056" Po 335 -197 $EndPAD $PAD @@ -11495,7 +10803,7 @@ Sc 4D963831 AR /4B6E16F2/4D963119 Op 0 0 0 T0 325 750 320 320 0 70 N V 21 N "RA108" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11504,17 +10812,15 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000102" +Ne 125 "N-000100" Po -98 -197 -Le 160 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000042" +Ne 103 "N-000042" Po 98 -197 -Le 160 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11522,7 +10828,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 30 "/SNES_Slot/SNES_EXT_A18" Po -98 197 -Le 160 $EndPAD $PAD Sh "3" R 118 197 0 0 0 @@ -11530,23 +10835,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 39 "/SNES_Slot/SNES_EXT_A5" Po 98 197 -Le 80 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000097" +Ne 124 "N-000095" Po -335 -197 -Le 60 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000048" +Ne 98 "N-000037" Po 335 -197 -Le 320 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11554,7 +10856,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 29 "/SNES_Slot/SNES_EXT_A17" Po 335 197 -Le 320 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11562,7 +10863,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 38 "/SNES_Slot/SNES_EXT_A4" Po -335 197 -Le 320 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11572,7 +10872,7 @@ Sc 4D96382F AR /4B6E16F2/4D963103 Op 0 0 0 T0 175 750 320 320 0 70 N V 21 N "RA109" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11588,7 +10888,7 @@ $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000126" +Ne 133 "N-000120" Po 98 -197 $EndPAD $PAD @@ -11609,14 +10909,14 @@ $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "N-000051" +Ne 107 "N-000050" Po -335 -197 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000127" +Ne 135 "N-000127" Po 335 -197 $EndPAD $PAD @@ -11641,7 +10941,7 @@ Sc 4D96382D AR /4B6E16F2/4D963107 Op 0 0 0 T0 0 -725 320 320 0 70 N V 21 N "RA110" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11650,17 +10950,15 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000162" +Ne 151 "N-000161" Po -98 -197 -Le 42401568 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "N-000161" +Ne 150 "N-000160" Po 98 -197 -Le 42401920 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11668,7 +10966,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 26 "/SNES_Slot/SNES_EXT_A14" Po -98 197 -Le 42402272 $EndPAD $PAD Sh "3" R 118 197 0 0 0 @@ -11676,23 +10973,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 43 "/SNES_Slot/SNES_EXT_A9" Po 98 197 -Le 42402800 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000128" +Ne 136 "N-000137" Po -335 -197 -Le 42403328 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "N-000160" +Ne 149 "N-000159" Po 335 -197 -Le 42403680 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11700,7 +10994,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 25 "/SNES_Slot/SNES_EXT_A13" Po 335 197 -Le 42404032 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11708,7 +11001,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 42 "/SNES_Slot/SNES_EXT_A8" Po -335 197 -Le 42404560 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -11718,7 +11010,7 @@ Sc 4D96382B AR /4B6E16F2/4D96310A Op 0 0 0 T0 0 750 320 320 0 70 N V 21 N "RA111" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11727,14 +11019,14 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "N-000159" +Ne 148 "N-000158" Po -98 -197 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "N-000158" +Ne 147 "N-000157" Po 98 -197 $EndPAD $PAD @@ -11755,14 +11047,14 @@ $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000148" +Ne 140 "N-000146" Po -335 -197 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "N-000157" +Ne 146 "N-000156" Po 335 -197 $EndPAD $PAD @@ -11787,7 +11079,7 @@ Sc 4D963829 AR /4B6E16F2/4D96310C Op 0 0 0 T0 0 775 320 320 900 70 M V 20 N "RA112" -T1 0 0 320 320 900 70 M V 20 N "220" +T1 0 0 320 320 900 70 M V 20 N "100" DS -551 394 551 394 75 20 DS 551 394 551 -394 75 20 DS 551 -394 -551 -394 75 20 @@ -11798,7 +11090,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 59 "/SNES_Slot/SNES_EXT_PA6" Po -98 197 -Le 31000 $EndPAD $PAD Sh "6" R 118 197 0 0 900 @@ -11806,23 +11097,20 @@ Dr 0 0 0 At SMD N 00440001 Ne 60 "/SNES_Slot/SNES_EXT_PA7" Po 98 197 -Le 34260 $EndPAD $PAD Sh "2" R 118 197 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "N-000154" +Ne 143 "N-000152" Po -98 -197 -Le 30177 $EndPAD $PAD Sh "3" R 118 197 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "N-000155" +Ne 144 "N-000153" Po 98 -197 -Le 31109 $EndPAD $PAD Sh "8" R 197 197 0 0 900 @@ -11830,7 +11118,6 @@ Dr 0 0 0 At SMD N 00440001 Ne 16 "/SNES_Slot/SNES_EXT_/PAWR" Po -335 197 -Le 34843 $EndPAD $PAD Sh "5" R 197 197 0 0 900 @@ -11838,33 +11125,30 @@ Dr 0 0 0 At SMD N 00440001 Ne 61 "/SNES_Slot/SNES_EXT_REFRESH" Po 335 197 -Le 35640 $EndPAD $PAD Sh "4" R 197 197 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 145 "N-000156" +Ne 145 "N-000154" Po 335 -197 -Le 66762400 $EndPAD $PAD Sh "1" R 197 197 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 142 "N-000153" +Ne 142 "N-000151" Po -335 -197 -Le 704643072 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 -Po 54550 49075 0 15 4D96E877 4D95D318 ~~ +Po 54550 49075 0 15 4EBE961A 4D95D318 ~~ Li R_PACK_0804 Sc 4D95D318 AR /4B6E16F2/4D95CDCD Op 0 0 0 T0 0 750 320 320 0 70 N V 21 N "RA103" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "FB" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11873,17 +11157,15 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "N-000077" +Ne 116 "N-000078" Po -98 -197 -Le 47278 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "N-000082" +Ne 110 "N-000071" Po 98 -197 -Le 50073 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11891,7 +11173,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 52 "/SNES_Slot/SNES_EXT_D7" Po -98 197 -Le 51205 $EndPAD $PAD Sh "3" R 118 197 0 0 0 @@ -11899,23 +11180,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 47 "/SNES_Slot/SNES_EXT_D2" Po 98 197 -Le 37562 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "N-000073" +Ne 113 "N-000074" Po -335 -197 -Le 55872 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000086" +Ne 120 "N-000086" Po 335 -197 -Le 57427 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -11923,7 +11201,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 51 "/SNES_Slot/SNES_EXT_D6" Po 335 197 -Le 58983 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -11931,17 +11208,16 @@ Dr 0 0 0 At SMD N 00888000 Ne 48 "/SNES_Slot/SNES_EXT_D3" Po -335 197 -Le 37562 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 -Po 55700 49075 0 15 4D96E87C 4D95D316 ~~ +Po 55700 49075 0 15 4EBE961F 4D95D316 ~~ Li R_PACK_0804 Sc 4D95D316 AR /4B6E16F2/4D95CDD4 Op 0 0 0 T0 350 750 320 320 0 70 N V 21 N "RA104" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "FB" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -11950,17 +11226,15 @@ $PAD Sh "7" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000110" +Ne 131 "N-000107" Po -98 -197 -Le 44340 $EndPAD $PAD Sh "6" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "N-000071" +Ne 111 "N-000072" Po 98 -197 -Le 44340 $EndPAD $PAD Sh "2" R 118 197 0 0 0 @@ -11968,7 +11242,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 50 "/SNES_Slot/SNES_EXT_D5" Po -98 197 -Le 44340 $EndPAD $PAD Sh "3" R 118 197 0 0 0 @@ -11976,23 +11249,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 45 "/SNES_Slot/SNES_EXT_D0" Po 98 197 -Le 76217 $EndPAD $PAD Sh "8" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000091" +Ne 122 "N-000091" Po -335 -197 -Le 75233 $EndPAD $PAD Sh "5" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "N-000074" +Ne 114 "N-000075" Po 335 -197 -Le 76217 $EndPAD $PAD Sh "4" R 197 197 0 0 0 @@ -12000,7 +11270,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 49 "/SNES_Slot/SNES_EXT_D4" Po 335 197 -Le 61834 $EndPAD $PAD Sh "1" R 197 197 0 0 0 @@ -12008,7 +11277,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 46 "/SNES_Slot/SNES_EXT_D1" Po -335 197 -Le 58925 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -12018,7 +11286,7 @@ Sc 4D97B6C6 AR /4B6E16F2/4D97B45F Op 0 0 0 T0 -75 725 320 320 0 70 N V 21 N "RA114" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -12029,7 +11297,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 307 "SNES_D5" Po -98 -197 -Le 50157 $EndPAD $PAD Sh "6" R 118 197 0 0 0 @@ -12037,23 +11304,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 302 "SNES_D0" Po 98 -197 -Le 62814 $EndPAD $PAD Sh "2" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000092" +Ne 139 "N-000145" Po -98 197 -Le 51712 $EndPAD $PAD Sh "3" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000087" +Ne 121 "N-000087" Po 98 197 -Le 64370 $EndPAD $PAD Sh "8" R 197 197 0 0 0 @@ -12061,7 +11325,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 303 "SNES_D1" Po -335 -197 -Le 53268 $EndPAD $PAD Sh "5" R 197 197 0 0 0 @@ -12069,23 +11332,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 306 "SNES_D4" Po 335 -197 -Le 65925 $EndPAD $PAD Sh "4" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "N-000083" +Ne 118 "N-000083" Po 335 197 -Le 54824 $EndPAD $PAD Sh "1" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000111" +Ne 132 "N-000108" Po -335 197 -Le 67481 $EndPAD $EndMODULE R_PACK_0804 $MODULE R_PACK_0804 @@ -12095,7 +11355,7 @@ Sc 4D97B6C8 AR /4B6E16F2/4D97B45C Op 0 0 0 T0 -600 725 320 320 0 70 N V 21 N "RA113" -T1 0 0 320 320 0 70 N V 21 N "220" +T1 0 0 320 320 0 70 N V 21 N "100" DS -551 -394 551 -394 75 21 DS 551 -394 551 394 75 21 DS 551 394 -551 394 75 21 @@ -12106,7 +11366,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 309 "SNES_D7" Po -98 -197 -Le 69452 $EndPAD $PAD Sh "6" R 118 197 0 0 0 @@ -12114,23 +11373,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 304 "SNES_D2" Po 98 -197 -Le 59915 $EndPAD $PAD Sh "2" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "N-000081" +Ne 117 "N-000082" Po -98 197 -Le 68475 $EndPAD $PAD Sh "3" R 118 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "N-000075" +Ne 115 "N-000076" Po 98 197 -Le 69452 $EndPAD $PAD Sh "8" R 197 197 0 0 0 @@ -12138,7 +11394,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 305 "SNES_D3" Po -335 -197 -Le 61753 $EndPAD $PAD Sh "5" R 197 197 0 0 0 @@ -12146,23 +11401,20 @@ Dr 0 0 0 At SMD N 00888000 Ne 308 "SNES_D6" Po 335 -197 -Le 69452 $EndPAD $PAD Sh "4" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "N-000072" +Ne 112 "N-000073" Po 335 197 -Le 75140 $EndPAD $PAD Sh "1" R 197 197 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000084" +Ne 119 "N-000084" Po -335 197 -Le 69886 $EndPAD $EndMODULE R_PACK_0804 $MODULE SM0805_FIXEDMASK @@ -12186,7 +11438,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -375 0 -Le 68981 $EndPAD $PAD Sh "2" R 350 550 0 0 1800 @@ -12194,7 +11445,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 5 "+3.3VDAC" Po 375 0 -Le 76675 $EndPAD $SHAPE3D Na "smd/chip_cms.wrl" @@ -12204,7 +11454,7 @@ Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SM0805_FIXEDMASK $MODULE GS2 -Po 44475 48900 2700 15 4DB4303C 4DB3607B ~~ +Po 44475 48900 2700 15 4EBE960C 4DB3607B ~~ Li GS2 Cd Pontet Goute de soudure Sc 4DB3607B @@ -12212,7 +11462,7 @@ AR /4B6EC9C3/4DB35D41 Op 0 0 0 At VIRTUAL T0 -1175 100 320 320 2700 70 N V 21 N "JP341" -T1 600 0 300 300 3600 50 N I 21 N "JUMPER" +T1 600 0 300 300 3600 50 N I 21 N "FB_0603" DS -350 -500 -350 500 75 21 DS 350 500 350 -500 75 21 DS 350 500 -350 500 75 21 @@ -12223,7 +11473,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 0 -250 -Le 42666976 $EndPAD $PAD Sh "2" R 500 380 0 0 2700 @@ -12231,7 +11480,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 65 "AGND" Po 0 250 -Le 42674720 $EndPAD $EndMODULE GS2 $MODULE @@ -12624,7 +11872,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 1 "+1.2V" Po -314 483 -Le 92676128 $EndPAD $PAD Sh "2" R 79 651 0 0 900 @@ -12639,7 +11886,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 0 502 -Le 42704288 $EndPAD $PAD Sh "4" R 79 651 0 0 900 @@ -12647,7 +11893,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 11 "/Power_Supply_/_Misc./REG_SW1" Po 157 502 -Le 42704640 $EndPAD $PAD Sh "5" R 79 651 0 0 900 @@ -12655,7 +11900,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 88 "GND" Po 314 502 -Le 42705168 $EndPAD $PAD Sh "6" R 79 651 0 0 900 @@ -12663,7 +11907,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po 314 -502 -Le 42705520 $EndPAD $PAD Sh "7" R 79 651 0 0 900 @@ -12671,7 +11914,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 12 "/Power_Supply_/_Misc./REG_SW2" Po 157 -502 -Le 42705872 $EndPAD $PAD Sh "8" R 79 651 0 0 900 @@ -12679,7 +11921,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po 0 -502 -Le 42706400 $EndPAD $PAD Sh "9" R 79 651 0 0 900 @@ -12687,7 +11928,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 6 "+5V" Po -157 -502 -Le 42706752 $EndPAD $PAD Sh "10" R 79 651 0 0 900 @@ -12695,7 +11935,6 @@ Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -314 -502 -Le 42707104 $EndPAD $EndMODULE QFN10-2x2_LONGPADS $MODULE SNESCART_EXT2 @@ -12778,7 +12017,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" Po -16732 -197 -Le 19 $EndPAD $PAD Sh "2" R 591 2756 0 0 1800 @@ -12786,7 +12024,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 0 "" Po -15748 -197 -Le 86 $EndPAD $PAD Sh "3" R 591 2756 0 0 1800 @@ -12794,7 +12031,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 59 "/SNES_Slot/SNES_EXT_PA6" Po -14764 -197 -Le 98 $EndPAD $PAD Sh "4" R 591 2756 0 0 1800 @@ -12802,7 +12038,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 15 "/SNES_Slot/SNES_EXT_/PARD" Po -13780 -197 -Le 353 $EndPAD $PAD Sh "5" R 787 2756 0 0 1800 @@ -12810,7 +12045,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 88 "GND" Po -10925 -197 -Le 46326 $EndPAD $PAD Sh "6" R 591 2756 0 0 1800 @@ -12818,7 +12052,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 23 "/SNES_Slot/SNES_EXT_A11" Po -9843 -197 -Le 41840 $EndPAD $PAD Sh "7" R 591 2756 0 0 1800 @@ -12826,7 +12059,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 22 "/SNES_Slot/SNES_EXT_A10" Po -8858 -197 -Le 33 $EndPAD $PAD Sh "8" R 591 2756 0 0 1800 @@ -12834,7 +12066,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 43 "/SNES_Slot/SNES_EXT_A9" Po -7874 -197 -Le 10 $EndPAD $PAD Sh "9" R 591 2756 0 0 1800 @@ -12842,7 +12073,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 42 "/SNES_Slot/SNES_EXT_A8" Po -6890 -197 -Le 40686 $EndPAD $PAD Sh "10" R 591 2756 0 0 1800 @@ -12850,7 +12080,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 41 "/SNES_Slot/SNES_EXT_A7" Po -5906 -197 -Le 32 $EndPAD $PAD Sh "11" R 591 2756 0 0 1800 @@ -12858,7 +12087,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 40 "/SNES_Slot/SNES_EXT_A6" Po -4921 -197 -Le 26720752 $EndPAD $PAD Sh "12" R 591 2756 0 0 1800 @@ -12866,7 +12094,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 39 "/SNES_Slot/SNES_EXT_A5" Po -3937 -197 -Le 44474 $EndPAD $PAD Sh "13" R 591 2756 0 0 1800 @@ -12874,7 +12101,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 38 "/SNES_Slot/SNES_EXT_A4" Po -2953 -197 -Le 41300 $EndPAD $PAD Sh "14" R 591 2756 0 0 1800 @@ -12882,7 +12108,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 37 "/SNES_Slot/SNES_EXT_A3" Po -1969 -197 -Le 26690192 $EndPAD $PAD Sh "15" R 591 2756 0 0 1800 @@ -12890,7 +12115,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 32 "/SNES_Slot/SNES_EXT_A2" Po -984 -197 -Le 778140282 $EndPAD $PAD Sh "16" R 591 2756 0 0 1800 @@ -12898,7 +12122,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 21 "/SNES_Slot/SNES_EXT_A1" Po 0 -197 -Le 45976 $EndPAD $PAD Sh "17" R 591 2756 0 0 1800 @@ -12906,7 +12129,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 20 "/SNES_Slot/SNES_EXT_A0" Po 984 -197 -Le 26692384 $EndPAD $PAD Sh "18" R 591 2756 0 0 1800 @@ -12914,7 +12136,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 14 "/SNES_Slot/SNES_EXT_/IRQ" Po 1969 -197 -Le 33 $EndPAD $PAD Sh "19" R 591 2756 0 0 1800 @@ -12922,7 +12143,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 45 "/SNES_Slot/SNES_EXT_D0" Po 2953 -197 -Le 101 $EndPAD $PAD Sh "20" R 591 2756 0 0 1800 @@ -12930,7 +12150,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 46 "/SNES_Slot/SNES_EXT_D1" Po 3937 -197 -Le 72 $EndPAD $PAD Sh "21" R 591 2756 0 0 1800 @@ -12938,7 +12157,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 47 "/SNES_Slot/SNES_EXT_D2" Po 4921 -197 -Le 1362898584 $EndPAD $PAD Sh "22" R 591 2756 0 0 1800 @@ -12946,7 +12164,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 48 "/SNES_Slot/SNES_EXT_D3" Po 5906 -197 -Le 193 $EndPAD $PAD Sh "23" R 591 2756 0 0 1800 @@ -12954,7 +12171,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 17 "/SNES_Slot/SNES_EXT_/RD" Po 6890 -197 -Le 1 $EndPAD $PAD Sh "24" R 591 2756 0 0 1800 @@ -12962,7 +12178,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 84 "EXT_CIC_DATA1" Po 7874 -197 -Le -268371600 $EndPAD $PAD Sh "25" R 591 2756 0 0 1800 @@ -12970,7 +12185,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 73 "CIC_RESET" Po 8858 -197 -Le 44216 $EndPAD $PAD Sh "26" R 591 2756 0 0 1800 @@ -12978,7 +12192,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 274 "SNES_/RESET" Po 9843 -197 -Le 26710224 $EndPAD $PAD Sh "27" R 787 2756 0 0 1800 @@ -12986,7 +12199,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 7 "+5VL" Po 10925 -197 -Le -268358496 $EndPAD $PAD Sh "28" R 591 2756 0 0 1800 @@ -12994,7 +12206,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 53 "/SNES_Slot/SNES_EXT_PA0" Po 13780 -197 -Le 40657 $EndPAD $PAD Sh "29" R 591 2756 0 0 1800 @@ -13002,7 +12213,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 55 "/SNES_Slot/SNES_EXT_PA2" Po 14764 -197 -Le 42 $EndPAD $PAD Sh "30" R 591 2756 0 0 1800 @@ -13010,7 +12220,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 57 "/SNES_Slot/SNES_EXT_PA4" Po 15748 -197 -Le 27776368 $EndPAD $PAD Sh "31" R 591 2756 0 0 1800 @@ -13018,7 +12227,6 @@ Dr 0 0 0 At CONN N 00000001 Ne 66 "AUDIO_L" Po 16732 -197 -Le 1376453976 $EndPAD $PAD Sh "32" R 591 2756 0 0 1800 @@ -13026,7 +12234,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 0 "" Po -16732 -197 -Le -65794 $EndPAD $PAD Sh "33" R 591 2756 0 0 1800 @@ -13034,7 +12241,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 61 "/SNES_Slot/SNES_EXT_REFRESH" Po -15748 -197 -Le -197380 $EndPAD $PAD Sh "34" R 591 2756 0 0 1800 @@ -13042,7 +12248,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 60 "/SNES_Slot/SNES_EXT_PA7" Po -14764 -197 -Le 26706208 $EndPAD $PAD Sh "35" R 591 2756 0 0 1800 @@ -13050,7 +12255,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 16 "/SNES_Slot/SNES_EXT_/PAWR" Po -13780 -197 -Le 48 $EndPAD $PAD Sh "36" R 787 2756 0 0 1800 @@ -13058,7 +12262,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 88 "GND" Po -10925 -197 -Le 26698352 $EndPAD $PAD Sh "37" R 591 2756 0 0 1800 @@ -13066,7 +12269,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 24 "/SNES_Slot/SNES_EXT_A12" Po -9843 -197 -Le 26703872 $EndPAD $PAD Sh "38" R 591 2756 0 0 1800 @@ -13074,7 +12276,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 25 "/SNES_Slot/SNES_EXT_A13" Po -8858 -197 -Le 2513 $EndPAD $PAD Sh "39" R 591 2756 0 0 1800 @@ -13082,7 +12283,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 26 "/SNES_Slot/SNES_EXT_A14" Po -7874 -197 -Le 48 $EndPAD $PAD Sh "40" R 591 2756 0 0 1800 @@ -13090,7 +12290,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 27 "/SNES_Slot/SNES_EXT_A15" Po -6890 -197 -Le 14164224 $EndPAD $PAD Sh "41" R 591 2756 0 0 1800 @@ -13098,7 +12297,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 28 "/SNES_Slot/SNES_EXT_A16" Po -5906 -197 -Le 14319616 $EndPAD $PAD Sh "42" R 591 2756 0 0 1800 @@ -13106,7 +12304,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 29 "/SNES_Slot/SNES_EXT_A17" Po -4921 -197 -Le 14154752 $EndPAD $PAD Sh "43" R 591 2756 0 0 1800 @@ -13114,7 +12311,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 30 "/SNES_Slot/SNES_EXT_A18" Po -3937 -197 -Le 192512 $EndPAD $PAD Sh "44" R 591 2756 0 0 1800 @@ -13122,7 +12318,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 31 "/SNES_Slot/SNES_EXT_A19" Po -2953 -197 -Le 39524 $EndPAD $PAD Sh "45" R 591 2756 0 0 1800 @@ -13130,7 +12325,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 33 "/SNES_Slot/SNES_EXT_A20" Po -1969 -197 -Le 1077956333 $EndPAD $PAD Sh "46" R 591 2756 0 0 1800 @@ -13138,7 +12332,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 34 "/SNES_Slot/SNES_EXT_A21" Po -984 -197 -Le 39959 $EndPAD $PAD Sh "47" R 591 2756 0 0 1800 @@ -13146,7 +12339,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 35 "/SNES_Slot/SNES_EXT_A22" Po 0 -197 -Le 1077938791 $EndPAD $PAD Sh "48" R 591 2756 0 0 1800 @@ -13154,7 +12346,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 36 "/SNES_Slot/SNES_EXT_A23" Po 984 -197 -Le 40274 $EndPAD $PAD Sh "49" R 591 2756 0 0 1800 @@ -13162,7 +12353,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 18 "/SNES_Slot/SNES_EXT_/ROMSEL" Po 1969 -197 -Le 40357 $EndPAD $PAD Sh "50" R 591 2756 0 0 1800 @@ -13170,7 +12360,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 49 "/SNES_Slot/SNES_EXT_D4" Po 2953 -197 -Le 40449 $EndPAD $PAD Sh "51" R 591 2756 0 0 1800 @@ -13178,7 +12367,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 50 "/SNES_Slot/SNES_EXT_D5" Po 3937 -197 -Le 1077956333 $EndPAD $PAD Sh "52" R 591 2756 0 0 1800 @@ -13186,7 +12374,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 51 "/SNES_Slot/SNES_EXT_D6" Po 4921 -197 -Le 23484672 $EndPAD $PAD Sh "53" R 591 2756 0 0 1800 @@ -13194,7 +12381,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 52 "/SNES_Slot/SNES_EXT_D7" Po 5906 -197 -Le 23484672 $EndPAD $PAD Sh "54" R 591 2756 0 0 1800 @@ -13202,7 +12388,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 19 "/SNES_Slot/SNES_EXT_/WR" Po 6890 -197 -Le 23484672 $EndPAD $PAD Sh "55" R 591 2756 0 0 1800 @@ -13210,7 +12395,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 83 "EXT_CIC_DATA0" Po 7874 -197 -Le 23484672 $EndPAD $PAD Sh "56" R 591 2756 0 0 1800 @@ -13218,7 +12402,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 69 "CIC_CLK" Po 8858 -197 -Le 23484672 $EndPAD $PAD Sh "57" R 591 2756 0 0 1800 @@ -13226,7 +12409,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 44 "/SNES_Slot/SNES_EXT_CPU_CLK" Po 9843 -197 -Le 23484672 $EndPAD $PAD Sh "58" R 787 2756 0 0 1800 @@ -13234,7 +12416,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 7 "+5VL" Po 10925 -197 -Le 23484672 $EndPAD $PAD Sh "59" R 591 2756 0 0 1800 @@ -13242,7 +12423,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 54 "/SNES_Slot/SNES_EXT_PA1" Po 13780 -197 -Le 23484672 $EndPAD $PAD Sh "60" R 591 2756 0 0 1800 @@ -13250,7 +12430,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 56 "/SNES_Slot/SNES_EXT_PA3" Po 14764 -197 -Le 23484672 $EndPAD $PAD Sh "61" R 591 2756 0 0 1800 @@ -13258,7 +12437,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 58 "/SNES_Slot/SNES_EXT_PA5" Po 15748 -197 -Le 1077941145 $EndPAD $PAD Sh "62" R 591 2756 0 0 1800 @@ -13266,7 +12444,6 @@ Dr 0 0 0 At CONN N 00008000 Ne 67 "AUDIO_R" Po 16732 -197 -Le 23484672 $EndPAD $PAD Sh "" R 4921 3150 0 0 1800 @@ -13274,7 +12451,6 @@ Dr 0 0 0 At CONN N 00C00000 Ne 0 "" Po -15256 -394 -Le 23484672 $EndPAD $PAD Sh "" R 4921 3150 0 0 1800 @@ -13282,7 +12458,6 @@ Dr 0 0 0 At CONN N 00C00000 Ne 0 "" Po 15256 -394 -Le 23484672 $EndPAD $PAD Sh "" R 23622 3150 0 0 1800 @@ -13290,7 +12465,6 @@ Dr 0 0 0 At CONN N 00C00000 Ne 0 "" Po 0 -394 -Le 23484672 $EndPAD $PAD Sh "" R 2362 1969 0 0 1800 @@ -13298,7 +12472,6 @@ Dr 0 0 0 At CONN N 00800000 Ne 0 "" Po -10945 3819 -Le 23484672 $EndPAD $PAD Sh "" R 2283 2362 0 0 1800 @@ -13306,43 +12479,42 @@ Dr 0 0 0 At CONN N 00800000 Ne 0 "" Po 14331 3780 -Le 23484672 $EndPAD $EndMODULE SNESCART_EXT2 $TEXTPCB Te "USE_BATT" Po 46575 27525 320 320 80 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "GPIO" Po 42775 26225 320 320 70 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "6" Po 47559 24409 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "5" Po 47559 26575 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "2" Po 45472 24409 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "1" Po 45472 26575 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P404" Po 46496 23780 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $DRAWSEGMENT Po 0 45728 25452 47263 25452 60 @@ -13375,37 +12547,37 @@ $EndDRAWSEGMENT $TEXTPCB Te "P1.10" Po 47027 24743 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P1.9" Po 47027 26161 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P1.8" Po 46515 24862 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P1.4" Po 46515 26161 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P1.1" Po 46003 24862 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "P1.0" Po 46003 26161 300 300 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "1" Po 39610 26260 394 394 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $DRAWSEGMENT Po 3 67425 28050 67475 28100 70 @@ -13446,22 +12618,22 @@ $EndDRAWSEGMENT $TEXTPCB Te "S/N" Po 45610 42460 700 700 100 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "CR2032" Po 39975 40350 320 320 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "SD Card" Po 58700 33750 320 320 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "USB" Po 46775 23625 320 320 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $DRAWSEGMENT Po 3 71275 43150 71375 43175 59 @@ -13470,32 +12642,32 @@ $EndDRAWSEGMENT $TEXTPCB Te "Write" Po 69575 25850 500 500 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "1" Po 40433 35984 394 394 60 900 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "14" Po 49370 41024 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "13" Po 53110 41024 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "2" Po 49488 43898 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "1" Po 52992 43898 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $DRAWSEGMENT Po 0 52795 41260 49685 41260 59 @@ -13544,127 +12716,127 @@ $EndDRAWSEGMENT $TEXTPCB Te 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-De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "TCK" Po 50669 42480 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "TMS" Po 50669 42007 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "TDO" Po 50669 41535 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "TX0" Po 50669 41062 300 300 60 0 -De 21 1 0 Normal +De 21 1 0 Normal C $EndTEXTPCB $TEXTPCB Te "Reset" Po 37700 37825 440 440 75 900 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "Freeze" Po 37700 40000 440 440 75 900 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "SD2SNES Mk.II" Po 45815 24905 700 700 120 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "©2009 - 2011 M. Rehkopf" Po 44000 27540 500 500 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "Rev.E / 2011-07-25" Po 44720 26500 500 500 75 0 -De 20 0 0 Normal +De 20 0 0 Normal C $EndTEXTPCB $TEXTPCB Te "!! This side to BACK of SNES !!" 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0 +Po 0 56116 44565 56116 43909 80 -1 +De 15 0 118 0 400800 +Po 0 56285 43740 56285 43122 80 -1 +De 15 0 118 0 800400 +Po 0 56116 43909 56285 43740 80 -1 +De 15 0 118 0 0 +Po 0 54148 44565 54148 44052 80 -1 +De 15 0 119 0 400800 +Po 0 54515 43685 54515 43122 80 -1 +De 15 0 119 0 800400 +Po 0 54148 44052 54515 43685 80 -1 +De 15 0 119 0 0 +Po 0 54885 48878 54885 48615 80 -1 +De 15 0 120 0 400800 +Po 0 54935 48565 54885 48615 80 -1 +De 15 0 120 0 0 +Po 0 54935 48565 54935 47635 80 -1 +De 15 0 120 0 800400 +Po 0 55920 44565 55920 43830 80 -1 +De 15 0 121 0 400800 +Po 0 56048 43702 56048 43122 80 -1 +De 15 0 121 0 800400 +Po 0 55920 43830 56048 43702 80 -1 +De 15 0 121 0 0 +Po 0 55365 48878 55365 48615 80 -1 +De 15 0 122 0 400800 +Po 0 55329 48579 55365 48615 80 -1 +De 15 0 122 0 0 +Po 0 55329 48579 55329 47635 80 -1 +De 15 0 122 0 800400 +Po 0 51647 48352 51823 48352 80 -1 +De 15 0 123 0 400800 +Po 0 51823 48352 52180 47995 80 -1 +De 15 0 123 0 0 +Po 0 52180 47995 52180 47635 80 -1 De 15 0 123 0 800400 Po 0 60890 48878 60890 48340 80 -1 De 15 0 124 0 400800 @@ -19911,112 +19083,112 @@ Po 0 51984 47916 51984 47635 80 -1 De 15 0 126 0 800400 Po 0 51785 48115 51850 48050 80 -1 De 15 0 126 0 0 -Po 0 51647 48352 51823 48352 80 -1 -De 15 0 127 0 400800 -Po 0 51823 48352 52180 47995 80 -1 -De 15 0 127 0 0 -Po 0 52180 47995 52180 47635 80 -1 -De 15 0 127 0 800400 Po 0 51647 48548 51978 48548 80 -1 -De 15 0 128 0 400800 +De 15 0 127 0 400800 Po 0 51978 48548 52574 47952 80 -1 -De 15 0 128 0 0 +De 15 0 127 0 0 Po 0 52574 47952 52574 47635 80 -1 -De 15 0 128 0 800400 +De 15 0 127 0 800400 Po 0 51647 48785 52015 48785 80 -1 -De 15 0 129 0 400800 +De 15 0 128 0 400800 Po 0 52015 48785 52771 48029 80 -1 -De 15 0 129 0 0 +De 15 0 128 0 0 Po 0 52771 48029 52771 47635 80 -1 -De 15 0 129 0 800400 +De 15 0 128 0 800400 Po 0 53115 48878 53115 48685 80 -1 -De 15 0 130 0 400800 +De 15 0 129 0 400800 Po 0 53165 48635 53115 48685 80 -1 -De 15 0 130 0 0 +De 15 0 129 0 0 Po 0 53165 48635 53165 47635 80 -1 -De 15 0 130 0 800400 +De 15 0 129 0 800400 Po 0 53352 48878 53352 47645 80 -1 -De 15 0 131 0 400800 +De 15 0 130 0 400800 Po 0 53352 47645 53362 47635 80 -1 -De 15 0 131 0 800400 +De 15 0 130 0 800400 Po 0 55602 48878 55602 48552 80 -1 -De 15 0 132 0 400800 +De 15 0 131 0 400800 Po 0 55526 48476 55602 48552 80 -1 -De 15 0 132 0 0 +De 15 0 131 0 0 Po 0 55526 48476 55526 47635 80 -1 -De 15 0 132 0 800400 +De 15 0 131 0 800400 Po 0 55329 44565 55329 43896 80 -1 -De 15 0 133 0 400800 +De 15 0 132 0 400800 Po 0 55615 43610 55615 43122 80 -1 -De 15 0 133 0 800400 +De 15 0 132 0 800400 Po 0 55329 43896 55615 43610 80 -1 +De 15 0 132 0 0 +Po 0 62973 48878 62973 47727 80 -1 +De 15 0 133 0 400800 +Po 0 62973 47727 63680 47020 80 -1 De 15 0 133 0 0 +Po 0 63680 47020 63680 46385 80 -1 +De 15 0 133 0 800400 Po 0 62777 48878 62777 47648 80 -1 De 15 0 134 0 400800 Po 0 62777 47648 63484 46941 80 -1 De 15 0 134 0 0 Po 0 63484 46941 63484 46385 80 -1 De 15 0 134 0 800400 -Po 0 62973 48878 62973 47727 80 -1 -De 15 0 135 0 400800 -Po 0 62973 47727 63680 47020 80 -1 -De 15 0 135 0 0 -Po 0 63680 47020 63680 46385 80 -1 -De 15 0 135 0 800400 Po 0 63210 48878 63210 47815 80 -1 -De 15 0 136 0 400800 +De 15 0 135 0 400800 Po 0 63210 47815 64074 46951 80 -1 -De 15 0 136 0 0 +De 15 0 135 0 0 Po 0 64074 46951 64074 46385 80 -1 -De 15 0 136 0 800400 +De 15 0 135 0 800400 Po 0 63715 48878 63715 47660 80 -1 -De 15 0 137 0 400800 +De 15 0 136 0 400800 Po 0 63715 47660 64271 47104 80 -1 -De 15 0 137 0 0 +De 15 0 136 0 0 Po 0 64271 47104 64271 46385 80 -1 -De 15 0 137 0 800400 +De 15 0 136 0 800400 Po 0 57498 48878 57498 48477 80 -1 -De 15 0 138 0 400800 +De 15 0 137 0 400800 Po 0 57980 47995 57498 48477 80 -1 -De 15 0 138 0 0 +De 15 0 137 0 0 Po 0 57980 47995 57980 47635 80 -1 -De 15 0 138 0 800400 +De 15 0 137 0 800400 Po 0 58075 47175 57950 47050 80 -1 -De 0 0 138 0 0 +De 0 0 137 0 0 Po 3 57950 47050 57950 47050 218 -1 -De 15 1 138 0 0 +De 15 1 137 0 0 Po 0 58075 47175 58075 47400 80 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53952 47298 54100 47150 80 -1 -De 15 0 139 0 0 +De 15 0 138 0 0 Po 0 53952 47635 53952 47298 80 -1 +De 15 0 138 0 400800 +Po 0 55526 44565 55526 43949 80 -1 De 15 0 139 0 400800 +Po 0 55852 43623 55852 43122 80 -1 +De 15 0 139 0 800400 +Po 0 55526 43949 55852 43623 80 -1 +De 15 0 139 0 0 Po 0 64890 48878 64890 47635 80 -1 De 15 0 140 0 400800 Po 0 64890 47635 65452 47073 80 -1 @@ -20149,16 +19321,16 @@ Po 0 58953 41130 58953 42147 80 -1 De 15 0 152 0 400800 Po 0 58953 42147 58825 42275 80 -1 De 15 0 152 0 800400 -Po 0 49050 48200 49050 47950 80 -1 -De 15 0 153 0 400800 -Po 0 49050 47950 49050 46300 80 -1 -De 15 0 153 0 0 -Po 0 49050 46300 49550 45800 80 -1 -De 15 0 153 0 0 -Po 0 49550 45800 49550 44575 80 -1 -De 15 0 153 0 800400 Po 0 54100 48475 53500 48475 320 -1 -De 0 0 154 0 C00C00 +De 0 0 153 0 C00C00 +Po 0 49050 48200 49050 47950 80 -1 +De 15 0 154 0 400800 +Po 0 49050 47950 49050 46300 80 -1 +De 15 0 154 0 0 +Po 0 49050 46300 49550 45800 80 -1 +De 15 0 154 0 0 +Po 0 49550 45800 49550 44575 80 -1 +De 15 0 154 0 800400 Po 0 41443 42385 41443 43343 80 -1 De 15 0 155 0 400800 Po 0 41575 43475 41575 43825 80 -1 @@ -20189,64 +19361,64 @@ Po 0 42325 44525 42325 45225 80 -1 De 15 0 160 0 C00C00 Po 0 42325 43825 42325 44525 80 -1 De 15 0 160 0 C00C00 -Po 0 53448 24903 53448 26402 80 -1 -De 0 0 161 0 400800 -Po 0 49354 29946 49354 30545 80 -1 -De 15 0 161 0 800400 -Po 0 49675 29625 49354 29946 80 -1 -De 15 0 161 0 0 -Po 0 50225 29625 49675 29625 80 -1 -De 15 0 161 0 0 -Po 3 50225 29625 50225 29625 218 -1 -De 15 1 161 0 0 -Po 0 53448 26402 50225 29625 80 -1 -De 0 0 161 0 0 Po 0 64775 22025 64750 22000 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 54100 28575 54500 28175 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 51875 28775 53900 28775 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 53900 28775 54100 28575 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 50830 32612 51312 32612 80 -1 -De 15 0 162 0 400800 +De 15 0 161 0 400800 Po 0 51575 32375 51575 29075 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 51325 32625 51575 32375 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 3 51325 32625 51325 32625 218 -1 -De 15 1 162 0 0 +De 15 1 161 0 0 Po 0 51312 32612 51325 32625 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 51575 29075 51875 28775 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 54825 22000 64300 22000 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 54500 22325 54825 22000 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 54500 28175 54500 22325 80 -1 -De 0 0 162 0 0 +De 0 0 161 0 0 Po 0 74901 25800 74525 25800 80 -1 -De 15 0 162 0 800400 +De 15 0 161 0 800400 Po 0 75075 25626 74901 25800 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 75075 23475 75075 25626 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 74975 23375 75075 23475 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 65425 23375 74975 23375 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 65300 23250 65425 23375 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 65300 22550 65300 23250 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 0 64775 22025 65300 22550 80 -1 -De 15 0 162 0 0 +De 15 0 161 0 0 Po 3 64300 22000 64300 22000 218 -1 -De 15 1 162 0 0 +De 15 1 161 0 0 Po 0 64750 22000 64300 22000 80 -1 +De 15 0 161 0 0 +Po 0 53448 24903 53448 26402 80 -1 +De 0 0 162 0 400800 +Po 0 49354 29946 49354 30545 80 -1 +De 15 0 162 0 800400 +Po 0 49675 29625 49354 29946 80 -1 De 15 0 162 0 0 +Po 0 50225 29625 49675 29625 80 -1 +De 15 0 162 0 0 +Po 3 50225 29625 50225 29625 218 -1 +De 15 1 162 0 0 +Po 0 53448 26402 50225 29625 80 -1 +De 0 0 162 0 0 Po 0 47925 42025 47925 41850 80 -1 De 15 0 163 0 400800 Po 0 48173 41602 48173 36055 80 -1 @@ -20479,79 +19651,79 @@ Po 0 51350 29700 50850 29700 80 -1 De 15 0 175 0 400000 Po 0 48370 29880 48370 30545 80 -1 De 15 0 175 0 800000 -Po 0 45860 34780 45860 31565 80 -1 -De 0 0 176 0 0 -Po 0 45856 34776 45860 34780 80 -1 -De 15 0 176 0 0 -Po 3 45860 34780 45860 34780 218 -1 -De 15 1 176 0 0 -Po 0 45320 34776 45856 34776 80 -1 -De 15 0 176 0 400800 -Po 0 49814 24336 49425 24725 80 -1 -De 0 0 176 0 0 -Po 0 49425 24725 49425 28000 80 -1 -De 0 0 176 0 0 -Po 0 49425 28000 45860 31565 80 -1 -De 0 0 176 0 0 -Po 0 49814 24336 49820 24336 80 -1 -De 0 0 176 0 800400 Po 0 49945 36055 49945 38870 80 -1 -De 15 0 177 0 400800 +De 15 0 176 0 400800 Po 0 49945 38870 50000 38925 80 -1 -De 15 0 177 0 800400 -Po 0 43550 35177 42798 35177 80 -1 -De 15 0 178 0 400800 -Po 0 45320 34185 44542 34185 80 -1 -De 15 0 178 0 400800 -Po 0 44542 34185 43550 35177 80 -1 -De 15 0 178 0 800400 -Po 0 42798 35177 42550 35425 80 -1 -De 15 0 178 0 800400 -Po 0 41502 36900 41502 37577 160 -1 -De 15 0 179 0 400800 -Po 0 41677 37752 42200 38275 160 -1 -De 15 0 179 0 800400 -Po 0 41502 37577 41677 37752 160 -1 -De 15 0 179 0 0 -Po 0 44475 35598 44475 35700 160 -1 -De 15 0 179 0 0 -Po 0 44752 34973 44475 35250 160 -1 -De 15 0 179 0 0 -Po 0 44475 35250 44475 35598 160 -1 -De 15 0 179 0 0 -Po 0 45320 34973 44752 34973 80 -1 -De 15 0 179 0 400800 -Po 0 42475 36900 41502 36900 160 -1 -De 15 0 179 0 800400 -Po 0 43375 36000 42475 36900 160 -1 -De 15 0 179 0 0 -Po 0 44175 36000 43375 36000 160 -1 -De 15 0 179 0 0 -Po 0 44475 35700 44175 36000 160 -1 -De 15 0 179 0 0 -Po 0 45023 37752 45023 37075 160 -1 -De 15 0 180 0 0 -Po 0 44500 38275 45023 37752 160 -1 -De 15 0 180 0 400800 -Po 0 45023 37075 44848 36900 160 -1 -De 15 0 180 0 800400 -Po 0 44725 35350 44725 36777 160 -1 -De 15 0 180 0 0 -Po 0 44905 35170 44725 35350 160 -1 -De 15 0 180 0 0 -Po 0 45320 35170 44905 35170 80 -1 -De 15 0 180 0 400800 -Po 0 44725 36777 44848 36900 160 -1 -De 15 0 180 0 800400 +De 15 0 176 0 800400 +Po 0 45860 34780 45860 31565 80 -1 +De 0 0 177 0 0 +Po 0 45856 34776 45860 34780 80 -1 +De 15 0 177 0 0 +Po 3 45860 34780 45860 34780 218 -1 +De 15 1 177 0 0 +Po 0 45320 34776 45856 34776 80 -1 +De 15 0 177 0 400800 +Po 0 49814 24336 49425 24725 80 -1 +De 0 0 177 0 0 +Po 0 49425 24725 49425 28000 80 -1 +De 0 0 177 0 0 +Po 0 49425 28000 45860 31565 80 -1 +De 0 0 177 0 0 +Po 0 49814 24336 49820 24336 80 -1 +De 0 0 177 0 800400 Po 0 43550 33523 42798 33523 80 -1 -De 15 0 181 0 400800 +De 15 0 178 0 400800 Po 0 45320 33792 44542 33792 80 -1 -De 15 0 181 0 400800 +De 15 0 178 0 400800 Po 0 44542 33792 44273 33523 80 -1 -De 15 0 181 0 0 +De 15 0 178 0 0 Po 0 44273 33523 43550 33523 80 -1 -De 15 0 181 0 800400 +De 15 0 178 0 800400 Po 0 42798 33523 42550 33275 80 -1 +De 15 0 178 0 800400 +Po 0 43550 35177 42798 35177 80 -1 +De 15 0 179 0 400800 +Po 0 45320 34185 44542 34185 80 -1 +De 15 0 179 0 400800 +Po 0 44542 34185 43550 35177 80 -1 +De 15 0 179 0 800400 +Po 0 42798 35177 42550 35425 80 -1 +De 15 0 179 0 800400 +Po 0 41502 36900 41502 37577 160 -1 +De 15 0 180 0 400800 +Po 0 41677 37752 42200 38275 160 -1 +De 15 0 180 0 800400 +Po 0 41502 37577 41677 37752 160 -1 +De 15 0 180 0 0 +Po 0 44475 35598 44475 35700 160 -1 +De 15 0 180 0 0 +Po 0 44752 34973 44475 35250 160 -1 +De 15 0 180 0 0 +Po 0 44475 35250 44475 35598 160 -1 +De 15 0 180 0 0 +Po 0 45320 34973 44752 34973 80 -1 +De 15 0 180 0 400800 +Po 0 42475 36900 41502 36900 160 -1 +De 15 0 180 0 800400 +Po 0 43375 36000 42475 36900 160 -1 +De 15 0 180 0 0 +Po 0 44175 36000 43375 36000 160 -1 +De 15 0 180 0 0 +Po 0 44475 35700 44175 36000 160 -1 +De 15 0 180 0 0 +Po 0 45023 37752 45023 37075 160 -1 +De 15 0 181 0 0 +Po 0 44500 38275 45023 37752 160 -1 +De 15 0 181 0 400800 +Po 0 45023 37075 44848 36900 160 -1 +De 15 0 181 0 800400 +Po 0 44725 35350 44725 36777 160 -1 +De 15 0 181 0 0 +Po 0 44905 35170 44725 35350 160 -1 +De 15 0 181 0 0 +Po 0 45320 35170 44905 35170 80 -1 +De 15 0 181 0 400800 +Po 0 44725 36777 44848 36900 160 -1 De 15 0 181 0 800400 Po 0 54975 26250 54750 26250 80 -1 De 15 0 182 0 400800 diff --git a/pcb/kicad/RevE/sd2snes.net b/pcb/kicad/RevE/sd2snes.net index 255f7f7..4505e7b 100644 --- a/pcb/kicad/RevE/sd2snes.net +++ b/pcb/kicad/RevE/sd2snes.net @@ -1,8 +1,8 @@ -# EESchema Netlist Version 1.1 created Sun 24 Jul 2011 03:04:56 PM CEST +# EESchema Netlist Version 1.1 created Fri 02 Dec 2011 09:50:17 AM CET ( - ( /4B6E16F2/4D97B45F $noname RA114 220 {Lib=R_PACK4} - ( 1 N-000111 ) - ( 2 N-000092 ) + ( /4B6E16F2/4D97B45F $noname RA114 100 {Lib=R_PACK4} + ( 1 N-000108 ) + ( 2 N-000145 ) ( 3 N-000087 ) ( 4 N-000083 ) ( 5 SNES_D4 ) @@ -10,37 +10,37 @@ ( 7 SNES_D5 ) ( 8 SNES_D1 ) ) - ( /4B6E16F2/4D97B45C $noname RA113 220 {Lib=R_PACK4} + ( /4B6E16F2/4D97B45C $noname RA113 100 {Lib=R_PACK4} ( 1 N-000084 ) - ( 2 N-000081 ) - ( 3 N-000075 ) - ( 4 N-000072 ) + ( 2 N-000082 ) + ( 3 N-000076 ) + ( 4 N-000073 ) ( 5 SNES_D6 ) ( 6 SNES_D2 ) ( 7 SNES_D7 ) ( 8 SNES_D3 ) ) - ( /4B6E16F2/4D963119 $noname RA108 220 {Lib=R_PACK4} + ( /4B6E16F2/4D963119 $noname RA108 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A4 ) ( 2 /SNES_Slot/SNES_EXT_A18 ) ( 3 /SNES_Slot/SNES_EXT_A5 ) ( 4 /SNES_Slot/SNES_EXT_A17 ) - ( 5 N-000048 ) + ( 5 N-000037 ) ( 6 N-000042 ) - ( 7 N-000102 ) - ( 8 N-000097 ) + ( 7 N-000100 ) + ( 8 N-000095 ) ) - ( /4B6E16F2/4D963117 $noname RA107 220 {Lib=R_PACK4} + ( /4B6E16F2/4D963117 $noname RA107 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A2 ) ( 2 /SNES_Slot/SNES_EXT_A20 ) ( 3 /SNES_Slot/SNES_EXT_A3 ) ( 4 /SNES_Slot/SNES_EXT_A19 ) - ( 5 N-000093 ) - ( 6 N-000054 ) - ( 7 N-000050 ) + ( 5 N-000056 ) + ( 6 N-000053 ) + ( 7 N-000049 ) ( 8 N-000047 ) ) - ( /4B6E16F2/4D963115 $noname RA106 220 {Lib=R_PACK4} + ( /4B6E16F2/4D963115 $noname RA106 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A0 ) ( 2 /SNES_Slot/SNES_EXT_A22 ) ( 3 /SNES_Slot/SNES_EXT_A1 ) @@ -50,102 +50,102 @@ ( 7 N-000040 ) ( 8 N-000039 ) ) - ( /4B6E16F2/4D96310E $noname RA105 220 {Lib=R_PACK4} + ( /4B6E16F2/4D96310E $noname RA105 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_/IRQ ) ( 2 /SNES_Slot/SNES_EXT_/RD ) ( 3 /SNES_Slot/SNES_EXT_/ROMSEL ) ( 4 /SNES_Slot/SNES_EXT_A23 ) ( 5 N-000038 ) - ( 6 N-000146 ) + ( 6 N-000143 ) ( 7 N-000012 ) - ( 8 N-000149 ) + ( 8 N-000147 ) ) - ( /4B6E16F2/4D96310C $noname RA112 220 {Lib=R_PACK4} - ( 1 N-000153 ) - ( 2 N-000154 ) - ( 3 N-000155 ) - ( 4 N-000156 ) + ( /4B6E16F2/4D96310C $noname RA112 100 {Lib=R_PACK4} + ( 1 N-000151 ) + ( 2 N-000152 ) + ( 3 N-000153 ) + ( 4 N-000154 ) ( 5 /SNES_Slot/SNES_EXT_REFRESH ) ( 6 /SNES_Slot/SNES_EXT_PA7 ) ( 7 /SNES_Slot/SNES_EXT_PA6 ) ( 8 /SNES_Slot/SNES_EXT_/PAWR ) ) - ( /4B6E16F2/4D96310A $noname RA111 220 {Lib=R_PACK4} + ( /4B6E16F2/4D96310A $noname RA111 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A10 ) ( 2 /SNES_Slot/SNES_EXT_A12 ) ( 3 /SNES_Slot/SNES_EXT_A11 ) ( 4 /SNES_Slot/SNES_EXT_/PARD ) - ( 5 N-000157 ) - ( 6 N-000158 ) - ( 7 N-000159 ) - ( 8 N-000148 ) + ( 5 N-000156 ) + ( 6 N-000157 ) + ( 7 N-000158 ) + ( 8 N-000146 ) ) - ( /4B6E16F2/4D963107 $noname RA110 220 {Lib=R_PACK4} + ( /4B6E16F2/4D963107 $noname RA110 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A8 ) ( 2 /SNES_Slot/SNES_EXT_A14 ) ( 3 /SNES_Slot/SNES_EXT_A9 ) ( 4 /SNES_Slot/SNES_EXT_A13 ) - ( 5 N-000160 ) - ( 6 N-000161 ) - ( 7 N-000162 ) - ( 8 N-000128 ) + ( 5 N-000159 ) + ( 6 N-000160 ) + ( 7 N-000161 ) + ( 8 N-000137 ) ) - ( /4B6E16F2/4D963103 $noname RA109 220 {Lib=R_PACK4} + ( /4B6E16F2/4D963103 $noname RA109 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_A6 ) ( 2 /SNES_Slot/SNES_EXT_A16 ) ( 3 /SNES_Slot/SNES_EXT_A7 ) ( 4 /SNES_Slot/SNES_EXT_A15 ) ( 5 N-000127 ) - ( 6 N-000126 ) + ( 6 N-000120 ) ( 7 N-000125 ) - ( 8 N-000051 ) + ( 8 N-000050 ) ) - ( /4B6E16F2/4D9630F4 $noname RA102 220 {Lib=R_PACK4} + ( /4B6E16F2/4D9630F4 $noname RA102 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_PA0 ) ( 2 /SNES_Slot/SNES_EXT_PA1 ) ( 3 /SNES_Slot/SNES_EXT_/WR ) ( 4 /SNES_Slot/SNES_EXT_CPU_CLK ) - ( 5 N-000147 ) + ( 5 N-000144 ) ( 6 N-000013 ) - ( 7 N-000109 ) - ( 8 N-000108 ) + ( 7 N-000106 ) + ( 8 N-000105 ) ) - ( /4B6E16F2/4D9630F0 $noname RA101 220 {Lib=R_PACK4} + ( /4B6E16F2/4D9630F0 $noname RA101 100 {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_PA4 ) ( 2 /SNES_Slot/SNES_EXT_PA5 ) ( 3 /SNES_Slot/SNES_EXT_PA2 ) ( 4 /SNES_Slot/SNES_EXT_PA3 ) - ( 5 N-000107 ) - ( 6 N-000106 ) - ( 7 N-000105 ) - ( 8 N-000104 ) + ( 5 N-000104 ) + ( 6 N-000103 ) + ( 7 N-000092 ) + ( 8 N-000102 ) ) - ( /4B6E16F2/4D95CDD4 $noname RA104 220 {Lib=R_PACK4} + ( /4B6E16F2/4D95CDD4 $noname RA104 FB {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_D1 ) ( 2 /SNES_Slot/SNES_EXT_D5 ) ( 3 /SNES_Slot/SNES_EXT_D0 ) ( 4 /SNES_Slot/SNES_EXT_D4 ) - ( 5 N-000074 ) - ( 6 N-000071 ) - ( 7 N-000110 ) + ( 5 N-000075 ) + ( 6 N-000072 ) + ( 7 N-000107 ) ( 8 N-000091 ) ) - ( /4B6E16F2/4D95CDCD $noname RA103 220 {Lib=R_PACK4} + ( /4B6E16F2/4D95CDCD $noname RA103 FB {Lib=R_PACK4} ( 1 /SNES_Slot/SNES_EXT_D3 ) ( 2 /SNES_Slot/SNES_EXT_D7 ) ( 3 /SNES_Slot/SNES_EXT_D2 ) ( 4 /SNES_Slot/SNES_EXT_D6 ) ( 5 N-000086 ) - ( 6 N-000082 ) - ( 7 N-000077 ) - ( 8 N-000073 ) + ( 6 N-000071 ) + ( 7 N-000078 ) + ( 8 N-000074 ) ) ( /4B6E16F2/4D115250 SM0805_FIXEDMASK C128 10p {Lib=C} - ( 1 N-000157 ) + ( 1 N-000156 ) ( 2 GND ) ) ( /4B6E16F2/4D11524F SM0805_FIXEDMASK C127 10p {Lib=C} - ( 1 N-000153 ) + ( 1 N-000151 ) ( 2 GND ) ) ( /4B6E16F2/4D11524E SM0805_FIXEDMASK C126 10p {Lib=C} @@ -161,29 +161,29 @@ ( 2 GND ) ) ( /4B6E16F2/4D113CAA SM0805_FIXEDMASK C123 10p {Lib=C} - ( 1 N-000149 ) + ( 1 N-000147 ) ( 2 GND ) ) ( /4B6E16F2/4D113C9C SM0805_FIXEDMASK C122 10p {Lib=C} - ( 1 N-000146 ) + ( 1 N-000143 ) ( 2 GND ) ) ( /4B6E16F2/4D113C55 SM0805_FIXEDMASK C121 10p {Lib=C} - ( 1 N-000147 ) + ( 1 N-000144 ) ( 2 GND ) ) ( /4B6E16F2/4C7EAF13 $noname R103 4k7 {Lib=R} ( 1 SNES_IRQ_EN ) - ( 2 N-000037 ) + ( 2 N-000036 ) ) ( /4B6E16F2/4C7EAEBF $noname R102 1k {Lib=R} - ( 1 N-000037 ) + ( 1 N-000036 ) ( 2 GND ) ) ( /4B6E16F2/4C7EAD01 $noname Q101 2N2222A {Lib=NPN} ( 1 GND ) - ( 2 N-000037 ) - ( 3 N-000149 ) + ( 2 N-000036 ) + ( 3 N-000147 ) ) ( /4B6E16F2/4BFB119A SM0805_FIXEDMASK C111 100n {Lib=C} ( 1 +5V ) @@ -304,26 +304,26 @@ ( /4B6E16F2/4B6E1748 TSSOP48 U103 74ALVC164245DGG {Lib=74ALVC164245} ( 1 GND ) ( 2 N-000125 ) - ( 3 N-000126 ) + ( 3 N-000120 ) ( 4 GND ) ( 5 N-000127 ) - ( 6 N-000128 ) + ( 6 N-000137 ) ( 7 +5V ) - ( 8 N-000162 ) - ( 9 N-000161 ) + ( 8 N-000161 ) + ( 9 N-000160 ) ( 10 GND ) - ( 11 N-000160 ) - ( 12 N-000148 ) - ( 13 N-000159 ) - ( 14 N-000158 ) + ( 11 N-000159 ) + ( 12 N-000146 ) + ( 13 N-000158 ) + ( 14 N-000157 ) ( 15 GND ) - ( 16 N-000157 ) - ( 17 N-000153 ) + ( 16 N-000156 ) + ( 17 N-000151 ) ( 18 +5V ) - ( 19 N-000154 ) - ( 20 N-000155 ) + ( 19 N-000152 ) + ( 20 N-000153 ) ( 21 GND ) - ( 22 N-000156 ) + ( 22 N-000154 ) ( 23 /SNES_Slot/SNES_EXT_SYS_CLK ) ( 24 GND ) ( 25 GND ) @@ -354,7 +354,7 @@ ( /4B6E16F2/4B6E1744 TSSOP48 U102 74ALVC164245DGG {Lib=74ALVC164245} ( 1 GND ) ( 2 N-000012 ) - ( 3 N-000146 ) + ( 3 N-000143 ) ( 4 GND ) ( 5 N-000038 ) ( 6 N-000039 ) @@ -364,17 +364,17 @@ ( 10 GND ) ( 11 N-000045 ) ( 12 N-000047 ) - ( 13 N-000050 ) - ( 14 N-000054 ) + ( 13 N-000049 ) + ( 14 N-000053 ) ( 15 GND ) - ( 16 N-000093 ) - ( 17 N-000097 ) + ( 16 N-000056 ) + ( 17 N-000095 ) ( 18 +5V ) - ( 19 N-000102 ) + ( 19 N-000100 ) ( 20 N-000042 ) ( 21 GND ) - ( 22 N-000048 ) - ( 23 N-000051 ) + ( 22 N-000037 ) + ( 23 N-000050 ) ( 24 GND ) ( 25 GND ) ( 26 SNES_A6 ) @@ -403,40 +403,40 @@ ) ( /4B6E16F2/4B6E1740 TSSOP48 U101 74ALVC164245DGG {Lib=74ALVC164245} ( 1 GND ) - ( 2 N-000104 ) - ( 3 N-000105 ) + ( 2 N-000102 ) + ( 3 N-000092 ) ( 4 GND ) - ( 5 N-000106 ) - ( 6 N-000107 ) + ( 5 N-000103 ) + ( 6 N-000104 ) ( 7 +5V ) - ( 8 N-000108 ) - ( 9 N-000109 ) + ( 8 N-000105 ) + ( 9 N-000106 ) ( 10 GND ) ( 11 N-000013 ) - ( 12 N-000147 ) - ( 13 N-000073 ) - ( 14 N-000077 ) + ( 12 N-000144 ) + ( 13 N-000074 ) + ( 14 N-000078 ) ( 15 GND ) - ( 16 N-000082 ) + ( 16 N-000071 ) ( 17 N-000086 ) ( 18 +5V ) ( 19 N-000091 ) - ( 20 N-000110 ) + ( 20 N-000107 ) ( 21 GND ) - ( 22 N-000071 ) - ( 23 N-000074 ) + ( 22 N-000072 ) + ( 23 N-000075 ) ( 24 DATABUS_DIR ) ( 25 DATABUS_/OE ) ( 26 N-000083 ) ( 27 N-000087 ) ( 28 GND ) - ( 29 N-000092 ) - ( 30 N-000111 ) + ( 29 N-000145 ) + ( 30 N-000108 ) ( 31 +3.3V ) - ( 32 N-000072 ) - ( 33 N-000075 ) + ( 32 N-000073 ) + ( 33 N-000076 ) ( 34 GND ) - ( 35 N-000081 ) + ( 35 N-000082 ) ( 36 N-000084 ) ( 37 SNES_CPU_CLK ) ( 38 SNES_/WR ) @@ -614,7 +614,7 @@ ( 2 N-000311 ) ) ( /4B6ED75B/4C0DA785 SM0805_FIXEDMASK R403 680 {Lib=R} - ( 1 N-000324 ) + ( 1 N-000323 ) ( 2 N-000311 ) ) ( /4B6ED75B/4C0943CA pin_array_7x2 P401 CONN_7X2 {Lib=CONN_7X2} @@ -650,20 +650,20 @@ ( 2 N-000327 ) ) ( /4B6ED75B/4BF850A9 SM0805_FIXEDMASK R406 100 {Lib=R} - ( 1 N-000325 ) + ( 1 N-000324 ) ( 2 PROG_B ) ) ( /4B6ED75B/4BF847B1 SM0805_FIXEDMASK R402 680 {Lib=R} - ( 1 N-000323 ) + ( 1 N-000322 ) ( 2 N-000305 ) ) ( /4B6ED75B/4BF847A7 SM0805_FIXEDMASK R401 680 {Lib=R} - ( 1 N-000295 ) - ( 2 N-000318 ) + ( 1 N-000294 ) + ( 2 N-000316 ) ) ( /4B6ED75B/4BF8328D LED-3MM-FIXED D401 LED_2mA_1.9V,_green {Lib=LED} ( 1 +3.3V ) - ( 2 N-000318 ) + ( 2 N-000316 ) ) ( /4B6ED75B/4BF8324A LED-3MM-FIXED D402 LED_2mA_1.8V,_yellow {Lib=LED} ( 1 +3.3V ) @@ -690,7 +690,7 @@ ( 2 GND ) ) ( /4B6ED75B/4BF00175 USB-MINIB-THT J421 Molex_54819 {Lib=USB_MINIB} - ( 1 N-000326 ) + ( 1 N-000328 ) ( 2 N-000310 ) ( 3 N-000315 ) ( 5 GND ) @@ -711,34 +711,34 @@ ( 7 SD_DAT0 ) ( 8 SD_DAT1 ) ( 9 SD_DAT2 ) - ( DT N-000319 ) + ( DT N-000318 ) ( GND1 GND ) ( GND2 GND ) - ( WP N-000294 ) + ( WP N-000295 ) ) - ( /4B6ED75B/4BEECBD1 SM0805_FIXEDMASK C409 22p {Lib=C} + ( /4B6ED75B/4BEECBD1 SM0805_FIXEDMASK C409 10p {Lib=C} + ( 1 N-000338 ) + ( 2 GND ) + ) + ( /4B6ED75B/4BEECBCD SM0805_FIXEDMASK C408 10p {Lib=C} ( 1 N-000337 ) ( 2 GND ) ) - ( /4B6ED75B/4BEECBCD SM0805_FIXEDMASK C408 22p {Lib=C} - ( 1 N-000340 ) - ( 2 GND ) - ) ( /4B6ED75B/4BEECBCA SM0805_FIXEDMASK C407 33p {Lib=C} - ( 1 N-000339 ) + ( 1 N-000340 ) ( 2 GND ) ) ( /4B6ED75B/4BEECBC1 SM0805_FIXEDMASK C406 33p {Lib=C} - ( 1 N-000338 ) + ( 1 N-000339 ) ( 2 GND ) ) ( /4B6ED75B/4BC243CB XTAL_SMD_05019 X402 32.768kHz {Lib=CRYSTAL} - ( 1 N-000340 ) - ( 2 N-000337 ) + ( 1 N-000337 ) + ( 2 N-000338 ) ) ( /4B6ED75B/4BC243C8 XTAL_SMD_05032 X401 12MHz {Lib=CRYSTAL} - ( 1 N-000338 ) - ( 2 N-000339 ) + ( 1 N-000339 ) + ( 2 N-000340 ) ) ( /4B6ED75B/4B6F321A LQFP80-.5 U401 LPC1754 {Lib=LPC1754} ( 1 EXT_TDO ) @@ -753,14 +753,14 @@ ( 10 +3.3V ) ( 11 ? ) ( 12 GND ) - ( 13 N-000340 ) + ( 13 N-000337 ) ( 14 /RESET ) - ( 15 N-000337 ) + ( 15 N-000338 ) ( 16 +BATT ) ( 17 ? ) - ( 18 N-000326 ) - ( 19 N-000338 ) - ( 20 N-000339 ) + ( 18 N-000328 ) + ( 19 N-000339 ) + ( 20 N-000340 ) ( 21 +3.3V ) ( 22 N-000309 ) ( 23 N-000314 ) @@ -769,7 +769,7 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 N-000324 ) + ( 29 N-000323 ) ( 30 DAC_/DEM ) ( 31 N-000300 ) ( 32 SNES_/RESET ) @@ -793,8 +793,8 @@ ( 50 DIN+MCU_/OVR ) ( 51 ? ) ( 52 ? ) - ( 53 N-000323 ) - ( 54 N-000295 ) + ( 53 N-000322 ) + ( 54 N-000294 ) ( 55 SD_DAT3 ) ( 56 +3.3V ) ( 57 GND ) @@ -802,14 +802,14 @@ ( 59 SD_DAT1 ) ( 60 SD_DAT0 ) ( 61 SD_CMD ) - ( 62 N-000319 ) + ( 62 N-000318 ) ( 63 SD_CLK ) - ( 64 N-000294 ) + ( 64 N-000295 ) ( 65 USB_SWCONN ) ( 66 GND ) ( 67 +3.3V ) ( 68 ? ) - ( 69 N-000325 ) + ( 69 N-000324 ) ( 70 /USEBATT ) ( 71 P2_D0 ) ( 72 P2_CLK ) @@ -822,7 +822,7 @@ ( 79 TX0 ) ( 80 RX0 ) ) - ( /4B6EC9C3/4DB35D41 $noname JP341 JUMPER {Lib=JUMPER} + ( /4B6EC9C3/4DB35D41 $noname JP341 FB_0603 {Lib=JUMPER} ( 1 GND ) ( 2 AGND ) ) @@ -832,11 +832,11 @@ ) ( /4B6EC9C3/4D4BE786 SM0805_FIXEDMASK R301 20k {Lib=R} ( 1 GND ) - ( 2 N-000277 ) + ( 2 N-000273 ) ) ( /4B6EC9C3/4D4BCF29 $noname Q301 IRLML6402PbF {Lib=MOSFET_P} ( D +5VL ) - ( G N-000277 ) + ( G N-000273 ) ( S +5V ) ) ( /4B6EC9C3/4CA655D4 SM0805_FIXEDMASK C332 100p {Lib=C} @@ -856,7 +856,7 @@ ( 2 EXT_CIC_DATA0 ) ) ( /4B6EC9C3/4C42D578 SM0805_FIXEDMASK R331 680 {Lib=R} - ( 1 N-000276 ) + ( 1 N-000277 ) ( 2 CIC_CLK ) ) ( /4B6EC9C3/4C17DE31 SM0805_FIXEDMASK C342 1u {Lib=C} @@ -985,7 +985,7 @@ ) ( /4B6EC9C3/4BAA92DB SO8N U331 PIC12F629-I/P {Lib=PIC12F629} ( 1 +5V ) - ( 2 N-000276 ) + ( 2 N-000277 ) ( 3 CIC_STATUS ) ( 4 CIC_MCLR ) ( 5 CIC_RESET ) @@ -1360,12 +1360,14 @@ $component R103 SM0603 SM0805 R?-* + SM1206 $endlist $component R102 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C111 SM* @@ -1402,6 +1404,7 @@ $component R101 SM0603 SM0805 R?-* + SM1206 $endlist $component C116 SM* @@ -1438,18 +1441,21 @@ $component R511 SM0603 SM0805 R?-* + SM1206 $endlist $component R513 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R512 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C502 SM* @@ -1471,18 +1477,21 @@ $component R407 SM0603 SM0805 R?-* + SM1206 $endlist $component R422 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R421 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C412 SM* @@ -1503,6 +1512,7 @@ $component R403 SM0603 SM0805 R?-* + SM1206 $endlist $component C405 SM* @@ -1514,36 +1524,42 @@ $component R404 SM0603 SM0805 R?-* + SM1206 $endlist $component R423 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R405 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R406 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R402 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R401 R? SM0603 SM0805 R?-* + SM1206 $endlist $component D401 LED-3MM @@ -1613,6 +1629,7 @@ $component R301 SM0603 SM0805 R?-* + SM1206 $endlist $component C332 SM* @@ -1629,18 +1646,21 @@ $component R333 SM0603 SM0805 R?-* + SM1206 $endlist $component R332 R? SM0603 SM0805 R?-* + SM1206 $endlist $component R331 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C342 SM* @@ -1672,12 +1692,14 @@ $component R341 SM0603 SM0805 R?-* + SM1206 $endlist $component R342 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C349 SM* @@ -1699,12 +1721,14 @@ $component R344 SM0603 SM0805 R?-* + SM1206 $endlist $component R343 R? SM0603 SM0805 R?-* + SM1206 $endlist $component C347 SM* @@ -1875,427 +1899,428 @@ $endfootprintlist } { Pin List by Nets Net 1 "GND" "GND" + U201 202 + C102 2 + U201 105 + C101 2 + U201 145 + U201 195 + U201 112 + U201 163 + U201 129 + U201 179 + U201 206 + U201 186 + U201 118 + C103 2 + C208 2 + C207 2 + C206 2 + C205 2 + C204 2 + U201 134 + C203 2 + C116 2 + C115 2 + C114 2 U103 21 - C202 2 - C201 2 - U201 1 + U201 82 + U201 14 + U201 25 + U201 75 + U201 41 + U103 1 + U201 91 + U201 157 + U103 4 + U201 53 + U201 59 + U201 99 + U201 66 + U201 170 + U103 10 + U201 151 + U201 47 + U101 39 + JP341 1 + U102 28 + U102 48 + U102 39 + U101 1 + C332 2 + C322 2 + C312 2 + U101 34 + C311 2 + U101 15 + U101 45 + U101 4 + C321 2 + U101 28 + BT351 2 + U101 48 + J101 5 U201 8 U201 30 + U201 1 C222 2 C221 2 C213 2 C212 2 C211 2 C210 2 - C208 2 - C207 2 - C206 2 - U103 1 - U103 4 - U103 10 - U201 129 - U201 179 - U201 206 - U201 186 - U201 157 - U201 118 - U201 14 - C205 2 - C204 2 - J101 36 - C203 2 - U201 134 - U201 105 - U201 145 - U201 195 - U201 202 - U201 112 - U201 163 - U101 10 - U101 21 - C331 2 - C312 2 - C311 2 - C321 2 - U301 3 - U301 5 - C301 2 - U102 28 - U102 48 - U102 39 - U101 1 - U101 4 - C303 2 - C302 2 - C304 2 - C115 2 - C114 2 - C103 2 - C102 2 - C101 2 - C332 2 C333 2 R301 1 - J101 5 - C322 2 - BT351 2 - JP341 1 - C116 2 - C209 2 - C231 2 - C233 2 + U101 10 + U101 21 + C202 2 + C201 2 C234 2 - U201 170 - C223 2 - U201 151 - C224 2 - U201 47 - U201 25 - U201 75 - U201 66 - U201 41 - U201 91 - U201 82 - U201 53 - U201 59 - U201 99 - C215 2 + C233 2 C232 2 + C215 2 + J101 36 + C224 2 + C209 2 C214 2 - C124 2 - C406 2 - C123 2 - C407 2 - C122 2 - C408 2 - C121 2 - J411 6 - J411 3 - J421 7 - J421 6 - J421 5 - C411 2 - P403 1 + C223 2 + C231 2 C412 2 P401 3 - C128 2 - C405 2 - C127 2 C126 2 - C125 2 - U401 24 - U401 43 - U401 33 - U401 66 - U401 57 - U401 9 - U401 12 - J411 GND1 - J411 GND2 + P403 1 + C405 2 + C411 2 + U511 16 + C401 2 + C402 2 + C403 2 + C404 2 + U401 78 + C408 2 + J421 5 + J421 6 + J421 7 + P402 1 + R102 2 + J411 6 C409 2 - C501 2 - C511 2 - U501 J3 - R101 1 - U501 J2 + J411 3 + J411 GND2 + Q101 1 + C407 2 + C128 2 + C406 2 + C127 2 + U401 57 + C125 2 + C124 2 + C123 2 + C122 2 + C121 2 U501 D1 + R101 1 + U501 J3 + U501 J2 U501 E6 U501 A6 Q511 1 R513 2 - U511 16 - C404 2 - C403 2 - C402 2 - C401 2 - P402 1 - U401 78 + C501 2 + C511 2 C502 2 - U103 24 - U103 34 - U103 15 - U103 25 - U103 45 + JP402 1 U102 21 + U331 8 U102 24 U102 34 U102 15 U102 25 - U101 15 - U101 45 - U331 8 - U311 2 - U101 28 - U321 2 - U101 48 - U101 39 - U102 45 + U102 4 + U102 10 + U301 3 U103 28 + C302 2 U103 48 + C304 2 U103 39 U102 1 - JP402 1 - U101 34 + C303 2 + C331 2 + U103 24 + U102 45 + U311 2 + U321 2 + U103 34 + U301 5 + U103 15 + U103 25 + U103 45 + C301 2 + J411 GND1 + U401 33 + U401 43 + U401 24 + U401 66 + U401 9 + U401 12 + C104 2 C106 2 C113 2 - C111 2 C112 2 - R102 2 - U102 10 - Q101 1 - C104 2 + C111 2 C105 2 - U102 4 -Net 2 "/SNES Slot/SNES_EXT_A2" "SNES_EXT_A2" - RA107 1 +Net 2 "/SNES Slot/SNES_EXT_SYS_CLK" "SNES_EXT_SYS_CLK" + R101 2 + J101 1 + U103 23 +Net 3 "/SNES Slot/SNES_EXT_A2" "SNES_EXT_A2" J101 15 -Net 3 "/SNES Slot/SNES_EXT_/PARD" "SNES_EXT_/PARD" - J101 4 - RA111 4 + RA107 1 Net 4 "/SNES Slot/SNES_EXT_/PAWR" "SNES_EXT_/PAWR" RA112 8 J101 35 Net 5 "/SNES Slot/SNES_EXT_PA6" "SNES_EXT_PA6" - J101 3 RA112 7 + J101 3 Net 6 "/SNES Slot/SNES_EXT_PA7" "SNES_EXT_PA7" - J101 34 RA112 6 + J101 34 Net 7 "/SNES Slot/SNES_EXT_REFRESH" "SNES_EXT_REFRESH" RA112 5 C126 1 J101 33 Net 8 "/SNES Slot/SNES_EXT_D3" "SNES_EXT_D3" - J101 22 RA103 1 + J101 22 Net 9 "/SNES Slot/SNES_EXT_D7" "SNES_EXT_D7" - RA103 2 J101 53 + RA103 2 Net 10 "/SNES Slot/SNES_EXT_D2" "SNES_EXT_D2" - J101 21 RA103 3 + J101 21 Net 11 "/SNES Slot/SNES_EXT_D6" "SNES_EXT_D6" - J101 52 RA103 4 + J101 52 Net 12 "" "" + U102 2 C125 1 RA105 7 - U102 2 Net 13 "" "" + U101 11 C124 1 RA102 6 - U101 11 Net 14 "SNES_IRQ_EN" "SNES_IRQ_EN" U201 114 R103 1 Net 15 "/SNES Slot/SNES_EXT_A6" "SNES_EXT_A6" RA109 1 J101 11 -Net 16 "/SNES Slot/SNES_EXT_A7" "SNES_EXT_A7" - J101 10 - RA109 3 -Net 17 "/SNES Slot/SNES_EXT_PA0" "SNES_EXT_PA0" - RA102 1 +Net 16 "/SNES Slot/SNES_EXT_PA0" "SNES_EXT_PA0" J101 28 -Net 18 "/SNES Slot/SNES_EXT_PA1" "SNES_EXT_PA1" - J101 59 + RA102 1 +Net 17 "/SNES Slot/SNES_EXT_PA1" "SNES_EXT_PA1" RA102 2 -Net 19 "/SNES Slot/SNES_EXT_/WR" "SNES_EXT_/WR" - J101 54 + J101 59 +Net 18 "/SNES Slot/SNES_EXT_/WR" "SNES_EXT_/WR" RA102 3 -Net 20 "/SNES Slot/SNES_EXT_CPU_CLK" "SNES_EXT_CPU_CLK" + J101 54 +Net 19 "/SNES Slot/SNES_EXT_CPU_CLK" "SNES_EXT_CPU_CLK" RA102 4 J101 57 -Net 21 "/SNES Slot/SNES_EXT_PA4" "SNES_EXT_PA4" - J101 30 +Net 20 "/SNES Slot/SNES_EXT_PA4" "SNES_EXT_PA4" RA101 1 -Net 22 "/SNES Slot/SNES_EXT_PA5" "SNES_EXT_PA5" - J101 61 + J101 30 +Net 21 "/SNES Slot/SNES_EXT_PA5" "SNES_EXT_PA5" RA101 2 -Net 23 "/SNES Slot/SNES_EXT_PA2" "SNES_EXT_PA2" + J101 61 +Net 22 "/SNES Slot/SNES_EXT_PA2" "SNES_EXT_PA2" J101 29 RA101 3 -Net 24 "/SNES Slot/SNES_EXT_PA3" "SNES_EXT_PA3" - J101 60 +Net 23 "/SNES Slot/SNES_EXT_PA3" "SNES_EXT_PA3" RA101 4 -Net 25 "/SNES Slot/SNES_EXT_D1" "SNES_EXT_D1" - J101 20 + J101 60 +Net 24 "/SNES Slot/SNES_EXT_D1" "SNES_EXT_D1" RA104 1 -Net 26 "/SNES Slot/SNES_EXT_D5" "SNES_EXT_D5" + J101 20 +Net 25 "/SNES Slot/SNES_EXT_D5" "SNES_EXT_D5" RA104 2 J101 51 -Net 27 "/SNES Slot/SNES_EXT_D0" "SNES_EXT_D0" - RA104 3 +Net 26 "/SNES Slot/SNES_EXT_D0" "SNES_EXT_D0" J101 19 -Net 28 "/SNES Slot/SNES_EXT_D4" "SNES_EXT_D4" - RA104 4 + RA104 3 +Net 27 "/SNES Slot/SNES_EXT_D4" "SNES_EXT_D4" J101 50 -Net 29 "SNES_D4" "SNES_D4" - U201 108 + RA104 4 +Net 28 "SNES_D4" "SNES_D4" RA114 5 -Net 30 "SNES_D0" "SNES_D0" + U201 108 +Net 29 "SNES_D0" "SNES_D0" U201 107 RA114 6 -Net 31 "SNES_D5" "SNES_D5" - RA114 7 +Net 30 "SNES_D5" "SNES_D5" U201 106 -Net 32 "SNES_D1" "SNES_D1" + RA114 7 +Net 31 "SNES_D1" "SNES_D1" U201 102 RA114 8 -Net 33 "SNES_D6" "SNES_D6" - RA113 5 +Net 32 "SNES_D6" "SNES_D6" U201 101 -Net 34 "SNES_D2" "SNES_D2" - RA113 6 + RA113 5 +Net 33 "SNES_D2" "SNES_D2" U201 100 -Net 35 "SNES_D7" "SNES_D7" + RA113 6 +Net 34 "SNES_D7" "SNES_D7" U201 97 RA113 7 -Net 36 "SNES_D3" "SNES_D3" +Net 35 "SNES_D3" "SNES_D3" RA113 8 U201 96 -Net 37 "" "" +Net 36 "" "" + R103 2 Q101 2 R102 1 - R103 2 +Net 37 "" "" + U102 22 + RA108 5 Net 38 "" "" U102 5 RA105 5 Net 39 "" "" - RA106 8 U102 6 + RA106 8 Net 40 "" "" RA106 7 U102 8 Net 41 "" "" - RA106 6 U102 9 + RA106 6 Net 42 "" "" RA108 6 U102 20 Net 43 "SNES_A18" "SNES_A18" - U201 131 U102 30 + U201 131 Net 44 "SNES_A1" "SNES_A1" - U102 40 U201 122 + U102 40 Net 45 "" "" - U102 11 RA106 5 + U102 11 Net 46 "SNES_A22" "SNES_A22" U201 120 U102 41 Net 47 "" "" - RA107 8 U102 12 -Net 48 "" "" - U102 22 - RA108 5 -Net 49 "SNES_A4" "SNES_A4" - U201 130 + RA107 8 +Net 48 "SNES_A4" "SNES_A4" U102 32 -Net 50 "" "" + U201 130 +Net 49 "" "" U102 13 RA107 7 -Net 51 "" "" - RA109 8 +Net 50 "" "" U102 23 -Net 52 "SNES_A19" "SNES_A19" - U201 128 + RA109 8 +Net 51 "SNES_A19" "SNES_A19" U102 33 -Net 53 "SNES_A0" "SNES_A0" - U201 119 + U201 128 +Net 52 "SNES_A0" "SNES_A0" U102 43 -Net 54 "" "" - RA107 6 + U201 119 +Net 53 "" "" U102 14 -Net 55 "SNES_A23" "SNES_A23" - U201 117 + RA107 6 +Net 54 "SNES_A23" "SNES_A23" U102 44 -Net 56 "SNES_A3" "SNES_A3" - U201 126 + U201 117 +Net 55 "SNES_A3" "SNES_A3" U102 35 -Net 57 "SNES_/PAWR" "SNES_/PAWR" - U201 150 - U103 32 -Net 58 "SNES_/PARD" "SNES_/PARD" - U201 149 - U103 33 -Net 59 "SNES_A8" "SNES_A8" - U103 43 - U201 140 -Net 60 "SNES_A15" "SNES_A15" - U201 139 - U103 44 -Net 61 "SNES_A11" "SNES_A11" - U201 148 - U103 35 -Net 62 "SNES_SYS_CLK" "SNES_SYS_CLK" + U201 126 +Net 56 "" "" + RA107 5 + U102 16 +Net 57 "SNES_SYS_CLK" "SNES_SYS_CLK" U103 26 U201 180 -Net 63 "SNES_A12" "SNES_A12" - U201 147 +Net 58 "SNES_/PAWR" "SNES_/PAWR" + U103 32 + U201 150 +Net 59 "SNES_/PARD" "SNES_/PARD" + U103 33 + U201 149 +Net 60 "SNES_A8" "SNES_A8" + U201 140 + U103 43 +Net 61 "SNES_A15" "SNES_A15" + U201 139 + U103 44 +Net 62 "SNES_A11" "SNES_A11" + U103 35 + U201 148 +Net 63 "SNES_A6" "SNES_A6" + U102 26 + U201 135 +Net 64 "SNES_A12" "SNES_A12" U103 36 -Net 64 "SNES_A7" "SNES_A7" - U201 138 + U201 147 +Net 65 "SNES_A7" "SNES_A7" U103 46 -Net 65 "SNES_REFRESH" "SNES_REFRESH" - U201 155 + U201 138 +Net 66 "SNES_REFRESH" "SNES_REFRESH" U103 27 -Net 66 "SNES_A10" "SNES_A10" + U201 155 +Net 67 "SNES_A10" "SNES_A10" U103 37 U201 146 -Net 67 "SNES_A16" "SNES_A16" +Net 68 "SNES_A16" "SNES_A16" U103 47 U201 137 -Net 68 "SNES_A13" "SNES_A13" - U201 144 +Net 69 "SNES_A13" "SNES_A13" U103 38 -Net 69 "SNES_PA7" "SNES_PA7" + U201 144 +Net 70 "SNES_PA7" "SNES_PA7" U103 29 U201 154 -Net 70 "SNES_PA0" "SNES_PA0" - U201 90 - U101 41 Net 71 "" "" - U101 22 - RA104 6 -Net 72 "" "" - RA113 4 - U101 32 -Net 73 "" "" - RA103 8 - U101 13 -Net 74 "" "" - RA104 5 - U101 23 -Net 75 "" "" - U101 33 - RA113 3 -Net 76 "SNES_PA3" "SNES_PA3" - U201 87 - U101 43 -Net 77 "" "" - RA103 7 - U101 14 -Net 78 "DATABUS_DIR" "DATABUS_DIR" - U201 111 - U101 24 -Net 79 "SNES_PA2" "SNES_PA2" - U201 86 - U101 44 -Net 80 "DATABUS_/OE" "DATABUS_/OE" - U201 109 - U101 25 -Net 81 "" "" - U101 35 - RA113 2 -Net 82 "" "" U101 16 RA103 6 +Net 72 "" "" + U101 22 + RA104 6 +Net 73 "" "" + RA113 4 + U101 32 +Net 74 "" "" + U101 13 + RA103 8 +Net 75 "" "" + RA104 5 + U101 23 +Net 76 "" "" + RA113 3 + U101 33 +Net 77 "SNES_PA3" "SNES_PA3" + U201 87 + U101 43 +Net 78 "" "" + RA103 7 + U101 14 +Net 79 "DATABUS_DIR" "DATABUS_DIR" + U101 24 + U201 111 +Net 80 "SNES_PA2" "SNES_PA2" + U201 86 + U101 44 +Net 81 "DATABUS_/OE" "DATABUS_/OE" + U201 109 + U101 25 +Net 82 "" "" + RA113 2 + U101 35 Net 83 "" "" - U101 26 RA114 4 + U101 26 Net 84 "" "" RA113 1 U101 36 @@ -2306,389 +2331,388 @@ Net 86 "" "" RA103 5 U101 17 Net 87 "" "" - RA114 3 U101 27 + RA114 3 Net 88 "SNES_CPU_CLK" "SNES_CPU_CLK" - U201 95 U101 37 + U201 95 Net 89 "SNES_PA4" "SNES_PA4" - U101 47 U201 81 + U101 47 Net 90 "SNES_/WR" "SNES_/WR" U201 94 U101 38 Net 91 "" "" - RA104 8 U101 19 + RA104 8 Net 92 "" "" - RA114 2 - U101 29 -Net 93 "" "" - RA107 5 - U102 16 -Net 94 "SNES_A6" "SNES_A6" - U201 135 - U102 26 -Net 95 "SNES_A20" "SNES_A20" + RA101 7 + U101 3 +Net 93 "SNES_A20" "SNES_A20" U201 125 U102 36 -Net 96 "SNES_/ROMSEL" "SNES_/ROMSEL" - U102 46 +Net 94 "SNES_/ROMSEL" "SNES_/ROMSEL" U201 116 -Net 97 "" "" - RA108 8 + U102 46 +Net 95 "" "" U102 17 -Net 98 "SNES_A17" "SNES_A17" - U102 27 + RA108 8 +Net 96 "SNES_A17" "SNES_A17" U201 133 -Net 99 "SNES_A2" "SNES_A2" - U102 37 + U102 27 +Net 97 "SNES_A2" "SNES_A2" U201 124 -Net 100 "SNES_/RD" "SNES_/RD" + U102 37 +Net 98 "SNES_/RD" "SNES_/RD" U201 115 U102 47 -Net 101 "SNES_A21" "SNES_A21" +Net 99 "SNES_A21" "SNES_A21" U102 38 U201 123 -Net 102 "" "" +Net 100 "" "" RA108 7 U102 19 -Net 103 "SNES_A5" "SNES_A5" +Net 101 "SNES_A5" "SNES_A5" U102 29 U201 132 -Net 104 "" "" +Net 102 "" "" RA101 8 U101 2 -Net 105 "" "" - U101 3 - RA101 7 -Net 106 "" "" - U101 5 +Net 103 "" "" RA101 6 -Net 107 "" "" - U101 6 + U101 5 +Net 104 "" "" RA101 5 -Net 108 "" "" - U101 8 + U101 6 +Net 105 "" "" RA102 8 -Net 109 "" "" + U101 8 +Net 106 "" "" U101 9 RA102 7 -Net 110 "" "" +Net 107 "" "" U101 20 RA104 7 -Net 111 "" "" +Net 108 "" "" U101 30 RA114 1 -Net 112 "SNES_PA1" "SNES_PA1" - U101 40 +Net 109 "SNES_PA1" "SNES_PA1" U201 93 -Net 113 "+5V" "+5V" - U101 18 - C116 1 - U331 1 - C111 1 + U101 40 +Net 110 "SNES_PA0" "SNES_PA0" + U201 90 + U101 41 +Net 112 "+5V" "+5V" C112 1 + C113 1 + U301 2 + C115 1 + C114 1 + U331 1 + P401 2 + C331 1 U102 18 - C301 1 + C116 1 U301 9 U301 8 - Q301 S U301 6 + C302 1 + U101 18 + C111 1 + U103 18 U101 7 - U301 2 - C114 1 - C115 1 - C331 1 U102 7 U103 7 - P401 2 - C302 1 - U103 18 - C113 1 -Net 115 "/SNES Slot/SNES_EXT_A11" "SNES_EXT_A11" + Q301 S + C301 1 +Net 113 "/SNES Slot/SNES_EXT_A11" "SNES_EXT_A11" RA111 3 J101 6 -Net 116 "/SNES Slot/SNES_EXT_A10" "SNES_EXT_A10" +Net 114 "/SNES Slot/SNES_EXT_A10" "SNES_EXT_A10" RA111 1 J101 7 -Net 117 "/SNES Slot/SNES_EXT_A9" "SNES_EXT_A9" +Net 115 "/SNES Slot/SNES_EXT_A9" "SNES_EXT_A9" J101 8 RA110 3 -Net 118 "/SNES Slot/SNES_EXT_A8" "SNES_EXT_A8" +Net 116 "/SNES Slot/SNES_EXT_A8" "SNES_EXT_A8" J101 9 RA110 1 -Net 119 "/SNES Slot/SNES_EXT_A15" "SNES_EXT_A15" +Net 117 "/SNES Slot/SNES_EXT_A7" "SNES_EXT_A7" + J101 10 + RA109 3 +Net 118 "/SNES Slot/SNES_EXT_A15" "SNES_EXT_A15" J101 40 RA109 4 -Net 120 "+5VL" "+5VL" - J101 27 - J101 58 - Q301 D +Net 119 "AUDIO_L" "AUDIO_L" + J101 31 + C349 1 + R343 1 +Net 120 "" "" + RA109 6 + U103 3 Net 121 "/SNES Slot/SNES_EXT_A12" "SNES_EXT_A12" - J101 37 RA111 2 + J101 37 Net 122 "/SNES Slot/SNES_EXT_/IRQ" "SNES_EXT_/IRQ" - J101 18 RA105 1 + J101 18 Net 123 "/SNES Slot/SNES_EXT_A13" "SNES_EXT_A13" RA110 4 J101 38 Net 124 "/SNES Slot/SNES_EXT_A14" "SNES_EXT_A14" - RA110 2 J101 39 + RA110 2 Net 125 "" "" RA109 7 U103 2 -Net 126 "" "" - RA109 6 - U103 3 +Net 126 "+5VL" "+5VL" + J101 27 + J101 58 + Q301 D Net 127 "" "" U103 5 RA109 5 -Net 128 "" "" - RA110 8 - U103 6 -Net 129 "SNES_PA6" "SNES_PA6" - U103 30 +Net 128 "SNES_PA6" "SNES_PA6" U201 152 -Net 130 "SNES_A9" "SNES_A9" + U103 30 +Net 129 "SNES_A9" "SNES_A9" U201 143 U103 40 -Net 131 "SNES_A14" "SNES_A14" - U201 141 +Net 130 "SNES_A14" "SNES_A14" U103 41 -Net 132 "AUDIO_L" "AUDIO_L" - R343 1 - C349 1 - J101 31 -Net 133 "/SNES Slot/SNES_EXT_A16" "SNES_EXT_A16" - J101 41 + U201 141 +Net 131 "EXT_CIC_DATA1" "EXT_CIC_DATA1" + R333 1 + J101 24 +Net 132 "/SNES Slot/SNES_EXT_A16" "SNES_EXT_A16" RA109 2 -Net 135 "/SNES Slot/SNES_EXT_A17" "SNES_EXT_A17" - J101 42 + J101 41 +Net 134 "/SNES Slot/SNES_EXT_A17" "SNES_EXT_A17" RA108 4 -Net 136 "AUDIO_R" "AUDIO_R" - J101 62 + J101 42 +Net 135 "AUDIO_R" "AUDIO_R" R341 1 C347 1 -Net 137 "/SNES Slot/SNES_EXT_A18" "SNES_EXT_A18" + J101 62 +Net 136 "/SNES Slot/SNES_EXT_A18" "SNES_EXT_A18" RA108 2 J101 43 -Net 138 "EXT_CIC_DATA1" "EXT_CIC_DATA1" - J101 24 - R333 1 -Net 139 "/SNES Slot/SNES_EXT_A19" "SNES_EXT_A19" - J101 44 - RA107 4 -Net 140 "CIC_RESET" "CIC_RESET" - U331 5 +Net 137 "" "" + RA110 8 + U103 6 +Net 138 "CIC_RESET" "CIC_RESET" J101 25 -Net 141 "EXT_CIC_DATA0" "EXT_CIC_DATA0" + U331 5 +Net 139 "EXT_CIC_DATA0" "EXT_CIC_DATA0" R332 2 J101 55 -Net 142 "SNES_/RESET" "SNES_/RESET" +Net 140 "SNES_/RESET" "SNES_/RESET" U401 32 J101 26 -Net 143 "CIC_CLK" "CIC_CLK" +Net 141 "CIC_CLK" "CIC_CLK" J101 56 R331 2 -Net 144 "+3.3V" "+3.3V" - U321 1 +Net 142 "+3.3V" "+3.3V" + U101 31 + C201 1 + U301 10 + FB341 1 + U201 6 + L302 2 + U201 60 + U103 42 U321 3 - C231 1 - C232 1 - U201 164 - C233 1 - C234 1 + U321 1 U311 3 U311 1 - U201 60 - C311 1 - U201 6 - C201 1 - U103 31 C321 1 - U501 E1 + C311 1 + U201 153 + U101 42 + C106 1 + C304 1 C101 1 - C102 1 - FB341 1 + U102 42 + U102 31 + R407 2 + C104 1 C103 1 - U301 10 - C208 1 + U201 164 + C102 1 + C202 1 C207 1 C206 1 C205 1 C204 1 C203 1 - C202 1 - U101 31 - C501 1 - L302 2 - C304 1 - U201 110 - U201 201 - U102 42 - U102 31 - C104 1 + C208 1 C105 1 - C106 1 - U201 98 R404 2 - U201 32 - U103 42 - U201 23 - U201 73 - U201 49 - U401 42 - U401 21 - J411 4 - U401 34 - U401 56 - U401 10 - U401 8 - R407 2 - C209 1 - P401 1 - D403 1 - U201 84 C412 1 - U101 42 + D403 1 + P401 1 + U401 77 + U401 67 + D401 1 + D402 1 + C231 1 + C232 1 + C233 1 + C234 1 + C501 1 C404 1 - U201 136 C403 1 C402 1 - U201 127 C401 1 - U401 67 C411 1 - U401 77 - U201 177 - D511 1 - D402 1 - D401 1 - U201 188 - U201 153 R512 2 -Net 145 "/SNES Slot/SNES_EXT_SYS_CLK" "SNES_EXT_SYS_CLK" - R101 2 - U103 23 - J101 1 -Net 146 "" "" - C122 1 - U102 3 + D511 1 + U201 188 + C209 1 + U401 10 + U401 21 + U201 110 + U201 201 + U401 42 + U401 8 + U201 73 + U201 49 + U401 56 + U401 34 + U201 177 + U201 127 + U201 136 + U201 84 + U201 32 + U201 23 + U201 98 + J411 4 + U103 31 + U501 E1 +Net 143 "" "" RA105 6 -Net 147 "" "" - RA102 5 + U102 3 + C122 1 +Net 144 "" "" C121 1 + RA102 5 U101 12 -Net 148 "" "" - U103 12 +Net 145 "" "" + U101 29 + RA114 2 +Net 146 "" "" RA111 8 -Net 149 "" "" + U103 12 +Net 147 "" "" Q101 3 - RA105 8 C123 1 -Net 150 "/SNES Slot/SNES_EXT_/RD" "SNES_EXT_/RD" + RA105 8 +Net 148 "/SNES Slot/SNES_EXT_/RD" "SNES_EXT_/RD" J101 23 RA105 2 -Net 151 "/SNES Slot/SNES_EXT_/ROMSEL" "SNES_EXT_/ROMSEL" - J101 49 +Net 149 "/SNES Slot/SNES_EXT_/ROMSEL" "SNES_EXT_/ROMSEL" RA105 3 -Net 152 "/SNES Slot/SNES_EXT_A23" "SNES_EXT_A23" - J101 48 + J101 49 +Net 150 "/SNES Slot/SNES_EXT_A23" "SNES_EXT_A23" RA105 4 -Net 153 "" "" + J101 48 +Net 151 "" "" + RA112 1 C127 1 U103 17 - RA112 1 -Net 154 "" "" +Net 152 "" "" U103 19 RA112 2 -Net 155 "" "" +Net 153 "" "" U103 20 RA112 3 -Net 156 "" "" - RA112 4 +Net 154 "" "" U103 22 -Net 157 "" "" + RA112 4 +Net 155 "/SNES Slot/SNES_EXT_/PARD" "SNES_EXT_/PARD" + RA111 4 + J101 4 +Net 156 "" "" U103 16 RA111 5 C128 1 -Net 158 "" "" - U103 14 +Net 157 "" "" RA111 6 -Net 159 "" "" - RA111 7 + U103 14 +Net 158 "" "" U103 13 -Net 160 "" "" - U103 11 + RA111 7 +Net 159 "" "" RA110 5 -Net 161 "" "" - U103 9 + U103 11 +Net 160 "" "" RA110 6 -Net 162 "" "" - U103 8 + U103 9 +Net 161 "" "" RA110 7 -Net 163 "/SNES Slot/SNES_EXT_A4" "SNES_EXT_A4" + U103 8 +Net 162 "/SNES Slot/SNES_EXT_A4" "SNES_EXT_A4" RA108 1 J101 13 -Net 164 "/SNES Slot/SNES_EXT_A5" "SNES_EXT_A5" +Net 163 "/SNES Slot/SNES_EXT_A5" "SNES_EXT_A5" RA108 3 J101 12 -Net 165 "/SNES Slot/SNES_EXT_A20" "SNES_EXT_A20" +Net 164 "/SNES Slot/SNES_EXT_A20" "SNES_EXT_A20" RA107 2 J101 45 -Net 166 "/SNES Slot/SNES_EXT_A3" "SNES_EXT_A3" +Net 165 "/SNES Slot/SNES_EXT_A3" "SNES_EXT_A3" RA107 3 J101 14 +Net 166 "/SNES Slot/SNES_EXT_A19" "SNES_EXT_A19" + J101 44 + RA107 4 Net 167 "/SNES Slot/SNES_EXT_A0" "SNES_EXT_A0" - J101 17 RA106 1 + J101 17 Net 168 "/SNES Slot/SNES_EXT_A22" "SNES_EXT_A22" RA106 2 J101 47 Net 169 "/SNES Slot/SNES_EXT_A1" "SNES_EXT_A1" - J101 16 RA106 3 + J101 16 Net 170 "/SNES Slot/SNES_EXT_A21" "SNES_EXT_A21" RA106 4 J101 46 Net 171 "ROM_A12" "ROM_A12" U501 G3 U201 2 -Net 172 "SD_DAT3" "SD_DAT3" - U401 55 - U201 63 +Net 172 "DONE" "DONE" + U201 103 + U401 44 +Net 173 "SD_DAT3" "SD_DAT3" J411 1 -Net 173 "SD_DAT0" "SD_DAT0" + U201 63 + U401 55 +Net 174 "SD_DAT0" "SD_DAT0" + U201 65 J411 7 U401 60 - U201 65 -Net 174 "MCU_SPI_SS" "MCU_SPI_SS" +Net 175 "MCU_SPI_SS" "MCU_SPI_SS" U401 48 U201 68 -Net 175 "MCU_SPI_MISO" "MCU_SPI_MISO" - U401 46 +Net 176 "MCU_SPI_MISO" "MCU_SPI_MISO" U201 72 -Net 176 "DAC_MCLK" "DAC_MCLK" - U201 76 + U401 46 +Net 177 "DAC_MCLK" "DAC_MCLK" U341 4 -Net 177 "DAC_SDIN" "DAC_SDIN" - U341 1 + U201 76 +Net 178 "DAC_SDIN" "DAC_SDIN" U201 78 -Net 178 "ROM_/LB" "ROM_/LB" - U201 156 + U341 1 +Net 179 "ROM_/LB" "ROM_/LB" U501 A1 -Net 179 "DONE" "DONE" - U401 44 - U201 103 + U201 156 Net 180 "DIN+MCU_/OVR" "DIN+MCU_/OVR" U401 50 U201 92 Net 181 "RAM_A1" "RAM_A1" - U201 31 U511 11 + U201 31 Net 182 "RAM_/WE" "RAM_/WE" U201 50 U511 29 @@ -2705,8 +2729,8 @@ Net 186 "RAM_A6" "RAM_A6" U201 43 U511 6 Net 187 "RAM_DQ0" "RAM_DQ0" - U511 13 U201 26 + U511 13 Net 188 "RAM_A8" "RAM_A8" U201 44 U511 27 @@ -2721,120 +2745,120 @@ Net 191 "SD_DAT2" "SD_DAT2" U201 62 J411 9 Net 192 "SD_DAT1" "SD_DAT1" + U201 79 U401 59 J411 8 - U201 79 Net 193 "" "" - P113 1 U201 113 -Net 194 "RAM_A10" "RAM_A10" - U201 34 - U511 23 -Net 195 "RAM_A2" "RAM_A2" - U201 33 - U511 10 -Net 196 "RAM_DQ7" "RAM_DQ7" - U201 29 - U511 21 -Net 197 "RAM_A0" "RAM_A0" - U201 28 - U511 12 -Net 198 "RAM_DQ6" "RAM_DQ6" - U511 20 - U201 27 -Net 199 "RAM_DQ5" "RAM_DQ5" - U201 24 - U511 19 -Net 200 "RAM_DQ1" "RAM_DQ1" - U201 22 - U511 14 -Net 201 "RAM_DQ4" "RAM_DQ4" - U201 21 - U511 18 -Net 202 "RAM_DQ2" "RAM_DQ2" + P113 1 +Net 194 "RAM_DQ2" "RAM_DQ2" U201 20 U511 15 -Net 203 "RAM_DQ3" "RAM_DQ3" - U511 17 +Net 195 "RAM_A10" "RAM_A10" + U511 23 + U201 34 +Net 196 "RAM_A2" "RAM_A2" + U201 33 + U511 10 +Net 197 "RAM_DQ7" "RAM_DQ7" + U511 21 + U201 29 +Net 198 "RAM_A0" "RAM_A0" + U511 12 + U201 28 +Net 199 "RAM_DQ6" "RAM_DQ6" + U511 20 + U201 27 +Net 200 "RAM_DQ5" "RAM_DQ5" + U511 19 + U201 24 +Net 201 "RAM_DQ1" "RAM_DQ1" + U511 14 + U201 22 +Net 202 "RAM_DQ4" "RAM_DQ4" + U511 18 + U201 21 +Net 203 "RAM_/OE" "RAM_/OE" + U201 36 + U511 24 +Net 204 "RAM_DQ3" "RAM_DQ3" U201 19 -Net 204 "ROM_A5" "ROM_A5" + U511 17 +Net 205 "ROM_A5" "ROM_A5" U501 C3 U201 18 -Net 205 "ROM_DQ10" "ROM_DQ10" +Net 206 "ROM_DQ10" "ROM_DQ10" U501 C2 U201 15 -Net 206 "ROM_DQ9" "ROM_DQ9" - U201 13 +Net 207 "ROM_DQ9" "ROM_DQ9" U501 C1 -Net 207 "ROM_DQ11" "ROM_DQ11" - U501 D2 + U201 13 +Net 208 "ROM_DQ11" "ROM_DQ11" U201 12 -Net 208 "ROM_A17" "ROM_A17" + U501 D2 +Net 209 "ROM_A17" "ROM_A17" U501 D3 U201 11 -Net 209 "ROM_DQ12" "ROM_DQ12" +Net 210 "ROM_DQ12" "ROM_DQ12" U201 10 U501 E2 -Net 210 "ROM_DQ14" "ROM_DQ14" +Net 211 "ROM_DQ14" "ROM_DQ14" U201 9 U501 F1 -Net 211 "ROM_DQ13" "ROM_DQ13" - U201 7 +Net 212 "ROM_DQ13" "ROM_DQ13" U501 F2 -Net 212 "ROM_DQ15" "ROM_DQ15" + U201 7 +Net 213 "ROM_DQ15" "ROM_DQ15" U501 G1 U201 5 -Net 213 "ROM_A19" "ROM_A19" - U501 G2 +Net 214 "ROM_A19" "ROM_A19" U201 4 -Net 214 "ROM_A18" "ROM_A18" - U201 3 - U501 H1 -Net 215 "INIT_B+MCU_IRQ" "INIT_B+MCU_IRQ" - U401 49 - U201 83 -Net 216 "ROM_/UB" "ROM_/UB" - U501 B2 - U201 161 -Net 217 "RAM_A17" "RAM_A17" - U511 1 - U201 61 -Net 218 "RAM_A15" "RAM_A15" - U201 58 - U511 31 -Net 219 "RAM_A16" "RAM_A16" - U201 57 - U511 2 -Net 220 "RAM_A18" "RAM_A18" + U501 G2 +Net 215 "RAM_A18" "RAM_A18" U201 52 U511 30 -Net 221 "RAM_A14" "RAM_A14" +Net 216 "INIT_B+MCU_IRQ" "INIT_B+MCU_IRQ" + U401 49 + U201 83 +Net 217 "ROM_/UB" "ROM_/UB" + U201 161 + U501 B2 +Net 218 "RAM_A17" "RAM_A17" + U201 61 + U511 1 +Net 219 "RAM_A15" "RAM_A15" + U511 31 + U201 58 +Net 220 "RAM_A16" "RAM_A16" + U511 2 + U201 57 +Net 221 "ROM_A18" "ROM_A18" + U201 3 + U501 H1 +Net 222 "RAM_A14" "RAM_A14" U201 51 U511 3 -Net 222 "RAM_A12" "RAM_A12" - U201 48 +Net 223 "RAM_A12" "RAM_A12" U511 4 -Net 223 "RAM_A13" "RAM_A13" + U201 48 +Net 224 "RAM_A13" "RAM_A13" U511 28 U201 46 -Net 224 "RAM_A9" "RAM_A9" +Net 225 "RAM_A9" "RAM_A9" U201 42 U511 26 -Net 225 "RAM_A5" "RAM_A5" +Net 226 "RAM_A5" "RAM_A5" U201 40 U511 7 -Net 226 "RAM_A11" "RAM_A11" +Net 227 "RAM_A11" "RAM_A11" U201 39 U511 25 -Net 227 "RAM_/OE" "RAM_/OE" - U511 24 - U201 36 Net 228 "FPGA_CLK" "FPGA_CLK" - U201 80 U401 39 + U201 80 Net 229 "DAC_LRCK" "DAC_LRCK" - U201 77 U341 3 + U201 77 Net 230 "MCU_SPI_MOSI" "MCU_SPI_MOSI" U401 45 U201 74 @@ -2842,13 +2866,13 @@ Net 231 "MCU_SPI_SCK" "MCU_SPI_SCK" U201 71 U401 47 Net 232 "SD_CMD" "SD_CMD" + U401 61 U201 67 J411 2 - U401 61 Net 233 "SD_CLK" "SD_CLK" + J411 5 U401 63 U201 64 - J411 5 Net 234 "ROM_A8" "ROM_A8" U201 205 U501 H2 @@ -2862,23 +2886,23 @@ Net 237 "ROM_A14" "ROM_A14" U201 200 U501 F3 Net 238 "ROM_A16" "ROM_A16" - U201 199 U501 E4 + U201 199 Net 239 "ROM_A22" "ROM_A22" U501 J4 U201 198 -Net 240 "ROM_DQ8" "ROM_DQ8" - U501 B1 - U201 16 -Net 241 "ROM_A10" "ROM_A10" +Net 240 "ROM_A10" "ROM_A10" U501 H4 U201 197 +Net 241 "ROM_DQ8" "ROM_DQ8" + U201 16 + U501 B1 Net 242 "ROM_A11" "ROM_A11" U201 196 U501 H5 Net 243 "ROM_A13" "ROM_A13" - U501 G4 U201 194 + U501 G4 Net 244 "ROM_A20" "ROM_A20" U201 191 U501 H6 @@ -2886,41 +2910,41 @@ Net 245 "ROM_/WE" "ROM_/WE" U501 G5 U201 190 Net 246 "ROM_DQ7" "ROM_DQ7" - U501 G6 U201 189 + U501 G6 Net 247 "ROM_DQ5" "ROM_DQ5" U501 F5 U201 187 Net 248 "ROM_DQ6" "ROM_DQ6" - U201 185 U501 F6 + U201 185 Net 249 "ROM_A15" "ROM_A15" - U201 184 U501 F4 + U201 184 Net 250 "ROM_DQ4" "ROM_DQ4" - U201 183 U501 E5 + U201 183 Net 251 "ROM_DQ3" "ROM_DQ3" U501 D5 U201 182 Net 252 "ROM_DQ2" "ROM_DQ2" - U201 181 U501 C6 + U201 181 Net 253 "ROM_DQ1" "ROM_DQ1" U501 C5 U201 178 Net 254 "ROM_DQ0" "ROM_DQ0" - U201 176 U501 B6 + U201 176 Net 255 "ROM_A6" "ROM_A6" - U201 175 U501 C4 + U201 175 Net 256 "ROM_/CE" "ROM_/CE" - U501 B5 U201 172 + U501 B5 Net 257 "ROM_A2" "ROM_A2" - U501 A5 U201 171 + U501 A5 Net 258 "ROM_A4" "ROM_A4" U501 B4 U201 169 @@ -2928,70 +2952,70 @@ Net 259 "ROM_A1" "ROM_A1" U501 A4 U201 168 Net 260 "ROM_A7" "ROM_A7" - U201 167 U501 D4 + U201 167 Net 261 "ROM_A0" "ROM_A0" - U501 A3 U201 166 + U501 A3 Net 262 "ROM_A3" "ROM_A3" - U501 B3 U201 165 + U501 B3 Net 263 "ROM_/OE" "ROM_/OE" U201 162 U501 A2 Net 264 "+2.5V" "+2.5V" - U201 193 - C210 1 - C211 1 + C215 1 C212 1 + C322 1 U321 5 C213 1 - C322 1 + C211 1 + C210 1 U201 89 - U201 69 - C214 1 - U201 173 - C215 1 - U201 142 U201 121 - U201 38 U201 17 + U201 38 + U201 69 + U201 173 + U201 142 + C214 1 + U201 193 Net 265 "+1.2V" "+1.2V" - L301 1 C223 1 - C303 1 - U201 174 - U301 1 - U201 192 - U201 88 + C224 1 C222 1 + U201 192 U201 70 C221 1 - C224 1 -Net 273 "AGND" "AGND" - JP341 2 + U201 174 + U301 1 + L301 1 + C303 1 + U201 88 +Net 273 "" "" + Q301 G + R301 2 +Net 274 "AGND" "AGND" + R342 2 + R344 2 + C347 2 + C345 2 + C344 2 + C349 2 C342 2 C343 2 C341 2 - C344 2 - C345 2 - C347 2 - R342 2 U341 8 - C349 2 - R344 2 -Net 274 "/Power Supply / Misc./REG_SW2" "REG_SW2" - U301 7 + JP341 2 +Net 275 "/Power Supply / Misc./REG_SW2" "REG_SW2" L302 1 -Net 275 "DAC_/DEM" "DAC_/DEM" + U301 7 +Net 276 "DAC_/DEM" "DAC_/DEM" U341 2 U401 30 -Net 276 "" "" +Net 277 "" "" R331 1 U331 2 -Net 277 "" "" - R301 2 - Q301 G Net 278 "" "" U341 10 C346 2 @@ -2999,84 +3023,84 @@ Net 279 "" "" C345 1 U341 6 Net 280 "+3.3VDAC" "+3.3VDAC" - U341 9 - C342 1 FB341 2 + C342 1 C341 1 + U341 9 Net 281 "" "" - U341 7 C348 2 + U341 7 Net 282 "+BATT" "+BATT" D511 2 BT351 1 U401 16 Net 283 "CIC_DATA1" "CIC_DATA1" - C333 1 R333 2 U331 6 + C333 1 U401 37 Net 284 "" "" - C343 1 - U341 5 C344 1 + U341 5 + C343 1 Net 285 "/Power Supply / Misc./REG_SW1" "REG_SW1" - L301 2 U301 4 + L301 2 Net 288 "CIC_DATA0" "CIC_DATA0" - U331 7 - C332 1 - R332 1 U401 38 + C332 1 + U331 7 + R332 1 Net 289 "CIC_MCLR" "CIC_MCLR" - U331 4 JP401 2 + U331 4 Net 290 "CIC_STATUS" "CIC_STATUS" - U331 3 U401 36 + U331 3 Net 291 "+1.8V" "+1.8V" C502 1 U311 5 U501 D6 C312 1 Net 292 "" "" - R343 2 R344 1 + R343 2 C348 1 Net 293 "" "" C346 1 R342 1 R341 2 Net 294 "" "" + R401 1 + U401 54 +Net 295 "" "" J411 WP U401 64 -Net 295 "" "" - U401 54 - R401 1 -Net 296 "P1_D0" "P1_D0" - U401 76 - P404 1 -Net 297 "P_LATCH" "P_LATCH" - P404 3 - U401 74 -Net 298 "P2_CLK" "P2_CLK" - P404 5 - U401 72 -Net 299 "/USEBATT" "/USEBATT" - JP402 2 +Net 296 "/USEBATT" "/USEBATT" U401 70 + JP402 2 +Net 297 "P1_D0" "P1_D0" + P404 1 + U401 76 +Net 298 "P_LATCH" "P_LATCH" + U401 74 + P404 3 +Net 299 "P2_CLK" "P2_CLK" + U401 72 + P404 5 Net 300 "" "" JP401 1 U401 31 -Net 301 "P2.10" "P2.10" +Net 301 "P2_D0" "P2_D0" + P404 6 + U401 71 +Net 302 "P2.10" "P2.10" U401 41 - P401 4 R407 1 -Net 302 "P1_CLK" "P1_CLK" + P401 4 +Net 303 "P1_CLK" "P1_CLK" U401 75 P404 2 -Net 303 "P2_D0" "P2_D0" - U401 71 - P404 6 Net 304 "MCU_SPARE" "MCU_SPARE" U401 73 P404 4 @@ -3084,14 +3108,14 @@ Net 305 "" "" R402 2 D402 2 Net 306 "TX0" "TX0" - P401 14 U401 79 + P401 14 Net 307 "TCK" "TCK" P401 8 U401 5 Net 308 "EXT_TDI" "EXT_TDI" - P401 11 U401 2 + P401 11 Net 309 "" "" R421 2 U401 22 @@ -3108,85 +3132,85 @@ Net 313 "" "" U401 25 P403 2 Net 314 "" "" - R422 2 U401 23 + R422 2 Net 315 "" "" R421 1 J421 3 R423 1 -Net 316 "USB_SWCONN" "USB_SWCONN" - R423 2 - U401 65 -Net 317 "RX0" "RX0" - U401 80 - P401 13 -Net 318 "" "" +Net 316 "" "" D401 2 R401 2 -Net 319 "" "" - J411 DT +Net 317 "USB_SWCONN" "USB_SWCONN" + R423 2 + U401 65 +Net 318 "" "" U401 62 -Net 320 "/RESET" "/RESET" - P401 5 + J411 DT +Net 319 "/RESET" "/RESET" C405 1 - R404 1 + P401 5 U401 14 + R404 1 P402 2 -Net 321 "RX3" "RX3" - U401 6 +Net 320 "RX3" "RX3" P401 7 -Net 322 "/TRST" "/TRST" + U401 6 +Net 321 "/TRST" "/TRST" P401 9 U401 4 -Net 323 "" "" - U401 53 +Net 322 "" "" R402 1 -Net 324 "" "" - U401 29 + U401 53 +Net 323 "" "" R403 1 -Net 325 "" "" + U401 29 +Net 324 "" "" U401 69 R406 1 -Net 326 "" "" - J421 1 - U401 18 +Net 325 "RX0" "RX0" + P401 13 + U401 80 +Net 326 "EXT_TDO" "EXT_TDO" + U401 1 + P401 12 Net 327 "" "" R405 2 U401 40 -Net 328 "EXT_TDO" "EXT_TDO" - U401 1 - P401 12 +Net 328 "" "" + U401 18 + J421 1 Net 329 "TMS" "TMS" - P401 10 U401 3 + P401 10 Net 337 "" "" - X402 2 - C409 1 - U401 15 -Net 338 "" "" - X401 1 - U401 19 - C406 1 -Net 339 "" "" - U401 20 - X401 2 - C407 1 -Net 340 "" "" + C408 1 X402 1 U401 13 - C408 1 +Net 338 "" "" + U401 15 + C409 1 + X402 2 +Net 339 "" "" + C406 1 + X401 1 + U401 19 +Net 340 "" "" + C407 1 + X401 2 + U401 20 Net 343 "/Memory/RAM_/CE" "RAM_/CE" - R511 2 Q511 3 + R511 2 U511 22 Net 344 "" "" - R513 1 - R512 1 Q511 2 + R512 1 + R513 1 Net 345 "/Memory/SRAM_Vcc" "SRAM_Vcc" - C511 1 - R511 1 - U511 32 D511 3 + R511 1 + C511 1 + U511 32 } #End diff --git a/pcb/kicad/RevE/sd2snes.sch b/pcb/kicad/RevE/sd2snes.sch index 45bf9e7..e6ce0e2 100644 --- a/pcb/kicad/RevE/sd2snes.sch +++ b/pcb/kicad/RevE/sd2snes.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 1 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "E" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/snesslot.sch b/pcb/kicad/RevE/snesslot.sch index 0e24d0b..a487e76 100644 --- a/pcb/kicad/RevE/snesslot.sch +++ b/pcb/kicad/RevE/snesslot.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 29 Jul 2011 09:56:34 PM CEST +EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A3 16535 11700 encoding utf-8 Sheet 2 6 Title "sd2snes Mark II" -Date "24 jul 2011" +Date "2 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" @@ -855,7 +855,7 @@ L R_PACK4 RA114 U 1 1 4D97B45F P 15250 4750 F 0 "RA114" H 15250 4600 40 0000 C CNN -F 1 "220" H 15250 4950 40 0000 C CNN +F 1 "100" H 15250 4950 40 0000 C CNN 1 15250 4750 1 0 0 -1 $EndComp @@ -864,7 +864,7 @@ L R_PACK4 RA113 U 1 1 4D97B45C P 15250 4350 F 0 "RA113" H 15250 4800 40 0000 C CNN -F 1 "220" H 15250 4550 40 0000 C CNN +F 1 "100" H 15250 4550 40 0000 C CNN 1 15250 4350 1 0 0 -1 $EndComp @@ -913,7 +913,7 @@ L R_PACK4 RA108 U 1 1 4D963119 P 4150 8350 F 0 "RA108" H 4150 8300 40 0000 C CNN -F 1 "220" H 4150 8550 40 0000 C CNN +F 1 "100" H 4150 8550 40 0000 C CNN 1 4150 8350 -1 0 0 -1 $EndComp @@ -922,7 +922,7 @@ L R_PACK4 RA107 U 1 1 4D963117 P 4150 7950 F 0 "RA107" H 4150 8400 40 0000 C CNN -F 1 "220" H 4150 8150 40 0000 C CNN +F 1 "100" H 4150 8150 40 0000 C CNN 1 4150 7950 -1 0 0 -1 $EndComp @@ -931,7 +931,7 @@ L R_PACK4 RA106 U 1 1 4D963115 P 4150 7350 F 0 "RA106" H 4150 7300 40 0000 C CNN -F 1 "220" H 4150 7550 40 0000 C CNN +F 1 "100" H 4150 7550 40 0000 C CNN 1 4150 7350 -1 0 0 -1 $EndComp @@ -940,7 +940,7 @@ L R_PACK4 RA105 U 1 1 4D96310E P 4150 6950 F 0 "RA105" H 4150 7400 40 0000 C CNN -F 1 "220" H 4150 7150 40 0000 C CNN +F 1 "100" H 4150 7150 40 0000 C CNN 1 4150 6950 -1 0 0 -1 $EndComp @@ -949,7 +949,7 @@ L R_PACK4 RA112 U 1 1 4D96310C P 4150 4650 F 0 "RA112" H 4150 4600 40 0000 C CNN -F 1 "220" H 4150 4850 40 0000 C CNN +F 1 "100" H 4150 4850 40 0000 C CNN 1 4150 4650 1 0 0 -1 $EndComp @@ -958,7 +958,7 @@ L R_PACK4 RA111 U 1 1 4D96310A P 4150 4250 F 0 "RA111" H 4150 4700 40 0000 C CNN -F 1 "220" H 4150 4450 40 0000 C CNN +F 1 "100" H 4150 4450 40 0000 C CNN 1 4150 4250 -1 0 0 -1 $EndComp @@ -967,7 +967,7 @@ L R_PACK4 RA110 U 1 1 4D963107 P 4150 3650 F 0 "RA110" H 4150 3600 40 0000 C CNN -F 1 "220" H 4150 3850 40 0000 C CNN +F 1 "100" H 4150 3850 40 0000 C CNN 1 4150 3650 -1 0 0 -1 $EndComp @@ -976,7 +976,7 @@ L R_PACK4 RA109 U 1 1 4D963103 P 4150 3250 F 0 "RA109" H 4150 3700 40 0000 C CNN -F 1 "220" H 4150 3450 40 0000 C CNN +F 1 "100" H 4150 3450 40 0000 C CNN 1 4150 3250 -1 0 0 -1 $EndComp @@ -985,7 +985,7 @@ L R_PACK4 RA102 U 1 1 4D9630F4 P 12400 3750 F 0 "RA102" H 12400 3700 40 0000 C CNN -F 1 "220" H 12400 3950 40 0000 C CNN +F 1 "100" H 12400 3950 40 0000 C CNN 1 12400 3750 1 0 0 -1 $EndComp @@ -994,7 +994,7 @@ L R_PACK4 RA101 U 1 1 4D9630F0 P 12400 3350 F 0 "RA101" H 12400 3800 40 0000 C CNN -F 1 "220" H 12400 3550 40 0000 C CNN +F 1 "100" H 12400 3550 40 0000 C CNN 1 12400 3350 1 0 0 -1 $EndComp @@ -1005,7 +1005,7 @@ P 12400 4750 AR Path="/4B6E16F2/4D95CDCD" Ref="RP?" Part="1" AR Path="/4B6E16F2/4D95CDD4" Ref="RA104" Part="1" F 0 "RA104" H 12400 4650 40 0000 C CNN -F 1 "220" H 12400 4950 40 0000 C CNN +F 1 "FB" H 12400 4950 40 0000 C CNN 1 12400 4750 1 0 0 -1 $EndComp @@ -1014,7 +1014,7 @@ L R_PACK4 RA103 U 1 1 4D95CDCD P 12400 4350 F 0 "RA103" H 12400 4800 40 0000 C CNN -F 1 "220" H 12400 4550 40 0000 C CNN +F 1 "FB" H 12400 4550 40 0000 C CNN 1 12400 4350 1 0 0 -1 $EndComp From 9943eca29460edc16ca6818f27defee1bdd56ba7 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 10 Dec 2011 20:32:48 +0100 Subject: [PATCH 25/66] Firmware/bootloader: change CPU frequency from 92MHz to 96MHz --- src/bootldr/clock.c | 3 +-- src/bootldr/config.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/bootldr/clock.c b/src/bootldr/clock.c index f9a6a8b..d766ae6 100644 --- a/src/bootldr/clock.c +++ b/src/bootldr/clock.c @@ -48,8 +48,7 @@ void clock_init() { */ enableMainOsc(); setClkSrc(CLKSRC_MAINOSC); -// XXX setPLL0MultPrediv(429, 19); - setPLL0MultPrediv(23, 2); + setPLL0MultPrediv(12, 1); enablePLL0(); setCCLKDiv(3); connectPLL0(); diff --git a/src/bootldr/config.h b/src/bootldr/config.h index 88be1af..91f4a60 100644 --- a/src/bootldr/config.h +++ b/src/bootldr/config.h @@ -51,7 +51,7 @@ #define CONFIG_UART_NUM 3 // #define CONFIG_CPU_FREQUENCY 90315789 -#define CONFIG_CPU_FREQUENCY (92000000L) +#define CONFIG_CPU_FREQUENCY (96000000L) //#define CONFIG_CPU_FREQUENCY 46000000 #define CONFIG_UART_PCLKDIV 1 #define CONFIG_UART_TX_BUF_SHIFT 8 From e5285f819692a73cfd958204fdc6f12013270268 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 10 Dec 2011 20:33:52 +0100 Subject: [PATCH 26/66] Firmware/bootloader: reduce bootloader size to 8192 bytes --- src/bootldr/config.h | 6 +++--- src/bootldr/iap.c | 2 +- src/bootldr/lpc1754boot.ld | 2 +- src/bootldr/main.c | 7 ++++--- src/bootldr/uart.c | 10 +++++----- 5 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/bootldr/config.h b/src/bootldr/config.h index 91f4a60..3fde54b 100644 --- a/src/bootldr/config.h +++ b/src/bootldr/config.h @@ -1,7 +1,7 @@ #ifndef _CONFIG_H #define _CONFIG_H -#define DEBUG_BL +//#define DEBUG_BL // #define DEBUG_SD // #define DEBUG_IRQ @@ -19,7 +19,7 @@ #define DBG_BL while(0) #endif -#define FW_START (0x00003000L) +#define FW_START (0x00002000L) #define FLASH_SECTORS (17) @@ -56,7 +56,7 @@ #define CONFIG_UART_PCLKDIV 1 #define CONFIG_UART_TX_BUF_SHIFT 8 #define CONFIG_UART_BAUDRATE 921600 -#define CONFIG_UART_DEADLOCKABLE +//#define CONFIG_UART_DEADLOCKABLE #define SSP_CLK_DIVISOR_FAST 2 #define SSP_CLK_DIVISOR_SLOW 250 diff --git a/src/bootldr/iap.c b/src/bootldr/iap.c index 3fce3e9..4d23977 100644 --- a/src/bootldr/iap.c +++ b/src/bootldr/iap.c @@ -183,7 +183,7 @@ FLASH_RES flash_file(uint8_t *filename) { return ERR_FLASH; } } - if(total_read != file_header.size) { + if(total_read != (file_header.size + 0x100)) { DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size); DBG_UART uart_putc('X'); return ERR_FILECHK; diff --git a/src/bootldr/lpc1754boot.ld b/src/bootldr/lpc1754boot.ld index e0d8512..3ca18c6 100644 --- a/src/bootldr/lpc1754boot.ld +++ b/src/bootldr/lpc1754boot.ld @@ -10,7 +10,7 @@ ENTRY(_start) MEMORY { - flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x03000 + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000 ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x03fe0 /* leave room for IAP */ ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000 } diff --git a/src/bootldr/main.c b/src/bootldr/main.c index 6235cde..e19b8d6 100644 --- a/src/bootldr/main.c +++ b/src/bootldr/main.c @@ -29,7 +29,7 @@ int main(void) { SNES_CIC_PAIR_REG->FIODIR = BV(SNES_CIC_PAIR_BIT); BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1; /* LPC_GPIO2->FIODIR = BV(0) | BV(1) | BV(2); */ - LPC_GPIO0->FIODIR = BV(16); +// LPC_GPIO0->FIODIR = BV(16); /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */ LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */ @@ -50,7 +50,7 @@ int main(void) { writeled(0); /* do this last because the peripheral init()s change PCLK dividers */ clock_init(); - LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ +// LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ sdn_init(); DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28); DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY); @@ -61,7 +61,8 @@ DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP); LPC_TIM3->MCR=MR0R; LPC_TIM3->MR0=1; LPC_TIM3->TCR=1; - + NVIC->ICER[0] = 0xffffffff; + NVIC->ICER[1] = 0xffffffff; FLASH_RES res = flash_file((uint8_t*)"/sd2snes/firmware.img"); if(res == ERR_FLASHPREP || res == ERR_FLASHERASE || res == ERR_FLASH) { rdyled(0); diff --git a/src/bootldr/uart.c b/src/bootldr/uart.c index e4a1e83..15fee39 100644 --- a/src/bootldr/uart.c +++ b/src/bootldr/uart.c @@ -10,7 +10,7 @@ #include "uart.h" #include "led.h" -static uint8_t uart_lookupratio(float f_fr) { +/*static uint8_t uart_lookupratio(float f_fr) { uint16_t errors[72]={0,67,71,77,83,91,100,111,125, 133,143,154,167,182,200,214,222,231, 250,267,273,286,300,308,333,357,364, @@ -45,8 +45,8 @@ static uint8_t uart_lookupratio(float f_fr) { } return ratios[i_result]; } - -static uint32_t baud2divisor(unsigned int baudrate) { +*/ +/*static uint32_t baud2divisor(unsigned int baudrate) { uint32_t int_ratio; uint32_t error; uint32_t dl=0; @@ -73,7 +73,7 @@ static uint32_t baud2divisor(unsigned int baudrate) { return ((fract_ratio<<16)&0xff0000) | dl; } } - +*/ static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; static volatile unsigned int read_idx,write_idx; @@ -170,7 +170,7 @@ void uart_init(void) { /* set baud rate - no fractional stuff for now */ UART_REGS->LCR = BV(7) | 3; // always 8n1 - div = baud2divisor(CONFIG_UART_BAUDRATE); + div = 0x850004; // baud2divisor(CONFIG_UART_BAUDRATE); UART_REGS->DLL = div & 0xff; UART_REGS->DLM = (div >> 8) & 0xff; From a474ccf475ee521aa8320554b6d30cefe1d9ab72 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:03:01 +0100 Subject: [PATCH 27/66] Firmware/CLI: Add 'rm' command --- src/cli.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/cli.c b/src/cli.c index 3ddf70a..9c0c8e3 100644 --- a/src/cli.c +++ b/src/cli.c @@ -58,8 +58,8 @@ static char *curchar; /* Word lists */ static char command_words[] = - "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0"; -enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 }; + "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0"; +enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 }; /* ------------------------------------------------------------------------- */ /* Parse functions */ @@ -343,6 +343,11 @@ void cmd_put(void) { } } +void cmd_rm(void) { + FRESULT res = f_unlink(curchar); + if(res) printf("Error %d removing %s\n", res, curchar); +} + void cmd_mapper(void) { int32_t mapper; mapper = parse_unsigned(0,7,10); @@ -509,6 +514,10 @@ void cli_loop(void) { cmd_saveraw(); break; + case CMD_RM: + cmd_rm(); + break; + case CMD_D4: cmd_d4(); break; From 4a9d40b84151505b0b74f6b2707d5c23615f86ee Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:06:02 +0100 Subject: [PATCH 28/66] Firmware: update version number --- src/config | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/config b/src/config index 32d7be7..f1319e4 100644 --- a/src/config +++ b/src/config @@ -1,3 +1,4 @@ -CONFIG_VERSION=0.0.1 -CONFIG_FWVER=16777214 +CONFIG_VERSION=0.1.0 +#FWVER=000100 +CONFIG_FWVER=256 CONFIG_MCU_FOSC=12000000 From e880fac0ba88b82d84274485a860c40a09309476 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:07:41 +0100 Subject: [PATCH 29/66] Firmware: disable some debug messages --- src/filetypes.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/filetypes.c b/src/filetypes.c index 8c03d05..ad91bde 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -97,9 +97,9 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t if(next_subdir_tgt > dir_end) { dir_end = next_subdir_tgt; } - printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt); +// printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt); if(mkdb) { - printf("d=%d Saving %lx to Address %lx [end]\n", depth, 0L, next_subdir_tgt - 4); +// printf("d=%d Saving %lx to Address %lx [end]\n", depth, 0L, next_subdir_tgt - 4); sram_writelong(0L, next_subdir_tgt - 4); } } @@ -118,6 +118,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t db_tgt += 0x00010000; printf("new=%lx\n", db_tgt); } +// printf("writing link to parent, %lx to address %lx [../]\n", parent_tgt-SRAM_MENU_ADDR, db_tgt); sram_writelong((parent_tgt-SRAM_MENU_ADDR), db_tgt); sram_writebyte(0, db_tgt+sizeof(next_subdir_tgt)); sram_writeblock("../\0", db_tgt+sizeof(next_subdir_tgt)+sizeof(len), 4); From c97278c3d6fb3ed488d87266af9e6bf72d8dcd23 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:08:38 +0100 Subject: [PATCH 30/66] Firmware: adjust to reduced bootloader size --- src/flash.script | 2 +- src/lpc1754.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/flash.script b/src/flash.script index 969235c..916fd81 100644 --- a/src/flash.script +++ b/src/flash.script @@ -6,7 +6,7 @@ #flash info 0 reset init -flash write_image erase unlock obj/firmware.img 12288 +flash write_image erase unlock obj/firmware.img 8192 reset run shutdown diff --git a/src/lpc1754.ld b/src/lpc1754.ld index 69ac4e6..a470fba 100644 --- a/src/lpc1754.ld +++ b/src/lpc1754.ld @@ -10,7 +10,7 @@ ENTRY(_start) MEMORY { - flash (rx) : ORIGIN = 0x00003100, LENGTH = 0x1cf00 /* leave room for bootldr + metadata */ + flash (rx) : ORIGIN = 0x00002100, LENGTH = 0x1df00 /* leave room for bootldr + metadata */ ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x04000 ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000 } From 39b78ae91c87b2a50ab16d5426634ddbc00e712a Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:16:31 +0100 Subject: [PATCH 31/66] Firmware: SD debugging + minor cleanups --- src/ff.c | 3 --- src/fpga_spi.c | 3 +++ src/sdnative.c | 5 +++++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ff.c b/src/ff.c index 2d7862a..bcd68c1 100644 --- a/src/ff.c +++ b/src/ff.c @@ -2198,7 +2198,6 @@ FRESULT f_read ( #if !_FS_TINY #if !_FS_READONLY if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ -printf("DIRTY!?!\n"); if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) ABORT(fp->fs, FR_DISK_ERR); fp->flag &= ~FA__DIRTY; @@ -2222,7 +2221,6 @@ printf("DIRTY!?!\n"); mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ #else mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ - printf("final mem_cpy, rcnt=%d, rbuff-buff=%d\n", rcnt, (void*)rbuff-buff); } else { sd_offload_partial_start = fp->fptr % SS(fp->fs); sd_offload_partial_end = sd_offload_partial_start + rcnt; @@ -2376,7 +2374,6 @@ FRESULT f_sync ( res = validate(fp->fs, fp->id); /* Check validity of the object */ if (res == FR_OK) { if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ -printf("DIRTY?!?!?!\n"); #if !_FS_TINY /* Write-back dirty buffer */ if (fp->flag & FA__DIRTY) { if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) diff --git a/src/fpga_spi.c b/src/fpga_spi.c index ed315ad..ebdf7c5 100644 --- a/src/fpga_spi.c +++ b/src/fpga_spi.c @@ -133,6 +133,7 @@ #include "spi.h" #include "fpga_spi.h" #include "timer.h" +#include "sdnative.h" void fpga_spi_init(void) { spi_init(SPI_SPEED_FAST); @@ -230,10 +231,12 @@ void fpga_sddma(uint8_t tgt, uint8_t partial) { FPGA_SELECT(); FPGA_TX_BYTE(0xF1); /* STATUS */ FPGA_TX_BYTE(0x00); /* dummy */ + DBG_SD printf("FPGA DMA request sent, wait for completion..."); while((status=FPGA_RX_BYTE()) & 0x80) { FPGA_RX_BYTE(); /* eat the 2nd status byte */ test++; } + DBG_SD printf("...complete\n"); FPGA_DESELECT(); if(test<5)printf("loopy: %ld %02x\n", test, status); BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1; diff --git a/src/sdnative.c b/src/sdnative.c index 76218b9..474ebdb 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -449,9 +449,11 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){ j=datcnt; datshift=8; DBG_SD printf("response over, waiting for data...\n"); + /* wait for data start bit on DAT0 */ while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { wiggle_fast_neg1(); } + DBG_SD if(!timeout) printf("timed out!\n"); wiggle_fast_neg1(); /* eat the start bit */ if(sd_offload) { if(sd_offload_partial) { @@ -588,9 +590,12 @@ int stream_datablock(uint8_t *buf) { uint8_t datdata=0; uint32_t timeout=1000000; + DBG_SD printf("stream_datablock: wait for ready...\n"); while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { wiggle_fast_neg1(); } + DBG_SD if(!timeout) printf("timeout!\n"); + wiggle_fast_neg1(); /* eat the start bit */ if(sd_offload) { if(sd_offload_partial) { From d65d657ff71b8e48cad323c9e279af6fc65e6ec6 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:18:09 +0100 Subject: [PATCH 32/66] Firmware: increase ROM space for directory structure --- src/memory.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/memory.h b/src/memory.h index c2018f4..321563d 100644 --- a/src/memory.h +++ b/src/memory.h @@ -34,7 +34,7 @@ #define SRAM_SAVE_ADDR (0xE00000L) #define SRAM_MENU_ADDR (0xE00000L) -#define SRAM_DB_ADDR (0xE20000L) +#define SRAM_DB_ADDR (0xE40000L) #define SRAM_DIR_ADDR (0xE10000L) #define SRAM_CMD_ADDR (0xFF1000L) #define SRAM_PARAM_ADDR (0xFF1004L) From 37a9f09a7838b7d80f701b213e2a82edcc72a9bf Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 16 Dec 2011 19:19:51 +0100 Subject: [PATCH 33/66] Menu: simplify some memory accesses --- snes/data.a65 | 12 ++++++------ snes/menu.a65 | 52 +++++++++++++++++++++------------------------------ 2 files changed, 27 insertions(+), 37 deletions(-) diff --git a/snes/data.a65 b/snes/data.a65 index 0147868..df04d5d 100644 --- a/snes/data.a65 +++ b/snes/data.a65 @@ -1,15 +1,15 @@ .data ;don't anger the stack! dirptr_addr .word 0 -dirptr_bank .byt 0 +dirptr_bank .word 0 dirstart_addr .word 0 -dirstart_bank .byt 0 -dirend_addr .word 0 -dirend_bank .byt 0 +dirstart_bank .word 0 +dirend_addr .word 0 +dirend_bank .word 0 dirend_idx .word 0 dirptr_idx .word 0 -dirent_addr .word 0 -dirent_bank .byt 0 +dirent_addr .word 0 +dirent_bank .word 0 dirent_type .byt 0 dirend_onscreen .byt 0 dirlog_idx .byt 0,0,0 ; long ptr diff --git a/snes/menu.a65 b/snes/menu.a65 index d6d065d..d648f45 100644 --- a/snes/menu.a65 +++ b/snes/menu.a65 @@ -188,32 +188,26 @@ redraw_filelist_loop lsr cmp listdisp beq redraw_filelist_last - lda dirptr_bank - phb - pha - plb rep #$20 : .al - lda (dirptr_addr), y + lda [dirptr_addr], y sta @dirent_addr iny iny sep #$20 : .as - lda (dirptr_addr), y ; load fileinfo bank + lda [dirptr_addr], y ; load fileinfo bank clc adc #$c0 ; add $C0 for memory map sta @dirent_bank ; store as current bank cmp #$c0 ; if bank was 0 -> dirend entry in DB beq redraw_filelist_dirend ; handle dirend iny - lda (dirptr_addr), y + lda [dirptr_addr], y iny sta @dirent_type - plb sty dirptr_idx jsr print_direntry bra redraw_filelist_loop redraw_filelist_dirend - plb dey ; recover last valid direntry number dey ; (we had 2x iny of the direntry pointer above, dey ; so account for those too) @@ -225,15 +219,10 @@ redraw_filelist_dirend sta dirend_onscreen bra redraw_filelist_out redraw_filelist_last ;check if next offscreen item is end of dir - lda dirptr_bank - phb - pha - plb iny iny - lda (dirptr_addr), y + lda [dirptr_addr], y beq redraw_filelist_dirend - plb redraw_filelist_out ldx #$0000 stx dirptr_idx @@ -352,7 +341,7 @@ menu_key_down: lda listdisp dec cmp menu_sel - bne + + bne down_noscroll lda #$01 sta menu_dirty lda dirend_onscreen @@ -361,10 +350,13 @@ menu_key_down: lda dirptr_addr clc adc #$04 - sta dirptr_addr + bcc + + inc dirptr_bank ++ sta dirptr_addr sep #$20 : .as rts -+ lda dirend_onscreen +down_noscroll + lda dirend_onscreen beq + lda dirend_idx lsr @@ -380,7 +372,7 @@ down_out menu_key_up: lda menu_sel - bne + + bne up_noscroll lda #$01 sta menu_dirty rep #$20 : .al @@ -389,9 +381,12 @@ menu_key_up: beq up_out sec sbc #$04 - sta dirptr_addr + bcs + + dec dirptr_bank ++ sta dirptr_addr bra up_out -+ dec +up_noscroll + dec sta menu_sel up_out sep #$20 : .as @@ -480,14 +475,10 @@ select_item: asl tay sep #$20 : .as - lda dirptr_bank - phb - pha - plb iny iny iny - lda (dirptr_addr), y + lda [dirptr_addr], y cmp #$01 beq sel_is_file cmp #$04 @@ -497,7 +488,6 @@ select_item: cmp #$81 beq sel_is_parent select_item_cont - plb rts sel_is_file jsr select_file @@ -513,12 +503,12 @@ select_file: ; have avr load the rom dey rep #$20 : .al - lda (dirptr_addr), y + lda [dirptr_addr], y and #$00ff sta @AVR_PARAM+2 dey dey - lda (dirptr_addr), y + lda [dirptr_addr], y sta @AVR_PARAM sep #$20 : .as lda #$01 @@ -559,14 +549,14 @@ select_dir: ; y = direntry ptr txy dey - lda (dirptr_addr), y + lda [dirptr_addr], y clc adc #$c0 sta @dirent_bank dey dey rep #$20 : .al - lda (dirptr_addr), y + lda [dirptr_addr], y sta @dirent_addr tax sep #$20 : .as From 72642321a2b60efa142af52e010809c7305d1146 Mon Sep 17 00:00:00 2001 From: ikari Date: Sun, 18 Dec 2011 18:41:00 +0100 Subject: [PATCH 34/66] SuperCIC/key: fix unreliable pair mode entry (sync with lock) --- cic/supercic/supercic-key.asm | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/cic/supercic/supercic-key.asm b/cic/supercic/supercic-key.asm index 471599d..c9927de 100644 --- a/cic/supercic/supercic-key.asm +++ b/cic/supercic/supercic-key.asm @@ -64,6 +64,7 @@ processor p12f629 ; 0x4d buffer for eeprom access ; 0x4e loop variable for longwait ; 0x4f loop variable for wait +; 0x5c GPIO buffer variable for pair mode allow ; 0x5d 0: SuperCIC pair mode available flag ; 0x5e SuperCIC pair mode detect (phase 1) ; 0x5f SuperCIC pair mode detect (phase 2) @@ -90,8 +91,8 @@ isr clrf 0x5f ; clear pair mode detect bsf 0x5f, 1 ; clrf 0x5d ; clear pair mode available - nop - nop + clrf 0x5c ; clear pair mode allow buffer + bsf 0x5c, 3 ; assume disallow bsf INTCON, 7 ; re-enable interrupts (ISR will continue as main) goto main init @@ -296,8 +297,8 @@ swapskip ; indirect access, no post increment, etc. mangle call mangle_lock - nop - nop + movf GPIO, w ; buffer GPIO state + movwf 0x5c ; for pair mode "transaction" mangle_key movf 0x2f, w movwf 0x20 @@ -459,7 +460,7 @@ mangle_key_withskip ;-------pair mode code------- bcf GPIO, 0 movf GPIO, w - btfss GPIO, 3 + btfss 0x5c, 3 bsf GPIO, 0 movwf 0x5e movf GPIO, w @@ -642,7 +643,7 @@ mangle_lock_withskip goto scic_pair_skip1 btfsc 0x5f, 1 goto scic_pair_skip2 - btfsc GPIO, 3 + btfsc 0x5c, 3 goto scic_pair_skip3 goto supercic_pairmode scic_pair_skip1 From 0a6c7f125b694dd4e77e3f907bc90c3f65a58cb2 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 19 Dec 2011 22:17:49 +0100 Subject: [PATCH 35/66] Firmware: add test suite --- src/tests/Makefile | 318 ++++ src/tests/bits.h | 21 + src/tests/ccsbcs.c | 540 ++++++ src/tests/cic.c | 76 + src/tests/cic.h | 23 + src/tests/cli.c | 576 ++++++ src/tests/cli.h | 34 + src/tests/clock.c | 109 ++ src/tests/clock.h | 79 + src/tests/conf2h.awk | 29 + src/tests/config | 4 + src/tests/config.h | 97 + src/tests/crc.S | 92 + src/tests/crc.h | 11 + src/tests/crc32.c | 110 ++ src/tests/crc32.h | 68 + src/tests/diskio.h | 118 ++ src/tests/faulthandler.c | 20 + src/tests/ff.c | 3805 +++++++++++++++++++++++++++++++++++++ src/tests/ff.h | 547 ++++++ src/tests/ffconf.h | 188 ++ src/tests/fileops.c | 117 ++ src/tests/fileops.h | 54 + src/tests/filetypes.c | 315 +++ src/tests/filetypes.h | 58 + src/tests/flash.cfg | 4 + src/tests/flash.script | 12 + src/tests/fpga.c | 143 ++ src/tests/fpga.h | 68 + src/tests/fpga_spi.c | 528 +++++ src/tests/fpga_spi.h | 104 + src/tests/integer.h | 37 + src/tests/irq.c | 15 + src/tests/led.c | 145 ++ src/tests/led.h | 21 + src/tests/lpc1754.cfg | 77 + src/tests/lpc1754.ld | 131 ++ src/tests/main.c | 164 ++ src/tests/memory.c | 547 ++++++ src/tests/memory.h | 71 + src/tests/msu1.c | 256 +++ src/tests/msu1.h | 15 + src/tests/openocd-usb.cfg | 12 + src/tests/power.c | 26 + src/tests/power.h | 43 + src/tests/printf.c | 291 +++ src/tests/reset.cfg | 3 + src/tests/rle.c | 66 + src/tests/rle.h | 17 + src/tests/rtc.c | 135 ++ src/tests/rtc.h | 78 + src/tests/sdcard.h | 46 + src/tests/sdnative.c | 1015 ++++++++++ src/tests/sdnative.h | 29 + src/tests/smc.c | 252 +++ src/tests/smc.h | 79 + src/tests/snes.c | 174 ++ src/tests/snes.h | 48 + src/tests/sort.c | 122 ++ src/tests/sort.h | 15 + src/tests/spi.c | 213 +++ src/tests/spi.h | 68 + src/tests/startup.S | 101 + src/tests/tests.h | 27 + src/tests/timer.c | 133 ++ src/tests/timer.h | 51 + src/tests/uart.c | 288 +++ src/tests/uart.h | 49 + src/tests/xmodem.c | 37 + src/tests/xmodem.h | 14 + 70 files changed, 13179 insertions(+) create mode 100644 src/tests/Makefile create mode 100644 src/tests/bits.h create mode 100644 src/tests/ccsbcs.c create mode 100644 src/tests/cic.c create mode 100644 src/tests/cic.h create mode 100644 src/tests/cli.c create mode 100644 src/tests/cli.h create mode 100644 src/tests/clock.c create mode 100644 src/tests/clock.h create mode 100644 src/tests/conf2h.awk create mode 100644 src/tests/config create mode 100644 src/tests/config.h create mode 100644 src/tests/crc.S create mode 100644 src/tests/crc.h create mode 100644 src/tests/crc32.c create mode 100644 src/tests/crc32.h create mode 100644 src/tests/diskio.h create mode 100644 src/tests/faulthandler.c create mode 100644 src/tests/ff.c create mode 100644 src/tests/ff.h create mode 100644 src/tests/ffconf.h create mode 100644 src/tests/fileops.c create mode 100644 src/tests/fileops.h create mode 100644 src/tests/filetypes.c create mode 100644 src/tests/filetypes.h create mode 100644 src/tests/flash.cfg create mode 100644 src/tests/flash.script create mode 100644 src/tests/fpga.c create mode 100644 src/tests/fpga.h create mode 100644 src/tests/fpga_spi.c create mode 100644 src/tests/fpga_spi.h create mode 100644 src/tests/integer.h create mode 100644 src/tests/irq.c create mode 100644 src/tests/led.c create mode 100644 src/tests/led.h create mode 100644 src/tests/lpc1754.cfg create mode 100644 src/tests/lpc1754.ld create mode 100644 src/tests/main.c create mode 100644 src/tests/memory.c create mode 100644 src/tests/memory.h create mode 100644 src/tests/msu1.c create mode 100644 src/tests/msu1.h create mode 100644 src/tests/openocd-usb.cfg create mode 100644 src/tests/power.c create mode 100644 src/tests/power.h create mode 100644 src/tests/printf.c create mode 100644 src/tests/reset.cfg create mode 100644 src/tests/rle.c create mode 100644 src/tests/rle.h create mode 100644 src/tests/rtc.c create mode 100644 src/tests/rtc.h create mode 100644 src/tests/sdcard.h create mode 100644 src/tests/sdnative.c create mode 100644 src/tests/sdnative.h create mode 100644 src/tests/smc.c create mode 100644 src/tests/smc.h create mode 100644 src/tests/snes.c create mode 100644 src/tests/snes.h create mode 100644 src/tests/sort.c create mode 100644 src/tests/sort.h create mode 100644 src/tests/spi.c create mode 100644 src/tests/spi.h create mode 100644 src/tests/startup.S create mode 100644 src/tests/tests.h create mode 100644 src/tests/timer.c create mode 100644 src/tests/timer.h create mode 100644 src/tests/uart.c create mode 100644 src/tests/uart.h create mode 100644 src/tests/xmodem.c create mode 100644 src/tests/xmodem.h diff --git a/src/tests/Makefile b/src/tests/Makefile new file mode 100644 index 0000000..ec89962 --- /dev/null +++ b/src/tests/Makefile @@ -0,0 +1,318 @@ +# Hey Emacs, this is a -*- makefile -*- + +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Joerg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +# +# Extensively modified for sd2iec and later adapted for ARM by Ingo Korb +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + +# Read configuration file +ifdef CONFIG + CONFIGSUFFIX = $(CONFIG:config%=%) +else + CONFIG = config + CONFIGSUFFIX = +endif + +# Enable verbose compilation with "make V=1" +ifdef V + Q := + E := @: +else + Q := @ + E := @echo +endif + +# Include the configuration file +include $(CONFIG) + +# Directory for all generated files +OBJDIR := obj$(CONFIGSUFFIX) + +# Output format. (can be srec, ihex, binary) +FORMAT = binary + +# Linker script +LINKERSCRIPT = lpc1754.ld + +# Target file name (without extension). +TARGET = $(OBJDIR)/sd2snes + + +# List C source files here. (C dependencies are automatically generated.) +SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c tests.c + +# usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = startup.S crc.S + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +# Use s -mcall-prologues when you really need size... +#OPT = 2 +OPT = 2 + +# Debugging format. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here +CDEFS = -DF_OSC=$(CONFIG_MCU_FOSC)UL + + +# Place -I options here +CINCS = + + +# CPU-specific flags +ifndef CPUFLAGS + CPUFLAGS := -mthumb -mcpu=cortex-m3 +endif + +ifndef ARCH + ARCH := arm-none-eabi +endif + +# Define programs and commands. +# CC must be defined here to generate the correct CFLAGS +SHELL = sh +CC = $(ARCH)-gcc +OBJCOPY = $(ARCH)-objcopy +OBJDUMP = $(ARCH)-objdump +SIZE = $(ARCH)-size +NM = $(ARCH)-nm +REMOVE = rm -f +COPY = cp +AWK = awk + + +#---------------- Compiler Options ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += $(CPUFLAGS) -nostartfiles +#CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums +CFLAGS += -Wall -Wstrict-prototypes -Werror +CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst) +CFLAGS += -I$(OBJDIR) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) +CFLAGS += -ffunction-sections -fdata-sections + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +ASFLAGS = $(CPUFLAGS) -Wa,-adhlns=$(OBJDIR)/$(<:.S=.lst),-gstabs -I$(OBJDIR) + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += -T$(LINKERSCRIPT) +LDFLAGS += -Wl,--gc-sections +ifeq ($(CONFIG_LINKER_RELAX),y) + LDFLAGS += -Wl,-O9,--relax +endif + + +#============================================================================ + + +# De-dupe the list of C source files +CSRC := $(sort $(SRC)) + +# Define all object files. +OBJ := $(patsubst %,$(OBJDIR)/%,$(CSRC:.c=.o) $(ASRC:.S=.o)) + +# Define all listing files. +LST := $(patsubst %,$(OBJDIR)/%,$(CSRC:.c=.lst) $(ASRC:.S=.lst)) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -I. -x assembler-with-cpp $(ASFLAGS) $(CDEFS) + + + + + +# Default target. +all: build + +build: elf bin hex + $(E) " SIZE $(TARGET).elf" + $(Q)$(ELFSIZE)|grep -v debug + cp $(TARGET).bin $(OBJDIR)/firmware.img + utils/genhdr $(OBJDIR)/firmware.img SNSD $(CONFIG_FWVER) + +elf: $(TARGET).elf +bin: $(TARGET).bin +hex: $(TARGET).hex +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym + +# # A little helper target for the maintainer =) +# copy2card: +# cp $(TARGET).bin /mbed/hw_LPC1768.bin + + +program: build + utils/lpcchksum $(TARGET).bin + openocd -f openocd-usb.cfg -f lpc1754.cfg -f flash.cfg + +debug: build + openocd -f openocd-usb.cfg -f lpc1754.cfg + +reset: + openocd -f openocd-usb.cfg -f lpc1754.cfg -f reset.cfg + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf + + + +# Generate autoconf.h from config +.PRECIOUS : $(OBJDIR)/autoconf.h +$(OBJDIR)/autoconf.h: $(CONFIG) | $(OBJDIR) + $(E) " CONF2H $(CONFIG)" + $(Q)$(AWK) -f conf2h.awk $(CONFIG) > $(OBJDIR)/autoconf.h + +# Create final output files from ELF output file. +$(OBJDIR)/%.bin: $(OBJDIR)/%.elf + $(E) " BIN $@" + $(Q)$(OBJCOPY) -O binary $< $@ + +$(OBJDIR)/%.hex: $(OBJDIR)/%.elf + $(E) " HEX $@" + $(Q)$(OBJCOPY) -O $(FORMAT) $< $@ + +# Create extended listing file from ELF output file. +$(OBJDIR)/%.lss: $(OBJDIR)/%.elf + $(E) " LSS $<" + $(Q)$(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +$(OBJDIR)/%.sym: $(OBJDIR)/%.elf + $(E) " SYM $<" + $(E)$(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +$(TARGET).elf : $(OBJ) + $(E) " LINK $@" + $(Q)$(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c | $(OBJDIR) $(OBJDIR)/autoconf.h + $(E) " CC $<" + $(Q)$(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +$(OBJDIR)/%.s : %.c | $(OBJDIR) $(OBJDIR)/autoconf.h + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S | $(OBJDIR) $(OBJDIR)/autoconf.h + $(E) " AS $<" + $(Q)$(CC) -c $(ALL_ASFLAGS) $< -o $@ + +# Create preprocessed source for use in sending a bug report. +$(OBJDIR)/%.i : %.c | $(OBJDIR) $(OBJDIR)/autoconf.h + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + +# Create the output directory +$(OBJDIR) : + $(E) " MKDIR $(OBJDIR)" + $(Q)mkdir $(OBJDIR) + +# Target: clean project. +clean: begin clean_list end + +clean_list : + $(E) " CLEAN" + $(Q)$(REMOVE) $(TARGET).hex + $(Q)$(REMOVE) $(TARGET).bin + $(Q)$(REMOVE) $(TARGET).elf + $(Q)$(REMOVE) $(TARGET).map + $(Q)$(REMOVE) $(TARGET).sym + $(Q)$(REMOVE) $(TARGET).lss + $(Q)$(REMOVE) $(OBJ) + $(Q)$(REMOVE) $(OBJDIR)/autoconf.h + $(Q)$(REMOVE) $(OBJDIR)/*.bin + $(Q)$(REMOVE) $(LST) + $(Q)$(REMOVE) $(CSRC:.c=.s) + $(Q)$(REMOVE) $(CSRC:.c=.d) + $(Q)$(REMOVE) .dep/* + -$(Q)rmdir $(OBJDIR) + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter \ +build elf hex lss sym clean clean_list diff --git a/src/tests/bits.h b/src/tests/bits.h new file mode 100644 index 0000000..5055737 --- /dev/null +++ b/src/tests/bits.h @@ -0,0 +1,21 @@ +#ifndef _ARM_BITS_H +#define _ARM_BITS_H + +/* The classic macro */ +#define BV(x) (1<<(x)) + +/* CM3 bit-band access macro - no error checks! */ +#define BITBAND(addr,bit) \ + (*((volatile unsigned long *)( \ + ((unsigned long)&(addr) & 0x01ffffff)*32 + \ + (bit)*4 + 0x02000000 + ((unsigned long)&(addr) & 0xfe000000) \ + ))) + +#define BITBAND_OFF(addr,offset,bit) \ + (*((volatile unsigned long *)( \ + (((unsigned long)&(addr) + offset) & 0x01ffffff)*32 + \ + (bit)*4 + 0x02000000 + (((unsigned long)&(addr) + offset) & 0xfe000000) \ + ))) + + +#endif diff --git a/src/tests/ccsbcs.c b/src/tests/ccsbcs.c new file mode 100644 index 0000000..eb0ab4e --- /dev/null +++ b/src/tests/ccsbcs.c @@ -0,0 +1,540 @@ +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "../ff.h" + + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration. Remove from the project. +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR src, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (src < 0x80) { /* ASCII */ + c = src; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (src >= 0x100) ? 0 : Tbl[src - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (src == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + + +WCHAR ff_wtoupper ( /* Upper converted character */ + WCHAR chr /* Input character */ +) +{ + static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 }; + static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 }; + int i; + + + for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ; + + return tbl_lower[i] ? tbl_upper[i] : chr; +} diff --git a/src/tests/cic.c b/src/tests/cic.c new file mode 100644 index 0000000..20c7628 --- /dev/null +++ b/src/tests/cic.c @@ -0,0 +1,76 @@ +#include +#include "bits.h" +#include "config.h" +#include "uart.h" +#include "cic.h" + +char *cicstatenames[4] = { "CIC_OK", "CIC_FAIL", "CIC_PAIR", "CIC_SCIC" }; + +void print_cic_state() { + printf("CIC state: %s\n", get_cic_statename(get_cic_state())); +} + +inline char *get_cic_statename(enum cicstates state) { + return cicstatenames[state]; +} + +enum cicstates get_cic_state() { + uint32_t count; + uint32_t togglecount = 0; + uint8_t state, state_old; + + state_old = BITBAND(SNES_CIC_STATUS_REG->FIOPIN, SNES_CIC_STATUS_BIT); +/* this loop samples at ~10MHz */ + for(count=0; countFIOPIN, SNES_CIC_STATUS_BIT); + if(state != state_old) { + togglecount++; + } + state_old = state; + } +/* CIC_TOGGLE_THRESH_PAIR > CIC_TOGGLE_THRESH_SCIC */ + if(togglecount > CIC_TOGGLE_THRESH_PAIR) { + return CIC_PAIR; + } else if(togglecount > CIC_TOGGLE_THRESH_SCIC) { + return CIC_SCIC; + } else if(state) { + return CIC_OK; + } else return CIC_FAIL; +} + +void cic_init(int allow_pairmode) { + BITBAND(SNES_CIC_PAIR_REG->FIODIR, SNES_CIC_PAIR_BIT) = 1; + if(allow_pairmode) { + BITBAND(SNES_CIC_PAIR_REG->FIOCLR, SNES_CIC_PAIR_BIT) = 1; + } else { + BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1; + } + BITBAND(SNES_CIC_D0_REG->FIODIR, SNES_CIC_D0_BIT) = 0; + BITBAND(SNES_CIC_D1_REG->FIODIR, SNES_CIC_D1_BIT) = 0; +} + +/* prepare GPIOs for pair mode + set initial modes */ +void cic_pair(int init_vmode, int init_d4) { + cic_videomode(init_vmode); + cic_d4(init_d4); + + BITBAND(SNES_CIC_D0_REG->FIODIR, SNES_CIC_D0_BIT) = 1; + BITBAND(SNES_CIC_D1_REG->FIODIR, SNES_CIC_D1_BIT) = 1; +} + +void cic_videomode(int value) { + if(value) { + BITBAND(SNES_CIC_D0_REG->FIOSET, SNES_CIC_D0_BIT) = 1; + } else { + BITBAND(SNES_CIC_D0_REG->FIOCLR, SNES_CIC_D0_BIT) = 1; + } +} + +void cic_d4(int value) { + if(value) { + BITBAND(SNES_CIC_D1_REG->FIOSET, SNES_CIC_D1_BIT) = 1; + } else { + BITBAND(SNES_CIC_D1_REG->FIOCLR, SNES_CIC_D1_BIT) = 1; + } +} + diff --git a/src/tests/cic.h b/src/tests/cic.h new file mode 100644 index 0000000..03e0648 --- /dev/null +++ b/src/tests/cic.h @@ -0,0 +1,23 @@ +#ifndef _CIC_H +#define _CIC_H + +#define CIC_SAMPLECOUNT (100000) +#define CIC_TOGGLE_THRESH_PAIR (2500) +#define CIC_TOGGLE_THRESH_SCIC (10) + +#include +#include "bits.h" + +enum cicstates { CIC_OK = 0, CIC_FAIL, CIC_PAIR, CIC_SCIC }; +enum cic_region { CIC_NTSC = 0, CIC_PAL }; + +void print_cic_state(void); +char *get_cic_statename(enum cicstates state); +enum cicstates get_cic_state(void); +void cic_init(int allow_pairmode); + +void cic_pair(int init_vmode, int init_d4); +void cic_videomode(int value); +void cic_d4(int value); + +#endif diff --git a/src/tests/cli.c b/src/tests/cli.c new file mode 100644 index 0000000..57af456 --- /dev/null +++ b/src/tests/cli.c @@ -0,0 +1,576 @@ +/* tapplay - TAP file playback for sd2iec hardware + Copyright (C) 2009 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + cli.c: The command line interface + +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "config.h" +#include "diskio.h" +#include "ff.h" +#include "timer.h" +#include "uart.h" +#include "fileops.h" +#include "memory.h" +#include "snes.h" +#include "fpga.h" +#include "fpga_spi.h" +#include "cic.h" +#include "xmodem.h" +#include "rtc.h" + +#include "cli.h" + +#define MAX_LINE 250 + +/* Variables */ +static char cmdbuffer[MAX_LINE+1]; +static char *curchar; + +/* Word lists */ +static char command_words[] = + "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0memsel\0"; +enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16, CMD_MEMSEL }; + +/* ------------------------------------------------------------------------- */ +/* Parse functions */ +/* ------------------------------------------------------------------------- */ + +/* Skip spaces at curchar */ +static uint8_t skip_spaces(void) { + uint8_t res = (*curchar == ' ' || *curchar == 0); + + while (*curchar == ' ') + curchar++; + + return res; +} + +/* Parse the string in curchar for an integer with bounds [lower,upper] */ +static int32_t parse_unsigned(uint32_t lower, uint32_t upper, uint8_t base) { + char *end; + uint32_t result; + + if (strlen(curchar) == 1 && *curchar == '?') { + printf("Number between %ld[0x%lx] and %ld[0x%lx] expected\n",lower,lower,upper,upper); + return -2; + } + + result = strtoul(curchar, &end, base); + if ((*end != ' ' && *end != 0) || errno != 0) { + printf("Invalid numeric argument\n"); + return -1; + } + + curchar = end; + skip_spaces(); + + if (result < lower || result > upper) { + printf("Numeric argument out of range (%ld..%ld)\n",lower,upper); + return -1; + } + + return result; +} +/* Parse the string starting with curchar for a word in wordlist */ +static int8_t parse_wordlist(char *wordlist) { + uint8_t i, matched; + char *cur, *ptr; + char c; + + i = 0; + ptr = wordlist; + + // Command list on "?" + if (strlen(curchar) == 1 && *curchar == '?') { + printf("Commands available: \n "); + while (1) { + c = *ptr++; + if (c == 0) { + if (*ptr == 0) { + printf("\n"); + return -2; + } else { + printf("\n "); + } + } else + uart_putc(c); + } + } + + while (1) { + cur = curchar; + matched = 1; + c = *ptr; + do { + // If current word list character is \0: No match found + if (c == 0) { + printf("Unknown word: %s\n",curchar); + return -1; + } + + if (tolower(c) != tolower(*cur)) { + // Check for end-of-word + if (cur != curchar && (*cur == ' ' || *cur == 0)) { + // Partial match found, return that + break; + } else { + matched = 0; + break; + } + } + ptr++; + cur++; + c = *ptr; + } while (c != 0); + + if (matched) { + char *tmp = curchar; + + curchar = cur; + // Return match only if whitespace or end-of-string follows + // (avoids mismatching partial words) + if (skip_spaces()) { + return i; + } else { + printf("Unknown word: %s\n(use ? for help)\n",tmp); + return -1; + } + } else { + // Try next word in list + i++; + while (*ptr++ != 0) ; + } + } +} + +/* Read a line from serial, uses cmdbuffer as storage */ +static char *getline(char *prompt) { + int i=0; + char c; + + printf("\n%s",prompt); + memset(cmdbuffer,0,sizeof(cmdbuffer)); + + while (1) { + c = uart_getc(); + if (c == 13) + break; + + if (c == 27 || c == 3) { + printf("\\\n%s",prompt); + i = 0; + memset(cmdbuffer,0,sizeof(cmdbuffer)); + continue; + } + + if (c == 127 || c == 8) { + if (i > 0) { + i--; + uart_putc(8); // backspace + uart_putc(' '); // erase character + uart_putc(8); // backspace + } else + continue; + } else { + if (i < sizeof(cmdbuffer)-1) { + cmdbuffer[i++] = c; + uart_putc(c); + } + } + } + cmdbuffer[i] = 0; + return cmdbuffer; +} + + +/* ------------------------------------------------------------------------- */ +/* Command functions */ +/* ------------------------------------------------------------------------- */ + +/* Reset */ +static void cmd_reset(void) { + /* force watchdog reset */ + LPC_WDT->WDTC = 256; // minimal timeout + LPC_WDT->WDCLKSEL = BV(31); // internal RC, lock register + LPC_WDT->WDMOD = BV(0) | BV(1); // enable watchdog and reset-by-watchdog + LPC_WDT->WDFEED = 0xaa; + LPC_WDT->WDFEED = 0x55; // initial feed to really enable WDT +} + +/* Show the contents of the current directory */ +static void cmd_show_directory(void) { + FRESULT res; + DIR dh; + FILINFO finfo; + uint8_t *name; + + f_getcwd((TCHAR*)file_lfn, 255); + + res = f_opendir(&dh, (TCHAR*)file_lfn); + if (res != FR_OK) { + printf("f_opendir failed, result %d\n",res); + return; + } + + finfo.lfname = (TCHAR*)file_lfn; + finfo.lfsize = 255; + + do { + /* Read the next entry */ + res = f_readdir(&dh, &finfo); + if (res != FR_OK) { + printf("f_readdir failed, result %d\n",res); + return; + } + + /* Abort if none was found */ + if (!finfo.fname[0]) + break; + + /* Skip volume labels */ + if (finfo.fattrib & AM_VOL) + continue; + + /* Select between LFN and 8.3 name */ + if (finfo.lfname[0]) + name = (uint8_t*)finfo.lfname; + else { + name = (uint8_t*)finfo.fname; + strlwr((char *)name); + } + + printf("%s",name); + + /* Directory indicator (Unix-style) */ + if (finfo.fattrib & AM_DIR) + uart_putc('/'); + + printf("\n"); + } while (finfo.fname[0]); +} + + +static void cmd_loadrom(void) { + uint32_t address = 0; + uint8_t flags = LOADROM_WITH_SRAM | LOADROM_WITH_RESET; + load_rom((uint8_t*)curchar, address, flags); +} + +static void cmd_loadraw(void) { + uint32_t address = parse_unsigned(0,16777216,16); + load_sram((uint8_t*)curchar, address); +} + +static void cmd_saveraw(void) { + uint32_t address = parse_unsigned(0,16777216,16); + uint32_t length = parse_unsigned(0,16777216,16); + save_sram((uint8_t*)curchar, length, address); +} + +static void cmd_d4(void) { + int32_t hz; + + if(get_cic_state() != CIC_PAIR) { + printf("not in pair mode\n"); + } else { + hz = parse_unsigned(50,60,10); + if(hz==50) { + cic_d4(CIC_PAL); + } else { + cic_d4(CIC_NTSC); + } + printf("ok\n"); + } +} + +static void cmd_vmode(void) { + int32_t hz; + if(get_cic_state() != CIC_PAIR) { + printf("not in pair mode\n"); + } else { + hz = parse_unsigned(50,60,10); + if(hz==50) { + cic_videomode(CIC_PAL); + } else { + cic_videomode(CIC_NTSC); + } + printf("ok\n"); + } +} + +void cmd_put(void) { + if(*curchar != 0) { + file_open((uint8_t*)curchar, FA_CREATE_ALWAYS | FA_WRITE); + if(file_res) { + printf("FAIL: error opening file %s\n", curchar); + } else { + printf("OK, start xmodem transfer now.\n"); + xmodem_rxfile(&file_handle); + } + file_close(); + } else { + printf("Usage: put \n"); + } +} + +void cmd_rm(void) { + FRESULT res = f_unlink(curchar); + if(res) printf("Error %d removing %s\n", res, curchar); +} + +void cmd_mapper(void) { + int32_t mapper; + mapper = parse_unsigned(0,7,10); + set_mapper((uint8_t)mapper & 0x7); + printf("mapper set to %ld\n", mapper); +} + +void cmd_sreset(void) { + if(*curchar != 0) { + int32_t resetstate; + resetstate = parse_unsigned(0,1,10); + snes_reset(resetstate); + } else { + snes_reset(1); + delay_ms(20); + snes_reset(0); + } +} +void cmd_settime(void) { + struct tm time; + if(strlen(curchar) != 4+2+2 + 2+2+2) { + printf("invalid time format (need YYYYMMDDhhmmss)\n"); + } else { + time.tm_sec = atoi(curchar+4+2+2+2+2); + curchar[4+2+2+2+2] = 0; + time.tm_min = atoi(curchar+4+2+2+2); + curchar[4+2+2+2] = 0; + time.tm_hour = atoi(curchar+4+2+2); + curchar[4+2+2] = 0; + time.tm_mday = atoi(curchar+4+2); + curchar[4+2] = 0; + time.tm_mon = atoi(curchar+4); + curchar[4] = 0; + time.tm_year = atoi(curchar); + set_rtc(&time); + } +} + +void cmd_time(void) { + struct tm time; + read_rtc(&time); + printf("%04d-%02d-%02d %02d:%02d:%02d\n", time.tm_year, time.tm_mon, + time.tm_mday, time.tm_hour, time.tm_min, time.tm_sec); +} + +void cmd_setfeature(void) { + uint8_t feat = parse_unsigned(0, 255, 16); + fpga_set_features(feat); +} + +void cmd_hexdump(void) { + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint32_t len = parse_unsigned(0, 16777216, 16); + sram_hexdump(offset, len); +} + +void cmd_w8(void) { + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint8_t val = parse_unsigned(0, 255, 16); + sram_writebyte(val, offset); +} + +void cmd_w16(void) { + uint32_t offset = parse_unsigned(0, 16777215, 16); + uint16_t val = parse_unsigned(0, 65535, 16); + sram_writeshort(val, offset); +} + +void cmd_memsel(void) { + uint8_t unit = parse_unsigned(0,1,10); + fpga_select_mem(unit); +} +/* ------------------------------------------------------------------------- */ +/* CLI interface functions */ +/* ------------------------------------------------------------------------- */ + +void cli_init(void) { +} + +void cli_entrycheck() { + if(uart_gotc() && uart_getc() == 27) { + printf("*** BREAK\n"); + cli_loop(); + } +} + +void cli_loop(void) { + snes_reset(1); + while (1) { + curchar = getline(">"); + printf("\n"); + + /* Process medium changes before executing the command */ + if (disk_state != DISK_OK && disk_state != DISK_REMOVED) { + FRESULT res; + + printf("Medium changed... "); + res = f_mount(0,&fatfs); + if (res != FR_OK) { + printf("Failed to mount new medium, result %d\n",res); + } else { + printf("Ok\n"); + } + + } + + /* Remove whitespace */ + while (*curchar == ' ') curchar++; + while (strlen(curchar) > 0 && curchar[strlen(curchar)-1] == ' ') + curchar[strlen(curchar)-1] = 0; + + /* Ignore empty lines */ + if (strlen(curchar) == 0) + continue; + + /* Parse command */ + int8_t command = parse_wordlist(command_words); + if (command < 0) + continue; + + + FRESULT res; + switch (command) { + case CMD_CD: +#if _FS_RPATH + if (strlen(curchar) == 0) { + f_getcwd((TCHAR*)file_lfn, 255); + printf("%s\n",file_lfn); + break; + } + + res = f_chdir((const TCHAR *)curchar); + if (res != FR_OK) { + printf("chdir %s failed with result %d\n",curchar,res); + } else { + printf("Ok.\n"); + } +#else + printf("cd not supported.\n"); + res; +#endif + break; + case CMD_RESET: + cmd_reset(); + break; + + case CMD_SRESET: + cmd_sreset(); + break; + + case CMD_DIR: + case CMD_LS: + cmd_show_directory(); + break; + + case CMD_RESUME: + return; + break; + + case CMD_LOADROM: + cmd_loadrom(); + break; + + case CMD_LOADRAW: + cmd_loadraw(); + break; + + case CMD_SAVERAW: + cmd_saveraw(); + break; + + case CMD_RM: + cmd_rm(); + break; + + case CMD_D4: + cmd_d4(); + break; + + case CMD_VMODE: + cmd_vmode(); + break; + + case CMD_PUT: + cmd_put(); + break; + + case CMD_MAPPER: + cmd_mapper(); + break; + + case CMD_SETTIME: + cmd_settime(); + break; + + case CMD_TIME: + cmd_time(); + break; + + case CMD_TEST: + testbattery(); + break; + + case CMD_SETFEATURE: + cmd_setfeature(); + break; + + case CMD_HEXDUMP: + cmd_hexdump(); + break; + + case CMD_W8: + cmd_w8(); + break; + + case CMD_W16: + cmd_w16(); + break; + + case CMD_MEMSEL: + cmd_memsel(); + break; + + } + } +} diff --git a/src/tests/cli.h b/src/tests/cli.h new file mode 100644 index 0000000..69c2276 --- /dev/null +++ b/src/tests/cli.h @@ -0,0 +1,34 @@ +/* tapplay - TAP file playback for sd2iec hardware + Copyright (C) 2009 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + cli.h: Definitions for cli.c + +*/ + +#ifndef CLI_H +#define CLI_H + +void cli_init(void); +void cli_loop(void); +void cli_entrycheck(void); + +#endif diff --git a/src/tests/clock.c b/src/tests/clock.c new file mode 100644 index 0000000..b032e6f --- /dev/null +++ b/src/tests/clock.c @@ -0,0 +1,109 @@ +/* ___DISCLAIMER___ */ + +/* clock.c: PLL, CCLK, PCLK controls */ + +#include +#include "clock.h" +#include "bits.h" +#include "uart.h" + +void clock_disconnect() { + disconnectPLL0(); + disablePLL0(); +} + +void clock_init() { + +/* set flash access time to 5 clks (80 DAC freq = 44099.5 Hz + -> FPGA freq = 11289473.7Hz + First, disable and disconnect PLL0. +*/ +// clock_disconnect(); + +/* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed + reliably with PLL0 connected. + see: + http://ics.nxp.com/support/documents/microcontrollers/pdf/errata.lpc1754.pdf +*/ + + +/* continue with PLL0 setup: + enable the xtal oscillator and wait for it to become stable + set the oscillator as clk source for PLL0 + set PLL0 multiplier+predivider + enable PLL0 + set CCLK divider + wait for PLL0 to lock + connect PLL0 + done + */ + enableMainOsc(); + setClkSrc(CLKSRC_MAINOSC); +// XXX setPLL0MultPrediv(429, 19); +// XXX setPLL0MultPrediv(23, 2); + setPLL0MultPrediv(12, 1); + enablePLL0(); + setCCLKDiv(3); + connectPLL0(); +} + +void setFlashAccessTime(uint8_t clocks) { + LPC_SC->FLASHCFG=FLASHTIM(clocks); +} + +void setPLL0MultPrediv(uint16_t mult, uint8_t prediv) { + LPC_SC->PLL0CFG=PLL_MULT(mult) | PLL_PREDIV(prediv); + PLL0feed(); +} + +void enablePLL0() { + LPC_SC->PLL0CON |= PLLE0; + PLL0feed(); +} + +void disablePLL0() { + LPC_SC->PLL0CON &= ~PLLE0; + PLL0feed(); +} + +void connectPLL0() { + while(!(LPC_SC->PLL0STAT&PLOCK0)); + LPC_SC->PLL0CON |= PLLC0; + PLL0feed(); +} + +void disconnectPLL0() { + LPC_SC->PLL0CON &= ~PLLC0; + PLL0feed(); +} + +void setCCLKDiv(uint8_t div) { + LPC_SC->CCLKCFG=CCLK_DIV(div); +} + +void enableMainOsc() { + LPC_SC->SCS=OSCEN; + while(!(LPC_SC->SCS&OSCSTAT)); +} + +void disableMainOsc() { + LPC_SC->SCS=0; +} + +void PLL0feed() { + LPC_SC->PLL0FEED=0xaa; + LPC_SC->PLL0FEED=0x55; +} + +void setClkSrc(uint8_t src) { + LPC_SC->CLKSRCSEL=src; +} diff --git a/src/tests/clock.h b/src/tests/clock.h new file mode 100644 index 0000000..56be21a --- /dev/null +++ b/src/tests/clock.h @@ -0,0 +1,79 @@ +#ifndef _CLOCK_H +#define _CLOCK_H + +#define PLL_MULT(x) ((x-1)&0x7fff) +#define PLL_PREDIV(x) (((x-1)<<16)&0xff0000) +#define CCLK_DIV(x) ((x-1)&0xff) +#define CLKSRC_MAINOSC (1) +#define PLLE0 (1<<0) +#define PLLC0 (1<<1) +#define PLOCK0 (1<<26) +#define OSCEN (1<<5) +#define OSCSTAT (1<<6) +#define FLASHTIM(x) (((x-1)<<12)|0x3A) + +#define PCLK_CCLK(x) (1<<(x)) +#define PCLK_CCLK4(x) (0) +#define PCLK_CCLK8(x) (3<<(x)) +#define PCLK_CCLK2(x) (2<<(x)) + +/* shift values for use with PCLKSEL0 */ +#define PCLK_WDT (0) +#define PCLK_TIMER0 (2) +#define PCLK_TIMER1 (4) +#define PCLK_UART0 (6) +#define PCLK_UART1 (8) +#define PCLK_PWM1 (12) +#define PCLK_I2C0 (14) +#define PCLK_SPI (16) +#define PCLK_SSP1 (20) +#define PCLK_DAC (22) +#define PCLK_ADC (24) +#define PCLK_CAN1 (26) +#define PCLK_CAN2 (28) +#define PCLK_ACF (30) + +/* shift values for use with PCLKSEL1 */ +#define PCLK_QEI (0) +#define PCLK_GPIOINT (2) +#define PCLK_PCB (4) +#define PCLK_I2C1 (6) +#define PCLK_SSP0 (10) +#define PCLK_TIMER2 (12) +#define PCLK_TIMER3 (14) +#define PCLK_UART2 (16) +#define PCLK_UART3 (18) +#define PCLK_I2C2 (20) +#define PCLK_I2S (22) +#define PCLK_RIT (26) +#define PCLK_SYSCON (28) +#define PCLK_MC (30) + +void clock_disconnect(void); + +void clock_init(void); + +void setFlashAccessTime(uint8_t clocks); + +void setPLL0MultPrediv(uint16_t mult, uint8_t prediv); + +void enablePLL0(void); + +void disablePLL0(void); + +void connectPLL0(void); + +void disconnectPLL0(void); + +void setCCLKDiv(uint8_t div); + +void enableMainOsc(void); + +void disableMainOsc(void); + +void PLL0feed(void); + +void setClkSrc(uint8_t src); + + +#endif diff --git a/src/tests/conf2h.awk b/src/tests/conf2h.awk new file mode 100644 index 0000000..3818f89 --- /dev/null +++ b/src/tests/conf2h.awk @@ -0,0 +1,29 @@ +#! /usr/bin/gawk -f + +# Trivial little script to convert from a makefile-style configuration +# file to a C header. No copyright claimed. + +BEGIN { + print "// autoconf.h generated from " ARGV[1] " at " strftime() "\n" \ + "#ifndef AUTOCONF_H\n" \ + "#define AUTOCONF_H" +} + +/^#/ { sub(/^#/,"//") } + +/^CONFIG_.*=/ { + if (/=n$/) { + sub(/^/,"// "); + } else { + sub(/^/,"#define ") + if (/=y$/) { + sub(/=.*$/,"") + } else { + sub(/=/," ") + } + } +} + +{ print } + +END { print "#endif" } diff --git a/src/tests/config b/src/tests/config new file mode 100644 index 0000000..8332a4f --- /dev/null +++ b/src/tests/config @@ -0,0 +1,4 @@ +CONFIG_VERSION=0.0.1 +CONFIG_FWVER=16777214 +#CONFIG_FWVER=1146310227 +CONFIG_MCU_FOSC=12000000 diff --git a/src/tests/config.h b/src/tests/config.h new file mode 100644 index 0000000..6900ac2 --- /dev/null +++ b/src/tests/config.h @@ -0,0 +1,97 @@ +#ifndef _CONFIG_H +#define _CONFIG_H + +// #define DEBUG_FS +// #define DEBUG_SD +// #define DEBUG_IRQ +// #define DEBUG_MSU1 + +#define VER "0.0.1(NSFW)" +#define IN_AHBRAM __attribute__ ((section(".ahbram"))) + +#define SD_DT_INT_SETUP() do {\ + BITBAND(LPC_GPIOINT->IO2IntEnR, SD_DT_BIT) = 1;\ + BITBAND(LPC_GPIOINT->IO2IntEnF, SD_DT_BIT) = 1;\ + } while(0) + +#define SD_CHANGE_DETECT (BITBAND(LPC_GPIOINT->IO2IntStatR, SD_DT_BIT)\ + |BITBAND(LPC_GPIOINT->IO2IntStatF, SD_DT_BIT)) + +#define SD_CHANGE_CLR() do {LPC_GPIOINT->IO2IntClr = BV(SD_DT_BIT);} while(0) + +#define SD_DT_REG LPC_GPIO0 +#define SD_DT_BIT 8 +#define SD_WP_REG LPC_GPIO0 +#define SD_WP_BIT 6 + +#define SDCARD_DETECT (!(BITBAND(SD_DT_REG->FIOPIN, SD_DT_BIT))) +#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT)) +#define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */ +#define CONFIG_SD_BLOCKTRANSFER 1 +#define CONFIG_SD_AUTO_RETRIES 10 +// #define SD_CHANGE_VECT +// #define CONFIG_SD_DATACRC 1 + +#define CONFIG_UART_NUM 3 +// #define CONFIG_CPU_FREQUENCY 90315789 +#define CONFIG_CPU_FREQUENCY 96000000 +//#define CONFIG_CPU_FREQUENCY 46000000 +#define CONFIG_UART_PCLKDIV 1 +#define CONFIG_UART_TX_BUF_SHIFT 8 +#define CONFIG_UART_BAUDRATE 921600 +#define CONFIG_UART_DEADLOCKABLE + +#define SSP_CLK_DIVISOR_FAST 2 +#define SSP_CLK_DIVISOR_SLOW 250 + +#define SSP_CLK_DIVISOR_FPGA_FAST 6 +#define SSP_CLK_DIVISOR_FPGA_SLOW 20 + +#define SNES_RESET_REG LPC_GPIO1 +#define SNES_RESET_BIT 26 + +#define SNES_CIC_D0_REG LPC_GPIO0 +#define SNES_CIC_D0_BIT 1 + +#define SNES_CIC_D1_REG LPC_GPIO0 +#define SNES_CIC_D1_BIT 0 + +#define SNES_CIC_STATUS_REG LPC_GPIO1 +#define SNES_CIC_STATUS_BIT 29 + +#define SNES_CIC_PAIR_REG LPC_GPIO1 +#define SNES_CIC_PAIR_BIT 25 + +#define FPGA_MCU_RDY_REG LPC_GPIO2 +#define FPGA_MCU_RDY_BIT 9 + +#define QSORT_MAXELEM 2048 + +#define SSP_REGS LPC_SSP0 +#define SSP_PCLKREG PCLKSEL1 +// 1: PCLKSEL0 +#define SSP_PCLKBIT 10 +// 1: 20 +#define SSP_DMAID_TX 0 +// 1: 2 +#define SSP_DMAID_RX 1 +// 1: 3 +#define SSP_DMACH LPC_GPDMACH0 + +#define SD_CLKREG LPC_GPIO0 +#define SD_CMDREG LPC_GPIO0 +#define SD_DAT0REG LPC_GPIO2 +#define SD_DAT1REG LPC_GPIO2 +#define SD_DAT2REG LPC_GPIO2 +#define SD_DAT3REG LPC_GPIO2 + +#define SD_CLKPIN (7) +#define SD_CMDPIN (9) +#define SD_DAT0PIN (0) +#define SD_DAT1PIN (1) +#define SD_DAT2PIN (2) +#define SD_DAT3PIN (3) + +#define SD_DAT (LPC_GPIO2->FIOPIN0) + +#endif diff --git a/src/tests/crc.S b/src/tests/crc.S new file mode 100644 index 0000000..38a7479 --- /dev/null +++ b/src/tests/crc.S @@ -0,0 +1,92 @@ +/* CRC-7/CRC-16 (XModem) implementation for Cortex M3 + * + * Written 2010 by Ingo Korb + */ + + .syntax unified + .section .text + + /* uint8_t crc7update(uint8_t crc, const uint8_t data) */ + .global crc7update + .thumb_func +crc7update: + mov r2, #8 // number of bits to process + lsl r1, r1, #24 // pre-shift data byte to top of word + +loop: + lsl r0, r0, #1 // shift CRC + lsls r1, r1, #1 // shift data byte (highest bit now in C) + bcc 0f // jump if bit was 0 + eor r0, r0, #0x80 // invert top bit of CRC if not +0: tst r0, #0x80 // test top bit of CRC + beq 1f // skip if top bit is clear + eor r0, r0, #0x09 // apply polinomial +1: subs r2, r2, #1 // decrememt bit cointer + bne loop // loop for next bit + uxtb r0, r0 // clear top bits of result + bx lr // return + + + /* uint16_t crc_xmodem_block(uint16_t crc, uint8_t *data, uint32_t len) */ + .global crc_xmodem_block + .thumb_func +crc_xmodem_block: + adr r12, crc_table // load address of crc table +blockloop: + ldrb.w r3, [r1], #1 // read data byte + eor r3, r3, r0, lsr #8 // EOR data byte + ldrh r3, [r12, r3, lsl #1] // load value from CRC table + eor r0, r3, r0, lsl #8 // update CRC + uxth r0, r0 // clear top bits of result + subs r2, r2, #1 // decrement length + bne blockloop // loop while length > 0 + bx lr // return + + /* uint16_t crc_xmodem_block(uint16_t crc, uint8_t *data, uint32_t len) */ + .global crc_xmodem_update + .thumb_func +crc_xmodem_update: + adr r2, crc_table // load address of crc table + eor r1, r1, r0, lsr #8 // EOR data byte + ldrh r3, [r2, r1, lsl #1] // load value from CRC table + eor r0, r3, r0, lsl #8 // update CRC + uxth r0, r0 // clear top bits of result + bx lr // return + + +crc_table: + .short 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7 + .short 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef + .short 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6 + .short 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de + .short 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485 + .short 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d + .short 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4 + .short 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc + .short 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823 + .short 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b + .short 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12 + .short 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a + .short 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41 + .short 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49 + .short 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70 + .short 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78 + .short 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f + .short 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067 + .short 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e + .short 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256 + .short 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d + .short 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405 + .short 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c + .short 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634 + .short 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab + .short 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3 + .short 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a + .short 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92 + .short 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9 + .short 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1 + .short 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8 + .short 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 + + + .end diff --git a/src/tests/crc.h b/src/tests/crc.h new file mode 100644 index 0000000..34e0053 --- /dev/null +++ b/src/tests/crc.h @@ -0,0 +1,11 @@ +#ifndef CRC_H +#define CRC_H + +uint8_t crc7update(uint8_t crc, uint8_t data); +uint16_t crc_xmodem_update(uint16_t crc, uint8_t data); +uint16_t crc_xmodem_block(uint16_t crc, const uint8_t *data, uint32_t length); + +// AVR-libc compatibility +#define _crc_xmodem_update(crc,data) crc_xmodem_update(crc,data) + +#endif diff --git a/src/tests/crc32.c b/src/tests/crc32.c new file mode 100644 index 0000000..7928cf2 --- /dev/null +++ b/src/tests/crc32.c @@ -0,0 +1,110 @@ +/** + * \file crc32.c + * Functions and types for CRC checks. + * + * Generated on Sat Sep 25 18:06:34 2010, + * by pycrc v0.7.1, http://www.tty1.net/pycrc/ + * using the configuration: + * Width = 32 + * Poly = 0x04c11db7 + * XorIn = 0xffffffff + * ReflectIn = True + * XorOut = 0xffffffff + * ReflectOut = True + * Algorithm = table-driven + * Direct = True + *****************************************************************************/ +#include "crc32.h" +#include "config.h" +#include +#include + +/** + * Static table used for the table_driven implementation. + *****************************************************************************/ +static const uint32_t crc32_table[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +/** + * Update the crc value with new data. + * + * \param crc The current crc value. + * \param data Pointer to a buffer of \a data_len bytes. + * \param data_len Number of bytes in the \a data buffer. + * \return The updated crc value. + *****************************************************************************/ +uint32_t crc32_update(uint32_t crc, const unsigned char data) +{ + unsigned int tbl_idx; + + tbl_idx = (crc ^ data) & 0xff; + crc = (crc32_table[tbl_idx] ^ (crc >> 8)) & 0xffffffff; + + return crc & 0xffffffff; +} + + diff --git a/src/tests/crc32.h b/src/tests/crc32.h new file mode 100644 index 0000000..9da3054 --- /dev/null +++ b/src/tests/crc32.h @@ -0,0 +1,68 @@ +/** + * \file crc32.h + * Functions and types for CRC checks. + * + * Generated on Sat Sep 25 18:06:37 2010, + * by pycrc v0.7.1, http://www.tty1.net/pycrc/ + * using the configuration: + * Width = 32 + * Poly = 0x04c11db7 + * XorIn = 0xffffffff + * ReflectIn = True + * XorOut = 0xffffffff + * ReflectOut = True + * Algorithm = table-driven + * Direct = True + *****************************************************************************/ +#ifndef __CRC___H__ +#define __CRC___H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * The definition of the used algorithm. + *****************************************************************************/ +#define CRC_ALGO_TABLE_DRIVEN 1 + +/** + * Calculate the initial crc value. + * + * \return The initial crc value. + *****************************************************************************/ +static inline uint32_t crc_init(void) +{ + return 0xffffffff; +} + +/** + * Update the crc value with new data. + * + * \param crc The current crc value. + * \param data Pointer to a buffer of \a data_len bytes. + * \param data_len Number of bytes in the \a data buffer. + * \return The updated crc value. + *****************************************************************************/ +uint32_t crc32_update(uint32_t crc, const unsigned char data); + +/** + * Calculate the final crc value. + * + * \param crc The current crc value. + * \return The final crc value. + *****************************************************************************/ +static inline uint32_t crc32_finalize(uint32_t crc) +{ + return crc ^ 0xffffffff; +} + + +#ifdef __cplusplus +} /* closing brace for extern "C" */ +#endif + +#endif /* __CRC___H__ */ diff --git a/src/tests/diskio.h b/src/tests/diskio.h new file mode 100644 index 0000000..40a002f --- /dev/null +++ b/src/tests/diskio.h @@ -0,0 +1,118 @@ +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file (C)ChaN, 2010 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO + +#define _READONLY 0 /* 1: Remove write functions */ +#define _USE_IOCTL 1 /* 1: Use disk_ioctl fucntion */ + +#include + +#include "integer.h" + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + +/** + * struct diskinfo0_t - disk info data structure for page 0 + * @validbytes : Number of valid bytes in this struct + * @maxpage : Highest diskinfo page supported + * @disktype : type of the disk (DISK_TYPE_* values) + * @sectorsize : sector size divided by 256 + * @sectorcount: number of sectors on the disk + * + * This is the struct returned in the data buffer when disk_getinfo + * is called with page=0. + */ +typedef struct { + uint8_t validbytes; + uint8_t maxpage; + uint8_t disktype; + uint8_t sectorsize; /* divided by 256 */ + uint32_t sectorcount; /* 2 TB should be enough... (512 byte sectors) */ +} diskinfo0_t; + + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + +int assign_drives (int, int); +DSTATUS disk_initialize (BYTE); +DSTATUS disk_status (BYTE); +DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE); +#if _READONLY == 0 +DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE); +#endif +#define disk_ioctl(a,b,c) RES_OK + +void disk_init(void); + +/* Will be set to DISK_ERROR if any access on the card fails */ +enum diskstates { DISK_CHANGED = 0, DISK_REMOVED, DISK_OK, DISK_ERROR }; + +extern int sd_offload, ff_sd_offload, sd_offload_tgt, newcard; +extern int sd_offload_partial; +extern uint16_t sd_offload_partial_start; +extern uint16_t sd_offload_partial_end; +extern volatile enum diskstates disk_state; + +/* Disk type - part of the external API except for ATA2! */ +#define DISK_TYPE_ATA 0 +#define DISK_TYPE_ATA2 1 +#define DISK_TYPE_SD 2 +#define DISK_TYPE_DF 3 +#define DISK_TYPE_NONE 7 + + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (defined for FatFs) */ +#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ +#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ +#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ + +/* Generic command */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +/* NAND specific ioctl command */ +#define NAND_FORMAT 30 /* Create physical format */ + + +#define _DISKIO +#endif diff --git a/src/tests/faulthandler.c b/src/tests/faulthandler.c new file mode 100644 index 0000000..47d595f --- /dev/null +++ b/src/tests/faulthandler.c @@ -0,0 +1,20 @@ +#include +#include "uart.h" + +void HardFault_Handler(void) { + printf("HFSR: %lx\n", SCB->HFSR); + while (1) ; +} + +void MemManage_Handler(void) { + printf("MemManage - CFSR: %lx; MMFAR: %lx\n", SCB->CFSR, SCB->MMFAR); +} + +void BusFault_Handler(void) { + printf("BusFault - CFSR: %lx; BFAR: %lx\n", SCB->CFSR, SCB->BFAR); +} + +void UsageFault_Handler(void) { + printf("UsageFault - CFSR: %lx; BFAR: %lx\n", SCB->CFSR, SCB->BFAR); +} + diff --git a/src/tests/ff.c b/src/tests/ff.c new file mode 100644 index 0000000..bcd68c1 --- /dev/null +++ b/src/tests/ff.c @@ -0,0 +1,3805 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.08a (C)ChaN, 2010 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2010, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSInfo support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a buffer configuration option. (_FS_TINY) +/ Added long file name support. +/ Added multiple code page support. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size support. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended char. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH. +/ Fixed name matching error on the 13 char boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. +/ +/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) +/ Added file lock feature. (_FS_SHARE) +/ Added fast seek feature. (_USE_FASTSEEK) +/ Changed some types on the API, XCHAR->TCHAR. +/ Changed fname member in the FILINFO structure on Unicode cfg. +/ String functions support UTF-8 encoding files on Unicode cfg. +/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2) +/ Added sector erase feature. (_USE_ERASE) +/ Moved file lock semaphore table from fs object to the bss. +/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. +/ Fixed f_mkfs() creates wrong FAT32 volume. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* FatFs configurations and declarations */ +#include "diskio.h" /* Declarations of low level disk I/O functions */ +#include "config.h" +#include "uart.h" + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 8255 +#error Wrong include file (ff.h). +#endif + + +/* Definitions on sector size */ +#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 +#error Wrong sector size. +#endif +#if _MAX_SS != 512 +#define SS(fs) ((fs)->ssize) /* Multiple sector size */ +#else +#define SS(fs) 512U /* Fixed sector size */ +#endif + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area must not be used in re-entrant configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + +#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); } + + +/* File shareing feature */ +#if _FS_SHARE +#if _FS_READONLY +#error _FS_SHARE must be 0 on read-only cfg. +#endif +typedef struct { + FATFS *fs; /* File ID 1, volume (NULL:blank entry) */ + DWORD clu; /* File ID 2, directory */ + WORD idx; /* File ID 3, directory index */ + WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* Misc definitions */ +#define LD_CLUST(dir) (((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO)) +#define ST_CLUST(dir,cl) {ST_WORD(dir+DIR_FstClusLO, cl); ST_WORD(dir+DIR_FstClusHI, (DWORD)cl>>16);} + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* Name status flags */ +#define NS 11 /* Offset of name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + +/* FAT sub-type boundaries */ +/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */ +#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because there are incompatibility of the packing option +/ between compilers. */ + +#define BS_jmpBoot 0 +#define BS_OEMName 3 +#define BPB_BytsPerSec 11 +#define BPB_SecPerClus 13 +#define BPB_RsvdSecCnt 14 +#define BPB_NumFATs 16 +#define BPB_RootEntCnt 17 +#define BPB_TotSec16 19 +#define BPB_Media 21 +#define BPB_FATSz16 22 +#define BPB_SecPerTrk 24 +#define BPB_NumHeads 26 +#define BPB_HiddSec 28 +#define BPB_TotSec32 32 +#define BS_DrvNum 36 +#define BS_BootSig 38 +#define BS_VolID 39 +#define BS_VolLab 43 +#define BS_FilSysType 54 +#define BPB_FATSz32 36 +#define BPB_ExtFlags 40 +#define BPB_FSVer 42 +#define BPB_RootClus 44 +#define BPB_FSInfo 48 +#define BPB_BkBootSec 50 +#define BS_DrvNum32 64 +#define BS_BootSig32 66 +#define BS_VolID32 67 +#define BS_VolLab32 71 +#define BS_FilSysType32 82 +#define FSI_LeadSig 0 +#define FSI_StrucSig 484 +#define FSI_Free_Count 488 +#define FSI_Nxt_Free 492 +#define MBR_Table 446 +#define BS_55AA 510 + +#define DIR_Name 0 +#define DIR_Attr 11 +#define DIR_NTres 12 +#define DIR_CrtTime 14 +#define DIR_CrtDate 16 +#define DIR_FstClusHI 20 +#define DIR_WrtTime 22 +#define DIR_WrtDate 24 +#define DIR_FstClusLO 26 +#define DIR_FileSize 28 +#define LDIR_Ord 0 +#define LDIR_Attr 11 +#define LDIR_Type 12 +#define LDIR_Chksum 13 +#define LDIR_FstClusLO 26 + + + +/*------------------------------------------------------------*/ +/* Work area */ + +#if _VOLUMES +static +FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +#else +#error Number of drives must not be 0. +#endif + +static +WORD Fsid; /* File system mount ID */ + +#if _FS_RPATH +static +BYTE CurrVol; /* Current drive */ +#endif + +#if _FS_SHARE +static +FILESEM Files[_FS_SHARE]; /* File lock semaphores */ +#endif + +#if _USE_LFN == 0 /* No LFN */ +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) (dobj).fn = sfn +#define FREE_BUF() + +#elif _USE_LFN == 1 /* LFN with static LFN working buffer */ +static WCHAR LfnBuf[_MAX_LFN+1]; +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; } +#define FREE_BUF() + +#elif _USE_LFN == 2 /* LFN with dynamic LFN working buffer on the stack */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } +#define FREE_BUF() + +#elif _USE_LFN == 3 /* LFN with dynamic LFN working buffer on the heap */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn +#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ + if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ + (dobj).lfn = lfn; (dobj).fn = sfn; } +#define FREE_BUF() ff_memfree(lfn) + +#else +#error Wrong LFN configuration. +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Copy memory to memory */ +static +void mem_cpy (void* dst, const void* src, UINT cnt) { + BYTE *d = (BYTE*)dst; + const BYTE *s = (const BYTE*)src; + +#if _WORD_ACCESS == 1 + while (cnt >= sizeof(int)) { + *(int*)d = *(int*)s; + d += sizeof(int); s += sizeof(int); + cnt -= sizeof(int); + } +#endif + while (cnt--) + *d++ = *s++; +} + +/* Fill memory */ +static +void mem_set (void* dst, int val, UINT cnt) { + BYTE *d = (BYTE*)dst; + + while (cnt--) + *d++ = (BYTE)val; +} + +/* Compare memory to memory */ +static +int mem_cmp (const void* dst, const void* src, UINT cnt) { + const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + int r = 0; + + while (cnt-- && (r = *d++ - *s++) == 0) ; + return r; +} + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + while (*str && *str != chr) str++; + return *str; +} + + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT + +static +int lock_fs ( + FATFS *fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS *fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* File shareing control functions */ +/*-----------------------------------------------------------------------*/ +#if _FS_SHARE + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dj, /* Directory object pointing the file to be checked */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < _FS_SHARE; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */ + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } else { /* Blank entry */ + be++; + } + } + if (i == _FS_SHARE) /* The file is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */ + + /* The file has been opened. Reject any open against writing file and all write mode open */ + return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock ( /* Check if an entry is available for a new file */ + FATFS* fs /* File system object */ +) +{ + UINT i; + + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + return (i == _FS_SHARE) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */ + DIR* dj, /* Directory object pointing the file to register or increment */ + int acc /* Desired access mode (0:Read, !0:Write) */ +) +{ + UINT i; + + + for (i = 0; i < _FS_SHARE; i++) { /* Find the file */ + if (Files[i].fs == dj->fs && + Files[i].clu == dj->sclust && + Files[i].idx == dj->index) break; + } + + if (i == _FS_SHARE) { /* Not opened. Register it as new. */ + for (i = 0; i < _FS_SHARE && Files[i].fs; i++) ; + if (i == _FS_SHARE) return 0; /* No space to register (int err) */ + Files[i].fs = dj->fs; + Files[i].clu = dj->sclust; + Files[i].idx = dj->index; + Files[i].ctr = 0; + } + + if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement file open counter */ + UINT i /* Semaphore index */ +) +{ + WORD n; + FRESULT res; + + + if (--i < _FS_SHARE) { + n = Files[i].ctr; + if (n == 0x100) n = 0; + if (n) n--; + Files[i].ctr = n; + if (!n) Files[i].fs = 0; + res = FR_OK; + } else { + res = FR_INT_ERR; + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < _FS_SHARE; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Change window offset */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT move_window ( + FATFS *fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) /* Move to zero only writes back dirty window */ +{ + DWORD wsect; + + + wsect = fs->winsect; + if (wsect != sector) { /* Changed current window */ +#if !_FS_READONLY + if (fs->wflag) { /* Write back dirty window if needed */ + if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */ + BYTE nf; + for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } +#endif + if (sector) { + if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) + return FR_DISK_ERR; + fs->winsect = sector; + } + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Clean-up cached data */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS *fs /* File system object */ +) +{ + FRESULT res; + + + res = move_window(fs, 0); + if (res == FR_OK) { + /* Update FSInfo sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag) { + fs->winsect = 0; + mem_set(fs->win, 0, 512); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + disk_write(fs->drv, fs->win, fs->fsi_sector, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, (void*)0) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + BYTE *p; + + + if (clst < 2 || clst >= fs->n_fatent) /* Chack range */ + return 1; + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc = fs->win[bc % SS(fs)]; bc++; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc |= fs->win[bc % SS(fs)] << 8; + return (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; + p = &fs->win[clst * 2 % SS(fs)]; + return LD_WORD(p); + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; + p = &fs->win[clst * 4 % SS(fs)]; + return LD_DWORD(p) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS *fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + FRESULT res; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + switch (fs->fs_type) { + case FS_FAT12 : + bc = clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + p = &fs->win[clst * 2 % SS(fs)]; + ST_WORD(p, (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + p = &fs->win[clst * 4 % SS(fs)]; + val |= LD_DWORD(p) & 0xF0000000; + ST_DWORD(p, val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; +#if _USE_ERASE + DWORD scl = clst, ecl = clst, resion[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->n_fatent) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */ + fs->free_clust++; + fs->fsi_flag = 1; + } +#if _USE_ERASE + if (ecl + 1 == nxt) { /* Next cluster is contiguous */ + ecl = nxt; + } else { /* End of contiguous clusters */ + resion[0] = clust2sect(fs, scl); /* Start sector */ + resion[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, resion); /* Erase the block */ + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS *fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (!scl || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch the current chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ + } + if (res == FR_OK) { + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag = 1; + } + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; + } + + return ncl; /* Return new cluster number or error code */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( + DIR *dj, /* Pointer to directory object */ + WORD idx /* Directory index number */ +) +{ + DWORD clst; + WORD ic; + + + dj->index = idx; + clst = dj->sclust; + if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dj->fs->dirbase; + + if (clst == 0) { /* Static table (root-dir in FAT12/16) */ + dj->clust = clst; + if (idx >= dj->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / 32); /* Sector# */ + } + else { /* Dynamic table (sub-dirs or root-dir in FAT32) */ + ic = SS(dj->fs) / 32 * dj->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dj->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dj->clust = clst; + dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / 32); /* Sector# */ + } + + dj->dir = dj->fs->win + (idx % (SS(dj->fs) / 32)) * 32; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */ + DIR *dj, /* Pointer to directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD clst; + WORD i; + + + i = dj->index + 1; + if (!i || !dj->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dj->fs) / 32))) { /* Sector changed? */ + dj->sect++; /* Next sector */ + + if (dj->clust == 0) { /* Static table */ + if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dj->fs) / 32)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dj->fs, dj->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */ +#if !_FS_READONLY + BYTE c; + if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */ + clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up stretched table */ + if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */ + mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */ + dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */ + for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */ + dj->fs->wflag = 1; + if (move_window(dj->fs, 0)) return FR_DISK_ERR; + dj->fs->winsect++; + } + dj->fs->winsect -= c; /* Rewind window address */ +#else + return FR_NO_FILE; /* Report EOT */ +#endif + } + dj->clust = clst; /* Initialize data for new cluster */ + dj->sect = clust2sect(dj->fs, clst); + } + } + } + + dj->index = i; + dj->dir = dj->fs->win + (i % (SS(dj->fs) / 32)) * 32; + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */ + + +static +int cmp_lfn ( /* 1:Matched, 0:Not matched */ + WCHAR *lfnbuf, /* Pointer to the LFN to be compared */ + BYTE *dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0xBF) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return 0; /* Not matched */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Repeat until all chars in the entry are checked */ + + if ((dir[LDIR_Ord] & 0x40) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return 0; + + return 1; /* The part of LFN matched */ +} + + + +static +int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ + WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE *dir /* Pointer to the directory entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last char has not been processed */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & 0x40) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR *lfnbuf, /* Pointer to the LFN buffer */ + BYTE *dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding chars following last char */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= 0x40; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname ( + BYTE *dst, /* Pointer to generated SFN */ + const BYTE *src, /* Pointer to source SFN to be modified */ + const WCHAR *lfn, /* Pointer to LFN */ + WORD seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ + do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa */ + i = 7; + do { + c = (seq % 16) + '0'; + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE *dir /* Ptr to directory entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR *dj /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dj, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dj->lfn) { + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; /* LFN start order */ + dj->lfn_idx = dj->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +FRESULT dir_read ( + DIR *dj /* Pointer to the directory object that pointing the entry to be read */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dj->sect) { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + dir = dj->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == 0xE5 || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & 0x40) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= 0xBF; ord = c; + dj->lfn_idx = dj->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dj->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != 0xE5 && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dj, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dj->sect = 0; + + return res; +} +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR *dj /* Target directory with object name to be created */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN /* LFN configuration */ + WORD n, ne, is; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dj->fn; lfn = dj->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ + return FR_INVALID_NAME; + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dj->lfn = 0; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dj); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dj->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */ + for (ne = 0; lfn[ne]; ne++) ; + ne = (ne + 25) / 13; + } else { /* Otherwise reserve only an SFN entry. */ + ne = 1; + } + + /* Reserve contiguous entries */ + res = dir_sdi(dj, 0); + if (res != FR_OK) return res; + n = is = 0; + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; /* Check the entry status */ + if (c == 0xE5 || c == 0) { /* Is it a blank entry? */ + if (n == 0) is = dj->index; /* First index of the contiguous entry */ + if (++n == ne) break; /* A contiguous entry that required count is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + + if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */ + res = dir_sdi(dj, is); + if (res == FR_OK) { + sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */ + ne--; + do { /* Store LFN entries in bottom first */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum); + dj->fs->wflag = 1; + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK && --ne); + } + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, 0); + if (res == FR_OK) { + do { /* Find a blank entry for the SFN */ + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + c = *dj->dir; + if (c == 0xE5 || c == 0) break; /* Is it a blank entry? */ + res = dir_next(dj, 1); /* Next entry with table stretch */ + } while (res == FR_OK); + } +#endif + + if (res == FR_OK) { /* Initialize the SFN entry */ + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + dir = dj->dir; + mem_set(dir, 0, 32); /* Clean the entry */ + mem_cpy(dir, dj->fn, 11); /* Put SFN */ +#if _USE_LFN + dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + dj->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR *dj /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dj->index; /* SFN index */ + res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dj->fs, dj->sect); + if (res != FR_OK) break; + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dj, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_sdi(dj, dj->index); + if (res == FR_OK) { + res = move_window(dj->fs, dj->sect); + if (res == FR_OK) { + *dj->dir = 0xE5; /* Mark the entry "deleted" */ + dj->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR *dj, /* Pointer to the directory object */ + const TCHAR **path /* Pointer to pointer to the segment in the path string */ +) +{ +#ifdef _EXCVT + static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */ +#endif + +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR w, *lfn; + UINT i, ni, si, di; + const TCHAR *p; + + /* Create LFN in Unicode */ + si = di = 0; + p = *path; + lfn = dj->lfn; + for (;;) { + w = p[si++]; /* Get a character */ + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) + return FR_INVALID_NAME; /* Reject invalid sequence */ + w = (w << 8) + b; /* Create a DBC */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode char */ + } + *path = &p[si]; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dj->fn[i] = (i < di) ? '.' : ' '; + dj->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di-1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject nul string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dj->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN char */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII char */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dj->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte char */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dj->fn[i++] = (BYTE)w; + } + + if (dj->fn[0] == 0xE5) dj->fn[0] = 0x05; /* If the first char collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dj->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + sfn = dj->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; + p = *path; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended char? */ + b |= 3; /* Eliminate NT flag */ +#ifdef _EXCVT + c = excvt[c-0x80]; /* Upper conversion (SBCS) */ +#else +#if !_DF1S /* ASCII only cfg */ + return FR_INVALID_NAME; +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject nul string */ + if (sfn[0] == 0xE5) sfn[0] = 0x05; /* When first char collides with 0xE5, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 +static +void get_fileinfo ( /* No return code */ + DIR *dj, /* Pointer to the directory object */ + FILINFO *fno /* Pointer to the file information to be filled */ +) +{ + UINT i; + BYTE nt, *dir; + TCHAR *p, c; + + + p = fno->fname; + if (dj->sect) { + dir = dj->dir; + nt = dir[DIR_NTres]; /* NT flag */ + for (i = 0; i < 8; i++) { /* Copy name body */ + c = dir[i]; + if (c == ' ') break; + if (c == 0x05) c = (TCHAR)0xE5; + if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + if (dir[8] != ' ') { /* Copy name extension */ + *p++ = '.'; + for (i = 8; i < 11; i++) { + c = dir[i]; + if (c == ' ') break; + if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20; +#if _LFN_UNICODE + if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1])) + c = (c << 8) | dir[++i]; + c = ff_convert(c, 1); + if (!c) c = '?'; +#endif + *p++ = c; + } + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + fno->clust = ((DWORD)LD_WORD(dir+DIR_FstClusHI) << 16) + | LD_WORD(dir+DIR_FstClusLO); + } + *p = 0; /* Terminate SFN str by a \0 */ + +#if _USE_LFN + if (fno->lfname && fno->lfsize) { + TCHAR *tp = fno->lfname; + WCHAR w, *lfn; + + i = 0; + if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */ + lfn = dj->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN char */ +#if !_LFN_UNICODE + w = ff_convert(w, 0); /* Unicode -> OEM conversion */ + if (!w) { i = 0; break; } /* Could not convert, no LFN */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ + tp[i++] = (TCHAR)(w >> 8); +#endif + if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */ + tp[i++] = (TCHAR)w; + } + } + tp[i] = 0; /* Terminate the LFN str by a \0 */ + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR *dj, /* Directory object to return last directory and found object */ + const TCHAR *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, ns; + + +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dj->sclust = 0; /* Strip it and start from the root dir */ + } else { /* No heading separator */ + dj->sclust = dj->fs->cdir; /* Start from the current dir */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dj->sclust = 0; /* Start from the root dir */ +#endif + + if ((UINT)*path < ' ') { /* Nul path means the start directory itself */ + res = dir_sdi(dj, 0); + dj->dir = 0; + + } else { /* Follow path */ + for (;;) { + res = create_name(dj, &path); /* Get a segment */ + if (res != FR_OK) break; + res = dir_find(dj); /* Find it */ + ns = *(dj->fn+NS); + if (res != FR_OK) { /* Failed to find the object */ + if (res != FR_NO_FILE) break; /* Abort if any hard error occured */ + /* Object not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */ + dj->sclust = 0; dj->dir = 0; /* It is the root dir */ + res = FR_OK; + if (!(ns & NS_LAST)) continue; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; + } + break; + } + if (ns & NS_LAST) break; /* Last segment match. Function completed. */ + dir = dj->dir; /* There is next segment. Follow the sub directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */ + res = FR_NO_PATH; break; + } + dj->sclust = LD_CLUST(dir); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load boot record and check if it is an FAT boot record */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:The FAT BR, 1:Valid BR but not an FAT, 2:Not a BR, 3:Disk error */ + FATFS *fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */ + return 3; + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file system object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */ + const TCHAR **path, /* Pointer to pointer to the path name (drive number) */ + FATFS **rfs, /* Pointer to pointer to the found file system object */ + BYTE chk_wp /* !=0: Check media write protection for write access */ +) +{ + BYTE fmt, b, *tbl; + UINT vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat; + WORD nrsv; + const TCHAR *p = *path; + FATFS *fs; + + /* Get logical drive number from the path name */ + vol = p[0] - '0'; /* Is there a drive number? */ + if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */ + p += 2; *path = p; /* Return pointer to the path name */ + } else { /* No drive number is given */ +#if _FS_RPATH + vol = CurrVol; /* Use current drive */ +#else + vol = 0; /* Use drive 0 */ +#endif + } + + /* Check if the logical drive is valid or not */ + if (vol >= _VOLUMES) /* Is the drive number valid? */ + return FR_INVALID_DRIVE; + *rfs = fs = FatFs[vol]; /* Return pointer to the corresponding file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock file system */ + + if (fs->fs_type) { /* If the logical drive has been mounted */ + stat = disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */ +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + return FR_OK; /* The file system object is valid */ + } + } + + /* The logical drive must be mounted. */ + /* Following code attempts to mount a volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + fs->drv = (BYTE)LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = disk_initialize(fs->drv); /* Initialize low level disk I/O layer */ + if (stat & STA_NOINIT) /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no media or hard error */ +#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) + return FR_DISK_ERR; +#endif +#if !_FS_READONLY + if (chk_wp && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#endif + /* Search FAT partition on the drive. Supports only generic partitionings, FDISK and SFD. */ + fmt = check_fs(fs, bsect = 0); /* Check sector 0 if it is a VBR */ + if (fmt == 1) { /* Not an FAT-VBR, the disk may be partitioned */ + /* Check the partition listed in top of the partition table */ + tbl = &fs->win[MBR_Table + LD2PT(vol) * 16]; /* Partition table */ + if (tbl[4]) { /* Is the partition existing? */ + bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */ + fmt = check_fs(fs, bsect); /* Check the partition */ + } + } + if (fmt == 3) return FR_DISK_ERR; + if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* Following code initializes the file system object */ + + if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= b; /* Number of sectors for FAT area */ + + fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / 32)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */ + + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + + nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / 32); /* RSV+FAT+DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT12; + if (nclst >= MIN_FAT16) fmt = FS_FAT16; + if (nclst >= MIN_FAT32) fmt = FS_FAT32; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->database = bsect + sysect; /* Data start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + if (fmt == FS_FAT32) { + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Required FAT size) */ + } else { + if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (FAT size must not be less than FAT sectors */ + return FR_NO_FILESYSTEM; + +#if !_FS_READONLY + /* Initialize cluster allocation information */ + fs->free_clust = 0xFFFFFFFF; + fs->last_clust = 0; + + /* Get fsinfo if available */ + if (fmt == FS_FAT32) { + fs->fsi_flag = 0; + fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo); + if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK && + LD_WORD(fs->win+BS_55AA) == 0xAA55 && + LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 && + LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) { + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = ++Fsid; /* File system mount ID */ + fs->winsect = 0; /* Invalidate sector cache */ + fs->wflag = 0; +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif +#if _FS_SHARE /* Clear file lock semaphores */ + clear_lock(fs); +#endif + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/dir object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + FATFS *fs, /* Pointer to the file system object */ + WORD id /* Member id of the target object to be checked */ +) +{ +// printf("fs=%p fs->fs_type=%d fs->id=%d id=%d\n", fs, fs->fs_type, fs->id, id); + if (!fs || !fs->fs_type || fs->id != id) + return FR_INVALID_OBJECT; + + ENTER_FF(fs); /* Lock file system */ + + if (disk_status(fs->drv) & STA_NOINIT) + return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + BYTE vol, /* Logical drive number to be mounted/unmounted */ + FATFS *fs /* Pointer to new file system object (NULL for unmount)*/ +) +{ + FATFS *rfs; + + + if (vol >= _VOLUMES) /* Check if the drive number is valid */ + return FR_INVALID_DRIVE; + rfs = FatFs[vol]; /* Get current fs object */ + + if (rfs) { +#if _FS_SHARE + clear_lock(rfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR; +#endif + rfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + fp->fs = 0; /* Clear file object */ + +#if !_FS_READONLY + mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; + res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ)); +#else + mode &= FA_READ; + res = chk_mounted(&path, &dj.fs, 0); +#endif + INIT_BUF(dj); + if (res == FR_OK) + res = follow_path(&dj, path); /* Follow the file path */ + dir = dj.dir; + +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (!dir) /* Current dir itself */ + res = FR_INVALID_NAME; +#if _FS_SHARE + else + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD dw, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#if _FS_SHARE + res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + dir = dj.dir; /* New entry */ + } + else { /* Any object is already existing */ + if (mode & FA_CREATE_NEW) { /* Cannot create new */ + res = FR_EXIST; + } else { + if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = get_fattime(); /* Created time */ + ST_DWORD(dir+DIR_CrtTime, dw); + dir[DIR_Attr] = 0; /* Reset attribute */ + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + cl = LD_CLUST(dir); /* Get start cluster */ + ST_CLUST(dir, 0); /* cluster = 0 */ + dj.fs->wflag = 1; + if (cl) { /* Remove the cluster chain if exist */ + dw = dj.fs->winsect; + res = remove_chain(dj.fs, cl); + if (res == FR_OK) { + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + res = move_window(dj.fs, dw); + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Follow succeeded */ + if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + res = FR_DENIED; + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA__WRITTEN; + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#if _FS_SHARE + fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->lockid) res = FR_INT_ERR; +#endif + } + +#else /* R/O configuration */ + if (res == FR_OK) { /* Follow succeeded */ + if (!dir) { /* Current dir itself */ + res = FR_INVALID_NAME; + } else { + if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ + res = FR_NO_FILE; + } + } +#endif + FREE_BUF(); + + if (res == FR_OK) { + fp->flag = mode; /* File access mode */ + fp->org_clust = LD_CLUST(dir); /* File start cluster */ + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; /* File pointer */ + fp->dsect = 0; +#if _USE_FASTSEEK + fp->cltbl = 0; /* No cluster link map table */ +#endif + fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */ + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL *fp, /* Pointer to the file object */ + void *buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT *br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE csect, *rbuff = buff; + + if(btr>512 && !ff_sd_offload) printf("WARNING: read >512 bytes but offloading is inactive!!\n"); + + *br = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data transferred */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; +/* XXX OFFLOAD GOES HERE */ + if (ff_sd_offload) { + sd_offload = 1; + } + if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + sd_offload = 0; +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc){ + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); uart_putc('Y');} +#endif +#endif + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write sector I/O buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if(!ff_sd_offload) { + if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } + } +#endif + fp->dsect = sect; + } + rcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; + if(!ff_sd_offload) { +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ + } else { + sd_offload_partial_start = fp->fptr % SS(fp->fs); + sd_offload_partial_end = sd_offload_partial_start + rcnt; +// printf("partial dma. sect=%08lx start=%d end=%d\n", fp->dsect, sd_offload_partial_start, sd_offload_partial_end); + /* set start + end */ + sd_offload = 1; + sd_offload_partial = 1; + if(disk_read(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) { + sd_offload = 0; + ABORT(fp->fs, FR_DISK_ERR); + } + sd_offload = 0; +#endif + } + } + ff_sd_offload = 0; + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL *fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT *bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = buff; + BYTE csect; + + + *bw = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fsize + btw < fp->fsize) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data transferred */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->org_clust; /* Follow from the origin */ + if (clst == 0) /* When there is no cluster chain, */ + fp->org_clust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ + clst = create_chain(fp->fs, fp->curr_clust); /* Follow or stretch cluster chain */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write back data buffer prior to following direct transfer */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write back data buffer prior to following direct transfer */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets dirty by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly buffer filling at growing edge */ + if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector buffer with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + wcnt = SS(fp->fs) - (fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file change flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tim; + BYTE *dir; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ +#if !_FS_TINY /* Write-back dirty buffer */ + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + ST_CLUST(dir, fp->org_clust); /* Update start cluster */ + tim = get_fattime(); /* Update updated time */ + ST_DWORD(dir+DIR_WrtTime, tim); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + +#if _FS_READONLY + FATFS *fs = fp->fs; + res = validate(fs, fp->id); + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + LEAVE_FF(fs, res); + +#else + res = f_sync(fp); /* Flush cached data */ +#if _FS_SHARE + if (res == FR_OK) { /* Decrement open counter */ +#if _FS_REENTRANT + res = validate(fp->fs, fp->id); + if (res == FR_OK) { + res = dec_lock(fp->lockid); + unlock_fs(fp->fs, FR_OK); + } +#else + res = dec_lock(fp->lockid); +#endif + } +#endif + if (res == FR_OK) fp->fs = 0; /* Discard file object */ + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Current Drive/Directory Handlings */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH >= 1 + +FRESULT f_chdrive ( + BYTE drv /* Drive number */ +) +{ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + + CurrVol = drv; + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the path */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (!dj.dir) { + dj.fs->cdir = dj.sclust; /* Start directory itself */ + } else { + if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ + dj.fs->cdir = LD_CLUST(dj.dir); + else + res = FR_NO_PATH; /* Reached but a file */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR *path, /* Pointer to the directory path */ + UINT sz_path /* Size of path */ +) +{ + FRESULT res; + DIR dj; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMEBUF; + + + *path = 0; + res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */ + if (res == FR_OK) { + INIT_BUF(dj); + i = sz_path; /* Bottom of buffer (dir stack base) */ + dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */ + while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */ + res = dir_sdi(&dj, 1); /* Get parent dir */ + if (res != FR_OK) break; + res = dir_read(&dj); + if (res != FR_OK) break; + dj.sclust = LD_CLUST(dj.dir); /* Goto parent dir */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child dir */ + res = dir_read(&dj); + if (res != FR_OK) break; + if (ccl == LD_CLUST(dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; +#if _USE_LFN + fno.lfname = path; + fno.lfsize = i; +#endif + get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */ + tp = fno.fname; + if (_USE_LFN && *path) tp = path; + for (n = 0; tp[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) path[--i] = tp[--n]; + path[--i] = '/'; + } + tp = path; + if (res == FR_OK) { + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; + if (i == sz_path) { /* Root-dir */ + *tp++ = '/'; + } else { /* Sub-dir */ + do /* Add stacked path str */ + *tp++ = path[i++]; + while (i < sz_path); + } + } + *tp = 0; + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL *fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check abort flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + DWORD cl, pcl, ncl, tcl, dsc, tlen, *tbl = fp->cltbl; + BYTE csc; + + tlen = *tbl++; + if (ofs == CREATE_LINKMAP) { /* Create link map table */ + cl = fp->org_clust; + if (cl) { + do { + if (tlen < 4) { /* Not enough table items */ + res = FR_NOT_ENOUGH_CORE; break; + } + tcl = cl; ncl = 0; + do { /* Get a fragment and store the top and length */ + pcl = cl; ncl++; + cl = get_fat(fp->fs, cl); + if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + } while (cl == pcl + 1); + *tbl++ = ncl; *tbl++ = tcl; + tlen -= 2; + } while (cl < fp->fs->n_fatent); + } + *tbl = 0; /* Terminate table */ + + } else { /* Fast seek */ + if (ofs > fp->fsize) /* Clip offset at the file size */ + ofs = fp->fsize; + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + dsc = (ofs - 1) / SS(fp->fs); + cl = dsc / fp->fs->csize; + for (;;) { + ncl = *tbl++; + if (!ncl) ABORT(fp->fs, FR_INT_ERR); + if (cl < ncl) break; + cl -= ncl; tbl++; + } + fp->curr_clust = cl + *tbl; + csc = (BYTE)(dsc & (fp->fs->csize - 1)); + dsc = clust2sect(fp->fs, fp->curr_clust); + if (!dsc) ABORT(fp->fs, FR_INT_ERR); + dsc += csc; + if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { + DWORD clst, bcs, nsect, ifptr; + + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->curr_clust; + } else { /* When seek to back cluster, */ + clst = fp->org_clust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->org_clust = clst; + } +#endif + fp->curr_clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); + fp->curr_clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += ofs / SS(fp->fs); + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Flush dirty buffer if needed */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if(!ff_sd_offload) { + sd_offload_partial=0; + if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } else { + sd_offload_partial=1; + sd_offload_partial_start = fp->fptr % SS(fp->fs); + } +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set change flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + } + ff_sd_offload = 0; + LEAVE_FF(fp->fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directroy Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR *dj, /* Pointer to directory object to create */ + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj->fs, 0); + if (res == FR_OK) { + INIT_BUF(*dj); + res = follow_path(dj, path); /* Follow the path to the directory */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (dj->dir) { /* It is not the root dir */ + if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */ + dj->sclust = LD_CLUST(dj->dir); + } else { /* The object is not a directory */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dj->id = dj->fs->id; + res = dir_sdi(dj, 0); /* Rewind dir */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entry in Sequense */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR *dj, /* Pointer to the open directory object */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = validate(dj->fs, dj->id); /* Check validity of the object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dj, 0); /* Rewind the directory object */ + } else { + INIT_BUF(*dj); + res = dir_read(dj); /* Read an directory item */ + if (res == FR_NO_FILE) { /* Reached end of dir */ + dj->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dj, fno); /* Get the object information */ + res = dir_next(dj, 0); /* Increment index for next */ + if (res == FR_NO_FILE) { + dj->sect = 0; + res = FR_OK; + } + } + FREE_BUF(); + } + } + + LEAVE_FF(dj->fs, res); +} + + +FRESULT l_opendirbycluster ( + FATFS *fs, + DIR *dj, + const TCHAR *path, + DWORD clust +) +{ + FRESULT res; + res = chk_mounted(&path, &fs, 0); + DEF_NAMEBUF; + INIT_BUF(*dj); + dj->sclust = clust; + dj->fs = fs; + dj->id = fs->id; + dj->dir = 0; + res = dir_sdi(dj, 0); + FREE_BUF(); + return res; +} + +FRESULT l_openfilebycluster ( + FATFS *fs, /* Pointer to file system object */ + FIL *fp, /* Pointer to the blank file object */ + const TCHAR *path, + DWORD clust, /* Cluster number to be opened */ + DWORD fsize /* File size to be assumed */ +) +{ + chk_mounted(&path, &fs, 0); + fp->flag = FA_READ; + fp->org_clust = clust; + fp->fsize = fsize; + fp->fptr = 0; + fp->dsect = 0; + fp->fs = fs; + + return FR_OK; +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR *path, /* Pointer to the file path */ + FILINFO *fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) /* Found an object */ + get_fileinfo(&dj, fno); + else /* It is root dir */ + res = FR_INVALID_NAME; + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR *path, /* Pointer to the logical drive number (root dir) */ + DWORD *nclst, /* Pointer to the variable to return number of free clusters */ + FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */ +) +{ + FRESULT res; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get drive number */ + res = chk_mounted(&path, fatfs, 0); + if (res == FR_OK) { + /* If free_clust is valid, return it without full cluster scan */ + if ((*fatfs)->free_clust <= (*fatfs)->n_fatent - 2) { + *nclst = (*fatfs)->free_clust; + } else { + /* Get number of free clusters */ + fat = (*fatfs)->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(*fatfs, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) n++; + } while (++clst < (*fatfs)->n_fatent); + } else { + clst = (*fatfs)->n_fatent; + sect = (*fatfs)->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(*fatfs, sect++); + if (res != FR_OK) break; + p = (*fatfs)->win; + i = SS(*fatfs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + (*fatfs)->free_clust = n; + if (fat == FS_FAT32) (*fatfs)->fsi_flag = 1; + *nclst = n; + } + } + LEAVE_FF(*fatfs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL *fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__ERROR) { /* Check abort flag */ + res = FR_INT_ERR; + } else { + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + res = FR_DENIED; + } + } + if (res == FR_OK) { + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->org_clust); + fp->org_clust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->curr_clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->n_fatent) { + res = put_fat(fp->fs, fp->curr_clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } + } + if (res != FR_OK) fp->flag |= FA__ERROR; + } + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + BYTE *dir; + DWORD dclst; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; /* Cannot remove dot entry */ +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ +#endif + if (res == FR_OK) { /* The object is accessible */ + dir = dj.dir; + if (!dir) { + res = FR_INVALID_NAME; /* Cannot remove the start directory */ + } else { + if (dir[DIR_Attr] & AM_RDO) + res = FR_DENIED; /* Cannot remove R/O object */ + } + dclst = LD_CLUST(dir); + if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ + if (dclst < 2) { + res = FR_INT_ERR; + } else { + mem_cpy(&sdj, &dj, sizeof(DIR)); /* Check if the sub-dir is empty or not */ + sdj.sclust = dclst; + res = dir_sdi(&sdj, 2); /* Exclude dot entries */ + if (res == FR_OK) { + res = dir_read(&sdj); + if (res == FR_OK /* Not empty dir */ +#if _FS_RPATH + || dclst == sdj.fs->cdir /* Current dir */ +#endif + ) res = FR_DENIED; + if (res == FR_NO_FILE) res = FR_OK; /* Empty */ + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK) { + if (dclst) /* Remove the cluster chain if exist */ + res = remove_chain(dj.fs, dclst); + if (res == FR_OK) res = sync(dj.fs); + } + } + } + FREE_BUF(); + } + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir, n; + DWORD dsc, dcl, pcl, tim = get_fattime(); + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) /* Flush FAT */ + res = move_window(dj.fs, 0); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(dj.fs, dcl); + dir = dj.fs->win; + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + ST_DWORD(dir+DIR_WrtTime, tim); + ST_CLUST(dir, dcl); + mem_cpy(dir+32, dir, 32); /* Create ".." entry */ + dir[33] = '.'; pcl = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) + pcl = 0; + ST_CLUST(dir+32, pcl); + for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + dj.fs->winsect = dsc++; + dj.fs->wflag = 1; + res = move_window(dj.fs, 0); + if (res != FR_OK) break; + mem_set(dir, 0, SS(dj.fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res != FR_OK) { + remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */ + ST_CLUST(dir, dcl); /* Table start cluster */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR *path, /* Pointer to the file/directory name */ + const FILINFO *fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR dj; + BYTE *dir; + DEF_NAMEBUF; + + + res = chk_mounted(&path, &dj.fs, 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR *path_old, /* Pointer to the old name */ + const TCHAR *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + BYTE buf[21], *dir; + DWORD dw; + DEF_NAMEBUF; + + + res = chk_mounted(&path_old, &djo.fs, 1); + if (res == FR_OK) { + djn.fs = djo.fs; + INIT_BUF(djo); + res = follow_path(&djo, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; +#if _FS_SHARE + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Old object is found */ + if (!djo.dir) { /* Is root dir? */ + res = FR_NO_FILE; + } else { + mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ + mem_cpy(&djn, &djo, sizeof(DIR)); /* Check new object */ + res = follow_path(&djn, path_new); + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ +/* Start critical section that any interruption or error can cause cross-link */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy object information except for name */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + djo.fs->wflag = 1; + if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ + dw = clust2sect(djn.fs, LD_CLUST(dir)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(djn.fs, dw); + dir = djn.fs->win+32; /* .. entry */ + if (res == FR_OK && dir[1] == '.') { + dw = (djn.fs->fs_type == FS_FAT32 && djn.sclust == djn.fs->dirbase) ? 0 : djn.sclust; + ST_CLUST(dir, dw); + djn.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) + res = sync(djo.fs); + } + } +/* End critical section */ + } + } + } + FREE_BUF(); + } + LEAVE_FF(djo.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (available on only tiny cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL *fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btr, /* Number of bytes to forward */ + UINT *bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + BYTE csect; + + + *bf = 0; /* Initialize byte counter */ + + res = validate(fp->fs, fp->id); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->flag & FA__ERROR) /* Check error flag */ + LEAVE_FF(fp->fs, FR_INT_ERR); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) { + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->org_clust : get_fat(fp->fs, fp->curr_clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->curr_clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fp->fs, fp->curr_clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btr) rcnt = btr; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Multiple of 32 */ +#define N_FATS 1 /* 1 or 2 */ + + +FRESULT f_mkfs ( + BYTE drv, /* Logical drive number */ + BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ + UINT au /* Allocation unit size [bytes] */ +) +{ + static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; + static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; + BYTE fmt, md, *tbl; + DWORD n_clst, vs, n, wsect; + UINT i; + DWORD b_vol, b_fat, b_dir, b_data; /* Offset (LBA) */ + DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ + FATFS *fs; + DSTATUS stat; + + + /* Check mounted drive and clear work area */ + if (drv >= _VOLUMES) return FR_INVALID_DRIVE; + fs = FatFs[drv]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + drv = LD2PD(drv); + + /* Get disk statics */ + stat = disk_initialize(drv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) + return FR_DISK_ERR; +#endif + if (disk_ioctl(drv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) + return FR_DISK_ERR; + b_vol = (sfd) ? 0 : 63; /* Volume start sector */ + n_vol -= b_vol; + if (au & (au - 1)) au = 0; /* Check validity of the allocation unit size */ + if (!au) { /* AU auto selection */ + vs = n_vol / (2000 / (SS(fs) / 512)); + for (i = 0; vs < vst[i]; i++) ; + au = cst[i]; + } + au /= SS(fs); /* Number of sectors per cluster */ + if (au == 0) au = 1; + if (au > 128) au = 128; + + /* Pre-compute number of clusters and FAT syb-type */ + n_clst = n_vol / au; + fmt = FS_FAT12; + if (n_clst >= MIN_FAT16) fmt = FS_FAT16; + if (n_clst >= MIN_FAT32) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + if (fmt == FS_FAT32) { + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 32; + n_dir = 0; + } else { + n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; + n_fat = (n_fat + SS(fs) - 1) / SS(fs); + n_rsv = 1; + n_dir = N_ROOTDIR * 32UL / SS(fs); + } + b_fat = b_vol + n_rsv; /* FAT area start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ + b_data = b_dir + n_dir; /* Data area start sector */ + if (n_vol < b_data + au) return FR_MKFS_ABORTED; /* Too small volume */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(drv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; + n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ + n = (n - b_data) / N_FATS; + if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ + n_rsv += n; + b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + n_fat += n; + } + + /* Determine number of cluster and final check of validity of the FAT sub-type */ + n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; + if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) + || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) + return FR_MKFS_ABORTED; + + /* Create partition table if required */ + if (sfd) { + md = 0xF0; + } else { + DWORD n_disk = b_vol + n_vol; + + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; + ST_DWORD(tbl, 0x00010180); /* Partition start in CHS */ + if (n_disk < 63UL * 255 * 1024) { /* Partition end in CHS */ + n_disk = n_disk / 63 / 255; + tbl[7] = (BYTE)n_disk; + tbl[6] = (BYTE)((n_disk >> 2) | 63); + } else { + ST_WORD(&tbl[6], 0xFFFF); + } + tbl[5] = 254; + if (fmt != FS_FAT32) /* System ID */ + tbl[4] = (n_vol < 0x10000) ? 0x04 : 0x06; + else + tbl[4] = 0x0c; + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ + ST_WORD(tbl+64, 0xAA55); /* Signature */ + if (disk_write(drv, fs->win, 0, 1) != RES_OK) + return FR_DISK_ERR; + md = 0xF8; + } + + /* Create volume boot record */ + tbl = fs->win; /* Clear sector */ + mem_set(tbl, 0, SS(fs)); + mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot code, OEM name */ + i = SS(fs); /* Sector size */ + ST_WORD(tbl+BPB_BytsPerSec, i); + tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */ + ST_WORD(tbl+BPB_RootEntCnt, i); + if (n_vol < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_vol); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_vol); + } + tbl[BPB_Media] = md; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ + n = get_fattime(); /* Use current time as VSN */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+BS_VolID32, n); /* VSN */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID, n); /* VSN */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ + if (disk_write(drv, tbl, b_vol, 1) != RES_OK)/* Write original (VBR) */ + return FR_DISK_ERR; + if (fmt == FS_FAT32) /* Write backup (VBR+6) */ + disk_write(drv, tbl, b_vol + 6, 1); + + /* Initialize FAT area */ + wsect = b_fat; + for (i = 0; i < N_FATS; i++) { + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + n = md; /* Media descriptor byte */ + if (fmt != FS_FAT32) { + n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + n |= 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */ + } + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ + for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector write */ + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } + } + + /* Initialize root directory */ + i = (fmt == FS_FAT32) ? au : n_dir; + do { + if (disk_write(drv, tbl, wsect++, 1) != RES_OK) + return FR_DISK_ERR; + } while (--i); + +#if _USE_ERASE /* Erase data area if needed */ + { + DWORD eb[2]; + + eb[0] = wsect; eb[1] = wsect + n_clst * au - 1; + disk_ioctl(drv, CTRL_ERASE_SECTOR, eb); + } +#endif + + /* Create FSInfo if needed */ + if (fmt == FS_FAT32) { + ST_WORD(tbl+BS_55AA, 0xAA55); + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); + ST_DWORD(tbl+FSI_Nxt_Free, 0xFFFFFFFF); + disk_write(drv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ + disk_write(drv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ + } + + return (disk_ioctl(drv, CTRL_SYNC, (void*)0) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fil /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read bytes until buffer gets filled */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; /* Break on EOF or error */ + c = s[0]; +#if _LFN_UNICODE /* Read a character in UTF-8 encoding */ + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequense */ + f_read(fil, s, 1, &rc); + if (rc != 1) break; + c = ((c & 0x1F) << 6) | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequense */ + f_read(fil, s, 2, &rc); + if (rc != 2) break; + c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequense */ + c = '?'; + } + } + } +#endif +#if _USE_STRFUNC >= 2 + if (c == '\r') continue; /* Strip '\r' */ +#endif + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + UINT bw, btw; + BYTE s[3]; + + +#if _USE_STRFUNC >= 2 + if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */ +#endif + +#if _LFN_UNICODE /* Write the character in UTF-8 encoding */ + if (c < 0x80) { /* 7-bit */ + s[0] = (BYTE)c; + btw = 1; + } else { + if (c < 0x800) { /* 11-bit */ + s[0] = (BYTE)(0xC0 | (c >> 6)); + s[1] = (BYTE)(0x80 | (c & 0x3F)); + btw = 2; + } else { /* 16-bit */ + s[0] = (BYTE)(0xE0 | (c >> 12)); + s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F)); + s[2] = (BYTE)(0x80 | (c & 0x3F)); + btw = 3; + } + } +#else /* Write the character without conversion */ + s[0] = (BYTE)c; + btw = 1; +#endif + f_write(fil, s, btw, &bw); /* Write the char to the file */ + return (bw == btw) ? 1 : EOF; /* Return the result */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fil /* Pointer to the file object */ +) +{ + int n; + + + for (n = 0; *str; str++, n++) { + if (f_putc(*str, fil) == EOF) return EOF; + } + return n; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ +int f_printf ( + FIL* fil, /* Pointer to the file object */ + const TCHAR* str, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + BYTE f, r; + UINT i, w; + ULONG val; + TCHAR c, d, s[16]; + int res, cc; + + + va_start(arp, str); + + for (cc = res = 0; cc != EOF; res += cc) { + c = *str++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + cc = f_putc(c, fil); + if (cc != EOF) cc = 1; + continue; + } + w = f = 0; + c = *str++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *str++; + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *str++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 2; c = *str++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + cc = f_puts(va_arg(arp, TCHAR*), fil); continue; + case 'C' : /* Character */ + cc = f_putc((TCHAR)va_arg(arp, int), fil); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown */ + cc = f_putc(c, fil); continue; + } + + /* Get an argument */ + val = (f & 2) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : va_arg(arp, unsigned int)); + if (d == 'D' && (val & 0x80000000)) { + val = 0 - val; + f |= 4; + } + /* Put it in numeral string */ + i = 0; + do { + d = (TCHAR)(val % r); val /= r; + if (d > 9) { + d += 7; + if (c == 'x') d += 0x20; + } + s[i++] = d + '0'; + } while (val && i < sizeof(s) / sizeof(s[0])); + if (f & 4) s[i++] = '-'; + cc = 0; + while (i < w-- && cc != EOF) { + cc = f_putc((TCHAR)((f & 1) ? '0' : ' '), fil); + res++; + } + do { + cc = f_putc(s[--i], fil); + res++; + } while (i && cc != EOF); + if (cc != EOF) cc = 0; + } + + va_end(arp); + return (cc == EOF) ? cc : res; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ diff --git a/src/tests/ff.h b/src/tests/ff.h new file mode 100644 index 0000000..55abce9 --- /dev/null +++ b/src/tests/ff.h @@ -0,0 +1,547 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.08a (C)ChaN, 2010 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following trems. +/ +/ Copyright (C) 2010, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/----------------------------------------------------------------------------*/ + +#ifndef _FATFS +#define _FATFS 8255 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONF +#error Wrong configuration file (ffconf.h). +#endif + + +/* DBCS code ranges and SBCS extend char conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + + +/* Definitions of volume management */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ +#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive# */ +#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition# */ +typedef struct { + BYTE pd; /* Physical drive# */ + BYTE pt; /* Partition # (0-3) */ +} PARTITION; +extern const PARTITION VolToPart[]; /* Volume - Physical location resolution table */ + +#else /* Single partition configuration */ +#define LD2PD(vol) (vol) /* Logical drive# is bound to the same physical drive# */ +#define LD2PT(vol) 0 /* Always mounts the 1st partition */ + +#endif + + + +/* Type of path name strings on FatFs API */ + +#if _LFN_UNICODE /* Unicode string */ +#if !_USE_LFN +#error _LFN_UNICODE must be 0 in non-LFN cfg. +#endif +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#endif + +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + +#endif + + + +/* File system object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* FAT sub-type (0:Not mounted) */ + BYTE drv; /* Physical drive number */ + BYTE csize; /* Sectors per cluster (1,2,4...128) */ + BYTE n_fats; /* Number of FAT copies (1,2) */ + BYTE wflag; /* win[] dirty flag (1:must be written back) */ + BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ +#if _MAX_SS != 512 + WORD ssize; /* Bytes per sector (512,1024,2048,4096) */ +#endif +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ + DWORD fsi_sector; /* fsinfo sector (FAT32) */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#endif + DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ + DWORD fsize; /* Sectors per FAT */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */ +} FATFS; + + + +/* File object structure (FIL) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + BYTE flag; /* File status flags */ + BYTE pad1; + DWORD fptr; /* File read/write pointer (0 on file open) */ + DWORD fsize; /* File size */ + DWORD org_clust; /* File start cluster (0 when fsize==0) */ + DWORD curr_clust; /* Current cluster */ + DWORD dsect; /* Current data sector */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Ponter to the directory entry in the window */ +#endif +#if _USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */ +#endif +#if _FS_SHARE + UINT lockid; /* File lock ID (index of file semaphore table) */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS]; /* File data read/write buffer */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object */ + WORD id; /* Owner file system mount ID */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Root dir) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR; + + + +/* File status structure (FILINFO) */ + +typedef struct { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + TCHAR fname[13]; /* Short file name (8.3 format) */ + DWORD clust; /* start cluster */ +#if _USE_LFN + TCHAR* lfname; /* Pointer to the LFN buffer */ + UINT lfsize; /* Size of LFN buffer in TCHAR */ +#endif +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occured in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Acces denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Acces denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume on the physical drive */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file shareing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES /* (18) Number of open files > _FS_SHARE */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +/* Low Level functions */ +FRESULT l_openfilebycluster(FATFS *fs, FIL *fp, const TCHAR *path, DWORD clust, DWORD fsize); /* Open a file by its start cluster using supplied file size */ +FRESULT l_opendirbycluster (FATFS *fs, DIR *dj, const TCHAR *path, DWORD clust); + +/* application level functions */ +FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */ +FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */ +FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */ +FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */ +FRESULT f_close (FIL*); /* Close an open file object */ +FRESULT f_opendir (DIR*, const TCHAR*); /* Open an existing directory */ +FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */ +FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */ + +#if !_FS_READONLY +FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */ +FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */ +FRESULT f_truncate (FIL*); /* Truncate file */ +FRESULT f_sync (FIL*); /* Flush cached data of a writing file */ +FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */ +FRESULT f_mkdir (const TCHAR*); /* Create a new directory */ +FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attriburte of the file/dir */ +FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change timestamp of the file/dir */ +FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */ +#endif + +#if _USE_FORWARD +FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */ +#endif + +#if _USE_MKFS +FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */ +#endif + +#if _FS_RPATH +FRESULT f_chdrive (BYTE); /* Change current drive */ +FRESULT f_chdir (const TCHAR*); /* Change current directory */ +FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */ +#endif + +#if _USE_STRFUNC +int f_putc (TCHAR, FIL*); /* Put a character to the file */ +int f_puts (const TCHAR*, FIL*); /* Put a string to the file */ +int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */ +#ifndef EOF +#define EOF (-1) +#endif +#endif + +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->fsize) + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !_FS_READONLY +DWORD get_fattime (void); +#endif + +/* Unicode support functions */ +#if _USE_LFN /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT); /* Allocate memory block */ +void ff_memfree (void*); /* Free memory block */ +#endif +#endif + +/* Sync functions */ +#if _FS_REENTRANT +int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */ +int ff_del_syncobj (_SYNC_t); /* Delete a sync object */ +int ff_req_grant (_SYNC_t); /* Lock sync object */ +void ff_rel_grant (_SYNC_t); /* Unlock sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 +#define FA__ERROR 0x80 + +#if !_FS_READONLY +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* Fast seek function */ +#define CREATE_LINKMAP 0xFFFFFFFF + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*(BYTE*)((ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*(BYTE*)((ptr)+3)<<24)|((DWORD)*(BYTE*)((ptr)+2)<<16)|((WORD)*(BYTE*)((ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *(BYTE*)((ptr)+1)=(BYTE)((WORD)(val)>>8); *(BYTE*)((ptr)+2)=(BYTE)((DWORD)(val)>>16); *(BYTE*)((ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _FATFS */ diff --git a/src/tests/ffconf.h b/src/tests/ffconf.h new file mode 100644 index 0000000..14551ed --- /dev/null +++ b/src/tests/ffconf.h @@ -0,0 +1,188 @@ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.08a (C)ChaN, 2010 +/----------------------------------------------------------------------------/ +/ +/ CAUTION! Do not forget to make clean the project after any changes to +/ the configuration options. +/ +/----------------------------------------------------------------------------*/ +#ifndef _FFCONF +#define _FFCONF 8255 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Function and Buffer Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system +/ object instead of the sector buffer in the individual file object for file +/ data transfer. This reduces memory consumption 512 bytes each file object. */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename, +/ f_truncate and useless f_getfree. */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove some functions. +/ +/ 0: Full function. +/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename +/ are removed. +/ 2: f_opendir and f_readdir are removed in addition to 1. +/ 3: f_lseek is removed in addition to 2. */ + + +#define _USE_STRFUNC 0 /* 0:Disable or 1/2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 0 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +#define _USE_FASTSEEK 1 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII only (Valid for non LFN cfg.) +*/ + + +#define _USE_LFN 1 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN support. +/ +/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN, +/ Unicode handling functions ff_convert() and ff_wtoupper() must be added +/ to the project. When enable to use heap, memory control functions +/ ff_memalloc() and ff_memfree() must be added to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character code set on FatFs API to Unicode, +/ enable LFN feature and set _LFN_UNICODE to 1. */ + + +#define _FS_RPATH 2 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() are available. +/ 2: f_getcwd() is available in addition to 1. +/ +/ Note that output of the f_readdir fnction is affected by this option. */ + + + +/*---------------------------------------------------------------------------/ +/ Physical Drive Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* Maximum sector size to be handled. +/ Always set 512 for memory card and hard disk but a larger value may be +/ required for floppy disk (512/1024) and optical disk (512/2048). +/ When _MAX_SS is larger than 512, GET_SECTOR_SIZE command must be implememted +/ to the disk_ioctl function. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition or 1:Multiple partition */ +/* When set to 0, each volume is bound to the same physical drive number and +/ it can mount only first primaly partition. When it is set to 1, each volume +/ is tied to the partitions listed in VolToPart[]. */ + + +#define _USE_ERASE 0 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _WORD_ACCESS 0 /* 0 or 1 */ +/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS +/ option defines which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. +/ 1: Word access. Do not choose this unless following condition is met. +/ +/ When the byte order on the memory is big-endian or address miss-aligned word +/ access results incorrect behavior, the _WORD_ACCESS must be set to 0. +/ If it is not the case, the value can also be set to 1 to improve the +/ performance and code size. */ + + +/* Include a header file here to define sync object types on the O/S */ +/* #include , , or ohters. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ + +/* The _FS_REENTRANT option switches the reentrancy of the FatFs module. +/ +/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect. +/ 1: Enable reentrancy. Also user provided synchronization handlers, +/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj +/ function must be added to the project. */ + + +#define _FS_SHARE 0 /* 0:Disable or >=1:Enable */ +/* To enable file shareing feature, set _FS_SHARE to 1 or greater. The value + defines how many files can be opened simultaneously. */ + + +#endif /* _FFCONFIG */ diff --git a/src/tests/fileops.c b/src/tests/fileops.c new file mode 100644 index 0000000..4e681d1 --- /dev/null +++ b/src/tests/fileops.c @@ -0,0 +1,117 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fileops.c: simple file access functions +*/ + +#include "config.h" +#include "uart.h" +#include "ff.h" +#include "fileops.h" +#include "diskio.h" + +/* +WCHAR ff_convert(WCHAR w, UINT dir) { + return w; +}*/ + +int newcard; + +void file_init() { + file_res=f_mount(0, &fatfs); + newcard = 0; +} + +void file_reinit(void) { + disk_init(); + file_init(); +} + +FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno) { + return l_opendirbycluster(&fatfs, dir, (TCHAR*)"", fno->clust); +} + +void file_open_by_filinfo(FILINFO* fno) { + file_res = l_openfilebycluster(&fatfs, &file_handle, (TCHAR*)"", fno->clust, fno->fsize); +} + +void file_open(uint8_t* filename, BYTE flags) { + if (disk_state == DISK_CHANGED) { + file_reinit(); + newcard = 1; + } + file_res = f_open(&file_handle, (TCHAR*)filename, flags); + file_block_off = sizeof(file_buf); + file_block_max = sizeof(file_buf); + file_status = file_res ? FILE_ERR : FILE_OK; +} + +void file_close() { + file_res = f_close(&file_handle); +} + +void file_seek(uint32_t offset) { + file_res = f_lseek(&file_handle, (DWORD)offset); +} + +UINT file_read() { + UINT bytes_read; + file_res = f_read(&file_handle, file_buf, sizeof(file_buf), &bytes_read); + return bytes_read; +} + +UINT file_write() { + UINT bytes_written; + file_res = f_write(&file_handle, file_buf, sizeof(file_buf), &bytes_written); + if(bytes_written < sizeof(file_buf)) { + printf("wrote less than expected - card full?\n"); + } + return bytes_written; +} + +UINT file_readblock(void* buf, uint32_t addr, uint16_t size) { + UINT bytes_read; + file_res = f_lseek(&file_handle, addr); + if(file_handle.fptr != addr) { + return 0; + } + file_res = f_read(&file_handle, buf, size, &bytes_read); + return bytes_read; +} + +UINT file_writeblock(void* buf, uint32_t addr, uint16_t size) { + UINT bytes_written; + file_res = f_lseek(&file_handle, addr); + if(file_res) return 0; + file_res = f_write(&file_handle, buf, size, &bytes_written); + return bytes_written; +} + +uint8_t file_getc() { + if(file_block_off == file_block_max) { + file_block_max = file_read(); + if(file_block_max == 0) file_status = FILE_EOF; + file_block_off = 0; + } + return file_buf[file_block_off++]; +} diff --git a/src/tests/fileops.h b/src/tests/fileops.h new file mode 100644 index 0000000..633ee25 --- /dev/null +++ b/src/tests/fileops.h @@ -0,0 +1,54 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fileops.h: simple file access functions +*/ + +#ifndef FILEOPS_H +#define FILEOPS_H +#include +#include "ff.h" + +enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF }; + +BYTE file_buf[512]; +FATFS fatfs; +FIL file_handle; +FRESULT file_res; +uint8_t file_lfn[258]; +uint16_t file_block_off, file_block_max; +enum filestates file_status; + +void file_init(void); +void file_open(uint8_t* filename, BYTE flags); +FRESULT dir_open_by_filinfo(DIR* dir, FILINFO* fno_param); +void file_open_by_filinfo(FILINFO* fno); +void file_close(void); +void file_seek(uint32_t offset); +UINT file_read(void); +UINT file_write(void); +UINT file_readblock(void* buf, uint32_t addr, uint16_t size); +UINT file_writeblock(void* buf, uint32_t addr, uint16_t size); + +uint8_t file_getc(void); +#endif diff --git a/src/tests/filetypes.c b/src/tests/filetypes.c new file mode 100644 index 0000000..fca7dfc --- /dev/null +++ b/src/tests/filetypes.c @@ -0,0 +1,315 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + filetypes.c: directory scanning and file type detection +*/ + +#include +#include "config.h" +#include "uart.h" +#include "filetypes.h" +#include "ff.h" +#include "smc.h" +#include "fileops.h" +#include "crc32.h" +#include "memory.h" +#include "led.h" +#include "sort.h" + +uint16_t scan_flat(const char* path) { + DIR dir; + FRESULT res; + FILINFO fno; + fno.lfname = NULL; + res = f_opendir(&dir, (TCHAR*)path); + uint16_t numentries = 0; + if (res == FR_OK) { + for (;;) { + res = f_readdir(&dir, &fno); + if(res != FR_OK || fno.fname[0] == 0)break; + numentries++; + } + } + return numentries; +} + +uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_tgt) { + DIR dir; + FILINFO fno; + FRESULT res; + uint8_t len; + TCHAR* fn; + static unsigned char depth = 0; + static uint32_t crc; + static uint32_t db_tgt; + static uint32_t next_subdir_tgt; + static uint32_t parent_tgt; + static uint32_t dir_end = 0; + static uint8_t was_empty = 0; + uint32_t dir_tgt; + uint16_t numentries; + uint32_t dirsize; + uint8_t pass = 0; + char buf[7]; + char *size_units[3] = {" ", "k", "M"}; + uint32_t entry_fsize; + uint8_t entry_unit_idx; + + dir_tgt = this_dir_tgt; + if(depth==0) { + crc = 0; + db_tgt = SRAM_DB_ADDR+0x10; + dir_tgt = SRAM_DIR_ADDR; + next_subdir_tgt = SRAM_DIR_ADDR; + this_dir_tgt = SRAM_DIR_ADDR; + parent_tgt = 0; + printf("root dir @%lx\n", dir_tgt); + } + + fno.lfsize = 255; + fno.lfname = (TCHAR*)file_lfn; + numentries=0; + for(pass = 0; pass < 2; pass++) { + if(pass) { + dirsize = 4*(numentries); + next_subdir_tgt += dirsize + 4; + if(parent_tgt) next_subdir_tgt += 4; + if(next_subdir_tgt > dir_end) { + dir_end = next_subdir_tgt; + } +// printf("path=%s depth=%d ptr=%lx entries=%d parent=%lx next subdir @%lx\n", path, depth, db_tgt, numentries, parent_tgt, next_subdir_tgt); + if(mkdb) { +// printf("d=%d Saving %lx to Address %lx [end]\n", depth, 0L, next_subdir_tgt - 4); + sram_writelong(0L, next_subdir_tgt - 4); + } + } + if(fno_param) { + res = dir_open_by_filinfo(&dir, fno_param); + } else { + res = f_opendir(&dir, path); + } + if (res == FR_OK) { + if(pass && parent_tgt && mkdb) { + /* write backlink to parent dir + switch to next bank if record does not fit in current bank */ + if((db_tgt&0xffff) > ((0x10000-(sizeof(next_subdir_tgt)+sizeof(len)+4))&0xffff)) { + printf("switch! old=%lx ", db_tgt); + db_tgt &= 0xffff0000; + db_tgt += 0x00010000; + printf("new=%lx\n", db_tgt); + } +// printf("writing link to parent, %lx to address %lx [../]\n", parent_tgt-SRAM_MENU_ADDR, db_tgt); + sram_writelong((parent_tgt-SRAM_MENU_ADDR), db_tgt); + sram_writebyte(0, db_tgt+sizeof(next_subdir_tgt)); + sram_writeblock("../\0", db_tgt+sizeof(next_subdir_tgt)+sizeof(len), 4); + sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x81<<24), dir_tgt); + db_tgt += sizeof(next_subdir_tgt)+sizeof(len)+4; + dir_tgt += 4; + } + len = strlen((char*)path); + for (;;) { +// toggle_read_led(); + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) { + if(pass) { + if(!numentries) was_empty=1; + } + break; + } + fn = *fno.lfname ? fno.lfname : fno.fname; + if ((*fn == '.') || !(memcmp(fn, SYS_DIR_NAME, sizeof(SYS_DIR_NAME)))) continue; + if (fno.fattrib & AM_DIR) { + depth++; + if(depth < FS_MAX_DEPTH) { + numentries++; + if(pass) { + path[len]='/'; + strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len); + if(mkdb) { + uint16_t pathlen = strlen(path); +// printf("d=%d Saving %lx to Address %lx [dir]\n", depth, db_tgt, dir_tgt); + /* save element: + - path name + - pointer to sub dir structure */ + if((db_tgt&0xffff) > ((0x10000-(sizeof(next_subdir_tgt) + sizeof(len) + pathlen + 2))&0xffff)) { + printf("switch! old=%lx ", db_tgt); + db_tgt &= 0xffff0000; + db_tgt += 0x00010000; + printf("new=%lx\n", db_tgt); + } +// printf(" Saving dir descriptor to %lx tgt=%lx, path=%s\n", db_tgt, next_subdir_tgt, path); + /* write element pointer to current dir structure */ + sram_writelong((db_tgt-SRAM_MENU_ADDR)|((uint32_t)0x80<<24), dir_tgt); + /* save element: + - path name + - pointer to sub dir structure */ + sram_writelong((next_subdir_tgt-SRAM_MENU_ADDR), db_tgt); + sram_writebyte(len+1, db_tgt+sizeof(next_subdir_tgt)); + sram_writeblock(path, db_tgt+sizeof(next_subdir_tgt)+sizeof(len), pathlen); + sram_writeblock("/\0", db_tgt + sizeof(next_subdir_tgt) + sizeof(len) + pathlen, 2); + db_tgt += sizeof(next_subdir_tgt) + sizeof(len) + pathlen + 2; + } + parent_tgt = this_dir_tgt; + scan_dir(path, &fno, mkdb, next_subdir_tgt); + dir_tgt += 4; + was_empty = 0; + } + } + depth--; + path[len]=0; + } else { + SNES_FTYPE type = determine_filetype((char*)fn); + if(type != TYPE_UNKNOWN) { + numentries++; + if(pass) { + if(mkdb) { +/* snes_romprops_t romprops; */ + path[len]='/'; + strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len); + uint16_t pathlen = strlen(path); + switch(type) { + case TYPE_IPS: + case TYPE_SMC: +/* file_open_by_filinfo(&fno); + if(file_res){ + printf("ZOMG NOOOO %d\n", file_res); + } + smc_id(&romprops); + file_close(); */ + + /* write element pointer to current dir structure */ + DBG_FS printf("d=%d Saving %lX to Address %lX [file %s]\n", depth, db_tgt, dir_tgt, path); + if((db_tgt&0xffff) > ((0x10000-(sizeof(len) + pathlen + sizeof(buf)-1 + 1))&0xffff)) { + printf("switch! old=%lx ", db_tgt); + db_tgt &= 0xffff0000; + db_tgt += 0x00010000; + printf("new=%lx\n", db_tgt); + } + sram_writelong((db_tgt-SRAM_MENU_ADDR) | ((uint32_t)type << 24), dir_tgt); + dir_tgt += 4; + /* save element: + - index of last slash character + - file name + - file size */ +/* sram_writeblock((uint8_t*)&romprops, db_tgt, sizeof(romprops)); */ + entry_fsize = fno.fsize; + entry_unit_idx = 0; + while(entry_fsize > 9999) { + entry_fsize >>= 10; + entry_unit_idx++; + } + snprintf(buf, sizeof(buf), "% 5ld", entry_fsize); + strncat(buf, size_units[entry_unit_idx], 1); + sram_writeblock(buf, db_tgt, sizeof(buf)-1); + sram_writebyte(len+1, db_tgt + sizeof(buf)-1); + sram_writeblock(path, db_tgt + sizeof(len) + sizeof(buf)-1, pathlen + 1); +// sram_writelong(fno.fsize, db_tgt + sizeof(len) + pathlen + 1); + db_tgt += sizeof(len) + pathlen + sizeof(buf)-1 + 1; + break; + case TYPE_UNKNOWN: + default: + break; + } + path[len]=0; +/* printf("%s ", path); + _delay_ms(30); */ + } + } else { + TCHAR* fn2 = fn; + while(*fn2 != 0) { + crc += crc32_update(crc, *((unsigned char*)fn2++)); + } + } + } +/* printf("%s/%s\n", path, fn); + _delay_ms(50); */ + } + } + } else uart_putc(0x30+res); + } +// printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end); + sram_writelong(db_tgt, SRAM_DB_ADDR+4); + sram_writelong(dir_end, SRAM_DB_ADDR+8); + return crc; +} + + +SNES_FTYPE determine_filetype(char* filename) { + char* ext = strrchr(filename, '.'); + if(ext == NULL) + return TYPE_UNKNOWN; + if( (!strcasecmp(ext+1, "SMC")) + ||(!strcasecmp(ext+1, "SFC")) + ||(!strcasecmp(ext+1, "FIG")) + ||(!strcasecmp(ext+1, "BS")) + ) { + return TYPE_SMC; + } + if( (!strcasecmp(ext+1, "IPS")) + ||(!strcasecmp(ext+1, "UPS")) + ) { + return TYPE_IPS; + } + /* later + if(!strcasecmp_P(ext+1, PSTR("SRM"))) { + return TYPE_SRM; + } + if(!strcasecmp_P(ext+1, PSTR("SPC"))) { + return TYPE_SPC; + }*/ + return TYPE_UNKNOWN; +} + +FRESULT get_db_id(uint32_t* id) { + file_open((uint8_t*)"/sd2snes/sd2snes.db", FA_READ); + if(file_res == FR_OK) { + file_readblock(id, 0, 4); +/* XXX */// *id=0xdead; + file_close(); + } else { + *id=0xdeadbeef; + } + return file_res; +} + +int get_num_dirent(uint32_t addr) { + int result = 0; + while(sram_readlong(addr+result*4)) { + result++; + } + return result; +} + +void sort_all_dir(uint32_t endaddr) { + uint32_t entries = 0; + uint32_t current_base = SRAM_DIR_ADDR; + while(current_base<(endaddr)) { + while(sram_readlong(current_base+entries*4)) { + entries++; + } + printf("sorting dir @%lx, entries: %ld\n", current_base, entries); + sort_dir(current_base, entries); + current_base += 4*entries + 4; + entries = 0; + } +} diff --git a/src/tests/filetypes.h b/src/tests/filetypes.h new file mode 100644 index 0000000..d42546a --- /dev/null +++ b/src/tests/filetypes.h @@ -0,0 +1,58 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + filetypes.h: directory scanning and file type detection +*/ + +#ifndef FILETYPES_H +#define FILETYPES_H + +#ifdef DEBUG_FS +#define DBG_FS +#else +#define DBG_FS while(0) +#endif + +#include "ff.h" + +#define FS_MAX_DEPTH (10) +#define SYS_DIR_NAME ((const uint8_t*)"sd2snes") +typedef enum { + TYPE_UNKNOWN = 0, /* 0 */ + TYPE_SMC, /* 1 */ + TYPE_SRM, /* 2 */ + TYPE_SPC, /* 3 */ + TYPE_IPS /* 4 */ +} SNES_FTYPE; + + +char fs_path[256]; +SNES_FTYPE determine_filetype(char* filename); +//uint32_t scan_fs(); +uint16_t scan_flat(const char* path); +uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_subdir_tgt); +FRESULT get_db_id(uint32_t*); +int get_num_dirent(uint32_t addr); +void sort_all_dir(uint32_t endaddr); + +#endif diff --git a/src/tests/flash.cfg b/src/tests/flash.cfg new file mode 100644 index 0000000..2973ea1 --- /dev/null +++ b/src/tests/flash.cfg @@ -0,0 +1,4 @@ +# script running on reset +init +script flash.script + diff --git a/src/tests/flash.script b/src/tests/flash.script new file mode 100644 index 0000000..7d90b6e --- /dev/null +++ b/src/tests/flash.script @@ -0,0 +1,12 @@ +# mthomas 4/2008, tested with OpenOCD SVN555 + +#flash probe 0 +#flash erase_check 0 +#flash protect_check 0 +#flash info 0 + +reset init +flash write_image erase unlock obj/sd2snes.bin 0 +reset run +shutdown + diff --git a/src/tests/fpga.c b/src/tests/fpga.c new file mode 100644 index 0000000..b2328a4 --- /dev/null +++ b/src/tests/fpga.c @@ -0,0 +1,143 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fpga.c: FPGA (re)configuration +*/ + + +/* + FPGA pin mapping + ================ + CCLK P0.11 out + PROG_B P1.15 out + INIT_B P2.9 in + DIN P2.8 out + DONE P0.22 in + */ + +#include +#include "bits.h" + +#include "fpga.h" +#include "fpga_spi.h" +#include "config.h" +#include "uart.h" +#include "diskio.h" +#include "integer.h" +#include "ff.h" +#include "fileops.h" +#include "spi.h" +#include "led.h" +#include "timer.h" +#include "rle.h" + +void fpga_set_prog_b(uint8_t val) { + if(val) + BITBAND(PROGBREG->FIOSET, PROGBBIT) = 1; + else + BITBAND(PROGBREG->FIOCLR, PROGBBIT) = 1; +} + +void fpga_set_cclk(uint8_t val) { + if(val) + BITBAND(CCLKREG->FIOSET, CCLKBIT) = 1; + else + BITBAND(CCLKREG->FIOCLR, CCLKBIT) = 1; +} + +int fpga_get_initb() { + return BITBAND(INITBREG->FIOPIN, INITBBIT); +} + +void fpga_init() { +/* mainly GPIO directions */ + BITBAND(CCLKREG->FIODIR, CCLKBIT) = 1; /* CCLK */ + BITBAND(DONEREG->FIODIR, DONEBIT) = 0; /* DONE */ + BITBAND(PROGBREG->FIODIR, PROGBBIT) = 1; /* PROG_B */ + BITBAND(DINREG->FIODIR, DINBIT) = 1; /* DIN */ + BITBAND(INITBREG->FIODIR, INITBBIT) = 0; /* INIT_B */ + + LPC_GPIO2->FIOMASK1 = 0; + + SPI_OFFLOAD=0; + fpga_set_cclk(0); /* initial clk=0 */ +} + +int fpga_get_done(void) { + return BITBAND(DONEREG->FIOPIN, DONEBIT); +} + +void fpga_postinit() { + LPC_GPIO2->FIOMASK1 = 0; +} + +void fpga_pgm(uint8_t* filename) { + int MAXRETRIES = 10; + int retries = MAXRETRIES; + uint8_t data; + int i; + tick_t timeout; + do { + i=0; + timeout = getticks() + 100; + fpga_set_prog_b(0); + uart_putc('P'); + fpga_set_prog_b(1); + while(!fpga_get_initb()){ + if(getticks() > timeout) { + printf("no response from FPGA trying to initiate configuration!\n"); + led_panic(); + } + }; + LPC_GPIO2->FIOMASK1 = ~(BV(0)); + uart_putc('p'); + + + /* open configware file */ + file_open(filename, FA_READ); + if(file_res) { + uart_putc('?'); + uart_putc(0x30+file_res); + return; + } + uart_putc('C'); + + for (;;) { + data = rle_file_getc(); + i++; + if (file_status || file_res) break; /* error or eof */ + FPGA_SEND_BYTE_SERIAL(data); + } + uart_putc('c'); + file_close(); + printf("fpga_pgm: %d bytes programmed\n", i); + delay_ms(1); + } while (!fpga_get_done() && retries--); + if(!fpga_get_done()) { + printf("FPGA failed to configure after %d tries.\n", MAXRETRIES); + led_panic(); + } + printf("FPGA configured\n"); + fpga_postinit(); +} + diff --git a/src/tests/fpga.h b/src/tests/fpga.h new file mode 100644 index 0000000..c0b8ecd --- /dev/null +++ b/src/tests/fpga.h @@ -0,0 +1,68 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fpga.h: FPGA (re)configuration +*/ + +#ifndef FPGA_H +#define FPGA_H + +#include +#include "bits.h" + +void fpga_set_prog_b(uint8_t val); +void fpga_set_cclk(uint8_t val); +int fpga_get_initb(void); + +void fpga_init(void); +void fpga_postinit(void); +void fpga_pgm(uint8_t* filename); + +uint8_t SPI_OFFLOAD; + +#define CCLKREG LPC_GPIO0 +#define PROGBREG LPC_GPIO1 +#define INITBREG LPC_GPIO2 +#define DINREG LPC_GPIO2 +#define DONEREG LPC_GPIO0 + +#define CCLKBIT (11) +#define PROGBBIT (15) +#define INITBBIT (9) +#define DINBIT (8) +#define DONEBIT (22) + + +#define FPGA_TEST_TOKEN (0xa5) + +// some macros for bulk transfers (faster) +#define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\ +SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\ +SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\ +SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\ +SET_FPGA_DIN(data); CCLK();} while (0) +#define SET_CCLK() do {BITBAND(LPC_GPIO0->FIOSET, 11) = 1;} while (0) +#define CLR_CCLK() do {BITBAND(LPC_GPIO0->FIOCLR, 11) = 1;} while (0) +#define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0) +#define SET_FPGA_DIN(data) do {LPC_GPIO2->FIOPIN1 = data;} while (0) +#endif diff --git a/src/tests/fpga_spi.c b/src/tests/fpga_spi.c new file mode 100644 index 0000000..380427e --- /dev/null +++ b/src/tests/fpga_spi.c @@ -0,0 +1,528 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration +*/ +/* + + SPI commands + + cmd param function + ============================================= + 0t bbhhll set address to 0xbbhhll + t = target + target: 0 = RAM + 1 = MSU Audio buffer + 2 = MSU Data buffer + targets 1 & 2 only require 2 address bytes to + be written. + + 10 bbhhll set SNES input address mask to 0xbbhhll + 20 bbhhll set SRAM address mask to 0xbbhhll + + 3m - set mapper to m + 0=HiROM, 1=LoROM, 2=ExHiROM, 6=SF96, 7=Menu + + 4s - trigger SD DMA (512b from SD to memory) + s: Bit 2 = partial, Bit 1:0 = target + target: see above + + 60 sssseeee set SD DMA partial transfer start+end + ssss = start offset (msb first) + eeee = end offset (msb first) + + 8p - read (RAM only) + p: 0 = no increment after read + 8 = increment after read + + 9p {xx}* write xx + p: i-tt + tt = target (see above) + i = increment (see above) + + E0 ssrr set MSU-1 status register (=FPGA status [7:0]) + ss = bits to set in status register (1=set) + rr = bits to reset in status register (1=reset) + + E1 - pause DAC + E2 - resume/play DAC + E3 - reset DAC playback pointer (0) + E4 hhll set MSU read pointer + + E5 tt{7} set RTC (SPC7110 format + 1000s of year, + nibbles packed) + eg 0x20111210094816 is 2011-12-10, 9:48:16 + E6 ssrr set/reset BS-X status register [7:0] + E7 - reset SRTC state + E8 - reset DSP program and data ROM write pointers + E9 hhmmllxxxx write+incr. DSP program ROM (xxxx=dummy writes) + EA hhllxxxx write+incr. DSP data ROM (xxxx=dummy writes) + EB - put DSP into reset + EC - release DSP from reset + ED - set feature enable bits (see below) + EE - select memory (0: ROM (PSRAM), 1: RAM (SRAM)) + F0 - receive test token (to see if FPGA is alive) + F1 - receive status (16bit, MSB first), see below + + F2 - get MSU data address (32bit, MSB first) + F3 - get MSU audio track no. (16bit, MSB first) + F4 - get MSU volume (8bit) + + FE - get SNES master clock frequency (32bit, MSB first) + measured 1x/sec + FF {xx}* echo (returns the sent data in the next byte) + + FPGA status word: + bit function + ========================================================================== + 15 SD DMA busy (0=idle, 1=busy) + 14 DAC read pointer MSB + 13 MSU read pointer MSB + 12 [TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0] + 11 reserved (0) + 10 reserved (0) + 9 reserved (0) + 8 reserved (0) + 7 reserved (0) + 6 reserved (0) + 5 MSU1 Audio request from SNES + 4 MSU1 Data request from SNES + 3 reserved (0) + 2 MSU1 Audio control status: 0=no repeat, 1=repeat + 1 MSU1 Audio control status: 0=pause, 1=play + 0 MSU1 Audio control request + + FPGA feature enable bits: + bit function + ========================================================================== + 7 - + 6 - + 5 - + 4 - + 3 enable MSU1 registers + 2 enable SRTC registers + 1 enable ST0010 mapping + 0 enable DSPx mapping + +*/ + +#include +#include "bits.h" +#include "fpga.h" +#include "config.h" +#include "uart.h" +#include "spi.h" +#include "fpga_spi.h" +#include "timer.h" +#include "sdnative.h" + +void fpga_spi_init(void) { + spi_init(SPI_SPEED_FAST); + BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0; +} + +void set_msu_addr(uint16_t address) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x02); + FPGA_TX_BYTE((address>>8)&0xff); + FPGA_TX_BYTE((address)&0xff); + FPGA_DESELECT(); +} + +void set_dac_addr(uint16_t address) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x01); + FPGA_TX_BYTE((address>>8)&0xff); + FPGA_TX_BYTE((address)&0xff); + FPGA_DESELECT(); +} + +void set_mcu_addr(uint32_t address) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x00); + FPGA_TX_BYTE((address>>16)&0xff); + FPGA_TX_BYTE((address>>8)&0xff); + FPGA_TX_BYTE((address)&0xff); + FPGA_DESELECT(); +} + +void set_saveram_mask(uint32_t mask) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x20); + FPGA_TX_BYTE((mask>>16)&0xff); + FPGA_TX_BYTE((mask>>8)&0xff); + FPGA_TX_BYTE((mask)&0xff); + FPGA_DESELECT(); +} + +void set_rom_mask(uint32_t mask) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x10); + FPGA_TX_BYTE((mask>>16)&0xff); + FPGA_TX_BYTE((mask>>8)&0xff); + FPGA_TX_BYTE((mask)&0xff); + FPGA_DESELECT(); +} + +void set_mapper(uint8_t val) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x30 | (val & 0x0f)); + FPGA_DESELECT(); +} + +uint8_t fpga_test() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF0); /* TEST */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint8_t result = FPGA_RX_BYTE(); + FPGA_DESELECT(); + return result; +} + +uint16_t fpga_status() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF1); /* STATUS */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint16_t result = (FPGA_RX_BYTE()) << 8; + result |= FPGA_RX_BYTE(); + FPGA_DESELECT(); + return result; +} + +void fpga_set_sddma_range(uint16_t start, uint16_t end) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x60); /* DMA_RANGE */ + FPGA_TX_BYTE(start>>8); + FPGA_TX_BYTE(start&0xff); + FPGA_TX_BYTE(end>>8); + FPGA_TX_BYTE(end&0xff); +//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test); + FPGA_DESELECT(); +} + +void fpga_sddma(uint8_t tgt, uint8_t partial) { + uint32_t test = 0; + uint8_t status = 0; + BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0; + FPGA_SELECT(); + FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */ + FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */ +//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test); + FPGA_DESELECT(); + FPGA_SELECT(); + FPGA_TX_BYTE(0xF1); /* STATUS */ + FPGA_TX_BYTE(0x00); /* dummy */ + DBG_SD printf("FPGA DMA request sent, wait for completion..."); + while((status=FPGA_RX_BYTE()) & 0x80) { + FPGA_RX_BYTE(); /* eat the 2nd status byte */ + test++; + } + DBG_SD printf("...complete\n"); + FPGA_DESELECT(); + if(test<5)printf("loopy: %ld %02x\n", test, status); + BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1; +} + +void set_dac_vol(uint8_t volume) { + FPGA_SELECT(); + FPGA_TX_BYTE(0x50); + FPGA_TX_BYTE(volume); + FPGA_TX_BYTE(0x00); /* latch rise */ + FPGA_TX_BYTE(0x00); /* latch fall */ + FPGA_DESELECT(); +} + +void dac_play() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe2); + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +void dac_pause() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe1); + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +void dac_reset() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe3); + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +void msu_reset(uint16_t address) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe4); + FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */ + FPGA_TX_BYTE(address & 0xff); /* address lo */ + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +void set_msu_status(uint8_t set, uint8_t reset) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe0); + FPGA_TX_BYTE(set); + FPGA_TX_BYTE(reset); + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +uint8_t get_msu_volume() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint8_t result = FPGA_RX_BYTE(); + FPGA_DESELECT(); + return result; +} + +uint16_t get_msu_track() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF3); /* MSU_TRACK */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint16_t result = (FPGA_RX_BYTE()) << 8; + result |= FPGA_RX_BYTE(); + FPGA_DESELECT(); + return result; +} + +uint32_t get_msu_offset() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_romselclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF7); + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_cpuclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF8); + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_readclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xF9); + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_writeclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xFA); /* GET_SYSCLK */ + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_pardclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xFB); /* GET_SYSCLK */ + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_pawrclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xFC); /* GET_SYSCLK */ + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_refreshclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xFD); /* GET_SYSCLK */ + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +uint32_t get_snes_sysclk() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */ + FPGA_TX_BYTE(0x00); /* dummy */ + FPGA_TX_BYTE(0x00); /* dummy */ + uint32_t result = (FPGA_RX_BYTE()) << 24; + result |= (FPGA_RX_BYTE()) << 16; + result |= (FPGA_RX_BYTE()) << 8; + result |= (FPGA_RX_BYTE()); + FPGA_DESELECT(); + return result; +} + +void set_bsx_regs(uint8_t set, uint8_t reset) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe6); + FPGA_TX_BYTE(set); + FPGA_TX_BYTE(reset); + FPGA_TX_BYTE(0x00); /* latch reset */ + FPGA_DESELECT(); +} + +void set_fpga_time(uint64_t time) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe5); + FPGA_TX_BYTE((time >> 48) & 0xff); + FPGA_TX_BYTE((time >> 40) & 0xff); + FPGA_TX_BYTE((time >> 32) & 0xff); + FPGA_TX_BYTE((time >> 24) & 0xff); + FPGA_TX_BYTE((time >> 16) & 0xff); + FPGA_TX_BYTE((time >> 8) & 0xff); + FPGA_TX_BYTE(time & 0xff); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_reset_srtc_state() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe7); + FPGA_TX_BYTE(0x00); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_reset_dspx_addr() { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe8); + FPGA_TX_BYTE(0x00); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_write_bram_data(uint8_t data) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe9); + FPGA_TX_BYTE(data); + FPGA_TX_BYTE(0x00); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_write_dspx_dat(uint16_t data) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xea); + FPGA_TX_BYTE((data>>8)&0xff); + FPGA_TX_BYTE((data)&0xff); + FPGA_TX_BYTE(0x00); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_dspx_reset(uint8_t reset) { + FPGA_SELECT(); + FPGA_TX_BYTE(reset ? 0xeb : 0xec); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +void fpga_set_features(uint8_t feat) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xed); + FPGA_TX_BYTE(feat); + FPGA_DESELECT(); +} + +void fpga_select_mem(uint8_t unit) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xee); + FPGA_TX_BYTE(unit); + FPGA_DESELECT(); +} + +void fpga_set_bram_addr(uint16_t addr) { + FPGA_SELECT(); + FPGA_TX_BYTE(0xe8); + FPGA_TX_BYTE((addr>>8)&0xff); + FPGA_TX_BYTE((addr)&0xff); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); +} + +uint8_t fpga_read_bram_data() { + uint8_t data; + FPGA_SELECT(); + FPGA_TX_BYTE(0xf5); + FPGA_TX_BYTE(0x00); + data = FPGA_RX_BYTE(); + FPGA_TX_BYTE(0x00); + FPGA_DESELECT(); + return data; +} diff --git a/src/tests/fpga_spi.h b/src/tests/fpga_spi.h new file mode 100644 index 0000000..6d9922e --- /dev/null +++ b/src/tests/fpga_spi.h @@ -0,0 +1,104 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + uC firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration +*/ + +#ifndef _FPGA_SPI_H +#define _FPGA_SPI_H + +#include +#include "bits.h" +#include "spi.h" +#include "config.h" + +#define FPGA_SS_BIT 16 +#define FPGA_SS_REG LPC_GPIO0 + +#define FPGA_SELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0) +#define FPGA_SELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOCLR, FPGA_SS_BIT) = 1;} while (0) +#define FPGA_DESELECT() do {FPGA_TX_SYNC(); BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0) +#define FPGA_DESELECT_ASYNC() do {BITBAND(FPGA_SS_REG->FIOSET, FPGA_SS_BIT) = 1;} while (0) + +#define FPGA_TX_SYNC() spi_tx_sync() +#define FPGA_TX_BYTE(x) spi_tx_byte(x) +#define FPGA_RX_BYTE() spi_rx_byte() +#define FPGA_TXRX_BYTE(x) spi_txrx_byte(x) +#define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y) +#define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y) + +#define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST) +#define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW) + +#define FEAT_CX4 (1 << 4) +#define FEAT_MSU1 (1 << 3) +#define FEAT_SRTC (1 << 2) +#define FEAT_ST0010 (1 << 1) +#define FEAT_DSPX (1 << 0) + +#define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0) + +void fpga_spi_init(void); +uint8_t fpga_test(void); +uint16_t fpga_status(void); +void spi_fpga(void); +void spi_sd(void); +void spi_none(void); +void set_mcu_addr(uint32_t); +void set_dac_addr(uint16_t); +void set_dac_vol(uint8_t); +void dac_play(void); +void dac_pause(void); +void dac_reset(void); +void msu_reset(uint16_t); +void set_msu_addr(uint16_t); +void set_msu_status(uint8_t set, uint8_t reset); +void set_saveram_mask(uint32_t); +void set_rom_mask(uint32_t); +void set_mapper(uint8_t val); +void fpga_sddma(uint8_t tgt, uint8_t partial); +void fpga_set_sddma_range(uint16_t start, uint16_t end); +uint8_t get_msu_volume(void); +uint16_t get_msu_track(void); +uint32_t get_msu_offset(void); +uint32_t get_snes_sysclk(void); +uint32_t get_snes_readclk(void); +uint32_t get_snes_writeclk(void); +uint32_t get_snes_pardclk(void); +uint32_t get_snes_pawrclk(void); +uint32_t get_snes_refreshclk(void); +uint32_t get_snes_cpuclk(void); +uint32_t get_snes_romselclk(void); +void set_bsx_regs(uint8_t set, uint8_t reset); +void set_fpga_time(uint64_t time); +void fpga_reset_srtc_state(void); +void fpga_reset_dspx_addr(void); +void fpga_write_dspx_pgm(uint32_t data); +void fpga_write_dspx_dat(uint16_t data); +void fpga_dspx_reset(uint8_t reset); +void fpga_set_features(uint8_t feat); +void fpga_select_mem(uint8_t unit); +void fpga_set_bram_addr(uint16_t addr); +uint8_t fpga_read_bram_data(void); +void fpga_write_bram_data(uint8_t data); +#endif diff --git a/src/tests/integer.h b/src/tests/integer.h new file mode 100644 index 0000000..ccc97d3 --- /dev/null +++ b/src/tests/integer.h @@ -0,0 +1,37 @@ +/*-------------------------------------------*/ +/* Integer type definitions for FatFs module */ +/*-------------------------------------------*/ + +#ifndef _INTEGER +#define _INTEGER + +#ifdef _WIN32 /* FatFs development platform */ + +#include +#include + +#else /* Embedded platform */ + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + +#endif + +#endif diff --git a/src/tests/irq.c b/src/tests/irq.c new file mode 100644 index 0000000..b4f3ee8 --- /dev/null +++ b/src/tests/irq.c @@ -0,0 +1,15 @@ +#include +#include "bits.h" +#include "config.h" +#include "sdnative.h" +#include "uart.h" + +void EINT3_IRQHandler(void) { + NVIC_ClearPendingIRQ(EINT3_IRQn); + if(SD_CHANGE_DETECT) { + SD_CHANGE_CLR(); + sdn_changed(); + } +} + + diff --git a/src/tests/led.c b/src/tests/led.c new file mode 100644 index 0000000..d3da43b --- /dev/null +++ b/src/tests/led.c @@ -0,0 +1,145 @@ +/* ___DISCLAIMER___ */ + +#include +#include "bits.h" +#include "timer.h" +#include "led.h" +#include "cli.h" + +static uint8_t led_bright[16]={255,253,252,251,249,247,244,239,232,223,210,191,165,127,74,0}; + +int led_rdyledstate = 0; +int led_readledstate = 0; +int led_writeledstate = 0; +int led_pwmstate = 0; + +/* LED connections (Rev.C) + + LED color IO PWM + --------------------------- + ready green P2.4 PWM1[5] + read yellow P2.5 PWM1[6] + write red P1.23 PWM1[4] +*/ + +void rdyled(unsigned int state) { + if(led_pwmstate) { + rdybright(state?15:0); + } else { + BITBAND(LPC_GPIO2->FIODIR, 4) = state; + } + led_rdyledstate = state; +} + +void readled(unsigned int state) { + if(led_pwmstate) { + readbright(state?15:0); + } else { + BITBAND(LPC_GPIO2->FIODIR, 5) = state; + } + led_readledstate = state; +} + +void writeled(unsigned int state) { + if(led_pwmstate) { + writebright(state?15:0); + } else { + BITBAND(LPC_GPIO1->FIODIR, 23) = state; + } + led_writeledstate = state; +} + +void rdybright(uint8_t bright) { + LPC_PWM1->MR5 = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, 5) = 1; +} +void readbright(uint8_t bright) { + LPC_PWM1->MR6 = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, 6) = 1; +} +void writebright(uint8_t bright) { + LPC_PWM1->MR4 = led_bright[(bright & 15)]; + BITBAND(LPC_PWM1->LER, 4) = 1; +} + +void led_clkout32(uint32_t val) { + while(1) { + rdyled(1); + delay_ms(400); + readled((val & BV(31))>>31); + rdyled(0); + val<<=1; + delay_ms(400); + } +} + +void toggle_rdy_led() { + rdyled(~led_rdyledstate); +} + +void toggle_read_led() { + readled(~led_readledstate); +} + +void toggle_write_led() { + writeled(~led_writeledstate); +} + +void led_panic() { + while(1) { + LPC_GPIO2->FIODIR |= BV(4) | BV(5); + LPC_GPIO1->FIODIR |= BV(23); + delay_ms(350); + LPC_GPIO2->FIODIR &= ~(BV(4) | BV(5)); + LPC_GPIO1->FIODIR &= ~BV(23); + delay_ms(350); + cli_entrycheck(); + } +} + +void led_pwm() { +/* Rev.C P2.4, P2.5, P1.23 */ + BITBAND(LPC_PINCON->PINSEL4, 9) = 0; + BITBAND(LPC_PINCON->PINSEL4, 8) = 1; + + BITBAND(LPC_PINCON->PINSEL4, 11) = 0; + BITBAND(LPC_PINCON->PINSEL4, 10) = 1; + + BITBAND(LPC_PINCON->PINSEL3, 15) = 1; + BITBAND(LPC_PINCON->PINSEL3, 14) = 0; + + BITBAND(LPC_PWM1->PCR, 12) = 1; + BITBAND(LPC_PWM1->PCR, 13) = 1; + BITBAND(LPC_PWM1->PCR, 14) = 1; + + led_pwmstate = 1; +} + +void led_std() { + BITBAND(LPC_PINCON->PINSEL4, 9) = 0; + BITBAND(LPC_PINCON->PINSEL4, 8) = 0; + + BITBAND(LPC_PINCON->PINSEL4, 11) = 0; + BITBAND(LPC_PINCON->PINSEL4, 10) = 0; + + BITBAND(LPC_PINCON->PINSEL3, 15) = 0; + BITBAND(LPC_PINCON->PINSEL3, 14) = 0; + + BITBAND(LPC_PWM1->PCR, 12) = 0; + BITBAND(LPC_PWM1->PCR, 13) = 0; + BITBAND(LPC_PWM1->PCR, 14) = 0; + + led_pwmstate = 0; +} + +void led_init() { +/* power is already connected by default */ +/* set PCLK divider to 8 */ + BITBAND(LPC_SC->PCLKSEL0, 13) = 1; + BITBAND(LPC_SC->PCLKSEL0, 12) = 1; + LPC_PWM1->MR0 = 255; + BITBAND(LPC_PWM1->LER, 0) = 1; + BITBAND(LPC_PWM1->TCR, 0) = 1; + BITBAND(LPC_PWM1->TCR, 3) = 1; + BITBAND(LPC_PWM1->MCR, 1) = 1; +} diff --git a/src/tests/led.h b/src/tests/led.h new file mode 100644 index 0000000..bb45b1a --- /dev/null +++ b/src/tests/led.h @@ -0,0 +1,21 @@ +/* ___DISCLAIMER___ */ + +#ifndef _LED_H +#define _LED_H + +void readbright(uint8_t bright); +void writebright(uint8_t bright); +void rdybright(uint8_t bright); +void readled(unsigned int state); +void writeled(unsigned int state); +void rdyled(unsigned int state); +void led_clkout32(uint32_t val); +void toggle_rdy_led(void); +void toggle_read_led(void); +void toggle_write_led(void); +void led_panic(void); +void led_pwm(void); +void led_std(void); +void led_init(void); + +#endif diff --git a/src/tests/lpc1754.cfg b/src/tests/lpc1754.cfg new file mode 100644 index 0000000..fa34d17 --- /dev/null +++ b/src/tests/lpc1754.cfg @@ -0,0 +1,77 @@ +# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM, +# reset_config trst_and_srst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc1754 +} + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK ] } { + set _CCLK $CCLK +} else { + set _CCLK 4000 +} +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +#delays on reset lines +#if your OpenOCD version rejects "jtag_nsrst_delay" replace it with: +#adapter_nsrst_delay 200 +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 + +# LPC2000 & LPC1700 -> SRST causes TRST +#reset_config srst_pulls_trst +reset_config trst_and_srst srst_push_pull trst_push_pull + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +#jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0 + +# LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +# and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000). +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x4000 +$_TARGETNAME configure -work-area-phys 0x2007c000 -work-area-size 0x4000 + +# LPC1754 has 128kB of flash memory, managed by ROM code (including a +# boot loader which verifies the flash exception table's checksum). +# flash bank lpc2000 0 0 [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +jtag_khz 1000 + +$_TARGETNAME configure -event reset-init { + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + mww 0x400FC040 0x01 +} diff --git a/src/tests/lpc1754.ld b/src/tests/lpc1754.ld new file mode 100644 index 0000000..b10c20a --- /dev/null +++ b/src/tests/lpc1754.ld @@ -0,0 +1,131 @@ +/* Linker script for LPC1754 + * + * Written 2010 by Ingo Korb + * + * Partially based on the linker scripts of avr-libc + */ + +OUTPUT_FORMAT(elf32-littlearm) +ENTRY(_start) + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 /* leave room for bootldr + metadata */ + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x04000 + ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000 +} + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + + /* C++ con-/destructors */ + __ctors_start = . ; + *(.ctors) + __ctors_end = . ; + __dtors_start = . ; + *(.dtors) + __dtors_end = . ; + KEEP(SORT(*)(.ctors)) + KEEP(SORT(*)(.dtors)) + + KEEP(*(.fini)) + + __text_end = .; + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >flash + __exidx_end = .; + + /* I hope this does what I think it does */ + .rodata : AT (ALIGN(__exidx_end,4)) + { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; + } > flash + + /* Data section */ + .data : AT (ALIGN(__rodata_end,4)) + { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; + } > ram + + /* Addresses of in-rom data section */ + __data_load_start = LOADADDR(.data); + __data_load_end = __data_load_start + SIZEOF(.data); + + . = ALIGN(4); + + /* BSS */ + .bss : + { + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + __bss_end__ = .; + } > ram + + /* second BSS in AHB ram */ + .ahbram (NOLOAD) : + { + __ahbram_start__ = .; + *(.ahbram) + *(.ahbram.*) + __ahbram_end__ = .; + } > ahbram + + __heap_start = ALIGN(__bss_end__, 4); + + /* Default stack starts at end of ram */ + PROVIDE(__stack = ORIGIN(ram) + LENGTH(ram)) ; + + + /* Everyone seems to copy the stuff below straight from somewhere else, so I'll do that too */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } +} diff --git a/src/tests/main.c b/src/tests/main.c new file mode 100644 index 0000000..25ba103 --- /dev/null +++ b/src/tests/main.c @@ -0,0 +1,164 @@ +#include +#include +#include "config.h" +#include "obj/autoconf.h" +#include "clock.h" +#include "uart.h" +#include "bits.h" +#include "power.h" +#include "timer.h" +#include "ff.h" +#include "diskio.h" +#include "spi.h" +#include "fileops.h" +#include "fpga.h" +#include "fpga_spi.h" +#include "filetypes.h" +#include "memory.h" +#include "snes.h" +#include "led.h" +#include "sort.h" +#include "cic.h" +#include "tests.h" +#include "cli.h" +#include "sdnative.h" +#include "crc.h" +#include "smc.h" +#include "msu1.h" +#include "rtc.h" +#include "tests.h" + +#define EMC0TOGGLE (3<<4) +#define MR0R (1<<1) + +int i; + +int sd_offload = 0, ff_sd_offload = 0, sd_offload_tgt = 0; +int sd_offload_partial = 0; +uint16_t sd_offload_partial_start = 0; +uint16_t sd_offload_partial_end = 0; + +volatile enum diskstates disk_state; +extern volatile tick_t ticks; +extern snes_romprops_t romprops; +extern volatile int reset_changed; + +enum system_states { + SYS_RTC_STATUS = 0 +}; + +int main(void) { + LPC_GPIO2->FIODIR = BV(4) | BV(5); + LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT); + BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1; + LPC_GPIO0->FIODIR = BV(16); + + /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */ + LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */ + | BV(3) | BV(5); /* SSP0 (FPGA) except SS */ + LPC_PINCON->PINSEL0 = BV(31); /* SSP0 */ +/* | BV(13) | BV(15) | BV(17) | BV(19) SSP1 (SD) */ + + /* pull-down CIC data lines */ + LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3); + + clock_disconnect(); + snes_init(); + snes_reset(1); + power_init(); + timer_init(); + uart_init(); + fpga_spi_init(); + spi_preinit(); + led_init(); + /* do this last because the peripheral init()s change PCLK dividers */ + clock_init(); + LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ +led_pwm(); + sdn_init(); + printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); + printf("PCONP=%lx\n", LPC_SC->PCONP); + + file_init(); + cic_init(0); +/* setup timer (fpga clk) */ + LPC_TIM3->CTCR=0; + LPC_TIM3->EMR=EMC0TOGGLE; + LPC_TIM3->MCR=MR0R; + LPC_TIM3->MR0=1; + LPC_TIM3->TCR=1; + fpga_init(); + + char *testnames[11] = { "SD ", "USB ", "RTC ", "CIC ", + "FPGA ", "RAM ", "CLK ", "DAC ", + "SNES IRQ", "SNES RAM", "SNES PA "}; + + char *teststate_names [3] = { "no run", "\x1b[32;1mPassed\x1b[m", "\x1b[31;1mFAILED\x1b[m" }; + + int testresults[11] = { NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN, + NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN, + NO_RUN }; + + testresults[TEST_SD] = test_sd(); +//testresults[TEST_USB] = test_usb(); + testresults[TEST_RTC] = test_rtc(); + delay_ms(209); + testresults[TEST_CIC] = test_cic(); + testresults[TEST_FPGA] = test_fpga(); + testresults[TEST_RAM] = test_mem(); + printf("Loading SNES test ROM\n=====================\n"); + load_rom((uint8_t*)"/sd2snes/test.bin", 0, LOADROM_WITH_RESET); + printf("\n\n\n"); + delay_ms(1000); + testresults[TEST_CLK] = test_clk(); + fpga_set_bram_addr(0x1fff); + fpga_write_bram_data(0x01); // tell SNES test program to continue + uint8_t snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank; + uint8_t snestest_irq_done = 0, snestest_pa_done = 0, snestest_mem_done = 0; + uint8_t last_irq_state = 0x77, last_pa_state = 0x77, last_mem_state = 0x77, last_mem_bank = 0x77; + uint32_t failed_addr = 0; + while(!(snestest_irq_done & snestest_pa_done & snestest_mem_done)) { + fpga_set_bram_addr(0); + snestest_irq_state = fpga_read_bram_data(); + snestest_mem_state = fpga_read_bram_data(); + snestest_pa_state = fpga_read_bram_data(); + snestest_mem_bank = fpga_read_bram_data(); + if(snestest_irq_state != last_irq_state + || snestest_mem_state != last_mem_state + || snestest_pa_state != last_pa_state + || snestest_mem_bank != last_mem_bank) { + printf("SNES test status: IRQ: %02x PA: %02x MEM: %02x/%02x\r", snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank); + } + last_irq_state = snestest_irq_state; + last_mem_state = snestest_mem_state; + last_pa_state = snestest_pa_state; + last_mem_bank = snestest_mem_bank; + if(snestest_pa_state != 0x00) snestest_pa_done = 1; + if(snestest_irq_state != 0x00) snestest_irq_done = 1; + if(snestest_mem_state == 0xff || snestest_mem_state == 0x5a) snestest_mem_done = 1; + cli_entrycheck(); + } + printf("\n"); + if(snestest_pa_state == 0xff) testresults[TEST_SNES_PA] = FAILED; + else testresults[TEST_SNES_PA] = PASSED; + if(snestest_irq_state == 0xff) testresults[TEST_SNES_IRQ] = FAILED; + else testresults[TEST_SNES_IRQ] = PASSED; + if(snestest_mem_state == 0xff) { + testresults[TEST_SNES_RAM] = FAILED; + fpga_set_bram_addr(4); + failed_addr = fpga_read_bram_data(); + failed_addr |= fpga_read_bram_data() << 8; + failed_addr |= fpga_read_bram_data() << 16; + printf("SNES MEM test FAILED (failed address: %06lx)\n", failed_addr); + } + else testresults[TEST_SNES_RAM] = PASSED; + printf("\n\nTEST SUMMARY\n============\n\n"); + printf("Test Result\n----------------\n"); + int testcount; + for(testcount=0; testcount < 11; testcount++) { + printf("%s %s\n", testnames[testcount], teststate_names[testresults[testcount]]); + } + cli_loop(); + while(1); +} + diff --git a/src/tests/memory.c b/src/tests/memory.c new file mode 100644 index 0000000..64cedae --- /dev/null +++ b/src/tests/memory.c @@ -0,0 +1,547 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + memory.c: RAM operations +*/ + + +#include "config.h" +#include "uart.h" +#include "fpga.h" +#include "crc.h" +#include "crc32.h" +#include "ff.h" +#include "fileops.h" +#include "spi.h" +#include "fpga_spi.h" +#include "led.h" +#include "smc.h" +#include "memory.h" +#include "snes.h" +#include "timer.h" +#include "rle.h" +#include "diskio.h" +#include "msu1.h" + +#include +char* hex = "0123456789ABCDEF"; + +extern snes_romprops_t romprops; + +void sram_hexdump(uint32_t addr, uint32_t len) { + static uint8_t buf[16]; + uint32_t ptr; + for(ptr=0; ptr < len; ptr += 16) { + sram_readblock((void*)buf, ptr+addr, 16); + uart_trace(buf, 0, 16); + } +} + +void sram_writebyte(uint8_t val, uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x98); /* WRITE */ + FPGA_TX_BYTE(val); + FPGA_WAIT_RDY(); + FPGA_DESELECT(); +} + +uint8_t sram_readbyte(uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x88); /* READ */ + FPGA_WAIT_RDY(); + uint8_t val = FPGA_RX_BYTE(); + FPGA_DESELECT(); + return val; +} + +void sram_writeshort(uint16_t val, uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x98); /* WRITE */ + FPGA_TX_BYTE(val&0xff); + FPGA_WAIT_RDY(); + FPGA_TX_BYTE((val>>8)&0xff); + FPGA_WAIT_RDY(); + FPGA_DESELECT(); +} + +void sram_writelong(uint32_t val, uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x98); /* WRITE */ + FPGA_TX_BYTE(val&0xff); + FPGA_WAIT_RDY(); + FPGA_TX_BYTE((val>>8)&0xff); + FPGA_WAIT_RDY(); + FPGA_TX_BYTE((val>>16)&0xff); + FPGA_WAIT_RDY(); + FPGA_TX_BYTE((val>>24)&0xff); + FPGA_WAIT_RDY(); + FPGA_DESELECT(); +} + +uint16_t sram_readshort(uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x88); + FPGA_WAIT_RDY(); + uint32_t val = FPGA_RX_BYTE(); + FPGA_WAIT_RDY(); + val |= ((uint32_t)FPGA_RX_BYTE()<<8); + FPGA_DESELECT(); + return val; +} + +uint32_t sram_readlong(uint32_t addr) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x88); + FPGA_WAIT_RDY(); + uint32_t val = FPGA_RX_BYTE(); + FPGA_WAIT_RDY(); + val |= ((uint32_t)FPGA_RX_BYTE()<<8); + FPGA_WAIT_RDY(); + val |= ((uint32_t)FPGA_RX_BYTE()<<16); + FPGA_WAIT_RDY(); + val |= ((uint32_t)FPGA_RX_BYTE()<<24); + FPGA_DESELECT(); + return val; +} + +void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count) { + set_mcu_addr(addr); + FPGA_SELECT(); + FPGA_TX_BYTE(0x88); + uint16_t i=0; + while(i (romprops.romsize_bytes + romprops.offset)) { + romprops.romsize_bytes <<= 1; + } + + if(romprops.header.ramsize == 0) { + rammask = 0; + } else { + rammask = romprops.ramsize_bytes - 1; + } + rommask = romprops.romsize_bytes - 1; + printf("ramsize=%x rammask=%lx\nromsize=%x rommask=%lx\n", romprops.header.ramsize, rammask, romprops.header.romsize, rommask); + set_saveram_mask(rammask); + set_rom_mask(rommask); + readled(0); + if(flags & LOADROM_WITH_SRAM) { + if(romprops.ramsize_bytes) { + strcpy(strrchr((char*)filename, (int)'.'), ".srm"); + printf("SRM file: %s\n", filename); + load_sram(filename, SRAM_SAVE_ADDR); + } else { + printf("No SRAM\n"); + } + } + + printf("check MSU..."); + if(msu1_check(filename)) { + romprops.fpga_features |= FEAT_MSU1; + romprops.has_msu1 = 1; + } else { + romprops.has_msu1 = 0; + } + printf("done\n"); + + romprops.fpga_features |= FEAT_SRTC; + + fpga_set_features(romprops.fpga_features); + + if(flags & LOADROM_WITH_RESET) { + fpga_dspx_reset(1); + snes_reset(1); + delay_ms(10); + snes_reset(0); + fpga_dspx_reset(0); + } + + return (uint32_t)filesize; +} + +uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr) { + set_mcu_addr(base_addr); + UINT bytes_read; + DWORD filesize; + file_open(filename, FA_READ); + filesize = file_handle.fsize; + if(file_res) return 0; + for(;;) { + ff_sd_offload=1; + sd_offload_tgt=0; + bytes_read = file_read(); + if (file_res || !bytes_read) break; + } + file_close(); + return (uint32_t)filesize; +} + +uint32_t load_sram(uint8_t* filename, uint32_t base_addr) { + set_mcu_addr(base_addr); + UINT bytes_read; + DWORD filesize; + file_open(filename, FA_READ); + filesize = file_handle.fsize; + if(file_res) { + printf("load_sram: could not open %s, res=%d\n", filename, file_res); + return 0; + } + for(;;) { + bytes_read = file_read(); + if (file_res || !bytes_read) break; + FPGA_SELECT(); + FPGA_TX_BYTE(0x98); + for(int j=0; j + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + memory.h: RAM operations +*/ + +#ifndef MEMORY_H +#define MEMORY_H + +#include +#include "smc.h" + +#define SRAM_ROM_ADDR (0x000000L) +#define SRAM_SAVE_ADDR (0xE00000L) + +#define SRAM_MENU_ADDR (0xE00000L) +#define SRAM_DB_ADDR (0xE40000L) +#define SRAM_DIR_ADDR (0xE10000L) +#define SRAM_CMD_ADDR (0xFF1000L) +#define SRAM_PARAM_ADDR (0xFF1004L) +#define SRAM_STATUS_ADDR (0xFF1100L) +#define SRAM_MENU_SAVE_ADDR (0xFF0000L) +#define SRAM_SCRATCHPAD (0xFFFF00L) +#define SRAM_DIRID (0xFFFFF0L) +#define SRAM_RELIABILITY_SCORE (0x100) + +#define LOADROM_WITH_SRAM (1) +#define LOADROM_WITH_RESET (2) + +uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags); +uint32_t load_sram(uint8_t* filename, uint32_t base_addr); +uint32_t load_sram_offload(uint8_t* filename, uint32_t base_addr); +uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr); +void load_dspx(const uint8_t* filename, uint8_t st0010); +void sram_hexdump(uint32_t addr, uint32_t len); +uint8_t sram_readbyte(uint32_t addr); +uint16_t sram_readshort(uint32_t addr); +uint32_t sram_readlong(uint32_t addr); +void sram_writebyte(uint8_t val, uint32_t addr); +void sram_writeshort(uint16_t val, uint32_t addr); +void sram_writelong(uint32_t val, uint32_t addr); +void sram_readblock(void* buf, uint32_t addr, uint16_t size); +void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count); +void sram_writeblock(void* buf, uint32_t addr, uint16_t size); +void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr); +uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size); +uint8_t sram_reliable(void); +void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val); +uint64_t sram_gettime(uint32_t base_addr); + +#endif diff --git a/src/tests/msu1.c b/src/tests/msu1.c new file mode 100644 index 0000000..6dc298f --- /dev/null +++ b/src/tests/msu1.c @@ -0,0 +1,256 @@ +#include +#include "config.h" +#include "uart.h" +#include "ff.h" +#include "diskio.h" +#include "spi.h" +#include "fpga_spi.h" +#include "cli.h" +#include "fileops.h" +#include "msu1.h" +#include "snes.h" +#include "timer.h" +#include "smc.h" + +FIL msufile; +extern snes_romprops_t romprops; + +int msu1_check_reset(void) { + static tick_t rising_ticks; + + static uint8_t resbutton=0, resbutton_prev=0; + resbutton = get_snes_reset(); + if(resbutton && !resbutton_prev) { /* push */ + rising_ticks = getticks(); + } else if(resbutton && resbutton_prev) { /* hold */ + if(getticks() > rising_ticks + 99) { + return 1; + } + } + resbutton_prev = resbutton; + return 0; +} + +int msu1_check(uint8_t* filename) { +/* open MSU file */ + strcpy((char*)file_buf, (char*)filename); + strcpy(strrchr((char*)file_buf, (int)'.'), ".msu"); + printf("MSU datafile: %s\n", file_buf); + if(f_open(&msufile, (const TCHAR*)file_buf, FA_READ) != FR_OK) { + printf("MSU datafile not found\n"); + return 0; + } + romprops.fpga_features |= FEAT_MSU1; + return 1; +} + +int msu1_loop() { +/* it is assumed that the MSU file is already opened by calling msu1_check(). */ + UINT bytes_read = 1024; + UINT bytes_read2 = 1; + FRESULT res; + set_dac_vol(0x00); + while(fpga_status() & 0x4000); + uint16_t fpga_status_prev = fpga_status(); + uint16_t fpga_status_now = fpga_status(); + uint16_t dac_addr = 0; + uint16_t msu_addr = 0; + uint8_t msu_repeat = 0; + uint16_t msu_track = 0; + uint32_t msu_offset = 0; + uint32_t msu_loop_point = 0; + + uint32_t msu_page1_start = 0x0000; + uint32_t msu_page2_start = 0x2000; + uint32_t msu_page_size = 0x2000; + + set_msu_addr(0x0); + msu_reset(0x0); + ff_sd_offload=1; + sd_offload_tgt=2; + f_lseek(&msufile, 0L); + ff_sd_offload=1; + sd_offload_tgt=2; + f_read(&msufile, file_buf, 16384, &bytes_read2); + + set_dac_addr(dac_addr); + dac_pause(); + dac_reset(); +/* audio_start, data_start, 0, audio_ctrl[1:0], ctrl_start */ + while(1){ + cli_entrycheck(); + fpga_status_now = fpga_status(); + + /* Data buffer refill */ + if((fpga_status_now & 0x2000) != (fpga_status_prev & 0x2000)) { + DBG_MSU1 printf("data\n"); + uint8_t pageno = 0; + if(fpga_status_now & 0x2000) { + msu_addr = 0x0; + msu_page1_start = msu_page2_start + msu_page_size; + pageno = 1; + } else { + msu_addr = 0x2000; + msu_page2_start = msu_page1_start + msu_page_size; + pageno = 2; + } + set_msu_addr(msu_addr); + sd_offload_tgt=2; + ff_sd_offload=1; + res = f_read(&msufile, file_buf, 8192, &bytes_read2); + DBG_MSU1 printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", res, msu_page1_start, msu_page2_start); + } + + /* Audio buffer refill */ + if((fpga_status_now & 0x4000) != (fpga_status_prev & 0x4000)) { + if(fpga_status_now & 0x4000) { + dac_addr = 0; + } else { + dac_addr = MSU_DAC_BUFSIZE/2; + } + set_dac_addr(dac_addr); + sd_offload_tgt=1; + ff_sd_offload=1; + f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE/2, &bytes_read); + } + + if(fpga_status_now & 0x0020) { + char suffix[11]; + + /* get trackno */ + msu_track = get_msu_track(); + printf("Audio requested! Track=%d\n", msu_track); + + /* open file, fill buffer */ + f_close(&file_handle); + snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track); + strcpy((char*)file_buf, (char*)file_lfn); + strcpy(strrchr((char*)file_buf, (int)'.'), suffix); + printf("filename: %s\n", file_buf); + f_open(&file_handle, (const TCHAR*)file_buf, FA_READ); + f_lseek(&file_handle, 4L); + f_read(&file_handle, &msu_loop_point, 4, &bytes_read); + printf("loop point: %ld samples\n", msu_loop_point); + ff_sd_offload=1; + sd_offload_tgt=1; + f_lseek(&file_handle, 8L); + set_dac_addr(0); + dac_pause(); + dac_reset(); + ff_sd_offload=1; + sd_offload_tgt=1; + f_read(&file_handle, file_buf, MSU_DAC_BUFSIZE, &bytes_read); + + /* clear busy bit */ + set_msu_status(0x00, 0x20); /* set no bits, reset bit 5 */ + } + + if(fpga_status_now & 0x0010) { + /* get address */ + msu_offset=get_msu_offset(); + printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start); + if( ((msu_offset < msu_page1_start) + || (msu_offset >= msu_page1_start + msu_page_size)) + && ((msu_offset < msu_page2_start) + || (msu_offset >= msu_page2_start + msu_page_size))) { + printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start, + msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1); + /* "cache miss" */ + /* fill buffer */ + set_msu_addr(0x0); + sd_offload_tgt=2; + ff_sd_offload=1; + res = f_lseek(&msufile, msu_offset); + DBG_MSU1 printf("seek to %08lx, res = %d\n", msu_offset, res); + sd_offload_tgt=2; + ff_sd_offload=1; + + res = f_read(&msufile, file_buf, 16384, &bytes_read2); + DBG_MSU1 printf("read res = %d\n", res); + DBG_MSU1 printf("read %d bytes\n", bytes_read2); + msu_reset(0x0); + msu_page1_start = msu_offset; + msu_page2_start = msu_offset + msu_page_size; + } else { + if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) { + msu_reset(0x0000 + msu_offset - msu_page1_start); + DBG_MSU1 printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start); + if(!(msu_page2_start == msu_page1_start + msu_page_size)) { + set_msu_addr(0x2000); + sd_offload_tgt=2; + ff_sd_offload=1; + f_read(&msufile, file_buf, 8192, &bytes_read2); + DBG_MSU1 printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start); + msu_page2_start = msu_page1_start + msu_page_size; + DBG_MSU1 printf("%08lx)\n", msu_page2_start); + } + } else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) { + DBG_MSU1 printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start); + msu_reset(0x2000 + msu_offset - msu_page2_start); + if(!(msu_page1_start == msu_page2_start + msu_page_size)) { + set_msu_addr(0x0); + sd_offload_tgt=2; + ff_sd_offload=1; + f_read(&msufile, file_buf, 8192, &bytes_read2); + DBG_MSU1 printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start); + msu_page1_start = msu_page2_start + msu_page_size; + DBG_MSU1 printf("%08lx)\n", msu_page1_start); + } + } else printf("!!!WATWATWAT!!!\n"); + } + /* clear bank bit to mask bank reset artifact */ + fpga_status_now &= ~0x2000; + fpga_status_prev &= ~0x2000; + /* clear busy bit */ + set_msu_status(0x00, 0x10); + } + + if(fpga_status_now & 0x0001) { + if(fpga_status_now & 0x0004) { + msu_repeat = 1; + set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */ + printf("Repeat set!\n"); + } else { + msu_repeat = 0; + set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */ + printf("Repeat clear!\n"); + } + + if(fpga_status_now & 0x0002) { + printf("PLAY!\n"); + set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */ + dac_play(); + } else { + printf("PAUSE!\n"); + set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */ + dac_pause(); + } + } + + fpga_status_prev = fpga_status_now; + + /* handle loop / end */ + if(bytes_read < MSU_DAC_BUFSIZE / 2) { + ff_sd_offload=0; + sd_offload=0; + if(msu_repeat) { + printf("loop\n"); + ff_sd_offload=1; + sd_offload_tgt=1; + f_lseek(&file_handle, 8L+msu_loop_point*4); + ff_sd_offload=1; + sd_offload_tgt=1; + f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - bytes_read, &bytes_read); + } else { + set_msu_status(0x00, 0x02); /* clear play bit */ + } + bytes_read = MSU_DAC_BUFSIZE; + } + if(msu1_check_reset()) { + f_close(&msufile); + f_close(&file_handle); + return 1; + } + } +} +/* END OF MSU1 STUFF */ diff --git a/src/tests/msu1.h b/src/tests/msu1.h new file mode 100644 index 0000000..1407a32 --- /dev/null +++ b/src/tests/msu1.h @@ -0,0 +1,15 @@ +#ifndef MSU1_H +#define MSU1_H + +#ifdef DEBUG_MSU1 +#define DBG_MSU1 +#else +#define DBG_MSU1 while(0) +#endif + +#define MSU_DAC_BUFSIZE (2048) + +int msu1_check(uint8_t*); +int msu1_loop(void); + +#endif diff --git a/src/tests/openocd-usb.cfg b/src/tests/openocd-usb.cfg new file mode 100644 index 0000000..1fcd482 --- /dev/null +++ b/src/tests/openocd-usb.cfg @@ -0,0 +1,12 @@ +# +# Hubert Hoegl's USB to JTAG +# +# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html +# + +interface ft2232 +ft2232_vid_pid 0x0403 0x6010 +ft2232_device_desc "Dual RS232" +ft2232_layout "oocdlink" +ft2232_latency 2 +#adapter_khz 10 diff --git a/src/tests/power.c b/src/tests/power.c new file mode 100644 index 0000000..848159c --- /dev/null +++ b/src/tests/power.c @@ -0,0 +1,26 @@ +/* ___DISCLAIMER___ */ + +#include +#include "bits.h" +#include "power.h" + +/* + required units: + * SSP0 (FPGA interface) [enabled via spi_init] + * UART3 (debug console) [enabled via uart_init] + * TIM3 (FPGA clock) + * RTC + * GPIO + * GPDMA [enabled via spi_init] + * USB [enabled via usb_init] + * PWM1 +*/ +void power_init() { + LPC_SC->PCONP = BV(PCSSP0) + | BV(PCTIM3) + | BV(PCRTC) + | BV(PCGPIO) + | BV(PCPWM1) +// | BV(PCUSB) + ; +} diff --git a/src/tests/power.h b/src/tests/power.h new file mode 100644 index 0000000..65d3cac --- /dev/null +++ b/src/tests/power.h @@ -0,0 +1,43 @@ +/* ___DISCLAIMER___ */ + +#ifndef _POWER_H +#define _POWER_H + +#include "bits.h" + +#define PCUART0 (3) +#define PCUART1 (4) +#define PCUART2 (24) +#define PCUART3 (25) + +#define PCTIM0 (1) +#define PCTIM1 (2) +#define PCTIM2 (22) +#define PCTIM3 (23) +#define PCRTC (9) +#define PCRIT (16) + +#define PCCAN1 (13) +#define PCCAN2 (14) + +#define PCPWM1 (6) +#define PCMCPWM (17) + +#define PCSSP0 (21) +#define PCSSP1 (10) +#define PCSPI (8) + +#define PCI2C0 (7) +#define PCI2C1 (19) +#define PCI2C2 (26) + +#define PCI2S (27) +#define PCGPDMA (29) +#define PCENET (30) +#define PCUSB (31) +#define PCQEI (18) +#define PCGPIO (15) + +void power_init(void); + +#endif diff --git a/src/tests/printf.c b/src/tests/printf.c new file mode 100644 index 0000000..861c03d --- /dev/null +++ b/src/tests/printf.c @@ -0,0 +1,291 @@ +/* Small, noncompliant, not-full-featured printf implementation + * + * + * Copyright (c) 2010, Ingo Korb + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Ingo Korb nor the + * names of the contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * FIXME: Selection of output function should be more flexible + */ + +#include +#include +#include +#include "config.h" +#include "uart.h" + +#define outfunc(x) uart_putc(x) + +#define FLAG_ZEROPAD 1 +#define FLAG_LEFTADJ 2 +#define FLAG_BLANK 4 +#define FLAG_FORCESIGN 8 +#define FLAG_WIDTH 16 +#define FLAG_LONG 32 +#define FLAG_UNSIGNED 64 +#define FLAG_NEGATIVE 128 + +/* Digits used for conversion */ +static const char hexdigits[] = "0123456789abcdef"; + +/* Temporary buffer used for numbers - just large enough for 32 bit in octal */ +static char buffer[12]; + +/* Output string length */ +static unsigned int outlength; + +/* Output pointer */ +static char *outptr; +static int maxlen; + +/* printf */ +static void outchar(char x) { + if (maxlen) { + maxlen--; + outfunc(x); + outlength++; + } +} + +/* sprintf */ +static void outstr(char x) { + if (maxlen) { + maxlen--; + *outptr++ = x; + outlength++; + } +} + +static int internal_nprintf(void (*output_function)(char c), const char *fmt, va_list ap) { + unsigned int width; + unsigned int flags; + unsigned int base = 0; + char *ptr = NULL; + + outlength = 0; + + while (*fmt) { + while (1) { + if (*fmt == 0) + goto end; + + if (*fmt == '%') { + fmt++; + if (*fmt != '%') + break; + } + + output_function(*fmt++); + } + + flags = 0; + width = 0; + + /* read all flags */ + do { + if (flags < FLAG_WIDTH) { + switch (*fmt) { + case '0': + flags |= FLAG_ZEROPAD; + continue; + + case '-': + flags |= FLAG_LEFTADJ; + continue; + + case ' ': + flags |= FLAG_BLANK; + continue; + + case '+': + flags |= FLAG_FORCESIGN; + continue; + } + } + + if (flags < FLAG_LONG) { + if (*fmt >= '0' && *fmt <= '9') { + unsigned char tmp = *fmt - '0'; + width = 10*width + tmp; + flags |= FLAG_WIDTH; + continue; + } + + if (*fmt == 'h') + continue; + + if (*fmt == 'l') { + flags |= FLAG_LONG; + continue; + } + } + + break; + } while (*fmt++); + + /* Strings */ + if (*fmt == 'c' || *fmt == 's') { + switch (*fmt) { + case 'c': + buffer[0] = va_arg(ap, int); + ptr = buffer; + break; + + case 's': + ptr = va_arg(ap, char *); + break; + } + + goto output; + } + + /* Numbers */ + switch (*fmt) { + case 'u': + flags |= FLAG_UNSIGNED; + case 'd': + base = 10; + break; + + case 'o': + base = 8; + flags |= FLAG_UNSIGNED; + break; + + case 'p': // pointer + output_function('0'); + output_function('x'); + width -= 2; + case 'x': + case 'X': + base = 16; + flags |= FLAG_UNSIGNED; + break; + } + + unsigned int num; + + if (!(flags & FLAG_UNSIGNED)) { + int tmp = va_arg(ap, int); + if (tmp < 0) { + num = -tmp; + flags |= FLAG_NEGATIVE; + } else + num = tmp; + } else { + num = va_arg(ap, unsigned int); + } + + /* Convert number into buffer */ + ptr = buffer + sizeof(buffer); + *--ptr = 0; + do { + *--ptr = hexdigits[num % base]; + num /= base; + } while (num != 0); + + /* Sign */ + if (flags & FLAG_NEGATIVE) { + output_function('-'); + width--; + } else if (flags & FLAG_FORCESIGN) { + output_function('+'); + width--; + } else if (flags & FLAG_BLANK) { + output_function(' '); + width--; + } + + output: + /* left padding */ + if ((flags & FLAG_WIDTH) && !(flags & FLAG_LEFTADJ)) { + while (strlen(ptr) < width) { + if (flags & FLAG_ZEROPAD) + output_function('0'); + else + output_function(' '); + width--; + } + } + + /* data */ + while (*ptr) { + output_function(*ptr++); + if (width) + width--; + } + + /* right padding */ + if (flags & FLAG_WIDTH) { + while (width) { + output_function(' '); + width--; + } + } + + fmt++; + } + + end: + return outlength; +} + +int printf(const char *format, ...) { + va_list ap; + int res; + + maxlen = -1; + va_start(ap, format); + res = internal_nprintf(outchar, format, ap); + va_end(ap); + return res; +} + +int snprintf(char *str, size_t size, const char *format, ...) { + va_list ap; + int res; + + maxlen = size; + outptr = str; + va_start(ap, format); + res = internal_nprintf(outstr, format, ap); + va_end(ap); + if (res < size) + str[res] = 0; + return res; +} + +/* Required for gcc compatibility */ +int puts(const char *str) { + uart_puts(str); + uart_putc('\n'); + return 0; +} + +#undef putchar +int putchar(int c) { + uart_putc(c); + return 0; +} diff --git a/src/tests/reset.cfg b/src/tests/reset.cfg new file mode 100644 index 0000000..defd589 --- /dev/null +++ b/src/tests/reset.cfg @@ -0,0 +1,3 @@ +init +reset run +shutdown diff --git a/src/tests/rle.c b/src/tests/rle.c new file mode 100644 index 0000000..74e3d6d --- /dev/null +++ b/src/tests/rle.c @@ -0,0 +1,66 @@ + +#include "rle.h" +#include "fileops.h" + +uint8_t rle_file_getc() { + static uint16_t rle_filled = 0; + static uint8_t data; + if(!rle_filled) { + data = file_getc(); + switch(data) { + case RLE_RUN: + data = file_getc(); + rle_filled = file_getc()-1; + break; + case RLE_RUNLONG: + data = file_getc(); + rle_filled = file_getc(); + rle_filled |= file_getc() << 8; + rle_filled--; + break; + case RLE_ESC: + data = file_getc(); + break; + } + } else { + rle_filled--; + } + if(file_status || file_res) rle_filled = 0; + return data; +} + +void rle_mem_init(const uint8_t* address, uint32_t len) { + rle_mem_ptr = address; + rle_mem_endptr = address+len; + rle_state = 0; +} + +uint8_t rle_mem_getc() { + static uint16_t rle_mem_filled = 0; + static uint8_t rle_mem_data; + if(!rle_mem_filled) { + rle_mem_data = *(rle_mem_ptr++); + switch(rle_mem_data) { + case RLE_RUN: + rle_mem_data = *(rle_mem_ptr)++; + rle_mem_filled = *(rle_mem_ptr)++ - 1; + break; + case RLE_RUNLONG: + rle_mem_data = *(rle_mem_ptr)++; + rle_mem_filled = *(rle_mem_ptr)++; + rle_mem_filled |= *(rle_mem_ptr)++ << 8; + rle_mem_filled--; + break; + case RLE_ESC: + rle_mem_data = *(rle_mem_ptr)++; + break; + } + } else { + rle_mem_filled--; + } + if(rle_mem_ptr>=rle_mem_endptr){ + rle_mem_filled = 0; + rle_state = 1; + } + return rle_mem_data; +} diff --git a/src/tests/rle.h b/src/tests/rle.h new file mode 100644 index 0000000..9747043 --- /dev/null +++ b/src/tests/rle.h @@ -0,0 +1,17 @@ +#ifndef RLE_H +#define RLE_H + +#include + +#define RLE_ESC (0x9b) +#define RLE_RUN (0x5b) +#define RLE_RUNLONG (0x77) + +uint8_t rle_file_getc(void); +uint8_t rle_mem_getc(void); +void rle_mem_init(const uint8_t *address, uint32_t len); +const uint8_t *rle_mem_ptr; +const uint8_t *rle_mem_endptr; +uint8_t rle_state; + +#endif diff --git a/src/tests/rtc.c b/src/tests/rtc.c new file mode 100644 index 0000000..f060945 --- /dev/null +++ b/src/tests/rtc.c @@ -0,0 +1,135 @@ +#include +#include +#include "config.h" +#include "rtc.h" +#include "uart.h" +#include "timer.h" +#include "power.h" + +rtcstate_t rtc_state; + +#define CLKEN 0 +#define CTCRST 1 + +uint8_t rtc_isvalid(void) { + if(LPC_RTC->GPREG0 == RTC_MAGIC) { + return RTC_OK; + } + return RTC_INVALID; +} + +void rtc_init(void) { + if (LPC_RTC->CCR & BV(CLKEN)) { + rtc_state = RTC_OK; + } else { + rtc_state = RTC_INVALID; + } +} + +void read_rtc(struct tm *time) { + do { + time->tm_sec = LPC_RTC->SEC; + time->tm_min = LPC_RTC->MIN; + time->tm_hour = LPC_RTC->HOUR; + time->tm_mday = LPC_RTC->DOM; + time->tm_mon = LPC_RTC->MONTH; + time->tm_year = LPC_RTC->YEAR; + time->tm_wday = LPC_RTC->DOW; + } while (time->tm_sec != LPC_RTC->SEC); +} + +uint8_t calc_weekday(struct tm *time) { + int month = time->tm_mon; + int year = time->tm_year; + int day = time->tm_mday; + + /* Variation of Sillke for the Gregorian calendar. + * http://www.mathematik.uni-bielefeld.de/~sillke/ALGORITHMS/calendar/weekday.c */ + if (month <= 2) { + month += 10; + year--; + } else month -= 2; + return (83*month/32 + day + year + year/4 - year/100 + year/400) % 7; +} + +void set_rtc(struct tm *time) { + LPC_RTC->CCR = BV(CTCRST); + LPC_RTC->SEC = time->tm_sec; + LPC_RTC->MIN = time->tm_min; + LPC_RTC->HOUR = time->tm_hour; + LPC_RTC->DOM = time->tm_mday; + LPC_RTC->MONTH = time->tm_mon; + LPC_RTC->YEAR = time->tm_year; + LPC_RTC->DOW = calc_weekday(time); + LPC_RTC->CCR = BV(CLKEN); + LPC_RTC->GPREG0 = RTC_MAGIC; +} + +void invalidate_rtc() { + LPC_RTC->GPREG0 = 0; +} + +uint32_t get_fattime(void) { + struct tm time; + + read_rtc(&time); + return ((uint32_t)time.tm_year-1980) << 25 | + ((uint32_t)time.tm_mon) << 21 | + ((uint32_t)time.tm_mday) << 16 | + ((uint32_t)time.tm_hour) << 11 | + ((uint32_t)time.tm_min) << 5 | + ((uint32_t)time.tm_sec) >> 1; +} + +uint64_t get_bcdtime(void) { + struct tm time; + read_rtc(&time); + uint16_t year = time.tm_year; + + return ((uint64_t)(time.tm_wday % 7) << 56) + |((uint64_t)((year / 1000) % 10) << 52) + |((uint64_t)((year / 100) % 10) << 48) + |((uint64_t)((year / 10) % 10) << 44) + |((uint64_t)(year % 10) << 40) + |((uint64_t)(time.tm_mon / 10) << 36) + |((uint64_t)(time.tm_mon % 10) << 32) + |((time.tm_mday / 10) << 28) + |((time.tm_mday % 10) << 24) + |((time.tm_hour / 10) << 20) + |((time.tm_hour % 10) << 16) + |((time.tm_min / 10) << 12) + |((time.tm_min % 10) << 8) + |((time.tm_sec / 10) << 4) + |(time.tm_sec % 10); +} + +void set_bcdtime(uint64_t btime) { + struct tm time; + time.tm_sec = (btime & 0xf) + ((btime >> 4) & 0xf) * 10; + time.tm_min = ((btime >> 8) & 0xf) + ((btime >> 12) & 0xf) * 10; + time.tm_hour = ((btime >> 16) & 0xf) + ((btime >> 20) & 0xf) * 10; + time.tm_mday = ((btime >> 24) & 0xf) + ((btime >> 28) & 0xf) * 10; + time.tm_mon = ((btime >> 32) & 0xf) + ((btime >> 36) & 0xf) * 10; + time.tm_year = ((btime >> 40) & 0xf) + ((btime >> 44) & 0xf) * 10 + + ((btime >> 48) & 0xf) * 100 + ((btime >> 52) & 0xf) * 1000; + printtime(&time); + set_rtc(&time); +} + +void printtime(struct tm *time) { + printf("%04d-%02d-%02d %02d:%02d:%02d\n", time->tm_year, time->tm_mon, + time->tm_mday, time->tm_hour, time->tm_min, time->tm_sec); +} + +void testbattery() { + printf("%lx\n", LPC_RTC->GPREG0); + LPC_RTC->GPREG0 = RTC_MAGIC; + printf("%lx\n", LPC_RTC->GPREG0); + LPC_RTC->CCR = 0; + BITBAND(LPC_SC->PCONP, PCRTC) = 0; + delay_ms(20000); + BITBAND(LPC_SC->PCONP, PCRTC) = 1; + printf("%lx\n", LPC_RTC->GPREG0); + delay_ms(20); + LPC_RTC->CCR = BV(CLKEN); +} diff --git a/src/tests/rtc.h b/src/tests/rtc.h new file mode 100644 index 0000000..4e52a96 --- /dev/null +++ b/src/tests/rtc.h @@ -0,0 +1,78 @@ +/* sd2iec - SD/MMC to Commodore serial bus interface/controller + Copyright (C) 2007-2010 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + rtc.h: Definitions for RTC support + +*/ + +#ifndef RTC_H +#define RTC_H + +#include + +typedef enum { + RTC_NOT_FOUND, /* No RTC present */ + RTC_INVALID, /* RTC present, but contents invalid */ + RTC_OK /* RTC present and working */ +} rtcstate_t; + +struct tm { + uint8_t tm_sec; // 0..59 + uint8_t tm_min; // 0..59 + uint8_t tm_hour; // 0..23 + uint8_t tm_mday; // 1..[28..31] + uint8_t tm_mon; // 0..11 + uint16_t tm_year; // since 0 A.D. + uint8_t tm_wday; // 0 to 6, sunday is 6 + // A Unix struct tm has a few more fields we don't need in this application +}; + +#define RTC_MAGIC (0x43545253L) + +extern rtcstate_t rtc_state; + +void rtc_init(void); + +/* return RTC valid state based on magic token in backup register */ +uint8_t rtc_isvalid(void); + +/* Return current time in struct tm */ +void read_rtc(struct tm *time); + +/* Set time from struct tm, also sets RTC valid */ +void set_rtc(struct tm *time); + +/* Set RTC invalid */ +void invalidate_rtc(void); + +/* get current time in 60-bit BCD format (WYYYYMMDDHHMMSS) (W=DOW) */ +uint64_t get_bcdtime(void); + +/* set current time from 56-bit BCD format (YYYYMMDDHHMMSS) + DOW is calculated */ +void set_bcdtime(uint64_t btime); + +/* print the time to the console */ +void printtime(struct tm *time); + +void testbattery(void); +#endif diff --git a/src/tests/sdcard.h b/src/tests/sdcard.h new file mode 100644 index 0000000..e13e639 --- /dev/null +++ b/src/tests/sdcard.h @@ -0,0 +1,46 @@ +/* sd2iec - SD/MMC to Commodore serial bus interface/controller + Copyright (C) 2007-2010 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + sdcard.h: Definitions for the SD/MMC access routines + +*/ + +#ifndef SDCARD_H +#define SDCARD_H + +#include "diskio.h" + +#define SD_TX_BYTE(x) spi_tx_byte(x, SPI_SD); +#define SD_RX_BYTE(x) spi_rx_byte(x, SPI_SD); +#define SD_TX_BLOCK(x,y) spi_tx_block(x,y, SPI_SD); +#define SD_RX_BLOCK(x,y) spi_rx_block(x,y, SPI_SD); + +/* These functions are weak-aliased to disk_... */ +void sd_init(void); +DSTATUS sd_status(BYTE drv); +DSTATUS sd_initialize(BYTE drv); +DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count); +DRESULT sd_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count); +DRESULT sd_getinfo(BYTE drv, BYTE page, void *buffer); + +void sd_changed(void); +#endif diff --git a/src/tests/sdnative.c b/src/tests/sdnative.c new file mode 100644 index 0000000..965d418 --- /dev/null +++ b/src/tests/sdnative.c @@ -0,0 +1,1015 @@ +#include +#include +#include "config.h" +#include "crc.h" +#include "diskio.h" +#include "spi.h" +#include "timer.h" +#include "uart.h" +#include "led.h" +#include "sdnative.h" +#include "fileops.h" +#include "bits.h" +#include "fpga_spi.h" + +#define MAX_CARDS 1 + +// SD/MMC commands +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define ALL_SEND_CID 2 +#define SEND_RELATIVE_ADDR 3 +#define SWITCH_FUNC 6 +#define SELECT_CARD 7 +#define SEND_IF_COND 8 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_TRANSMISSION 12 +#define SEND_STATUS 13 +#define GO_INACTIVE_STATE 15 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define READ_MULTIPLE_BLOCK 18 +#define WRITE_BLOCK 24 +#define WRITE_MULTIPLE_BLOCK 25 +#define PROGRAM_CSD 27 +#define SET_WRITE_PROT 28 +#define CLR_WRITE_PROT 29 +#define SEND_WRITE_PROT 30 +#define ERASE_WR_BLK_STAR_ADDR 32 +#define ERASE_WR_BLK_END_ADDR 33 +#define ERASE 38 +#define LOCK_UNLOCK 42 +#define APP_CMD 55 +#define GEN_CMD 56 +#define READ_OCR 58 +#define CRC_ON_OFF 59 + +// SD ACMDs +#define SD_SET_BUS_WIDTH 6 +#define SD_STATUS 13 +#define SD_SEND_NUM_WR_BLOCKS 22 +#define SD_SET_WR_BLK_ERASE_COUNT 23 +#define SD_SEND_OP_COND 41 +#define SD_SET_CLR_CARD_DETECT 42 +#define SD_SEND_SCR 51 + +// R1 status bits +#define STATUS_IN_IDLE 1 +#define STATUS_ERASE_RESET 2 +#define STATUS_ILLEGAL_COMMAND 4 +#define STATUS_CRC_ERROR 8 +#define STATUS_ERASE_SEQ_ERROR 16 +#define STATUS_ADDRESS_ERROR 32 +#define STATUS_PARAMETER_ERROR 64 + + +/* Card types - cardtype == 0 is MMC */ +#define CARD_SD (1<<0) +#define CARD_SDHC (1<<1) + +/* + Rev.A Rev.C + 1 DAT3/SS P0.6 P2.3 + 2 CMD/DI P0.9 P0.9 + 5 Clock P0.7 P0.7 + 7 DAT0/DO P0.8 P2.0 + 8 DAT1/IRQ P1.14 P2.1 + 9 DAT2/NC P1.15 P2.2 +*/ + +/* SD init procedure + ================= + - initial clock frequency: ~100kHz + - cycle the clock for at least 74 cycles (some more may be safer) + - send CMD0 + - send CMD8 (SEND_OP_COND); if no response -> HCS=0; else HCS=1 + - send ACMD41 until OCR[31] (busy) becomes 1 (means: ready) + - if OCR[30] (CCS) set -> SDHC; else SDSC + - send CMD2 (read CID) (maybe log some stuff from the CID) + - send CMD3 (read RCA), store RCA +== end of initialisation == + - send CMD9 (read CSD) with RCA, maybe do sth with TRAN_SPEED + - send CMD7 with RCA, select card, put card in tran + - maybe send CMD13 with RCA to check state (tran) + - send ACMD51 with RCA to read SCR (maybe, to check 4bit support) + - increase clock speed + - send ACMD6 with RCA to set 4bit bus width + - send transfer cmds +*/ + +/* + static CMD payloads. (no CRC calc required) + - CMD0: 0x40 0x00 0x00 0x00 0x00 0x95 + - CMD8: 0x48 0x00 0x00 0x01 0xaa 0x87 + - CMD2: 0x42 0x00 0x00 0x00 0x00 0x4d + - CMD3: 0x43 0x00 0x00 0x00 0x00 0x21 + - CMD55: 0x77 0x00 0x00 0x00 0x00 0x65 +*/ + +uint8_t cmd[6]={0,0,0,0,0,0}; +uint8_t rsp[17]; +uint8_t csd[17]; +uint8_t ccs=0; +uint32_t rca; + +enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE }; +enum cmd_state { CMD_RSP = 0, CMD_RSPDAT, CMD_DAT }; + +int during_blocktrans = TRANS_NONE; +uint32_t last_block = 0; + +volatile int sd_changed; + +/** + * getbits - read value from bit buffer + * @buffer: pointer to the data buffer + * @start : index of the first bit in the value + * @bits : number of bits in the value + * + * This function returns a value from the memory region passed as + * buffer, starting with bit "start" and "bits" bit long. The buffer + * is assumed to be MSB first, passing 0 for start will read starting + * from the highest-value bit of the first byte of the buffer. + */ +static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) { + uint8_t *buf = buffer; + uint32_t result = 0; + + if ((start % 8) != 0) { + /* Unaligned start */ + result += buf[start / 8] & (0xff >> (start % 8)); + bits -= 8 - (start % 8); + start += 8 - (start % 8); + } + while (bits >= 8) { + result = (result << 8) + buf[start / 8]; + start += 8; + bits -= 8; + } + if (bits > 0) { + result = result << bits; + result = result + (buf[start / 8] >> (8-bits)); + } else if (bits < 0) { + /* Fraction of a single byte */ + result = result >> -bits; + } + return result; +} + +static inline void wiggle_slow_pos(uint16_t times) { + while(times--) { + delay_us(2); + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + delay_us(2); + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_slow_neg(uint16_t times) { + while(times--) { + delay_us(2); + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + delay_us(2); + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_fast_pos(uint16_t times) { + while(times--) { + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_fast_neg(uint16_t times) { + while(times--) { + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_fast_neg1(void) { + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; +} + +static inline void wiggle_fast_pos1(void) { + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; +} + + +int get_and_check_datacrc(uint8_t *buf) { + uint16_t crc0=0, crc1=0, crc2=0, crc3=0; + uint16_t sdcrc0=0, sdcrc1=0, sdcrc2=0, sdcrc3=0; + uint8_t d0=0, d1=0, d2=0, d3=0; + uint8_t datdata; + uint16_t datcnt; + /* get crcs from card */ + for (datcnt=0; datcnt < 16; datcnt++) { + datdata = SD_DAT; + wiggle_fast_neg1(); + sdcrc0 = ((sdcrc0 << 1) & 0xfffe) | ((datdata >> 3) & 0x0001); + sdcrc1 = ((sdcrc1 << 1) & 0xfffe) | ((datdata >> 2) & 0x0001); + sdcrc2 = ((sdcrc2 << 1) & 0xfffe) | ((datdata >> 1) & 0x0001); + sdcrc3 = ((sdcrc3 << 1) & 0xfffe) | ((datdata >> 0) & 0x0001); + } + wiggle_fast_neg1(); + /* calc crcs from data */ + for (datcnt=0; datcnt < 512; datcnt++) { + d0 = ((d0 << 2) & 0xfc) | ((buf[datcnt] >> 6) & 0x02) | ((buf[datcnt] >> 3) & 0x01) ; + d1 = ((d1 << 2) & 0xfc) | ((buf[datcnt] >> 5) & 0x02) | ((buf[datcnt] >> 2) & 0x01) ; + d2 = ((d2 << 2) & 0xfc) | ((buf[datcnt] >> 4) & 0x02) | ((buf[datcnt] >> 1) & 0x01) ; + d3 = ((d3 << 2) & 0xfc) | ((buf[datcnt] >> 3) & 0x02) | ((buf[datcnt] >> 0) & 0x01) ; + if((datcnt % 4) == 3) { + crc0 = crc_xmodem_update(crc0, d0); + crc1 = crc_xmodem_update(crc1, d1); + crc2 = crc_xmodem_update(crc2, d2); + crc3 = crc_xmodem_update(crc3, d3); + } + } + if((crc0 != sdcrc0) || (crc1 != sdcrc1) || (crc2 != sdcrc2) || (crc3 != sdcrc3)) { + printf("CRC mismatch\nSDCRC CRC\n %04x %04x\n %04x %04x\n %04x %04x\n %04x %04x\n", sdcrc0, crc0, sdcrc1, crc1, sdcrc2, crc2, sdcrc3, crc3); +while(1); + return 1; + } + return 0; +} + +static inline void wait_busy(void) { + while(!(BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) { + wiggle_fast_neg1(); + } + wiggle_fast_neg(4); +} + +/* + send_command_slow + send SD command and put response in rsp. + returns length of response or 0 if there was no response +*/ +int send_command_slow(uint8_t* cmd, uint8_t* rsp){ + uint8_t shift, i=6; + int rsplen; + uint8_t cmdno = *cmd & 0x3f; + wiggle_slow_pos(5); + switch(*cmd & 0x3f) { + case 0: + rsplen = 0; + break; + case 2: + case 9: + case 10: + rsplen = 17; + break; + default: + rsplen = 6; + } + /* send command */ + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + + while(i--) { + shift = 8; + do { + shift--; + uint8_t data = *cmd; + *cmd<<=1; + if(data&0x80) { + BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1; + } else { + BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1; + } + wiggle_slow_pos(1); + } while (shift); + cmd++; + } + + wiggle_slow_pos(1); + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0; + + if(rsplen) { + uint16_t timeout=1000; + while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) { + wiggle_slow_neg(1); + } + if(!timeout) { + printf("CMD%d timed out\n", cmdno); + return 0; /* no response within timeout */ + } + + i=rsplen; + while(i--) { + shift = 8; + uint8_t data=0; + do { + shift--; + data |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << shift; + wiggle_slow_neg(1); + } while (shift); + *rsp=data; + rsp++; + } + } + return rsplen; +} + + +/* + send_command_fast + send SD command and put response in rsp. + returns length of response or 0 if there was no response +*/ +int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){ + uint8_t datshift=8, cmdshift, i=6; + uint8_t cmdno = *cmd & 0x3f; + int rsplen, dat=0, waitbusy=0, datcnt=512, j=0; + static int state=CMD_RSP; + wiggle_fast_pos(9); /* give the card >=8 cycles after last command */ + DBG_SD printf("send_command_fast: sending CMD%d; payload=%02x%02x%02x%02x%02x%02x...\n", cmdno, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], cmd[5]); + switch(*cmd & 0x3f) { + case 0: + rsplen = 0; + break; + case 2: + case 9: + case 10: + rsplen = 17; + break; + case 12: + rsplen = 6; + waitbusy = 1; + break; + case 13: + case 17: + case 18: + dat = 1; + default: + rsplen = 6; + } + if(dat && (buf==NULL)) { + printf("send_command_fast error: buf is null but data transfer expected.\n"); + return 0; + } + /* send command */ + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + + while(i--) { + uint8_t data = *cmd; + cmdshift = 8; + do { + cmdshift--; + if(data&0x80) { + BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1; + } else { + BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1; + } + data<<=1; + wiggle_fast_pos1(); + } while (cmdshift); + cmd++; + } + + wiggle_fast_pos1(); + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0; + + if(rsplen) { + uint32_t timeout=2000000; + /* wait for response */ + while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) { + wiggle_fast_neg1(); + } + if(!timeout) { + printf("CMD%d timed out\n", cmdno); + return 0; /* no response within timeout */ + } + + i=rsplen; + uint8_t cmddata=0, datdata=0; + while(i--) { /* process response */ + cmdshift = 8; + do { + if(dat) { + if(!(BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) { + printf("data start during response\n"); + j=datcnt; + state=CMD_RSPDAT; + break; + } + } + cmdshift--; + cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift; + wiggle_fast_neg1(); + } while (cmdshift); + if(state==CMD_RSPDAT)break; + *rsp=cmddata; + cmddata=0; + rsp++; + } + + if(state==CMD_RSPDAT) { /* process response+data */ + int startbit=1; + DBG_SD printf("processing rsp+data cmdshift=%d i=%d j=%d\n", cmdshift, i, j); + datshift=8; + while(1) { + cmdshift--; + cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift; + if(!cmdshift) { + cmdshift=8; + *rsp=cmddata; + cmddata=0; + rsp++; + i--; + if(!i) { + DBG_SD printf("response end\n"); + if(j) state=CMD_DAT; /* response over, remaining data */ + break; + } + } + if(!startbit) { + datshift-=4; + datdata |= SD_DAT << datshift; + if(!datshift) { + datshift=8; + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + } + startbit=0; + wiggle_fast_neg1(); + } + } + + if(dat && state != CMD_DAT) { /* response ended before data */ + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + state=CMD_DAT; + j=datcnt; + datshift=8; + DBG_SD printf("response over, waiting for data...\n"); + /* wait for data start bit on DAT0 */ + while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { + wiggle_fast_neg1(); + } + DBG_SD if(!timeout) printf("timed out!\n"); + wiggle_fast_neg1(); /* eat the start bit */ + if(sd_offload) { + if(sd_offload_partial) { + fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end); + fpga_sddma(sd_offload_tgt, 1); + sd_offload_partial=0; + } else { + fpga_sddma(sd_offload_tgt, 0); + } + state=CMD_RSP; + return rsplen; + } + } + + if(state==CMD_DAT) { /* transfer rest of data */ + DBG_SD printf("remaining data: %d\n", j); + if(datshift==8) { + while(1) { + datdata |= SD_DAT << 4; + wiggle_fast_neg1(); + + datdata |= SD_DAT; + wiggle_fast_neg1(); + + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + } else { + + while(1) { + datshift-=4; + datdata |= SD_DAT << datshift; + if(!datshift) { + datshift=8; + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + wiggle_fast_neg1(); + } + } + } + if(dat) { +#ifdef CONFIG_SD_DATACRC + if(get_and_check_datacrc(buf-512)) { + return CRC_ERROR; + } +#else + /* eat the crcs */ + wiggle_fast_neg(17); +#endif + } + + if(waitbusy) { + DBG_SD printf("waitbusy after send_cmd\n"); + wait_busy(); + } + state=CMD_RSP; + } + rsp-=rsplen; + DBG_SD printf("send_command_fast: CMD%d response: %02x%02x%02x%02x%02x%02x\n", cmdno, rsp[0], rsp[1], rsp[2], rsp[3], rsp[4], rsp[5]); + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + return rsplen; +} + + +static inline void make_crc7(uint8_t* cmd) { + cmd[5]=crc7update(0, cmd[0]); + cmd[5]=crc7update(cmd[5], cmd[1]); + cmd[5]=crc7update(cmd[5], cmd[2]); + cmd[5]=crc7update(cmd[5], cmd[3]); + cmd[5]=crc7update(cmd[5], cmd[4]); + cmd[5]=(cmd[5] << 1) | 1; +} + +int cmd_slow(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) { + uint8_t cmdbuf[6]; + cmdbuf[0] = 0x40 | cmd; + cmdbuf[1] = param >> 24; + cmdbuf[2] = param >> 16; + cmdbuf[3] = param >> 8; + cmdbuf[4] = param; + if(!crc) { + make_crc7(cmdbuf); + } else { + cmdbuf[5] = crc; + } + return send_command_slow(cmdbuf, rsp); +} + +int acmd_slow(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) { + if(!(cmd_slow(APP_CMD, rca, 0, NULL, rsp))) { + return 0; + } + return cmd_slow(cmd, param, crc, dat, rsp); +} + +int cmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) { + uint8_t cmdbuf[6]; + cmdbuf[0] = 0x40 | cmd; + cmdbuf[1] = param >> 24; + cmdbuf[2] = param >> 16; + cmdbuf[3] = param >> 8; + cmdbuf[4] = param; + if(!crc) { + make_crc7(cmdbuf); + } else { + cmdbuf[5] = crc; + } + return send_command_fast(cmdbuf, rsp, dat); +} + +int acmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* rsp) { + if(!(cmd_fast(APP_CMD, rca, 0, NULL, rsp))) { + return 0; + } + return cmd_fast(cmd, param, crc, dat, rsp); +} + +void sdn_checkinit(BYTE drv) { + if(disk_state == DISK_CHANGED) { + disk_initialize(drv); + } +} + +int stream_datablock(uint8_t *buf) { +// uint8_t datshift=8; + int j=512; + uint8_t datdata=0; + uint32_t timeout=1000000; + + DBG_SD printf("stream_datablock: wait for ready...\n"); + while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { + wiggle_fast_neg1(); + } + DBG_SD if(!timeout) printf("timeout!\n"); + + wiggle_fast_neg1(); /* eat the start bit */ + if(sd_offload) { + if(sd_offload_partial) { + fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end); + fpga_sddma(sd_offload_tgt, 1); + sd_offload_partial=0; + } else { + fpga_sddma(sd_offload_tgt, 0); + } + } else { + while(1) { + datdata = SD_DAT << 4; + wiggle_fast_neg1(); + + datdata |= SD_DAT; + wiggle_fast_neg1(); + + *buf=datdata; + buf++; + j--; + if(!j) break; + } +#ifdef CONFIG_SD_DATACRC + return get_and_check_datacrc(buf-512); +#else + /* eat the crcs */ + wiggle_fast_neg(17); +#endif + } + return 0; +} + +void send_datablock(uint8_t *buf) { + uint16_t crc0=0, crc1=0, crc2=0, crc3=0, cnt=512; + uint8_t dat0=0, dat1=0, dat2=0, dat3=0, crcshift, datshift; + + wiggle_fast_pos1(); + BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 1; + BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 1; + BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 1; + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 1; + + BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1; + BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1; + BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1; + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + + wiggle_fast_pos1(); /* send start bit to card */ + crcshift=8; + while(cnt--) { + datshift=8; + do { + datshift-=4; +/* if(((*buf)>>datshift) & 0x8) { + BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1; + } else { + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + } + if(((*buf)>>datshift) & 0x4) { + BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1; + } else { + BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1; + } + if(((*buf)>>datshift) & 0x2){ + BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1; + } else { + BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1; + } + if(((*buf)>>datshift) & 0x1){ + BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1; + } else { + BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1; + }*/ + SD_DAT0REG->FIOPIN0 = (*buf) >> datshift; + wiggle_fast_pos1(); + } while (datshift); + + crcshift-=2; + dat0 |= (((*buf)&0x01) | (((*buf)&0x10) >> 3)) << crcshift; + dat1 |= ((((*buf)&0x02) >> 1) | (((*buf)&0x20) >> 4)) << crcshift; + dat2 |= ((((*buf)&0x04) >> 2) | (((*buf)&0x40) >> 5)) << crcshift; + dat3 |= ((((*buf)&0x08) >> 3) | (((*buf)&0x80) >> 6)) << crcshift; + if(!crcshift) { + crc0 = crc_xmodem_update(crc0, dat0); + crc1 = crc_xmodem_update(crc1, dat1); + crc2 = crc_xmodem_update(crc2, dat2); + crc3 = crc_xmodem_update(crc3, dat3); + crcshift=8; + dat0=0; + dat1=0; + dat2=0; + dat3=0; + } + buf++; + } +// printf("crc0=%04x crc1=%04x crc2=%04x crc3=%04x ", crc0, crc1, crc2, crc3); + /* send crcs */ + datshift=16; + do { + datshift--; + if((crc0 >> datshift) & 1) { + BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1; + } else { + BITBAND(SD_DAT0REG->FIOCLR, SD_DAT0PIN) = 1; + } + if((crc1 >> datshift) & 1) { + BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1; + } else { + BITBAND(SD_DAT1REG->FIOCLR, SD_DAT1PIN) = 1; + } + if((crc2 >> datshift) & 1) { + BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1; + } else { + BITBAND(SD_DAT2REG->FIOCLR, SD_DAT2PIN) = 1; + } + if((crc3 >> datshift) & 1) { + BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1; + } else { + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + } + wiggle_fast_pos1(); + } while(datshift); + /* send end bit */ + BITBAND(SD_DAT0REG->FIOSET, SD_DAT0PIN) = 1; + BITBAND(SD_DAT1REG->FIOSET, SD_DAT1PIN) = 1; + BITBAND(SD_DAT2REG->FIOSET, SD_DAT2PIN) = 1; + BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1; + + wiggle_fast_pos1(); + + BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 0; + BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 0; + BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 0; + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + + wiggle_fast_neg(3); + dat0=0; + + datshift=4; + do { + datshift--; + dat0 |= ((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) << datshift); + wiggle_fast_neg1(); + } while (datshift); + DBG_SD printf("crc %02x\n", dat0); + if((dat0 & 7) != 2) { + printf("crc error! %02x\n", dat0); + while(1); + } + if(dat0 & 8) { + printf("missing start bit in CRC status response...\n"); + } + wiggle_fast_neg(2); + wait_busy(); +} + +void read_block(uint32_t address, uint8_t *buf) { + if(during_blocktrans == TRANS_READ && (last_block == address-1)) { +//uart_putc('r'); +#ifdef CONFIG_SD_DATACRC + int cmd_res; + if((cmd_res = stream_datablock(buf)) == CRC_ERROR) { + while(cmd_res == CRC_ERROR) { + cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); + cmd_res = cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp); + } + } +#else + stream_datablock(buf); +#endif + last_block=address; + } else { + if(during_blocktrans) { +// uart_putc('_'); +//printf("nonseq read (%lx -> %lx), restarting transmission\n", last_block, address); + /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */ + cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); + } + last_block=address; + if(!ccs) { + address <<= 9; + } +#ifdef CONFIG_SD_DATACRC + while(1) { + if(cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp) != CRC_ERROR) break; + cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); + }; +#else + cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp); +#endif + during_blocktrans = TRANS_READ; + } +} + +void write_block(uint32_t address, uint8_t* buf) { + if(during_blocktrans == TRANS_WRITE && (last_block == address-1)) { + wait_busy(); + send_datablock(buf); + last_block=address; + } else { + if(during_blocktrans) { + /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */ + cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); + } + wait_busy(); + last_block=address; + if(!ccs) { + address <<= 9; + } + /* only send cmd & get response */ + cmd_fast(WRITE_MULTIPLE_BLOCK, address, 0, NULL, rsp); + DBG_SD printf("write_block: CMD25 response = %02x%02x%02x%02x%02x%02x\n", rsp[0], rsp[1], rsp[2], rsp[3], rsp[4], rsp[5]); + wiggle_fast_pos(8); + send_datablock(buf); + during_blocktrans = TRANS_WRITE; + } +} + +// +// Public functions +// + +DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) { + uint8_t sec; + if(drv >= MAX_CARDS) { + return RES_PARERR; + } + readled(1); + for(sec=0; sec=MAX_CARDS) { + return STA_NOINIT|STA_NODISK; + } + + if(sdn_status(drv) & STA_NODISK) { + return STA_NOINIT|STA_NODISK; + } + /* if the card is sending data from before a reset we try to deselect it + prior to initialization */ + for(rsplen=0; rsplen<2042; rsplen++) { + if(!(BITBAND(SD_DAT3REG->FIOPIN, SD_DAT3PIN))) { + printf("card seems to be sending data, attempting deselect\n"); + cmd_slow(SELECT_CARD, 0, 0, NULL, rsp); + } + wiggle_slow_neg(1); + } + printf("sd_init start\n"); + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 1; + BITBAND(SD_DAT3REG->FIOSET, SD_DAT3PIN) = 1; + cmd_slow(GO_IDLE_STATE, 0, 0x95, NULL, rsp); + + if((rsplen=cmd_slow(SEND_IF_COND, 0x000001aa, 0x87, NULL, rsp))) { + DBG_SD printf("CMD8 response:\n"); + DBG_SD uart_trace(rsp, 0, rsplen); + hcs=1; + } + while(1) { + if(!(acmd_slow(SD_SEND_OP_COND, (hcs << 30) | 0xfc0000, 0, NULL, rsp))) { + printf("ACMD41 no response!\n"); + } + if(rsp[1]&0x80) break; + } + + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + + ccs = (rsp[1]>>6) & 1; /* SDHC/XC */ + + cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp); + if(cmd_slow(SEND_RELATIVE_ADDR, 0, 0x21, NULL, rsp)) { + rca=(rsp[1]<<24) | (rsp[2]<<16); + printf("RCA: %04lx\n", rca>>16); + } else { + printf("CMD3 no response!\n"); + rca=0; + } + + /* record CSD for getinfo */ + cmd_slow(SEND_CSD, rca, 0, NULL, rsp); + + /* select the card */ + if(cmd_slow(SELECT_CARD, rca, 0, NULL, rsp)) { + printf("card selected!\n"); + } else { + printf("CMD7 no response!\n"); + } + + /* get card status */ + cmd_slow(SEND_STATUS, rca, 0, NULL, rsp); + + /* set bus width */ + acmd_slow(SD_SET_BUS_WIDTH, 0x2, 0, NULL, rsp); + + /* set block length */ + cmd_slow(SET_BLOCKLEN, 0x200, 0, NULL, rsp); + + printf("SD init complete. SDHC/XC=%d\n", ccs); + disk_state = DISK_OK; + during_blocktrans = TRANS_NONE; + return sdn_status(drv); +} + +DSTATUS disk_initialize(BYTE drv) __attribute__ ((weak, alias("sdn_initialize"))); + +void sdn_init(void) { + /* enable GPIO interrupt on SD detect pin, both edges */ +/* NVIC_EnableIRQ(EINT3_IRQn); + SD_DT_INT_SETUP(); */ + /* disconnect SSP1 */ + LPC_PINCON->PINSEL0 &= ~(BV(13) | BV(15) | BV(17) | BV(19)); + /* prepare GPIOs */ + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 0; + BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 0; + BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 0; + BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1; + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN) = 1; + LPC_GPIO2->FIOPIN0 = 0x00; + LPC_GPIO2->FIOMASK0 = ~0xf; +} +void disk_init(void) __attribute__ ((weak, alias("sdn_init"))); + + +DSTATUS sdn_status(BYTE drv) { + if (SDCARD_DETECT) { + if (SDCARD_WP) { + return STA_PROTECT; + } else { + return RES_OK; + } + } else { + return STA_NOINIT|STA_NODISK; + } +} +DSTATUS disk_status(BYTE drv) __attribute__ ((weak, alias("sdn_status"))); + +DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer) { + uint32_t capacity; + + if (drv >= MAX_CARDS) { + return RES_NOTRDY; + } + if (sdn_status(drv) & STA_NODISK) { + return RES_NOTRDY; + } + if (page != 0) { + return RES_ERROR; + } + if (ccs) { + /* Special CSD for SDHC cards */ + capacity = (1 + getbits(csd,127-69+8,22)) * 1024; + } else { + /* Assume that MMC-CSD 1.0/1.1/1.2 and SD-CSD 1.1 are the same... */ + uint8_t exponent = 2 + getbits(csd, 127-49+8, 3); + capacity = 1 + getbits(csd, 127-73+8, 12); + exponent += getbits(csd, 127-83+8,4) - 9; + while (exponent--) capacity *= 2; + } + + diskinfo0_t *di = buffer; + di->validbytes = sizeof(diskinfo0_t); + di->disktype = DISK_TYPE_SD; + di->sectorsize = 2; + di->sectorcount = capacity; + + printf("card capacity: %lu sectors\n", capacity); + return RES_OK; +} +DRESULT disk_getinfo(BYTE drv, BYTE page, void *buffer) __attribute__ ((weak, alias("sdn_getinfo"))); + +DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count) { + uint8_t sec; + uint8_t *buf = (uint8_t*)buffer; + if(drv >= MAX_CARDS) { + return RES_NOTRDY; + } + if (sdn_status(drv) & STA_NODISK) { + return RES_NOTRDY; + } + writeled(1); + for(sec=0; sec + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + smc.c: SMC file related operations +*/ + +#include "fileops.h" +#include "config.h" +#include "uart.h" +#include "smc.h" +#include "string.h" +#include "fpga_spi.h" + +snes_romprops_t romprops; + +uint32_t hdr_addr[6] = {0xffb0, 0x101b0, 0x7fb0, 0x81b0, 0x40ffb0, 0x4101b0}; +uint8_t countAllASCII(uint8_t* data, int size) { + uint8_t res = 0; + do { + size--; + if(data[size] >= 0x20 && data[size] <= 0x7e) { + res++; + } + } while (size); + return res; +} + +uint8_t countAllJISX0201(uint8_t* data, int size) { + uint8_t res = 0; + do { + size--; + if((data[size] >= 0x20 && data[size] <= 0x7e) + ||(data[size] >= 0xa1 && data[size] <= 0xdf)) { + res++; + } + } while (size); + return res; +} + +uint8_t isFixed(uint8_t* data, int size, uint8_t value) { + uint8_t res = 1; + do { + size--; + if(data[size] != value) { + res = 0; + } + } while (size); + return res; +} + +uint8_t checkChksum(uint16_t cchk, uint16_t chk) { + uint32_t sum = cchk + chk; + uint8_t res = 0; + if(sum==0x0000ffff) { + res = 0x10; + } + return res; +} + +void smc_id(snes_romprops_t* props) { + uint8_t score, maxscore=1, score_idx=2; /* assume LoROM */ + snes_header_t* header = &(props->header); + + props->has_dspx = 0; + props->has_st0010 = 0; + props->has_cx4 = 0; + props->fpga_features = 0; + props->fpga_conf = NULL; + for(uint8_t num = 0; num < 6; num++) { + if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t)) + || file_res) { + score = 0; + } else { + score = smc_headerscore(header)/(1+(num&1)); + if((file_handle.fsize & 0x2ff) == 0x200) { + if(num&1) { + score+=20; + } else { + score=0; + } + } else { + if(!(num&1)) { + score+=20; + } else { + score=0; + } + } + } +//printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ + if(score>=maxscore) { + score_idx=num; + maxscore=score; + } + } + + if(score_idx & 1) { + props->offset = 0x200; + } else { + props->offset = 0; + } + + /* restore the chosen one */ +/*dprintf("winner is %d\n", score_idx); */ + file_readblock(header, hdr_addr[score_idx], sizeof(snes_header_t)); + + if(header->name[0x13] == 0x00 || header->name[0x13] == 0xff) { + if(header->name[0x14] == 0x00) { + const uint8_t n15 = header->map; + if(n15 == 0x00 || n15 == 0x80 || n15 == 0x84 || n15 == 0x9c + || n15 == 0xbc || n15 == 0xfc) { + if(header->licensee == 0x33 || header->licensee == 0xff) { + props->mapper_id = 0; +/*XXX do this properly */ + props->ramsize_bytes = 0x8000; + props->romsize_bytes = 0x100000; + props->expramsize_bytes = 0; + props->mapper_id = 3; /* BS-X Memory Map */ + return; + } + } + } + } + switch(header->map & 0xef) { + + case 0x21: /* HiROM */ + props->mapper_id = 0; + if(header->map == 0x31 && (header->carttype == 0x03 || header->carttype == 0x05)) { + props->has_dspx = 1; + props->dsp_fw = DSPFW_1B; + props->fpga_features |= FEAT_DSPX; + } + break; + + case 0x20: /* LoROM */ + props->mapper_id = 1; + if (header->map == 0x20 && header->carttype == 0xf3) { + props->has_cx4 = 1; + props->dsp_fw = CX4FW; + props->fpga_conf = FPGA_CX4; + props->fpga_features |= FEAT_CX4; + } + else if ((header->map == 0x20 && header->carttype == 0x03) || + (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) { + props->has_dspx = 1; + props->fpga_features |= FEAT_DSPX; + // Pilotwings uses DSP1 instead of DSP1B + if(!memcmp(header->name, "PILOTWINGS", 10)) { + props->dsp_fw = DSPFW_1; + } else { + props->dsp_fw = DSPFW_1B; + } + } else if (header->map == 0x20 && header->carttype == 0x05) { + props->has_dspx = 1; + props->dsp_fw = DSPFW_2; + props->fpga_features |= FEAT_DSPX; + } else if (header->map == 0x30 && header->carttype == 0x05 && header->licensee == 0xb2) { + props->has_dspx = 1; + props->dsp_fw = DSPFW_3; + props->fpga_features |= FEAT_DSPX; + } else if (header->map == 0x30 && header->carttype == 0x03) { + props->has_dspx = 1; + props->dsp_fw = DSPFW_4; + props->fpga_features |= FEAT_DSPX; + } else if (header->map == 0x30 && header->carttype == 0xf6 && header->romsize >= 0xa) { + props->has_dspx = 1; + props->has_st0010 = 1; + props->dsp_fw = DSPFW_ST0010; + props->fpga_features |= FEAT_ST0010; + header->ramsize = 2; + } + break; + + case 0x25: /* ExHiROM */ + props->mapper_id = 2; + break; + + case 0x22: /* ExLoROM */ + if(file_handle.fsize > 0x400200) { + props->mapper_id = 6; /* SO96 */ + } else { + props->mapper_id = 1; + } + break; + + default: /* invalid/unsupported mapper, use header location */ + switch(score_idx) { + case 0: + case 1: + props->mapper_id = 0; + break; + case 2: + case 3: + if(file_handle.fsize > 0x800200) { + props->mapper_id = 6; /* SO96 interleaved */ + } else if(file_handle.fsize > 0x400200) { + props->mapper_id = 1; /* ExLoROM */ + } else { + props->mapper_id = 1; /* LoROM */ + } + break; + case 4: + case 5: + props->mapper_id = 2; + break; + default: + props->mapper_id = 1; // whatever + } + } + if(header->romsize == 0 || header->romsize > 13) { + header->romsize = 13; + } + props->ramsize_bytes = (uint32_t)1024 << header->ramsize; + props->romsize_bytes = (uint32_t)1024 << header->romsize; + props->expramsize_bytes = (uint32_t)1024 << header->expramsize; +/*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */ + if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) { + props->ramsize_bytes = 0; + } +/*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */ +} + +uint8_t smc_headerscore(snes_header_t* header) { + uint8_t score=0; + score += countAllASCII(header->maker, sizeof(header->maker)); + score += countAllASCII(header->gamecode, sizeof(header->gamecode)); + score += isFixed(header->fixed_00, sizeof(header->fixed_00), 0x00); + score += countAllJISX0201(header->name, sizeof(header->name)); + score += 3*isFixed(&header->licensee, sizeof(header->licensee), 0x33); + score += checkChksum(header->cchk, header->chk); + return score; +} + diff --git a/src/tests/smc.h b/src/tests/smc.h new file mode 100644 index 0000000..8e77b7c --- /dev/null +++ b/src/tests/smc.h @@ -0,0 +1,79 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + smc.h: SMC file structures +*/ + +#ifndef SMC_H +#define SMC_H + +#define DSPFW_1 ((const uint8_t*)"/sd2snes/dsp1.bin") +#define DSPFW_2 ((const uint8_t*)"/sd2snes/dsp2.bin") +#define DSPFW_3 ((const uint8_t*)"/sd2snes/dsp3.bin") +#define DSPFW_4 ((const uint8_t*)"/sd2snes/dsp4.bin") +#define DSPFW_1B ((const uint8_t*)"/sd2snes/dsp1b.bin") +#define DSPFW_ST0010 ((const uint8_t*)"/sd2snes/st0010.bin") +#define CX4FW ((const uint8_t*)"/sd2snes/cx4.bin") + +#define FPGA_CX4 ((const uint8_t*)"/sd2snes/fpga_cx4.bit") + +typedef struct _snes_header { + uint8_t maker[2]; /* 0xB0 */ + uint8_t gamecode[4]; /* 0xB2 */ + uint8_t fixed_00[7]; /* 0xB6 */ + uint8_t expramsize; /* 0xBD */ + uint8_t specver; /* 0xBE */ + uint8_t carttype2; /* 0xBF */ + uint8_t name[21]; /* 0xC0 */ + uint8_t map; /* 0xD5 */ + uint8_t carttype; /* 0xD6 */ + uint8_t romsize; /* 0xD7 */ + uint8_t ramsize; /* 0xD8 */ + uint8_t destcode; /* 0xD9 */ + uint8_t licensee; /* 0xDA */ + uint8_t ver; /* 0xDB */ + uint16_t cchk; /* 0xDC */ + uint16_t chk; /* 0xDE */ +} snes_header_t; + +typedef struct _snes_romprops { + uint16_t offset; /* start of actual ROM image */ + uint8_t mapper_id; /* FPGA mapper */ + uint8_t pad1; /* for alignment */ + uint32_t expramsize_bytes; /* ExpRAM size in bytes */ + uint32_t ramsize_bytes; /* CartRAM size in bytes */ + uint32_t romsize_bytes; /* ROM size in bytes (rounded up) */ + const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */ + const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */ + uint8_t has_dspx; /* DSP[1-4] presence flag */ + uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/ + uint8_t has_msu1; /* MSU1 presence flag */ + uint8_t has_cx4; /* CX4 presence flag */ + uint8_t fpga_features; /* feature/peripheral enable bits*/ + snes_header_t header; /* original header from ROM image */ +} snes_romprops_t; + +void smc_id(snes_romprops_t*); +uint8_t smc_headerscore(snes_header_t*); + +#endif diff --git a/src/tests/snes.c b/src/tests/snes.c new file mode 100644 index 0000000..3171502 --- /dev/null +++ b/src/tests/snes.c @@ -0,0 +1,174 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + snes.c: SNES hardware control and monitoring +*/ + +#include +#include "bits.h" +#include "config.h" +#include "uart.h" +#include "snes.h" +#include "memory.h" +#include "fileops.h" +#include "ff.h" +#include "led.h" +#include "smc.h" +#include "timer.h" +#include "cli.h" +#include "fpga.h" +#include "fpga_spi.h" + +uint8_t initloop=1; +uint32_t saveram_crc, saveram_crc_old; +extern snes_romprops_t romprops; + +volatile int reset_changed; + +void prepare_reset() { + snes_reset(1); + delay_ms(1); + if(romprops.ramsize_bytes && fpga_test() == FPGA_TEST_TOKEN) { + writeled(1); + save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR); + writeled(0); + } + rdyled(1); + readled(1); + writeled(1); + snes_reset(0); + while(get_snes_reset()); + snes_reset(1); + fpga_dspx_reset(1); + delay_ms(200); +} + +void snes_init() { + /* put reset level on reset pin */ + BITBAND(SNES_RESET_REG->FIOCLR, SNES_RESET_BIT) = 1; + /* reset the SNES */ + snes_reset(1); +} + +/* + * sets the SNES reset state. + * + * state: put SNES in reset state when 1, release when 0 + */ +void snes_reset(int state) { + BITBAND(SNES_RESET_REG->FIODIR, SNES_RESET_BIT) = state; +} + +/* + * gets the SNES reset state. + * + * returns: 1 when reset, 0 when not reset + */ +uint8_t get_snes_reset() { + return !BITBAND(SNES_RESET_REG->FIOPIN, SNES_RESET_BIT); +} + +/* + * SD2SNES main loop. + * monitors SRAM changes and other things + */ +uint32_t diffcount = 0, samecount = 0, didnotsave = 0; +uint8_t sram_valid = 0; +void snes_main_loop() { + if(!romprops.ramsize_bytes)return; + if(initloop) { + saveram_crc_old = calc_sram_crc(SRAM_SAVE_ADDR, romprops.ramsize_bytes); + initloop=0; + } + saveram_crc = calc_sram_crc(SRAM_SAVE_ADDR, romprops.ramsize_bytes); + sram_valid = sram_reliable(); + if(crc_valid && sram_valid) { + if(saveram_crc != saveram_crc_old) { + if(samecount) { + diffcount=1; + } else { + diffcount++; + didnotsave++; + } + samecount=0; + } + if(saveram_crc == saveram_crc_old) { + samecount++; + } + if(diffcount>=1 && samecount==5) { + printf("SaveRAM CRC: 0x%04lx; saving\n", saveram_crc); + writeled(1); + save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR); + writeled(0); + didnotsave=0; + } + if(didnotsave>50) { + printf("periodic save (sram contents keep changing...)\n"); + diffcount=0; + writeled(1); + save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR); + didnotsave=0; + writeled(0); + } + saveram_crc_old = saveram_crc; + } + printf("crc=%lx crc_valid=%d sram_valid=%d diffcount=%ld samecount=%ld, didnotsave=%ld\n", saveram_crc, crc_valid, sram_valid, diffcount, samecount, didnotsave); +} + +/* + * SD2SNES menu loop. + * monitors menu selection. return when selection was made. + */ +uint8_t menu_main_loop() { + uint8_t cmd = 0; + sram_writebyte(0, SRAM_CMD_ADDR); + while(!cmd) { + if(!get_snes_reset()) { + while(!sram_reliable())printf("hurr\n"); + cmd = sram_readbyte(SRAM_CMD_ADDR); + } + if(get_snes_reset()) { + cmd = 0; + } + sleep_ms(20); + cli_entrycheck(); + } + return cmd; +} + +void get_selected_name(uint8_t* fn) { + uint32_t addr; + addr = sram_readlong(SRAM_PARAM_ADDR); + printf("fd addr=%lx\n", addr); + sram_readblock(fn, addr + 7 + SRAM_MENU_ADDR, 256); +} + +void snes_bootprint(void* msg) { + sram_writeblock(msg, SRAM_CMD_ADDR, 33); +} + +void snes_menu_errmsg(int err, void* msg) { + sram_writeblock(msg, SRAM_CMD_ADDR+1, 64); + sram_writebyte(err, SRAM_CMD_ADDR); +} + diff --git a/src/tests/snes.h b/src/tests/snes.h new file mode 100644 index 0000000..fa7b762 --- /dev/null +++ b/src/tests/snes.h @@ -0,0 +1,48 @@ +/* sd2snes - SD card based universal cartridge for the SNES + Copyright (C) 2009-2010 Maximilian Rehkopf + AVR firmware portion + + Inspired by and based on code from sd2iec, written by Ingo Korb et al. + See sdcard.c|h, config.h. + + FAT file system access based on code by ChaN, Jim Brain, Ingo Korb, + see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + snes.h: SNES hardware control and monitoring +*/ + +#ifndef SNES_H +#define SNES_H + +#define SNES_CMD_LOADROM (1) +#define SNES_CMD_SETRTC (2) + +#define MENU_ERR_OK (0) +#define MENU_ERR_NODSP (1) +#define MENU_ERR_NOBSX (2) + +uint8_t crc_valid; + +void prepare_reset(void); +void snes_init(void); +void snes_reset(int state); +uint8_t get_snes_reset(void); +void snes_main_loop(void); +uint8_t menu_main_loop(void); +void get_selected_name(uint8_t* lfn); +void snes_bootprint(void* msg); +void snes_menu_errmsg(int err, void* msg); +#endif diff --git a/src/tests/sort.c b/src/tests/sort.c new file mode 100644 index 0000000..377a077 --- /dev/null +++ b/src/tests/sort.c @@ -0,0 +1,122 @@ + +#include +#include +#include +#include "config.h" +#include "uart.h" +#include "memory.h" +#include "sort.h" + +/* + heap sort algorithm for data located outside RAM + addr: start address of pointer table + i: index (in 32-bit elements) + heapsize: size of heap (in 32-bit elements) +*/ + +uint32_t stat_getstring = 0; +static char sort_str1[21], sort_str2[21]; +uint32_t ptrcache[QSORT_MAXELEM] IN_AHBRAM; + +/* get element from pointer table in external RAM*/ +uint32_t sort_get_elem(uint32_t base, unsigned int index) { + return sram_readlong(base+4*index); +} + +/* put element from pointer table in external RAM */ +void sort_put_elem(uint32_t base, unsigned int index, uint32_t elem) { + sram_writelong(elem, base+4*index); +} + +/* compare strings pointed to by elements of pointer table */ +int sort_cmp_idx(uint32_t base, unsigned int index1, unsigned int index2) { + uint32_t elem1, elem2; + elem1 = sort_get_elem(base, index1); + elem2 = sort_get_elem(base, index2); + return sort_cmp_elem((void*)&elem1, (void*)&elem2); +} + +int sort_cmp_elem(const void* elem1, const void* elem2) { + uint32_t el1 = *(uint32_t*)elem1; + uint32_t el2 = *(uint32_t*)elem2; + sort_getstring_for_dirent(sort_str1, el1); + sort_getstring_for_dirent(sort_str2, el2); +/*printf("i1=%d i2=%d elem1=%lx elem2=%lx ; compare %s --- %s\n", index1, index2, elem1, elem2, sort_str1, sort_str2); */ + + if ((el1 & 0x80000000) && !(el2 & 0x80000000)) { + return -1; + } + + if (!(el1 & 0x80000000) && (el2 & 0x80000000)) { + return 1; + } +/* + uint16_t cmp_i; + for(cmp_i=0; cmp_i<8 && sort_long1[cmp_i] == sort_long2[cmp_i]; cmp_i++); + if(cmp_i==8) { + return 0; + } + return sort_long1[cmp_i]-sort_long2[cmp_i]; */ + return strcasecmp(sort_str1, sort_str2); +} + +/* get truncated string from database */ +void sort_getstring_for_dirent(char *ptr, uint32_t addr) { + uint8_t leaf_offset; + if(addr & 0x80000000) { + /* is directory link, name offset 4 */ + leaf_offset = sram_readbyte(addr + 4 + SRAM_MENU_ADDR); + sram_readblock(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, 20); + } else { + /* is file link, name offset 6 */ + leaf_offset = sram_readbyte(addr + 6 + SRAM_MENU_ADDR); + sram_readblock(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, 20); + } + ptr[20]=0; +} + +void sort_heapify(uint32_t addr, unsigned int i, unsigned int heapsize) +{ + while(1) { + unsigned int l = 2*i+1; + unsigned int r = 2*i+2; + unsigned int largest = (l < heapsize && sort_cmp_idx(addr, i, l) < 0) ? l : i; + + if(r < heapsize && sort_cmp_idx(addr, largest, r) < 0) + largest = r; + + if(largest != i) { + uint32_t tmp = sort_get_elem(addr, i); + sort_put_elem(addr, i, sort_get_elem(addr, largest)); + sort_put_elem(addr, largest, tmp); + i = largest; + } + else break; + } +} + +void sort_dir(uint32_t addr, unsigned int size) +{ +stat_getstring=0; + if(size > QSORT_MAXELEM) { + printf("more than %d dir entries, doing slower in-place sort\n", QSORT_MAXELEM); + ext_heapsort(addr, size); + } else { + /* retrieve, sort, and store dir table */ + sram_readblock(ptrcache, addr, size*4); + qsort((void*)ptrcache, size, 4, sort_cmp_elem); + sram_writeblock(ptrcache, addr, size*4); + } +} + +void ext_heapsort(uint32_t addr, unsigned int size) { + for(unsigned int i = size/2; i > 0;) sort_heapify(addr, --i, size); + + for(unsigned int i = size-1; i>0; --i) { + uint32_t tmp = sort_get_elem(addr, 0); + sort_put_elem(addr, 0, sort_get_elem(addr, i)); + sort_put_elem(addr, i, tmp); + sort_heapify(addr, 0, i); + } +} + diff --git a/src/tests/sort.h b/src/tests/sort.h new file mode 100644 index 0000000..bb3ff00 --- /dev/null +++ b/src/tests/sort.h @@ -0,0 +1,15 @@ +#ifndef _SORT_H +#define _SORT_H + +#include + +uint32_t sort_get_elem(uint32_t base, unsigned int index); +void sort_put_elem(uint32_t base, unsigned int index, uint32_t elem); +int sort_cmp_idx(uint32_t base, unsigned int index1, unsigned int index2); +int sort_cmp_elem(const void* elem1, const void* elem2); +void sort_getstring_for_dirent(char *ptr, uint32_t addr); +void sort_getlong_for_dirent(uint32_t* ptr, uint32_t addr); +void sort_heapify(uint32_t addr, unsigned int i, unsigned int heapsize); +void sort_dir(uint32_t addr, unsigned int size); +void ext_heapsort(uint32_t addr, unsigned int size); +#endif diff --git a/src/tests/spi.c b/src/tests/spi.c new file mode 100644 index 0000000..2893a7a --- /dev/null +++ b/src/tests/spi.c @@ -0,0 +1,213 @@ +/* Sd2iec - SD/MMC to Commodore serial bus interface/controller + Copyright (C) 2007-2010 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + spi.c: Low-level SPI routines + +*/ + +#include +#include "bits.h" +#include "config.h" +#include "spi.h" +#include "uart.h" + +void spi_preinit() { + + /* Set clock prescaler to 1:1 */ + BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1; +} + +void spi_init(spi_speed_t speed) { + + /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */ + SSP_REGS->CR0 = (8-1); + + /* set clock prescaler */ + if (speed == SPI_SPEED_FAST) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST; + } else if (speed == SPI_SPEED_SLOW) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW; + } else if (speed == SPI_SPEED_FPGA_FAST) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST; + } else { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW; + } + + /* Enable SSP */ + SSP_REGS->CR1 = BV(1); + + /* Enable DMA controller, little-endian mode */ + BITBAND(LPC_SC->PCONP, 29) = 1; + LPC_GPDMA->DMACConfig = 1; +} + +void spi_tx_sync() { + /* Wait until TX fifo is flushed */ + while (BITBAND(SSP_REGS->SR, SSP_BSY)) ; +} + +void spi_tx_byte(uint8_t data) { + /* Wait until TX fifo can accept data */ + while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ; + + /* Send byte */ + SSP_REGS->DR = data; +} + +uint8_t spi_txrx_byte(uint8_t data) { + /* Wait until SSP is not busy */ + while (BITBAND(SSP_REGS->SR, SSP_BSY)) ; + + /* Clear RX fifo */ + while (BITBAND(SSP_REGS->SR, SSP_RNE)) + (void) SSP_REGS->DR; + + /* Transmit a single byte */ + SSP_REGS->DR = data; + + /* Wait until answer has been received */ + while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ; + + return SSP_REGS->DR; +} + +uint8_t spi_rx_byte() { + /* Wait until SSP is not busy */ + while (BITBAND(SSP_REGS->SR, SSP_BSY)) ; + + /* Clear RX fifo */ + while (BITBAND(SSP_REGS->SR, SSP_RNE)) + (void) SSP_REGS->DR; + + /* Transmit a single dummy byte */ + SSP_REGS->DR = 0xff; + + /* Wait until answer has been received */ + while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ; + + return SSP_REGS->DR; +} + +void spi_tx_block(const void *ptr, unsigned int length) { + const uint8_t *data = (const uint8_t *)ptr; + + while (length--) { + /* Wait until TX fifo can accept data */ + while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ; + + SSP_REGS->DR = *data++; + } +} + +void spi_rx_block(void *ptr, unsigned int length) { + uint8_t *data = (uint8_t *)ptr; + unsigned int txlen = length; + + /* Wait until SSP is not busy */ + while (BITBAND(SSP_REGS->SR, SSP_BSY)) ; + + /* Clear RX fifo */ + while (BITBAND(SSP_REGS->SR, SSP_RNE)) + (void) SSP_REGS->DR; + + if ((length & 3) != 0 || ((uint32_t)ptr & 3) != 0) { + /* Odd length or unaligned buffer */ + while (length > 0) { + /* Wait until TX or RX FIFO are ready */ + while (txlen > 0 && !BITBAND(SSP_REGS->SR, SSP_TNF) && + !BITBAND(SSP_REGS->SR, SSP_RNE)) ; + + /* Try to receive data */ + while (length > 0 && BITBAND(SSP_REGS->SR, SSP_RNE)) { + *data++ = SSP_REGS->DR; + length--; + } + + /* Send dummy data until TX full or RX ready */ + while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF) && !BITBAND(SSP_REGS->SR, SSP_RNE)) { + txlen--; + SSP_REGS->DR = 0xff; + } + } + } else { + /* Clear interrupt flags of DMA channels 0 */ + LPC_GPDMA->DMACIntTCClear = BV(0); + LPC_GPDMA->DMACIntErrClr = BV(0); + + /* Set up RX DMA channel */ + SSP_DMACH->DMACCSrcAddr = (uint32_t)&SSP_REGS->DR; + SSP_DMACH->DMACCDestAddr = (uint32_t)ptr; + SSP_DMACH->DMACCLLI = 0; // no linked list + SSP_DMACH->DMACCControl = length + | (0 << 12) // source burst size 1 (FIXME: Check if larger possible/useful) + | (0 << 15) // destination burst size 1 + | (0 << 18) // source transfer width 1 byte + | (2 << 21) // destination transfer width 4 bytes + | (0 << 26) // source address not incremented + | (1 << 27) // destination address incremented + ; + SSP_DMACH->DMACCConfig = 1 // enable channel + | (SSP_DMAID_RX << 1) // data source SSP RX + | (2 << 11) // transfer from peripheral to memory + ; + + /* Enable RX FIFO DMA */ + SSP_REGS->DMACR = 1; + + /* Write bytes into TX FIFO */ + // FIXME: Any value in doing this using DMA too? + while (txlen > 0) { + while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF)) { + txlen--; + SSP_REGS->DR = 0xff; + } + } + + /* Wait until DMA channel disables itself */ + while (SSP_DMACH->DMACCConfig & 1) ; + + /* Disable RX FIFO DMA */ + SSP_REGS->DMACR = 0; + } +} + +void spi_set_speed(spi_speed_t speed) { + /* Wait until TX fifo is empty */ + while (!BITBAND(SSP_REGS->SR, 0)) ; + + /* Disable SSP (FIXME: Is this required?) */ + SSP_REGS->CR1 = 0; + + /* Change clock divisor */ + if (speed == SPI_SPEED_FAST) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST; + } else if (speed == SPI_SPEED_SLOW) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW; + } else if (speed == SPI_SPEED_FPGA_FAST) { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST; + } else { + SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW; + } + + /* Enable SSP */ + SSP_REGS->CR1 = BV(1); +} diff --git a/src/tests/spi.h b/src/tests/spi.h new file mode 100644 index 0000000..8bb7a8c --- /dev/null +++ b/src/tests/spi.h @@ -0,0 +1,68 @@ +/* sd2iec - SD/MMC to Commodore serial bus interface/controller + Copyright (C) 2007-2010 Ingo Korb + + Inspiration and low-level SD/MMC access based on code from MMC2IEC + by Lars Pontoppidan et al., see sdcard.c|h and config.h. + + FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License only. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + + spi.h: Definitions for the low-level SPI routines + + Based on original code by Lars Pontoppidan et al., see spi.c + for full copyright details. + +*/ +#ifndef SPI_H +#define SPI_H + +#define SSP_TFE 0 // Transmit FIFO empty +#define SSP_TNF 1 // Transmit FIFO not full +#define SSP_RNE 2 // Receive FIFO not empty +#define SSP_RFF 3 // Receive FIFO full +#define SSP_BSY 4 // Busy + +/* Low speed 400kHz for init, fast speed <=20MHz (MMC limit) */ +typedef enum { SPI_SPEED_FAST, SPI_SPEED_SLOW, SPI_SPEED_FPGA_FAST, SPI_SPEED_FPGA_SLOW } spi_speed_t; + +/* Pre-Initialize SPI interface (PCLK divider before PLL setup) */ +void spi_preinit(void); + +/* Initialize SPI interface */ +void spi_init(spi_speed_t speed); + +/* Transmit a single byte */ +void spi_tx_byte(uint8_t data); + +/* Transmit a single byte and return received data */ +uint8_t spi_txrx_byte(uint8_t data); + +/* Transmit a data block */ +void spi_tx_block(const void *data, unsigned int length); + +/* Receive a single byte */ +uint8_t spi_rx_byte(void); + +/* Receive a data block */ +void spi_rx_block(void *data, unsigned int length); + +/* Switch speed of SPI interface */ +void spi_set_speed(spi_speed_t speed); + +/* wait for SPI TX FIFO to become empty */ +void spi_tx_sync(void); + +#endif diff --git a/src/tests/startup.S b/src/tests/startup.S new file mode 100644 index 0000000..8604e91 --- /dev/null +++ b/src/tests/startup.S @@ -0,0 +1,101 @@ +/* startup code for LPC17xx + * + * Written 2010 by Ingo Korb + */ + .syntax unified + + .section .vectors + + .macro except label + .weak \label + .set \label, __unhandled_exception + .word \label + .endm + + /* Cortex M3 standard except vectors */ + .word __stack + .word _start + except NMI_Handler + except HardFault_Handler + except MemManage_Handler + except BusFault_Handler + except UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + except SVC_Handler + except DebugMon_Handler + .word 0 + except PendSV_Handler + except SysTick_Handler + + /* External interrupt vectors */ + except WDT_IRQHandler + except TIMER0_IRQHandler + except TIMER1_IRQHandler + except TIMER2_IRQHandler + except TIMER3_IRQHandler + except UART0_IRQHandler + except UART1_IRQHandler + except UART2_IRQHandler + except UART3_IRQHandler + except PWM1_IRQHandler + except I2C0_IRQHandler + except I2C1_IRQHandler + except I2C2_IRQHandler + except SPI_IRQHandler + except SSP0_IRQHandler + except SSP1_IRQHandler + except PLL0_IRQHandler + except RTC_IRQHandler + except EINT0_IRQHandler + except EINT1_IRQHandler + except EINT2_IRQHandler + except EINT3_IRQHandler + except ADC_IRQHandler + except BOD_IRQHandler + except USB_IRQHandler + except CAN_IRQHandler + except DMA_IRQHandler + except I2S_IRQHandler + except ENET_IRQHandler + except RIT_IRQHandler + except MCPWM_IRQHandler + except QEI_IRQHandler + except PLL1_IRQHandler + + .section .text + + .global _start + .thumb_func +_start: + /* copy data section to ram */ + ldr r0, =__data_load_start + ldr r1, =__data_load_end + ldr r2, =__data_start +dataloop: + ldr.w r3, [r0], #4 + str.w r3, [r2], #4 + cmp r0, r1 + blo dataloop + + /* clear bss section */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + ldr r2, =0 +bssloop: + str.w r2, [r0], #4 + cmp r0, r1 + blo bssloop + + /* start main() */ + b main + + /* endless loop */ + .weak __unhandled_exception + .thumb_func +__unhandled_exception: + b __unhandled_exception + + .end diff --git a/src/tests/tests.h b/src/tests/tests.h new file mode 100644 index 0000000..1ac404b --- /dev/null +++ b/src/tests/tests.h @@ -0,0 +1,27 @@ +/* ___DISCLAIMER___ */ + +#ifndef _TESTS_H +#define _TESTS_H + +int test_sd(void); +int test_rtc(void); +int test_cic(void); +int test_fpga(void); +int test_mem(void); +int test_clk(void); + +enum tests { TEST_SD = 0, + TEST_USB, + TEST_RTC, + TEST_CIC, + TEST_FPGA, + TEST_RAM, + TEST_CLK, + TEST_DAC, + TEST_SNES_IRQ, + TEST_SNES_RAM, + TEST_SNES_PA }; + +enum teststates { NO_RUN = 0, PASSED, FAILED }; + +#endif diff --git a/src/tests/timer.c b/src/tests/timer.c new file mode 100644 index 0000000..d6012ae --- /dev/null +++ b/src/tests/timer.c @@ -0,0 +1,133 @@ +/* ___INGO___ */ + +#include +#include "bits.h" +#include "config.h" +#include "timer.h" +#include "clock.h" +#include "uart.h" +#include "sdnative.h" +#include "snes.h" +#include "led.h" +/* bit definitions */ +#define RITINT 0 +#define RITEN 3 + +#define PCRIT 16 + +extern volatile int sd_changed; +extern volatile int reset_changed; +volatile tick_t ticks; +volatile int wokefromrit; + +void __attribute__((weak,noinline)) SysTick_Hook(void) { + /* Empty function for hooking the systick handler */ +} + +/* Systick interrupt handler */ +void SysTick_Handler(void) { + ticks++; + static uint16_t sdch_state = 0; + static uint16_t reset_state = 0; + static uint16_t led_test_state = 0; + sdch_state = (sdch_state << 1) | SDCARD_DETECT | 0xe000; + if((sdch_state == 0xf000) || (sdch_state == 0xefff)) { + sd_changed = 1; + } + reset_state = (reset_state << 1) | get_snes_reset() | 0xe000; + if((reset_state == 0xf000) || (reset_state == 0xefff)) { + reset_changed = 1; + } + switch(led_test_state&0xc0) { + case 0xc0: led_test_state = 0; break; + case 0x00: + rdyled(1); + readled(0); + writeled(0); + break; + + case 0x40: + rdyled(0); + readled(1); + writeled(0); + break; + + case 0x80: + rdyled(0); + readled(0); + writeled(1); + break; + } +// led_test_state++; + sdn_changed(); + SysTick_Hook(); +} + +void __attribute__((weak,noinline)) RIT_Hook(void) { +} + +void RIT_IRQHandler(void) { + LPC_RIT->RICTRL = BV(RITINT); + NVIC_ClearPendingIRQ(RIT_IRQn); + wokefromrit = 1; + RIT_Hook(); +} + +void timer_init(void) { + /* turn on power to RIT */ + BITBAND(LPC_SC->PCONP, PCRIT) = 1; + + /* clear RIT mask */ + LPC_RIT->RIMASK = 0; /*xffffffff;*/ + + /* PCLK = CCLK */ + BITBAND(LPC_SC->PCLKSEL1, 26) = 1; + BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1; + /* enable SysTick */ + SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk)); +} + +void delay_us(unsigned int time) { + /* Prepare RIT */ + LPC_RIT->RICOUNTER = 0; + LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000000) * time; + LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT); + + /* Wait until RIT signals an interrupt */ + while (!(BITBAND(LPC_RIT->RICTRL, RITINT))) ; + + /* Disable RIT */ + LPC_RIT->RICTRL = 0; +} + +void delay_ms(unsigned int time) { + /* Prepare RIT */ + LPC_RIT->RICOUNTER = 0; + LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time; + LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT); + + /* Wait until RIT signals an interrupt */ + while (!(BITBAND(LPC_RIT->RICTRL, RITINT))) ; + + /* Disable RIT */ + LPC_RIT->RICTRL = 0; +} + +void sleep_ms(unsigned int time) { + + wokefromrit = 0; + /* Prepare RIT */ + LPC_RIT->RICOUNTER = 0; + LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time; + LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT); + NVIC_EnableIRQ(RIT_IRQn); + + /* Wait until RIT signals an interrupt */ +//uart_putc(';'); + while(!wokefromrit) { + __WFI(); + } + NVIC_DisableIRQ(RIT_IRQn); + /* Disable RIT */ + LPC_RIT->RICTRL = BV(RITINT); +} diff --git a/src/tests/timer.h b/src/tests/timer.h new file mode 100644 index 0000000..f775015 --- /dev/null +++ b/src/tests/timer.h @@ -0,0 +1,51 @@ +#ifndef TIMER_H +#define TIMER_H + +#include + +typedef unsigned int tick_t; + +extern volatile tick_t ticks; +#define HZ 100 + +/** + * getticks - return the current system tick count + * + * This inline function returns the current system tick count. + */ +static inline tick_t getticks(void) { + return ticks; +} + +#define MS_TO_TICKS(x) (x/10) + +/* Adapted from Linux 2.6 include/linux/jiffies.h: + * + * These inlines deal with timer wrapping correctly. You are + * strongly encouraged to use them + * 1. Because people otherwise forget + * 2. Because if the timer wrap changes in future you won't have to + * alter your driver code. + * + * time_after(a,b) returns true if the time a is after time b. + * + * Do this with "<0" and ">=0" to only test the sign of the result. A + * good compiler would generate better code (and a really good compiler + * wouldn't care). Gcc is currently neither. + * (">=0" refers to the time_after_eq macro which wasn't copied) + */ +#define time_after(a,b) \ + ((int)(b) - (int)(a) < 0) +#define time_before(a,b) time_after(b,a) + + +void timer_init(void); + +/* delay for "time" microseconds - uses the RIT */ +void delay_us(unsigned int time); + +/* delay for "time" milliseconds - uses the RIT */ +void delay_ms(unsigned int time); +void sleep_ms(unsigned int time); + +#endif diff --git a/src/tests/uart.c b/src/tests/uart.c new file mode 100644 index 0000000..4be863c --- /dev/null +++ b/src/tests/uart.c @@ -0,0 +1,288 @@ +/* + + uart.c: UART access routines + +*/ + +#include +#include "bits.h" +#include "config.h" +#include "uart.h" +#include "led.h" + +/* A few symbols to make this code work for all four UARTs */ +#if defined(CONFIG_UART_NUM) && CONFIG_UART_NUM == 0 +# define UART_PCONBIT 3 +# define UART_PCLKREG PCLKSEL0 +# define UART_PCLKBIT 6 +# define UART_REGS LPC_UART0 +# define UART_HANDLER UART0_IRQHandler +# define UART_IRQ UART0_IRQn +#elif CONFIG_UART_NUM == 1 +# define UART_PCONBIT 4 +# define UART_PCLKREG PCLKSEL0 +# define UART_PCLKBIT 8 +# define UART_REGS LPC_UART1 +# define UART_HANDLER UART1_IRQHandler +# define UART_IRQ UART1_IRQn +#elif CONFIG_UART_NUM == 2 +# define UART_PCONBIT 24 +# define UART_PCLKREG PCLKSEL1 +# define UART_PCLKBIT 16 +# define UART_REGS LPC_UART2 +# define UART_HANDLER UART2_IRQHandler +# define UART_IRQ UART2_IRQn +#elif CONFIG_UART_NUM == 3 +# define UART_PCONBIT 25 +# define UART_PCLKREG PCLKSEL1 +# define UART_PCLKBIT 18 +# define UART_REGS LPC_UART3 +# define UART_HANDLER UART3_IRQHandler +# define UART_IRQ UART3_IRQn +#else +# error CONFIG_UART_NUM is not set or has an invalid value! +#endif +static uint8_t uart_lookupratio(float f_fr) { + uint16_t errors[72]={0,67,71,77,83,91,100,111,125, + 133,143,154,167,182,200,214,222,231, + 250,267,273,286,300,308,333,357,364, + 375,385,400,417,429,444,455,462,467, + 500,533,538,545,556,571,583,600,615, + 625,636,643,667,692,700,714,727,733, + 750,769,778,786,800,818,833,846,857, + 867,875,889,900,909,917,923,929,933}; + + uint8_t ratios[72]={0x10,0xf1,0xe1,0xd1,0xc1,0xb1,0xa1,0x91,0x81, + 0xf2,0x71,0xd2,0x61,0xb2,0x51,0xe3,0x92,0xd3, + 0x41,0xf4,0xb3,0x72,0xa3,0xd4,0x31,0xe5,0xb4, + 0x83,0xd5,0x52,0xc5,0x73,0x94,0xb5,0xd6,0xf7, + 0x21,0xf8,0xd7,0xb6,0x95,0x74,0xc7,0x53,0xd8, + 0x85,0xb7,0xe9,0x32,0xd9,0xa7,0x75,0xb8,0xfb, + 0x43,0xda,0x97,0xeb,0x54,0xb9,0x65,0xdb,0x76, + 0xfd,0x87,0x98,0xa9,0xba,0xcb,0xdc,0xed,0xfe}; + + int fr = (f_fr-1)*1000; + int i=0, i_result=0; + int err=0, lasterr=1000; + for(i=0; i<72; i++) { + if(fr990) { + int_ratio++; + } else if(error>10) { + f_fr=1.5; + f_dl=f_pclk / (16 * baudrate * (f_fr)); + dl = (int)f_dl; + f_fr=f_pclk / (16 * baudrate * dl); + fract_ratio = uart_lookupratio(f_fr); + } + if(!dl) { + return int_ratio; + } else { + return ((fract_ratio<<16)&0xff0000) | dl; + } +} + +static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; +static volatile unsigned int read_idx,write_idx; + +void UART_HANDLER(void) { + int iir = UART_REGS->IIR; + if (!(iir & 1)) { + /* Interrupt is pending */ + switch (iir & 14) { +#if CONFIG_UART_NUM == 1 + case 0: /* modem status */ + (void) UART_REGS->MSR; // dummy read to clear + break; +#endif + + case 2: /* THR empty - send */ + if (read_idx != write_idx) { + int maxchars = 16; + while (read_idx != write_idx && --maxchars > 0) { + UART_REGS->THR = (unsigned char)txbuf[read_idx]; + read_idx = (read_idx+1) & (sizeof(txbuf)-1); + } + if (read_idx == write_idx) { + /* buffer empty - turn off THRE interrupt */ + BITBAND(UART_REGS->IER, 1) = 0; + } + } + break; + + case 12: /* RX timeout */ + case 4: /* data received - not implemented yet */ + (void) UART_REGS->RBR; // dummy read to clear + break; + + case 6: /* RX error */ + (void) UART_REGS->LSR; // dummy read to clear + + default: break; + } + } +} + +void uart_putc(char c) { + if (c == '\n') + uart_putc('\r'); + + unsigned int tmp = (write_idx+1) & (sizeof(txbuf)-1) ; + + if (read_idx == write_idx && (BITBAND(UART_REGS->LSR, 5))) { + /* buffer empty, THR empty -> send immediately */ + UART_REGS->THR = (unsigned char)c; + } else { +#ifdef CONFIG_UART_DEADLOCKABLE + while (tmp == read_idx) ; +#endif + BITBAND(UART_REGS->IER, 1) = 0; // turn off UART interrupt + txbuf[write_idx] = c; + write_idx = tmp; + BITBAND(UART_REGS->IER, 1) = 1; + } +} + +/* Polling version only */ +unsigned char uart_getc(void) { + /* wait for character */ + while (!(BITBAND(UART_REGS->LSR, 0))) ; + return UART_REGS->RBR; +} + +/* Returns true if a char is ready */ +unsigned char uart_gotc(void) { + return BITBAND(UART_REGS->LSR, 0); +} + +void uart_init(void) { + uint32_t div; + + /* Turn on power to UART */ + BITBAND(LPC_SC->PCONP, UART_PCONBIT) = 1; + + /* UART clock = CPU clock - this block is reduced at compile-time */ + if (CONFIG_UART_PCLKDIV == 1) { + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT ) = 1; + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT+1) = 0; + } else if (CONFIG_UART_PCLKDIV == 2) { + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT ) = 0; + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT+1) = 1; + } else if (CONFIG_UART_PCLKDIV == 4) { + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT ) = 0; + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT+1) = 0; + } else { // Fallback: Divide by 8 + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT ) = 1; + BITBAND(LPC_SC->UART_PCLKREG, UART_PCLKBIT+1) = 1; + } + + /* set baud rate - no fractional stuff for now */ + UART_REGS->LCR = BV(7) | 3; // always 8n1 + div = baud2divisor(CONFIG_UART_BAUDRATE); + UART_REGS->DLL = div & 0xff; + UART_REGS->DLM = (div >> 8) & 0xff; + BITBAND(UART_REGS->LCR, 7) = 0; + + if (div & 0xff0000) { + UART_REGS->FDR = (div >> 16) & 0xff; + } + + /* reset and enable FIFO */ + UART_REGS->FCR = BV(0); + + /* enable transmit interrupt */ + BITBAND(UART_REGS->IER, 1) = 1; + NVIC_EnableIRQ(UART_IRQ); + + UART_REGS->THR = '?'; +} + +/* --- generic code below --- */ +void uart_puthex(uint8_t num) { + uint8_t tmp; + tmp = (num & 0xf0) >> 4; + if (tmp < 10) + uart_putc('0'+tmp); + else + uart_putc('a'+tmp-10); + + tmp = num & 0x0f; + if (tmp < 10) + uart_putc('0'+tmp); + else + uart_putc('a'+tmp-10); +} + +void uart_trace(void *ptr, uint16_t start, uint16_t len) { + uint16_t i; + uint8_t j; + uint8_t ch; + uint8_t *data = ptr; + + data+=start; + for(i=0;i>8); + uart_puthex(start&0xff); + uart_putc('|'); + uart_putc(' '); + for(j=0;j<16;j++) { + if(i+j0x7e) + ch='.'; + uart_putc(ch); + } else { + uart_putc(' '); + } + } + uart_putc('|'); + uart_putcrlf(); + start+=16; + } +} + +void uart_flush(void) { + while (read_idx != write_idx) ; +} + +void uart_puts(const char *text) { + while (*text) { + uart_putc(*text++); + } +} diff --git a/src/tests/uart.h b/src/tests/uart.h new file mode 100644 index 0000000..32912de --- /dev/null +++ b/src/tests/uart.h @@ -0,0 +1,49 @@ +/* + + uart.h: Definitions for the UART access routines + +*/ + +#ifndef UART_H +#define UART_H + +#include +#include + +//#ifdef CONFIG_UART_DEBUG +#if 1 + +#ifdef __AVR__ +# include + void uart_puts_P(prog_char *text); +#else +# define uart_puts_P(str) uart_puts(str) +#endif + +void uart_init(void); +unsigned char uart_getc(void); +unsigned char uart_gotc(void); +void uart_putc(char c); +void uart_puts(const char *str); +void uart_puthex(uint8_t num); +void uart_trace(void *ptr, uint16_t start, uint16_t len); +void uart_flush(void); +int printf(const char *fmt, ...); +int snprintf(char *str, size_t size, const char *format, ...); +#define uart_putcrlf() uart_putc('\n') + +#else + +#define uart_init() do {} while(0) +#define uart_getc() 0 +#define uart_putc(x) do {} while(0) +#define uart_puthex(x) do {} while(0) +#define uart_flush() do {} while(0) +#define uart_puts_P(x) do {} while(0) +#define uart_puts(x) do {} while(0) +#define uart_putcrlf() do {} while(0) +#define uart_trace(a,b,c) do {} while(0) + +#endif + +#endif diff --git a/src/tests/xmodem.c b/src/tests/xmodem.c new file mode 100644 index 0000000..979f8d4 --- /dev/null +++ b/src/tests/xmodem.c @@ -0,0 +1,37 @@ +#include +#include "config.h" +#include "timer.h" +#include "uart.h" +#include "ff.h" +#include "xmodem.h" + +void xmodem_rxfile(FIL* fil) { + uint8_t rxbuf[XMODEM_BLKSIZE], sum=0, sender_sum; + uint8_t blknum, blknum2; + uint8_t count; + uint32_t totalbytes = 0; + uint32_t totalwritten = 0; + UINT written; + FRESULT res; + uart_flush(); + do { + delay_ms(3000); + uart_putc(ASC_NAK); + } while (uart_getc() != ASC_SOH); + do { + blknum=uart_getc(); + blknum2=uart_getc(); + for(count=0; count Date: Mon, 19 Dec 2011 22:22:51 +0100 Subject: [PATCH 36/66] SNES: add test suite (SNES side) --- snes/tests/Makefile | 17 ++ snes/tests/header.a65 | 121 +++++++++ snes/tests/reset.a65 | 29 +++ snes/tests/tests.a65 | 564 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 731 insertions(+) create mode 100644 snes/tests/Makefile create mode 100644 snes/tests/header.a65 create mode 100644 snes/tests/reset.a65 create mode 100644 snes/tests/tests.a65 diff --git a/snes/tests/Makefile b/snes/tests/Makefile new file mode 100644 index 0000000..22aac2e --- /dev/null +++ b/snes/tests/Makefile @@ -0,0 +1,17 @@ +OBJS = header.ips reset.o65 tests.o65 + +all: test.bin + +test.bin: $(OBJS) + sneslink -fsmc -o $@ $^ + +# Generic rule to create .o65 out from .a65 +%.o65: %.a65 + snescom -J -Wall -o $@ $< + +# Generic rule to create .ips out from .a65 +%.ips: %.a65 + snescom -I -J -Wall -o $@ $< + +clean: + rm -f *.ips *.o65 *~ test.bin diff --git a/snes/tests/header.a65 b/snes/tests/header.a65 new file mode 100644 index 0000000..b182b25 --- /dev/null +++ b/snes/tests/header.a65 @@ -0,0 +1,121 @@ +; This file is part of the snescom-asm demo - a demo of how to build a SNES program. +; See http://bisqwit.iki.fi/source/snescom.html for details. + +; Begin assembling to this address. +*= $C0F000 +LINETEST: + sei + clc + xce +- lda $0000 + lda $2100 + sta $2100 + bra - + +*= $C0F100 +IRQTEST: + sei + clc + xce + cli + sep #$20 : .as + rep #$10 : .xl + lda #$0f + sta $2100 + lda #$ff + sta $4209 + lda #$ff + sta $420a + lda #$ff + sta $4200 + lda #$01 +- sta @$002222 + bra - + +*= $C0F200 +BANKTEST: + sei + clc + xce + sep #$20 : .as + lda #$01 + sta @$0055aa +- bra - + +*= $C0FF00 + +RESET: + sei + clc + xce + rep #$20 : .al + lda #$1fff + tcs + lda #$00 + sta @$003333 + jmp @GAME_MAIN + +NMI_16bit: + php + rep #$30 : .al : .xl + pha: phx: phy: phd: phb + jsl @NMI_ROUTINE + rep #$30 : .al : .xl +int_exit: + plb: pld: ply: plx: pla + plp + rti + +IRQ_16bit: +ABT_8bit: ABT_16bit: + php + rep #$30 : .al : .xl + pha: phx: phy: phd: phb + jsl @IRQ_ROUTINE + rep #$30 : .al : .xl + bra int_exit + +;error vectors +BRK_8bit: BRK_16bit: +COP_8bit: COP_16bit: +IRQ_8bit: +NMI_8bit: + - wai: lda $ABCDEF : bra - + +*= $C0FFB0 + ; Zero the area from $FFB0 - $FFFF + ; to ensure that the linker won't get clever + ; and fill it with small pieces of code. + .word 0,0,0,0, 0,0,0,0 + .word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 + .word 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 + +*= $C0FFB0 + +.byt "MR" ;2 bytes - company id +.byt "TEST" ;4 bytes - rom id + +*= $C0FFC0 +.byt "SD2SNES TESTS " + ;123456789012345678901; - max 21 chars + +*= $C0FFD5 .byt $31 ;rom speed +*= $C0FFD6 .byt $02 ;rom type +*= $C0FFD7 .byt $06 ;rom size 64 kByte +*= $C0FFD8 .byt $03 ;sram size 8 kBit +*= $C0FFD9 .byt $09 ;rom region 4 = Finland +*= $C0FFDA .byt $33 ;company id flag + +*= $C0FFDC .word 0,0 ;checksums + +*= $C0FFE4 .word COP_16bit +*= $C0FFE6 .word BRK_16bit +*= $C0FFE8 .word ABT_16bit +*= $C0FFEA .word NMI_16bit +*= $C0FFEE .word IRQ_16bit +*= $C0FFF4 .word COP_8bit +*= $C0FFF8 .word ABT_8bit +*= $C0FFFA .word NMI_8bit +*= $C0FFFC .word RESET +*= $C0FFFE .word BRK_8bit +*= $C0FFFE .word IRQ_8bit diff --git a/snes/tests/reset.a65 b/snes/tests/reset.a65 new file mode 100644 index 0000000..d97fd06 --- /dev/null +++ b/snes/tests/reset.a65 @@ -0,0 +1,29 @@ +; This file is part of the snescom-asm demo - a demo of how to build a SNES program. +; See http://bisqwit.iki.fi/source/snescom.html for details. + +; NMI - called on VBlank +NMI_ROUTINE: + sep #$20 : .as + rep #$10 : .xl + lda #$00 + pha + plb + + lda $4210 ; ack interrupt + + rtl + +; IRQ - called when triggered +IRQ_ROUTINE: + sep #$20 : .as + lda $4211 ;Acknowledge irq + lda #$00 + sta @$002121 + lda #$ff + sta @$002122 + lda #$01 + sta @$002122 + lda #$5A + sta @$F00000 + rtl + diff --git a/snes/tests/tests.a65 b/snes/tests/tests.a65 new file mode 100644 index 0000000..75b5686 --- /dev/null +++ b/snes/tests/tests.a65 @@ -0,0 +1,564 @@ +GAME_MAIN: + sep #$20 : .as + stz $4200 ; inhibit VBlank NMI + lda #$01 + sta $420d ; fast cpu + jsr killdma + jsr waitblank + lda #$00 + sta @$f00000 + sta @$f00001 + sta @$f00002 + sta @$f00003 + lda #$00 + sta @$f01fff + jsr snes_init + jsr video_init + jsr linetest + jsr batest + jsr snes_init + jsr video_init + jsr copy_memtest + jsr irqtest + jsl $7e1800 +- bra - + +copy_memtest: + rep #$30 : .al : .xl + lda #$0300 + ldx #!memtest + ldy #$1800 + mvn $7e, ^memtest + rts + +linetest + sep #$20 : .as + lda #$00 + pha + plb +- lda $0000 + lda $2100 + sta $21ff + lda @$f01fff + cmp #$01 + bne - + rts + +irqtest: + cli + sep #$20 : .as + rep #$10 : .xl + lda #$0f + sta $2100 + lda #$ff + sta $4209 + lda #$ff + sta $420a + lda #$ff + sta $4200 + sta @$f00000 + lda #$01 + sta @$002222 + rts + +batest: + sei + sep #$20 : .as + rep #$10 : .xl + lda #$00 + ldx #$2100 +- sta !$0, x + inx + inc + bne - + lda #$e0 + pha + plb + lda #$00 + ldx #$0000 +- cmp !$0, x + bne batest_fail + inx + inc + bne - + lda #$5a + sta @$f00002 + lda #$00 + pha + plb + rts +batest_fail: + lda #$ff + sta @$f00002 + lda #$00 + pha + plb + rts + +memtest: +; test 4 areas: 00-3f:8000-ffff +; 40-7d:0000-ffff +; 80-bf:8000-ffff +; 80-ff:0000-ffff + sep #$20 : .as + rep #$10 : .xl + + lda #$01 + sta @$003333 ; switch to linear memory mode + ldx #$8000 + stx $00 + ldx #$8000 + stx $10 + lda #$00 + sta $03 ; bank no. +mem0_writeloop0: +; switch bank + pha + plb + lda #$01 + sta @$003333 +- lda $03 + clc + adc $01 + clc + adc $00 + sta !$0000, x + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$40 + bne mem0_writeloop0 + + ldx #$0000 + stx $10 +mem0_writeloop1: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + sta !$0000, x + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$7e + bne mem0_writeloop1 + + ldx #$8000 + stx $10 + lda #$80 + sta $03 ; bank no. +mem0_writeloop2: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + sta !$0000, x + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$c0 + bne mem0_writeloop2 + ldx #$0000 + stx $10 +mem0_writeloop3: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + sta !$0000, x + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + bne mem0_writeloop3 + + lda #$00 + sta @$002121 + lda #$ff + sta @$002122 + lda #$03 + sta @$002122 + + ldx #$8000 + stx $00 + ldx #$8000 + stx $10 + lda #$00 + sta $03 ; bank no. +mem0_verifyloop0: +; switch bank + lda #$01 + sta @$f00001 + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + cmp !$0000, x + bne mem0_fail + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$40 + bne mem0_verifyloop0 + + ldx #$0000 + stx $10 +mem0_verifyloop1: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + cmp !$0000, x + bne mem0_fail + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$7e + bne mem0_verifyloop1 + + ldx #$8000 + stx $10 + lda #$80 + sta $03 ; bank no. + bra mem0_verifyloop2 +mem0_fail: + lda #$00 + pha + plb + sta @$003333 + rep #$20 : .al + lda $00 + sta @$f00004 + sep #$20 : .as + lda $03 + sta @$f00006 + lda #$ff + sta @$f00001 + rtl +mem0_verifyloop2: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + cmp !$0000, x + bne mem0_fail + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + cmp #$c0 + bne mem0_verifyloop2 + + ldx #$0000 + stx $10 +mem0_verifyloop3: +; switch bank + lda #$01 + sta @$003333 + lda $03 + pha + plb +- lda $03 + clc + adc $01 + clc + adc $00 + cmp !$0000, x + bne mem0_fail + inx + stx $00 + bne - + ldx $10 + inc $03 + lda #$00 + sta @$003333 + lda $03 + sta @$f00003 + bne mem0_verifyloop3 + + lda #$00 + sta @$002121 + lda #$e0 + sta @$002122 + lda #$03 + sta @$002122 + + lda #$00 + pha + plb + sta @$003333 + lda #$5a + sta @$f00001 + rtl + rtl + rtl + rtl + rtl + rtl + +killdma: + stz $420b + stz $420c + stz $4310 + stz $4311 + stz $4312 + stz $4313 + stz $4314 + stz $4320 + stz $4321 + stz $4322 + stz $4323 + stz $4324 + stz $4330 + stz $4331 + stz $4332 + stz $4333 + stz $4334 + stz $4340 + stz $4341 + stz $4342 + stz $4343 + stz $4344 + stz $4350 + stz $4351 + stz $4352 + stz $4353 + stz $4354 + stz $4360 + stz $4361 + stz $4362 + stz $4363 + stz $4364 + rts + + + + +waitblank: +- lda $4212 + and #$80 + bne - +- lda $4212 + and #$80 + beq - + rts + +video_init: + sep #$20 : .as ;8-bit accumulator + rep #$10 : .xl ;16-bit index + lda #$03 ;mode 3, mode 5 via HDMA :D + sta $2105 + lda #$58 ;Tilemap addr 0xB000 + ora #$02 ;SC size 32x64 + sta $2107 ;for BG1 + lda #$50 ;Tilemap addr 0xA000 + ora #$02 ;SC size 32x64 + sta $2108 ;for BG2 + lda #$40 ;chr base addr: + sta $210b ;BG1=0x0000, BG2=0x8000 + lda #$01 ;cut off leftmost subscreen pixel garbage + sta $2126 + lda #$fe + sta $2127 + lda #$10 + sta $2130 + lda #$1f + sta $212e + sta $212f + stz $2121 + lda #$0f + sta $2100 ;screen on, full brightness + stz $2121 + lda #$1f ;red background + sta $2122 + stz $2122 + rts + +snes_init: + sep #$20 : .as ;8-bit accumulator + rep #$10 : .xl ;16-bit index + stz $4200 ; + lda #$ff + sta $4201 ; + stz $4202 ; + stz $4203 ; + stz $4204 ; + stz $4205 ; + stz $4206 ; + stz $4207 ; + stz $4208 ; + stz $4209 ; + stz $420a ; + stz $420b ; + stz $420c ; + lda #$8f + sta $2100 ;INIDISP: force blank + lda #$03 ; 8x8+16x16; name=0; base=3 + sta $2101 ; + stz $2102 ; + stz $2103 ; +; stz $2104 ; (OAM Data?!) +; stz $2104 ; (OAM Data?!) + stz $2105 ; + stz $2106 ; + stz $2107 ; + stz $2108 ; + stz $2109 ; + stz $210a ; + stz $210b ; + stz $210c ; + stz $210d ; + stz $210d ; + stz $210e ; + stz $210e ; + stz $210f ; + stz $210f ; + lda #$05 + sta $2110 ; + stz $2110 ; + stz $2111 ; + stz $2111 ; + stz $2112 ; + stz $2112 ; + stz $2113 ; + stz $2113 ; + stz $2114 ; + stz $2114 ; + lda #$80 + sta $2115 ; + stz $2116 ; + stz $2117 ; +; stz $2118 ;(VRAM Data?!) +; stz $2119 ;(VRAM Data?!) + stz $211a ; + stz $211b ; + lda #$01 + sta $211b ; + stz $211c ; + stz $211c ; + stz $211d ; + stz $211d ; + stz $211e ; + sta $211e ; + stz $211f ; + stz $211f ; + stz $2120 ; + stz $2120 ; + stz $2121 ; +; stz $2122 ; (CG Data?!) +; stz $2122 ; (CG Data?!) + stz $2123 ; + stz $2124 ; + stz $2125 ; + stz $2126 ; + stz $2127 ; + stz $2128 ; + stz $2129 ; + stz $212a ; + stz $212b ; + stz $212c ; + stz $212d ; + stz $212e ; + stz $212f ; + lda #$30 + sta $2130 ; + stz $2131 ; + lda #$e0 + sta $2132 ; + stz $2133 ; +;clear WRAM lower page +; ldx #$0200 +; stx $2181 +; lda #$00 +; sta $2183 +; DMA0(#$08, #$FF00, #^zero, #!zero, #$80) +; ldx #$0000 +; stx $2181 +; lda #$00 +; sta $2183 +; DMA0(#$08, #$1e0, #^zero, #!zero, #$80) + + rts + + From dc01edfe9a17a22dc18d5a769ae0755c45cb9996 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 19 Dec 2011 22:26:09 +0100 Subject: [PATCH 37/66] FPGA: add test suite --- verilog/sd2snes_test/address.v | 72 +++ verilog/sd2snes_test/clk_test.v | 120 ++++ verilog/sd2snes_test/dac.v | 146 +++++ verilog/sd2snes_test/dcm.v | 72 +++ verilog/sd2snes_test/ipcore_dir/PA.xco | 105 +++ verilog/sd2snes_test/ipcore_dir/PA.xise | 378 +++++++++++ verilog/sd2snes_test/ipcore_dir/bram.xco | 105 +++ verilog/sd2snes_test/ipcore_dir/bram.xise | 378 +++++++++++ verilog/sd2snes_test/ipcore_dir/dac_buf.xco | 105 +++ verilog/sd2snes_test/ipcore_dir/dac_buf.xise | 378 +++++++++++ verilog/sd2snes_test/main.ucf | 635 +++++++++++++++++++ verilog/sd2snes_test/main.v | 596 +++++++++++++++++ verilog/sd2snes_test/mcu_cmd.v | 618 ++++++++++++++++++ verilog/sd2snes_test/sd2snes_test.xise | 432 +++++++++++++ verilog/sd2snes_test/sd_dma.v | 132 ++++ verilog/sd2snes_test/spi.v | 113 ++++ 16 files changed, 4385 insertions(+) create mode 100644 verilog/sd2snes_test/address.v create mode 100644 verilog/sd2snes_test/clk_test.v create mode 100644 verilog/sd2snes_test/dac.v create mode 100644 verilog/sd2snes_test/dcm.v create mode 100644 verilog/sd2snes_test/ipcore_dir/PA.xco create mode 100644 verilog/sd2snes_test/ipcore_dir/PA.xise create mode 100644 verilog/sd2snes_test/ipcore_dir/bram.xco create mode 100644 verilog/sd2snes_test/ipcore_dir/bram.xise create mode 100644 verilog/sd2snes_test/ipcore_dir/dac_buf.xco create mode 100644 verilog/sd2snes_test/ipcore_dir/dac_buf.xise create mode 100644 verilog/sd2snes_test/main.ucf create mode 100644 verilog/sd2snes_test/main.v create mode 100644 verilog/sd2snes_test/mcu_cmd.v create mode 100644 verilog/sd2snes_test/sd2snes_test.xise create mode 100644 verilog/sd2snes_test/sd_dma.v create mode 100644 verilog/sd2snes_test/spi.v diff --git a/verilog/sd2snes_test/address.v b/verilog/sd2snes_test/address.v new file mode 100644 index 0000000..6dae255 --- /dev/null +++ b/verilog/sd2snes_test/address.v @@ -0,0 +1,72 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: address +// Project Name: +// Target Devices: +// Tool versions: +// Description: Address logic w/ SaveRAM masking +// +// Dependencies: +// +// Revision: +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module address( + input CLK, + input [23:0] SNES_ADDR, // requested address from SNES + output [23:0] ram0_addr, + output [18:0] ram1_addr, + output [7:0] PA_addr, + output [12:0] bram_addr, + input [7:0] ram0_bank, + input ram0_linear, + output ram0_enable, + output ram1_enable, + output PA_enable, + output bram_enable, + output irq_enable, + output bank_enable, + output linear_enable +); + +wire [23:0] SRAM_SNES_ADDR; + +assign ram0bank0_enable = (SNES_ADDR[23:15] == 9'h001) | (SNES_ADDR[23:16] == 8'hC0); +assign ram0bankx_enable = (SNES_ADDR[23:16] == 8'hC8); +assign ram0linear_enable = ram0_linear & (SNES_ADDR[22] | SNES_ADDR[15]); +assign ram0_enable = ram0linear_enable | ram0bank0_enable | ram0bankx_enable; +assign ram1_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hD); +assign PA_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hE); +assign bram_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hF); +wire bank_enable_ = (SNES_ADDR == 24'h0055AA); +wire irq_enable_ = (SNES_ADDR == 24'h002222); +wire linear_enable_ = (SNES_ADDR == 24'h003333); + +reg [2:0] bank_enable_r; +reg [2:0] irq_enable_r; +reg [2:0] linear_enable_r; +always @(posedge CLK) begin + bank_enable_r <= {bank_enable_r[1:0], bank_enable_}; + irq_enable_r <= {irq_enable_r[1:0], irq_enable_}; + linear_enable_r <= {linear_enable_r[1:0], linear_enable_}; +end +assign bank_enable = bank_enable_r[2]; +assign irq_enable = irq_enable_r[2]; +assign linear_enable = linear_enable_r[2]; + +assign ram0_addr = ram0_linear ? SNES_ADDR + : {2'b00,SNES_ADDR[21:0]}; + +assign ram1_addr = SNES_ADDR[18:0]; + +assign PA_addr = SNES_ADDR[7:0]; + +assign bram_addr = SNES_ADDR[12:0]; + +endmodule diff --git a/verilog/sd2snes_test/clk_test.v b/verilog/sd2snes_test/clk_test.v new file mode 100644 index 0000000..d00601d --- /dev/null +++ b/verilog/sd2snes_test/clk_test.v @@ -0,0 +1,120 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:40:46 12/20/2010 +// Design Name: +// Module Name: clk_test +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module clk_test( + input clk, + input sysclk, + input read, + input write, + input pawr, + input pard, + input refresh, + input cpuclk, + input romsel, + output reg [31:0] snes_sysclk_freq, + output reg [31:0] snes_read_freq, + output reg [31:0] snes_write_freq, + output reg [31:0] snes_pawr_freq, + output reg [31:0] snes_pard_freq, + output reg [31:0] snes_refresh_freq, + output reg [31:0] snes_cpuclk_freq, + output reg [31:0] snes_romsel_freq +); + +reg [31:0] sysclk_counter; +reg [31:0] sysclk_value; +reg [31:0] read_value; +reg [31:0] write_value; +reg [31:0] pard_value; +reg [31:0] pawr_value; +reg [31:0] refresh_value; +reg [31:0] cpuclk_value; +reg [31:0] romsel_value; + +initial snes_sysclk_freq = 32'hFFFFFFFF; +initial sysclk_counter = 0; +initial sysclk_value = 0; +initial read_value = 0; +initial write_value = 0; +initial pard_value = 0; +initial pawr_value = 0; +initial refresh_value = 0; +initial cpuclk_value = 0; +initial romsel_value = 0; + +reg [1:0] sysclk_sreg; +reg [1:0] read_sreg; +reg [1:0] write_sreg; +reg [1:0] pard_sreg; +reg [1:0] pawr_sreg; +reg [1:0] refresh_sreg; +reg [1:0] cpuclk_sreg; +reg [1:0] romsel_sreg; + +always @(posedge clk) romsel_sreg <= {romsel_sreg[0], romsel}; +wire romsel_rising = (romsel_sreg == 2'b01); +always @(posedge clk) cpuclk_sreg <= {cpuclk_sreg[0], cpuclk}; +wire cpuclk_rising = (cpuclk_sreg == 2'b01); +always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk}; +wire sysclk_rising = (sysclk_sreg == 2'b01); +always @(posedge clk) read_sreg <= {read_sreg[0], read}; +wire read_rising = (read_sreg == 2'b01); +always @(posedge clk) write_sreg <= {write_sreg[0], write}; +wire write_rising = (write_sreg == 2'b01); +always @(posedge clk) pard_sreg <= {pard_sreg[0], pard}; +wire pard_rising = (pard_sreg == 2'b01); +always @(posedge clk) pawr_sreg <= {pawr_sreg[0], pawr}; +wire pawr_rising = (pawr_sreg == 2'b01); +always @(posedge clk) refresh_sreg <= {refresh_sreg[0], refresh}; +wire refresh_rising = (refresh_sreg == 2'b01); + +always @(posedge clk) begin + if(sysclk_counter < 96000000) begin + sysclk_counter <= sysclk_counter + 1; + if(sysclk_rising) sysclk_value <= sysclk_value + 1; + if(read_rising) read_value <= read_value + 1; + if(write_rising) write_value <= write_value + 1; + if(pard_rising) pard_value <= pard_value + 1; + if(pawr_rising) pawr_value <= pawr_value + 1; + if(refresh_rising) refresh_value <= refresh_value + 1; + if(cpuclk_rising) cpuclk_value <= cpuclk_value + 1; + if(romsel_rising) romsel_value <= romsel_value + 1; + end else begin + snes_sysclk_freq <= sysclk_value; + snes_read_freq <= read_value; + snes_write_freq <= write_value; + snes_pard_freq <= pard_value; + snes_pawr_freq <= pawr_value; + snes_refresh_freq <= refresh_value; + snes_cpuclk_freq <= cpuclk_value; + snes_romsel_freq <= romsel_value; + sysclk_counter <= 0; + sysclk_value <= 0; + read_value <= 0; + write_value <= 0; + pard_value <= 0; + pawr_value <= 0; + refresh_value <= 0; + cpuclk_value <= 0; + romsel_value <= 0; + end +end + +endmodule diff --git a/verilog/sd2snes_test/dac.v b/verilog/sd2snes_test/dac.v new file mode 100644 index 0000000..db6d059 --- /dev/null +++ b/verilog/sd2snes_test/dac.v @@ -0,0 +1,146 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:26:11 07/23/2010 +// Design Name: +// Module Name: dac_test +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dac( + input clkin, + input sysclk, + input we, + input[10:0] pgm_address, + input[7:0] pgm_data, + input play, + input reset, + output sdout, + output lrck, + output mclk, + output DAC_STATUS +); + +reg[8:0] dac_address_r; +wire[8:0] dac_address = dac_address_r; + +wire[31:0] dac_data; +assign DAC_STATUS = dac_address_r[8]; +reg[7:0] vol_reg; +reg[7:0] vol_target_reg; +reg[1:0] vol_latch_reg; +reg vol_valid; +reg[2:0] sysclk_sreg; +wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01); + +reg [25:0] interpol_count; + +always @(posedge clkin) begin + sysclk_sreg <= {sysclk_sreg[1:0], sysclk}; +end + +dac_buf snes_dac_buf ( + .clka(clkin), + .wea(~we), // Bus [0 : 0] + .addra(pgm_address), // Bus [10 : 0] + .dina(pgm_data), // Bus [7 : 0] + .clkb(clkin), + .addrb(dac_address), // Bus [8 : 0] + .doutb(dac_data)); // Bus [31 : 0] + +reg [8:0] cnt; +reg [15:0] smpcnt; +reg [1:0] samples; +reg [15:0] smpshift; + +assign mclk = cnt[2]; // mclk = clk/8 +assign lrck = cnt[8]; // lrck = mclk/128 +wire sclk = cnt[3]; // sclk = lrck*32 + +reg [2:0] lrck_sreg; +reg [2:0] sclk_sreg; +wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01); +wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10); + +wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01); + +reg sdout_reg; +assign sdout = sdout_reg; + +reg [1:0] reset_sreg; +wire reset_rising = (reset_sreg[1:0] == 2'b01); + +reg play_r; + +initial begin + cnt = 9'h100; + smpcnt = 16'b0; + lrck_sreg = 2'b11; + sclk_sreg = 1'b0; + dac_address_r = 10'b0; + vol_valid = 1'b0; + vol_latch_reg = 1'b0; + vol_reg = 8'h0; + vol_target_reg = 8'hff; + samples <= 2'b00; +end + +always @(posedge clkin) begin + if(reset_rising) begin + dac_address_r <= 0; + interpol_count <= 0; + end else if(sysclk_rising) begin + if(interpol_count > 59378938) begin + interpol_count <= interpol_count + 122500 - 59501439; + dac_address_r <= dac_address_r + play_r; + end else begin + interpol_count <= interpol_count + 122500; + end + end +end + +always @(posedge clkin) begin + cnt <= cnt + 1; + lrck_sreg <= {lrck_sreg[1:0], lrck}; + sclk_sreg <= {sclk_sreg[1:0], sclk}; + play_r <= play; + reset_sreg <= {reset_sreg[0], reset}; +end + +// ramp volume only every 4 samples +always @(posedge clkin) begin + if (lrck_rising && &samples[1:0]) begin + if(vol_reg > vol_target_reg) + vol_reg <= vol_reg - 1; + else if(vol_reg < vol_target_reg) + vol_reg <= vol_reg + 1; + end +end + +always @(posedge clkin) begin + if (lrck_rising) begin // right channel + smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + samples <= samples + 1; + end else if (lrck_falling) begin // left channel + smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + end else begin + if (sclk_rising) begin + smpcnt <= smpcnt + 1; + sdout_reg <= smpshift[15]; + smpshift <= {smpshift[14:0], 1'b0}; + end + end +end + +endmodule diff --git a/verilog/sd2snes_test/dcm.v b/verilog/sd2snes_test/dcm.v new file mode 100644 index 0000000..90b516e --- /dev/null +++ b/verilog/sd2snes_test/dcm.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:06:52 06/28/2009 +// Design Name: +// Module Name: dcm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module my_dcm ( + input CLKIN, + output CLKFX, + output LOCKED, + input RST, + output[7:0] STATUS + ); + + // DCM: Digital Clock Manager Circuit + // Spartan-3 + // Xilinx HDL Language Template, version 11.1 + + DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(41.667), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hFFFF), // FACTORY JF values +// .LOC("DCM_X0Y0"), + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_inst ( + .CLK0(CLK0), // 0 degree DCM CLK output + .CLK180(CLK180), // 180 degree DCM CLK output + .CLK270(CLK270), // 270 degree DCM CLK output + .CLK2X(CLK2X), // 2X DCM CLK output + .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out + .CLK90(CLK90), // 90 degree DCM CLK output + .CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(CLKFX), // DCM CLK synthesis out (M/D) + .CLKFX180(CLKFX180), // 180 degree CLK synthesis out + .LOCKED(LOCKED), // DCM LOCK status output + .PSDONE(PSDONE), // Dynamic phase adjust done output + .STATUS(STATUS), // 8-bit DCM status bits output + .CLKFB(CLKFB), // DCM clock feedback + .CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(PSCLK), // Dynamic phase adjust clock input + .PSEN(PSEN), // Dynamic phase adjust enable input + .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement + .RST(RST) // DCM asynchronous reset input + ); +endmodule diff --git a/verilog/sd2snes_test/ipcore_dir/PA.xco b/verilog/sd2snes_test/ipcore_dir/PA.xco new file mode 100644 index 0000000..e25d689 --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/PA.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Fri Dec 9 20:36:25 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xa3s400 +SET devicefamily = aspartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pqg208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4q +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=PA +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=256 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: 213d12c4 diff --git a/verilog/sd2snes_test/ipcore_dir/PA.xise b/verilog/sd2snes_test/ipcore_dir/PA.xise new file mode 100644 index 0000000..33142d2 --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/PA.xise @@ -0,0 +1,378 @@ + + + +

+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_test/ipcore_dir/bram.xco b/verilog/sd2snes_test/ipcore_dir/bram.xco new file mode 100644 index 0000000..4312d26 --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/bram.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Fri Dec 9 20:35:22 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xa3s400 +SET devicefamily = aspartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pqg208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4q +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=bram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=8192 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: cb4729a5 diff --git a/verilog/sd2snes_test/ipcore_dir/bram.xise b/verilog/sd2snes_test/ipcore_dir/bram.xise new file mode 100644 index 0000000..8bf0faa --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/bram.xise @@ -0,0 +1,378 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_test/ipcore_dir/dac_buf.xco b/verilog/sd2snes_test/ipcore_dir/dac_buf.xco new file mode 100644 index 0000000..316029b --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/dac_buf.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Fri Dec 9 20:37:13 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xa3s400 +SET devicefamily = aspartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pqg208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4q +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dac_buf +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=32 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=32 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:43:52.000Z +# END Extra information +GENERATE +# CRC: 360f80d1 diff --git a/verilog/sd2snes_test/ipcore_dir/dac_buf.xise b/verilog/sd2snes_test/ipcore_dir/dac_buf.xise new file mode 100644 index 0000000..81e803a --- /dev/null +++ b/verilog/sd2snes_test/ipcore_dir/dac_buf.xise @@ -0,0 +1,378 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_test/main.ucf b/verilog/sd2snes_test/main.ucf new file mode 100644 index 0000000..e2457cb --- /dev/null +++ b/verilog/sd2snes_test/main.ucf @@ -0,0 +1,635 @@ +NET "CLKIN" TNM_NET = "CLKIN"; +TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %; +//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %; + +NET "p113_out" IOSTANDARD = LVCMOS33; +NET "p113_out" LOC = P113; + +NET "SPI_SCK" LOC = P71; +NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE; +NET "SPI_SCK" TNM_NET = "SPI_SCK"; +TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %; + +NET "SPI_SCK" IOSTANDARD = LVCMOS33; +NET "SPI_SCK" DRIVE = 8; +NET "SPI_SCK" PULLUP; + +NET "SNES_CS" IOSTANDARD = LVCMOS33; +NET "SNES_READ" IOSTANDARD = LVCMOS33; +NET "SNES_WRITE" IOSTANDARD = LVCMOS33; +NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33; +NET "SNES_REFRESH" IOSTANDARD = LVCMOS33; + +NET "CLKIN" IOSTANDARD = LVCMOS33; +//NET "CLKIN" PULLUP; +NET "SPI_SS" PULLUP; +//NET "DCM_RST" LOC = P46; +//NET "DCM_RST" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33; +NET "SNES_IRQ" IOSTANDARD = LVCMOS33; + +NET "ROM_CE" LOC = P172; +NET "ROM_CE" IOSTANDARD = LVCMOS33; +NET "ROM_CE" DRIVE = 8; + +NET "SNES_ADDR[0]" LOC = P119; +NET "SNES_ADDR[10]" LOC = P146; +NET "SNES_ADDR[11]" LOC = P148; +NET "SNES_ADDR[12]" LOC = P147; +NET "SNES_ADDR[13]" LOC = P144; +NET "SNES_ADDR[14]" LOC = P141; +NET "SNES_ADDR[15]" LOC = P139; +NET "SNES_ADDR[16]" LOC = P137; +NET "SNES_ADDR[17]" LOC = P133; +NET "SNES_ADDR[18]" LOC = P131; +NET "SNES_ADDR[19]" LOC = P128; +NET "SNES_ADDR[1]" LOC = P122; +NET "SNES_ADDR[20]" LOC = P125; +NET "SNES_ADDR[21]" LOC = P123; +NET "SNES_ADDR[22]" LOC = P120; +NET "SNES_ADDR[23]" LOC = P117; +NET "SNES_ADDR[2]" LOC = P124; +NET "SNES_ADDR[3]" LOC = P126; +NET "SNES_ADDR[4]" LOC = P130; +NET "SNES_ADDR[5]" LOC = P132; +NET "SNES_ADDR[6]" LOC = P135; +NET "SNES_ADDR[7]" LOC = P138; +NET "SNES_ADDR[8]" LOC = P140; +NET "SNES_ADDR[9]" LOC = P143; +NET "SNES_DATA[0]" LOC = P107; +NET "SNES_DATA[1]" LOC = P102; +NET "SNES_DATA[2]" LOC = P100; +NET "SNES_DATA[3]" LOC = P96; +NET "SNES_DATA[4]" LOC = P108; +NET "SNES_DATA[5]" LOC = P106; +NET "SNES_DATA[6]" LOC = P101; +NET "SNES_DATA[7]" LOC = P97; + + +NET "CLKIN" LOC = P80; +// NET "RST" LOC = P113; +NET "MCU_OVR" LOC = P92; + + +NET "MCU_OVR" IOSTANDARD = LVCMOS33; +NET "MCU_OVR" DRIVE = 8; + +NET "MCU_RDY" LOC = P83; +NET "MCU_RDY" IOSTANDARD = LVCMOS33; +NET "MCU_RDY" DRIVE = 8; + + +NET "ROM_ADDR[0]" LOC = P166; + + +NET "ROM_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[0]" DRIVE = 8; + + +NET "ROM_ADDR[10]" LOC = P197; + + +NET "ROM_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[10]" DRIVE = 8; + + +NET "ROM_ADDR[11]" LOC = P196; + + +NET "ROM_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[11]" DRIVE = 8; + + +NET "ROM_ADDR[12]" LOC = P2; + + +NET "ROM_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[12]" DRIVE = 8; + + +NET "ROM_ADDR[13]" LOC = P194; + + +NET "ROM_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[13]" DRIVE = 8; + + +NET "ROM_ADDR[14]" LOC = P200; + + +NET "ROM_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[14]" DRIVE = 8; + + +NET "ROM_ADDR[15]" LOC = P184; + + +NET "ROM_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[15]" DRIVE = 8; + + +NET "ROM_ADDR[16]" LOC = P199; + + +NET "ROM_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[16]" DRIVE = 8; + + +NET "ROM_ADDR[17]" LOC = P11; + + +NET "ROM_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[17]" DRIVE = 8; + + +NET "ROM_ADDR[18]" LOC = P3; + + +NET "ROM_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[18]" DRIVE = 8; + + +NET "ROM_ADDR[19]" LOC = P4; + + +NET "ROM_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[19]" DRIVE = 8; + + +NET "ROM_ADDR[1]" LOC = P168; + + +NET "ROM_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[1]" DRIVE = 8; + + +NET "ROM_ADDR[20]" LOC = P191; + + +NET "ROM_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[20]" DRIVE = 8; + + +NET "ROM_ADDR[21]" LOC = P203; + + +NET "ROM_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[21]" DRIVE = 8; + + +NET "ROM_ADDR[22]" LOC = P198; + + +NET "ROM_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[22]" DRIVE = 8; + + +NET "ROM_ADDR[2]" LOC = P171; + + +NET "ROM_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[2]" DRIVE = 8; + + +NET "ROM_ADDR[3]" LOC = P165; + + +NET "ROM_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[3]" DRIVE = 8; + + +NET "ROM_ADDR[4]" LOC = P169; + + +NET "ROM_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[4]" DRIVE = 8; + + +NET "ROM_ADDR[5]" LOC = P18; + + +NET "ROM_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[5]" DRIVE = 8; + + +NET "ROM_ADDR[6]" LOC = P175; + + +NET "ROM_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[6]" DRIVE = 8; + + +NET "ROM_ADDR[7]" LOC = P167; + + +NET "ROM_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[7]" DRIVE = 8; + + +NET "ROM_ADDR[8]" LOC = P205; + + +NET "ROM_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[8]" DRIVE = 8; + + +NET "ROM_ADDR[9]" LOC = P204; + + +NET "ROM_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[9]" DRIVE = 8; + + +NET "ROM_BHE" LOC = P161; + + +NET "ROM_BHE" IOSTANDARD = LVCMOS33; +NET "ROM_BHE" DRIVE = 8; + + +NET "ROM_BLE" LOC = P156; + + +NET "ROM_BLE" IOSTANDARD = LVCMOS33; +NET "ROM_BLE" DRIVE = 8; + + +NET "ROM_DATA[0]" LOC = P176; + + +NET "ROM_DATA[0]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[0]" DRIVE = 8; + + +NET "ROM_DATA[10]" LOC = P15; + + +NET "ROM_DATA[10]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[10]" DRIVE = 8; + + +NET "ROM_DATA[11]" LOC = P12; + + +NET "ROM_DATA[11]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[11]" DRIVE = 8; + + +NET "ROM_DATA[12]" LOC = P10; + + +NET "ROM_DATA[12]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[12]" DRIVE = 8; + + +NET "ROM_DATA[13]" LOC = P7; + + +NET "ROM_DATA[13]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[13]" DRIVE = 8; + + +NET "ROM_DATA[14]" LOC = P9; + + +NET "ROM_DATA[14]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[14]" DRIVE = 8; + + +NET "ROM_DATA[15]" LOC = P5; + + +NET "ROM_DATA[15]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[15]" DRIVE = 8; + + +NET "ROM_DATA[1]" LOC = P178; + + +NET "ROM_DATA[1]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[1]" DRIVE = 8; + + +NET "ROM_DATA[2]" LOC = P181; + + +NET "ROM_DATA[2]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[2]" DRIVE = 8; + + +NET "ROM_DATA[3]" LOC = P182; + + +NET "ROM_DATA[3]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[3]" DRIVE = 8; + + +NET "ROM_DATA[4]" LOC = P183; + + +NET "ROM_DATA[4]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[4]" DRIVE = 8; + + +NET "ROM_DATA[5]" LOC = P187; + + +NET "ROM_DATA[5]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[5]" DRIVE = 8; + + +NET "ROM_DATA[6]" LOC = P185; + + +NET "ROM_DATA[6]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[6]" DRIVE = 8; + + +NET "ROM_DATA[7]" LOC = P189; + + +NET "ROM_DATA[7]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[7]" DRIVE = 8; + + +NET "ROM_DATA[8]" LOC = P16; + + +NET "ROM_DATA[8]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[8]" DRIVE = 8; + + +NET "ROM_DATA[9]" LOC = P13; + + +NET "ROM_DATA[9]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[9]" DRIVE = 8; + + +NET "ROM_OE" LOC = P162; + + +NET "ROM_OE" IOSTANDARD = LVCMOS33; +NET "ROM_OE" DRIVE = 8; + + +NET "ROM_WE" LOC = P190; + + +NET "ROM_WE" IOSTANDARD = LVCMOS33; +NET "ROM_WE" DRIVE = 8; +NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[0]" DRIVE = 8; +NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[10]" DRIVE = 8; +NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[11]" DRIVE = 8; +NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[12]" DRIVE = 8; +NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[13]" DRIVE = 8; +NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[14]" DRIVE = 8; +NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[15]" DRIVE = 8; +NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[16]" DRIVE = 8; +NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[17]" DRIVE = 8; +NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[18]" DRIVE = 8; +NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[19]" DRIVE = 8; +NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[1]" DRIVE = 8; +NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[20]" DRIVE = 8; +NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[21]" DRIVE = 8; +NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[22]" DRIVE = 8; +NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[23]" DRIVE = 8; +NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[2]" DRIVE = 8; +NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[3]" DRIVE = 8; +NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[4]" DRIVE = 8; +NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[5]" DRIVE = 8; +NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[6]" DRIVE = 8; +NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[7]" DRIVE = 8; +NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[8]" DRIVE = 8; +NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[9]" DRIVE = 8; + + +NET "SNES_CPU_CLK" LOC = P95; +NET "SNES_CS" LOC = P116; +NET "SNES_DATABUS_DIR" LOC = P111; +NET "SNES_DATABUS_OE" LOC = P109; +NET "SNES_DATABUS_DIR" DRIVE = 8; +NET "SNES_DATABUS_OE" DRIVE = 8; + + +NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[0]" DRIVE = 8; +NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[1]" DRIVE = 8; +NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[2]" DRIVE = 8; +NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[3]" DRIVE = 8; +NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[4]" DRIVE = 8; +NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[5]" DRIVE = 8; +NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[6]" DRIVE = 8; +NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[7]" DRIVE = 8; + + +NET "SNES_IRQ" LOC = P114; +NET "SNES_READ" LOC = P115; +NET "SNES_REFRESH" LOC = P155; +NET "SNES_WRITE" LOC = P94; + +NET "SNES_PA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[0]" LOC = P90; +NET "SNES_PA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[1]" LOC = P93; +NET "SNES_PA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[2]" LOC = P86; +NET "SNES_PA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[3]" LOC = P87; +NET "SNES_PA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[4]" LOC = P81; +NET "SNES_PA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[5]" LOC = P85; +NET "SNES_PA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[6]" LOC = P152; +NET "SNES_PA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[7]" LOC = P154; + +NET "SNES_PARD" IOSTANDARD = LVCMOS33; +NET "SNES_PARD" LOC = P149; +NET "SNES_PAWR" IOSTANDARD = LVCMOS33; +NET "SNES_PAWR" LOC = P150; + +NET "SPI_MISO" LOC = P72; + + +NET "SPI_MISO" IOSTANDARD = LVCMOS33; +NET "SPI_MISO" DRIVE = 8; + + +NET "SPI_MOSI" LOC = P74; + + +NET "SPI_MOSI" IOSTANDARD = LVCMOS33; +NET "SPI_MOSI" DRIVE = 8; + + +NET "SPI_SS" LOC = P68; + + +NET "SPI_SS" IOSTANDARD = LVCMOS33; +NET "SPI_SS" DRIVE = 8; + + +NET "DAC_LRCK" LOC = P77; + + +NET "DAC_LRCK" IOSTANDARD = LVCMOS33; +NET "DAC_LRCK" DRIVE = 8; + + +NET "DAC_MCLK" LOC = P76; + + +NET "DAC_MCLK" IOSTANDARD = LVCMOS33; +NET "DAC_MCLK" DRIVE = 8; + + +NET "DAC_SDOUT" LOC = P78; + + +NET "DAC_SDOUT" IOSTANDARD = LVCMOS33; +NET "DAC_SDOUT" DRIVE = 8; + +# PlanAhead Generated physical constraints + +NET "SD_CLK" LOC = P64; +NET "SD_CMD" LOC = P67; +NET "SD_DAT[0]" LOC = P65; +NET "SD_DAT[1]" LOC = P79; +NET "SD_DAT[2]" LOC = P62; +NET "SD_DAT[3]" LOC = P63; + +# PlanAhead Generated IO constraints + +NET "SD_CLK" IOSTANDARD = LVCMOS33; +NET "SD_CMD" IOSTANDARD = LVCMOS33; +NET "SD_DAT[0]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[1]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[2]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[3]" IOSTANDARD = LVCMOS33; + +NET "SNES_SYSCLK" LOC = P180; +NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33; + +NET "RAM_DATA[0]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[0]" DRIVE = 8; +NET "RAM_DATA[0]" LOC = P26; +NET "RAM_DATA[1]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[1]" DRIVE = 8; +NET "RAM_DATA[1]" LOC = P22; +NET "RAM_DATA[2]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[2]" DRIVE = 8; +NET "RAM_DATA[2]" LOC = P20; +NET "RAM_DATA[3]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[3]" DRIVE = 8; +NET "RAM_DATA[3]" LOC = P19; +NET "RAM_DATA[4]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[4]" DRIVE = 8; +NET "RAM_DATA[4]" LOC = P21; +NET "RAM_DATA[5]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[5]" DRIVE = 8; +NET "RAM_DATA[5]" LOC = P24; +NET "RAM_DATA[6]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[6]" DRIVE = 8; +NET "RAM_DATA[6]" LOC = P27; +NET "RAM_DATA[7]" IOSTANDARD = LVCMOS33; +NET "RAM_DATA[7]" DRIVE = 8; +NET "RAM_DATA[7]" LOC = P29; + +NET "RAM_OE" IOSTANDARD = LVCMOS33; +NET "RAM_OE" DRIVE = 8; +NET "RAM_OE" LOC = P36; +NET "RAM_WE" IOSTANDARD = LVCMOS33; +NET "RAM_WE" DRIVE = 8; +NET "RAM_WE" LOC = P50; + +NET "RAM_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[0]" DRIVE = 8; +NET "RAM_ADDR[0]" LOC = P28; +NET "RAM_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[1]" DRIVE = 8; +NET "RAM_ADDR[1]" LOC = P31; +NET "RAM_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[2]" DRIVE = 8; +NET "RAM_ADDR[2]" LOC = P33; +NET "RAM_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[3]" DRIVE = 8; +NET "RAM_ADDR[3]" LOC = P35; +NET "RAM_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[4]" DRIVE = 8; +NET "RAM_ADDR[4]" LOC = P37; +NET "RAM_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[5]" DRIVE = 8; +NET "RAM_ADDR[5]" LOC = P40; +NET "RAM_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[6]" DRIVE = 8; +NET "RAM_ADDR[6]" LOC = P43; +NET "RAM_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[7]" DRIVE = 8; +NET "RAM_ADDR[7]" LOC = P45; +NET "RAM_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[8]" DRIVE = 8; +NET "RAM_ADDR[8]" LOC = P44; +NET "RAM_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[9]" DRIVE = 8; +NET "RAM_ADDR[9]" LOC = P42; +NET "RAM_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[10]" DRIVE = 8; +NET "RAM_ADDR[10]" LOC = P34; +NET "RAM_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[11]" DRIVE = 8; +NET "RAM_ADDR[11]" LOC = P39; +NET "RAM_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[12]" DRIVE = 8; +NET "RAM_ADDR[12]" LOC = P48; +NET "RAM_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[13]" DRIVE = 8; +NET "RAM_ADDR[13]" LOC = P46; +NET "RAM_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[14]" DRIVE = 8; +NET "RAM_ADDR[14]" LOC = P51; +NET "RAM_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[15]" DRIVE = 8; +NET "RAM_ADDR[15]" LOC = P58; +NET "RAM_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[16]" DRIVE = 8; +NET "RAM_ADDR[16]" LOC = P57; +NET "RAM_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[17]" DRIVE = 8; +NET "RAM_ADDR[17]" LOC = P61; +NET "RAM_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "RAM_ADDR[18]" DRIVE = 8; +NET "RAM_ADDR[18]" LOC = P52; diff --git a/verilog/sd2snes_test/main.v b/verilog/sd2snes_test/main.v new file mode 100644 index 0000000..e1adc44 --- /dev/null +++ b/verilog/sd2snes_test/main.v @@ -0,0 +1,596 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: main +// Project Name: +// Target Devices: +// Tool versions: +// Description: Master Control FSM +// +// Dependencies: address +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module main( + /* input clock */ + input CLKIN, + + /* SNES signals */ + input [23:0] SNES_ADDR, + input SNES_READ, + input SNES_WRITE, + input SNES_CS, + inout [7:0] SNES_DATA, + input SNES_CPU_CLK, + input SNES_REFRESH, + output SNES_IRQ, + output SNES_DATABUS_OE, + output SNES_DATABUS_DIR, + input SNES_SYSCLK, + + input [7:0] SNES_PA, + input SNES_PARD, + input SNES_PAWR, + + /* SRAM signals */ + /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */ + inout [15:0] ROM_DATA, + output [22:0] ROM_ADDR, + output ROM_CE, + output ROM_OE, + output ROM_WE, + output ROM_BHE, + output ROM_BLE, + + /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */ + inout [7:0] RAM_DATA, + output [18:0] RAM_ADDR, + output RAM_OE, + output RAM_WE, + + /* MCU signals */ + input SPI_MOSI, + inout SPI_MISO, + input SPI_SS, + inout SPI_SCK, + input MCU_OVR, + output MCU_RDY, + + output DAC_MCLK, + output DAC_LRCK, + output DAC_SDOUT, + + /* SD signals */ + input [3:0] SD_DAT, + inout SD_CMD, + inout SD_CLK, + + /* debug */ + output p113_out +); + +wire [31:0] snes_sysclk_freq; +wire [31:0] snes_read_freq; +wire [31:0] snes_write_freq; +wire [31:0] snes_pard_freq; +wire [31:0] snes_pawr_freq; +wire [31:0] snes_refresh_freq; +wire [31:0] snes_cpuclk_freq; +wire [31:0] snes_romsel_freq; + +clk_test snes_clk_test ( + .clk(CLK2), + .sysclk(SNES_SYSCLK), + .read(SNES_READ), + .write(SNES_WRITE), + .pard(SNES_PARD), + .pawr(SNES_PAWR), + .refresh(SNES_REFRESH), + .cpuclk(SNES_CPU_CLK), + .romsel(SNES_CS), + .snes_sysclk_freq(snes_sysclk_freq), + .snes_read_freq(snes_read_freq), + .snes_write_freq(snes_write_freq), + .snes_pard_freq(snes_pard_freq), + .snes_pawr_freq(snes_pawr_freq), + .snes_refresh_freq(snes_refresh_freq), + .snes_cpuclk_freq(snes_cpuclk_freq), + .snes_romsel_freq(snes_romsel_freq) +); + +wire [7:0] spi_cmd_data; +wire [7:0] spi_param_data; +wire [7:0] spi_input_data; +wire [31:0] spi_byte_cnt; +wire [2:0] spi_bit_cnt; +wire [23:0] MCU_ADDR; +wire [2:0] MAPPER; +wire [23:0] SAVERAM_MASK; +wire [23:0] ROM_MASK; +wire [7:0] SD_DMA_SRAM_DATA; +wire [1:0] SD_DMA_TGT; +wire [10:0] SD_DMA_PARTIAL_START; +wire [10:0] SD_DMA_PARTIAL_END; + +wire [10:0] dac_addr; + +wire [23:0] ram0_addr; +wire [18:0] ram1_addr; +wire [7:0] PA_addr; +wire [12:0] bram_addr; +wire ROM_ADDR0; + +sd_dma snes_sd_dma( + .CLK(CLK2), + .SD_DAT(SD_DAT), + .SD_CLK(SD_CLK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) +); + +wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)); + +dac snes_dac( + .clkin(CLK2), + .sysclk(SNES_SYSCLK), + .mclk(DAC_MCLK), + .lrck(DAC_LRCK), + .sdout(DAC_SDOUT), + .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1), + .pgm_address(dac_addr), + .pgm_data(SD_DMA_SRAM_DATA), + .DAC_STATUS(DAC_STATUS), + .play(dac_play), + .reset(dac_reset) +); + +spi snes_spi( + .clk(CLK2), + .MOSI(SPI_MOSI), + .MISO(SPI_MISO), + .SSEL(SPI_SS), + .SCK(SPI_SCK), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .endmessage(spi_endmessage), + .startmessage(spi_startmessage), + .input_data(spi_input_data), + .byte_cnt(spi_byte_cnt), + .bit_cnt(spi_bit_cnt) +); + +reg [7:0] MCU_DINr; +wire [7:0] MCU_DOUT; + +wire [7:0] mcu_bram_data_in; +wire [7:0] mcu_bram_data_out; +wire [12:0] mcu_bram_addr; + +mcu_cmd snes_mcu_cmd( + .clk(CLK2), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .mcu_mapper(MAPPER), + .mcu_write(MCU_WRITE), + .mcu_data_in(MCU_DINr), + .mcu_data_out(MCU_DOUT), + .spi_byte_cnt(spi_byte_cnt), + .spi_bit_cnt(spi_bit_cnt), + .spi_data_out(spi_input_data), + .addr_out(MCU_ADDR), + .saveram_mask_out(SAVERAM_MASK), + .rom_mask_out(ROM_MASK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_TGT(SD_DMA_TGT), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .dac_addr_out(dac_addr), + .DAC_STATUS(DAC_STATUS), +// .dac_volume_out(dac_volume), +// .dac_volume_latch_out(dac_vol_latch), + .dac_play_out(dac_play), + .dac_reset_out(dac_reset), + .featurebits_out(featurebits), + .mcu_rrq(MCU_RRQ), + .mcu_wrq(MCU_WRQ), + .mcu_rq_rdy(MCU_RDY), + .ramsel_out(MCU_RAMSEL), + .snes_sysclk_freq(snes_sysclk_freq), + .snes_read_freq(snes_read_freq), + .snes_write_freq(snes_write_freq), + .snes_pard_freq(snes_pard_freq), + .snes_pawr_freq(snes_pawr_freq), + .snes_refresh_freq(snes_refresh_freq), + .snes_cpuclk_freq(snes_cpuclk_freq), + .snes_romsel_freq(snes_romsel_freq), + .mcu_bram_addr(mcu_bram_addr), + .mcu_bram_data_in(mcu_bram_data_in), + .mcu_bram_data_out(mcu_bram_data_out), + .mcu_bram_we(mcu_bram_we) +); + +wire [7:0] DCM_STATUS; +// dcm1: dfs 4x +my_dcm snes_dcm( + .CLKIN(CLKIN), + .CLKFX(CLK2), + .LOCKED(DCM_LOCKED), + .RST(DCM_RST), + .STATUS(DCM_STATUS) +); + +assign DCM_RST=0; + +reg [5:0] SNES_READr; +reg [5:0] SNES_WRITEr; +reg [5:0] SNES_CPU_CLKr; + +wire SNES_RD_start = (SNES_READr == 6'b111110); +wire SNES_WR_start = (SNES_WRITEr == 6'b111110); +wire SNES_WR_rising = (SNES_WRITEr == 6'b000001); +wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); +wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); + +always @(posedge CLK2) begin + SNES_READr <= {SNES_READr[4:0], SNES_READ}; + SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; + SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK}; +end + +reg [7:0] ram0_bank; +initial ram0_bank = 8'h00; +reg ram0_linear; +initial ram0_linear = 1'b0; + +address snes_addr( + .CLK(CLK2), + .SNES_ADDR(SNES_ADDR), // requested address from SNES + .ram0_addr(ram0_addr), // Address to request from SRAM (active low) + .ram1_addr(ram1_addr), + .PA_addr(PA_addr), + .bram_addr(bram_addr), + .ram0_enable(ram0_enable), + .ram1_enable(ram1_enable), + .PA_enable(PA_enable), + .bram_enable(bram_enable), + .ram0_bank(ram0_bank), + .ram0_linear(ram0_linear), + .irq_enable(irq_enable), + .bank_enable(bank_enable), + .linear_enable(linear_enable) +); + +always @(posedge CLK2) begin + if(SNES_WR_rising && bank_enable) ram0_bank <= SNES_DATA; +end + +always @(posedge CLK2) begin + if(SNES_WR_rising && linear_enable) ram0_linear <= SNES_DATA[0]; +end + +reg [7:0] irq_count_r; +initial irq_count_r = 8'b0; +reg SNES_IRQr; +initial SNES_IRQr = 0; + +always @(posedge CLK2) begin + if(SNES_WR_rising & irq_enable) SNES_IRQr <= 1'b1; + else if(irq_count_r == 8'h00) SNES_IRQr <= 1'b0; +end + +always @(posedge CLK2) begin + if(SNES_WR_rising & irq_enable) irq_count_r <= 8'h01; + else irq_count_r <= irq_count_r + 1; +end + + +wire [7:0] bram_data_out; +bram test_bram ( + .clka(CLK2), // input clka + .wea(~SNES_WRITE & bram_enable), // input [0 : 0] wea + .addra(bram_addr), // input [12 : 0] addra + .dina(SNES_DATA), // input [7 : 0] dina + .douta(bram_data_out), // output [7 : 0] douta + .clkb(CLK2), // input clkb + .web(mcu_bram_we), // input [0 : 0] web + .addrb(mcu_bram_addr), // input [12 : 0] addrb + .dinb(mcu_bram_data_out), // input [7 : 0] dinb + .doutb(mcu_bram_data_in) // output [7 : 0] doutb +); +reg [1:0] SNES_PAWR_start_r; +always @(posedge CLK2) SNES_PAWR_start_r <= {SNES_PAWR_start_r[0], SNES_PAWR}; +wire SNES_PAWR_start = (SNES_PAWR_start_r == 2'b01); +wire [7:0] PA_data_out; +PA test_PA ( + .clka(CLK2), // input clka + .wea(SNES_PAWR_start), // input [0 : 0] wea + .addra(SNES_PA), // input [7 : 0] addra + .dina(SNES_DATA), // input [7 : 0] dina + .clkb(CLK2), // input clkb + .addrb(PA_addr), // input [7 : 0] addrb + .doutb(PA_data_out) // output [7 : 0] doutb +); + +parameter MODE_SNES = 1'b0; +parameter MODE_MCU = 1'b1; + +parameter ST_IDLE = 18'b000000000000000001; +parameter ST_SNES_RD_ADDR = 18'b000000000000000010; +parameter ST_SNES_RD_WAIT = 18'b000000000000000100; +parameter ST_SNES_RD_END = 18'b000000000000001000; +parameter ST_SNES_WR_ADDR = 18'b000000000000010000; +parameter ST_SNES_WR_WAIT1= 18'b000000000000100000; +parameter ST_SNES_WR_DATA = 18'b000000000001000000; +parameter ST_SNES_WR_WAIT2= 18'b000000000010000000; +parameter ST_SNES_WR_END = 18'b000000000100000000; +parameter ST_MCU_RD_ADDR = 18'b000000001000000000; +parameter ST_MCU_RD_WAIT = 18'b000000010000000000; +parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000; +parameter ST_MCU_RD_END = 18'b000001000000000000; +parameter ST_MCU_WR_ADDR = 18'b000010000000000000; +parameter ST_MCU_WR_WAIT = 18'b000100000000000000; +parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000; +parameter ST_MCU_WR_END = 18'b010000000000000000; + +parameter ROM_RD_WAIT = 4'h4; +parameter ROM_RD_WAIT_MCU = 4'h6; +parameter ROM_WR_WAIT1 = 4'h2; +parameter ROM_WR_WAIT2 = 4'h3; +parameter ROM_WR_WAIT_MCU = 4'h6; + +reg [17:0] STATE; +initial STATE = ST_IDLE; + +reg [7:0] SNES_DINr; +reg [7:0] ROM_DOUTr; +reg [7:0] RAM_DOUTr; + +assign SNES_DATA = (!SNES_READ) ? (ram0_enable ? SNES_DINr + :ram1_enable ? SNES_DINr + :bram_enable ? bram_data_out + :PA_enable ? PA_data_out + :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ; + +reg [3:0] ST_MEM_DELAYr; +reg MCU_RD_PENDr; +reg MCU_WR_PENDr; +reg [23:0] ROM_ADDRr; +reg [18:0] RAM_ADDRr; +reg NEED_SNES_ADDRr; +always @(posedge CLK2) begin + if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1; + else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0; +end + +wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr; + +assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? ram0_addr[23:1] : ROM_ADDRr[23:1]; +assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0]; + +assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr; + +reg ROM_WEr; +initial ROM_WEr = 1'b1; + +reg RAM_WEr; +initial RAM_WEr = 1'b1; + +reg RQ_MCU_RDYr; +initial RQ_MCU_RDYr = 1'b1; +assign MCU_RDY = RQ_MCU_RDYr; + +always @(posedge CLK2) begin + if(MCU_RRQ) begin + MCU_RD_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(MCU_WRQ) begin + MCU_WR_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin + MCU_RD_PENDr <= 1'b0; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; + end +end + +reg snes_wr_cycle; +wire ram_enable = ram0_enable | ram1_enable; +always @(posedge CLK2) begin + if(ram_enable & SNES_cycle_start & ~SNES_WR_start) begin + STATE <= ST_SNES_RD_ADDR; + end else if(ram_enable & SNES_WR_start) begin + snes_wr_cycle <= 1'b1; + STATE <= ST_SNES_WR_ADDR; + end else begin + case(STATE) + ST_IDLE: begin + if(ram0_enable) ROM_ADDRr <= ram0_addr; + if(ram1_enable) RAM_ADDRr <= ram1_addr; + if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; + else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; + else STATE <= ST_IDLE; + end + ST_SNES_RD_ADDR: begin + STATE <= ST_SNES_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT; + end + ST_SNES_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; + else STATE <= ST_SNES_RD_WAIT; + if(ram0_enable) begin + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end else if(ram1_enable) begin + SNES_DINr <= RAM_DATA[7:0]; + end + end + ST_SNES_RD_END: begin + STATE <= ST_IDLE; + if(ram0_enable) begin + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end else if(ram1_enable) begin + SNES_DINr <= RAM_DATA[7:0]; + end + end + ST_SNES_WR_ADDR: begin + if(ram0_enable) ROM_WEr <= 1'b0; + if(ram1_enable) RAM_WEr <= 1'b0; + STATE <= ST_SNES_WR_WAIT1; + ST_MEM_DELAYr <= ROM_WR_WAIT1; + end + ST_SNES_WR_WAIT1: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; + else STATE <= ST_SNES_WR_WAIT1; + end + ST_SNES_WR_DATA: begin + if(ram0_enable) ROM_DOUTr <= SNES_DATA; + if(ram1_enable) RAM_DOUTr <= SNES_DATA; + ST_MEM_DELAYr <= ROM_WR_WAIT2; + STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; + else STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_END: begin + STATE <= ST_IDLE; + ROM_WEr <= 1'b1; + RAM_WEr <= 1'b1; + snes_wr_cycle <= 1'b0; + end + ST_MCU_RD_ADDR: begin + if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR; + else RAM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; + end + ST_MCU_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_RD_WAIT; + if(MCU_RAMSEL == 1'b0) begin + if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; + else MCU_DINr <= ROM_DATA[15:8]; + end else MCU_DINr <= RAM_DATA; + end + ST_MCU_RD_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_END; + end else STATE <= ST_MCU_RD_WAIT2; + end + ST_MCU_RD_END: begin + STATE <= ST_IDLE; + end + ST_MCU_WR_ADDR: begin + if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR; + else RAM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_WR_WAIT; + ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; + if(MCU_RAMSEL == 1'b0) ROM_DOUTr <= MCU_DOUT; + else RAM_DOUTr <= MCU_DOUT; + if(MCU_RAMSEL == 1'b0) + ROM_WEr <= 1'b0; + else if(MCU_RAMSEL == 1'b1) + RAM_WEr <= 1'b0; + end + ST_MCU_WR_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + ROM_WEr <= 1'b1; + RAM_WEr <= 1'b1; + STATE <= ST_MCU_WR_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else begin + STATE <= ST_MCU_WR_WAIT; + end + end + ST_MCU_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_WR_END; + end else STATE <= ST_MCU_WR_WAIT2; + end + ST_MCU_WR_END: begin + STATE <= ST_IDLE; + end + endcase + end +end + +assign ROM_DATA[7:0] = ROM_ADDR0 + ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ) + :8'bZ; + +assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ + :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ); + +assign RAM_DATA = !RAM_WE ? RAM_DOUTr : 8'bZ; + +assign ROM_WE = SD_DMA_TO_ROM + ?MCU_WRITE + :ROM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram0_enable)); + +assign RAM_WE = RAM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram1_enable)); + +assign RAM_OE = 1'b0; + +// OE always active. Overridden by WE when needed. +assign ROM_OE = 1'b0; + +assign ROM_CE = 1'b0; + +assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0; +assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; + +assign SNES_DATABUS_OE = PA_enable ? 1'b0 + : bram_enable ? 1'b0 + : (~SNES_PAWR & SNES_READ) ? 1'b0 + : SNES_CS ? SNES_WRITE + :((SNES_CS) + |(!ram0_enable & !ram1_enable) + |(SNES_READ & SNES_WRITE) + ); + +assign SNES_DATABUS_DIR = ~SNES_READ ? 1'b1 : 1'b0; + +assign IRQ_DIR = 1'b0; +assign SNES_IRQ = SNES_IRQr; + +assign p113_out = 1'b0; + +endmodule diff --git a/verilog/sd2snes_test/mcu_cmd.v b/verilog/sd2snes_test/mcu_cmd.v new file mode 100644 index 0000000..c5e2bb7 --- /dev/null +++ b/verilog/sd2snes_test/mcu_cmd.v @@ -0,0 +1,618 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:57:50 08/25/2009 +// Design Name: +// Module Name: mcu_cmd +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mcu_cmd( + input clk, + input cmd_ready, + input param_ready, + input [7:0] cmd_data, + input [7:0] param_data, + output [2:0] mcu_mapper, + output mcu_rrq, + output mcu_write, + output mcu_wrq, + input mcu_rq_rdy, + output [7:0] mcu_data_out, + input [7:0] mcu_data_in, + output [7:0] spi_data_out, + input [31:0] spi_byte_cnt, + input [2:0] spi_bit_cnt, + output [23:0] addr_out, + output [23:0] saveram_mask_out, + output [23:0] rom_mask_out, + output reg ramsel_out, + + // SD "DMA" extension + output SD_DMA_EN, + input SD_DMA_STATUS, + input SD_DMA_NEXTADDR, + input [7:0] SD_DMA_SRAM_DATA, + input SD_DMA_SRAM_WE, + output [1:0] SD_DMA_TGT, + output SD_DMA_PARTIAL, + output [10:0] SD_DMA_PARTIAL_START, + output [10:0] SD_DMA_PARTIAL_END, + + // DAC + output [10:0] dac_addr_out, + input DAC_STATUS, + output dac_play_out, + output dac_reset_out, + + // MSU data + output [13:0] msu_addr_out, + input [6:0] MSU_STATUS, + output [5:0] msu_status_reset_out, + output [5:0] msu_status_set_out, + output msu_status_reset_we, + input [31:0] msu_addressrq, + input [15:0] msu_trackrq, + input [7:0] msu_volumerq, + output [13:0] msu_ptr_out, + output msu_reset_out, + + // BS-X + output [7:0] bsx_regs_reset_out, + output [7:0] bsx_regs_set_out, + output bsx_regs_reset_we, + + // generic RTC + output [55:0] rtc_data_out, + output rtc_pgm_we, + + // S-RTC + output srtc_reset, + + // uPD77C25 + output reg [23:0] dspx_pgm_data_out, + output reg [10:0] dspx_pgm_addr_out, + output reg dspx_pgm_we_out, + + output reg [15:0] dspx_dat_data_out, + output reg [10:0] dspx_dat_addr_out, + output reg dspx_dat_we_out, + + output reg dspx_reset_out, + + // feature enable + output reg [3:0] featurebits_out, + + // SNES control signal/clock freqs + + input [31:0] snes_cpuclk_freq, + input [31:0] snes_sysclk_freq, + input [31:0] snes_read_freq, + input [31:0] snes_write_freq, + input [31:0] snes_pard_freq, + input [31:0] snes_pawr_freq, + input [31:0] snes_refresh_freq, + input [31:0] snes_romsel_freq, + + output reg [12:0] mcu_bram_addr, + input [7:0] mcu_bram_data_in, + output reg [7:0] mcu_bram_data_out, + output reg mcu_bram_we + +); + +initial begin + dspx_pgm_addr_out = 11'b00000000000; + dspx_dat_addr_out = 10'b0000000000; + dspx_reset_out = 1'b1; + ramsel_out = 1'b0; +end + +reg [2:0] MAPPER_BUF; +reg [23:0] ADDR_OUT_BUF; +reg [10:0] DAC_ADDR_OUT_BUF; +reg [7:0] DAC_VOL_OUT_BUF; +reg DAC_VOL_LATCH_BUF; +reg DAC_PLAY_OUT_BUF; +reg DAC_RESET_OUT_BUF; +reg [13:0] MSU_ADDR_OUT_BUF; +reg [13:0] MSU_PTR_OUT_BUF; +reg [5:0] msu_status_set_out_buf; +reg [5:0] msu_status_reset_out_buf; +reg msu_status_reset_we_buf; +reg MSU_RESET_OUT_BUF; + +reg [7:0] bsx_regs_set_out_buf; +reg [7:0] bsx_regs_reset_out_buf; +reg bsx_regs_reset_we_buf; + +reg [55:0] rtc_data_out_buf; +reg rtc_pgm_we_buf; + +reg srtc_reset_buf; + +reg [31:0] SNES_SYSCLK_FREQ_BUF; + +reg [7:0] MCU_DATA_OUT_BUF; +reg [7:0] MCU_DATA_IN_BUF; +reg [1:0] mcu_nextaddr_buf; + +wire mcu_nextaddr; + +reg DAC_STATUSr; +reg SD_DMA_STATUSr; +reg [6:0] MSU_STATUSr; +always @(posedge clk) begin + DAC_STATUSr <= DAC_STATUS; + SD_DMA_STATUSr <= SD_DMA_STATUS; + MSU_STATUSr <= MSU_STATUS; +end + +reg SD_DMA_PARTIALr; +assign SD_DMA_PARTIAL = SD_DMA_PARTIALr; + +reg SD_DMA_ENr; +assign SD_DMA_EN = SD_DMA_ENr; + +reg [1:0] SD_DMA_TGTr; +assign SD_DMA_TGT = SD_DMA_TGTr; + +reg [10:0] SD_DMA_PARTIAL_STARTr; +reg [10:0] SD_DMA_PARTIAL_ENDr; +assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr; +assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr; + +reg [23:0] SAVERAM_MASK; +reg [23:0] ROM_MASK; + +assign spi_data_out = MCU_DATA_IN_BUF; + +initial begin + ADDR_OUT_BUF = 0; + DAC_ADDR_OUT_BUF = 0; + MSU_ADDR_OUT_BUF = 0; + SD_DMA_ENr = 0; + MAPPER_BUF = 1; +end + +// command interpretation +always @(posedge clk) begin + if (cmd_ready) begin + case (cmd_data[7:4]) + 4'h3: // select mapper + MAPPER_BUF <= cmd_data[2:0]; + 4'h4: begin// SD DMA + SD_DMA_ENr <= 1; + SD_DMA_TGTr <= cmd_data[1:0]; + SD_DMA_PARTIALr <= cmd_data[2]; + end + 4'h8: SD_DMA_TGTr <= 2'b00; + 4'h9: SD_DMA_TGTr <= cmd_data[1:0]; // not implemented + endcase + end else if (param_ready) begin + casex (cmd_data[7:0]) + 8'h1x: + case (spi_byte_cnt) + 32'h2: + ROM_MASK[23:16] <= param_data; + 32'h3: + ROM_MASK[15:8] <= param_data; + 32'h4: + ROM_MASK[7:0] <= param_data; + endcase + 8'h2x: + case (spi_byte_cnt) + 32'h2: + SAVERAM_MASK[23:16] <= param_data; + 32'h3: + SAVERAM_MASK[15:8] <= param_data; + 32'h4: + SAVERAM_MASK[7:0] <= param_data; + endcase + 8'h4x: + SD_DMA_ENr <= 1'b0; + 8'h6x: + case (spi_byte_cnt) + 32'h2: + SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0]; + 32'h3: + SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0}; + 32'h4: + SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0]; + 32'h5: + SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0}; + endcase + 8'h9x: + MCU_DATA_OUT_BUF <= param_data; + 8'he0: + case (spi_byte_cnt) + 32'h2: begin + msu_status_set_out_buf <= param_data[5:0]; + end + 32'h3: begin + msu_status_reset_out_buf <= param_data[5:0]; + msu_status_reset_we_buf <= 1'b1; + end + 32'h4: + msu_status_reset_we_buf <= 1'b0; + endcase + 8'he1: // pause DAC + DAC_PLAY_OUT_BUF <= 1'b0; + 8'he2: // resume DAC + DAC_PLAY_OUT_BUF <= 1'b1; + 8'he3: // reset DAC (set DAC playback address = 0) + case (spi_byte_cnt) + 32'h2: + DAC_RESET_OUT_BUF <= 1'b1; + 32'h3: + DAC_RESET_OUT_BUF <= 1'b0; + endcase + 8'he4: // reset MSU read buffer pointer + case (spi_byte_cnt) + 32'h2: begin + MSU_PTR_OUT_BUF[13:8] <= param_data[5:0]; + MSU_PTR_OUT_BUF[7:0] <= 8'h0; + end + 32'h3: begin + MSU_PTR_OUT_BUF[7:0] <= param_data; + MSU_RESET_OUT_BUF <= 1'b1; + end + 32'h4: + MSU_RESET_OUT_BUF <= 1'b0; + endcase + 8'he5: + case (spi_byte_cnt) + 32'h2: + rtc_data_out_buf[55:48] <= param_data; + 32'h3: + rtc_data_out_buf[47:40] <= param_data; + 32'h4: + rtc_data_out_buf[39:32] <= param_data; + 32'h5: + rtc_data_out_buf[31:24] <= param_data; + 32'h6: + rtc_data_out_buf[23:16] <= param_data; + 32'h7: + rtc_data_out_buf[15:8] <= param_data; + 32'h8: begin + rtc_data_out_buf[7:0] <= param_data; + rtc_pgm_we_buf <= 1'b1; + end + 32'h9: + rtc_pgm_we_buf <= 1'b0; + endcase + 8'he6: + case (spi_byte_cnt) + 32'h2: begin + bsx_regs_set_out_buf <= param_data[7:0]; + end + 32'h3: begin + bsx_regs_reset_out_buf <= param_data[7:0]; + bsx_regs_reset_we_buf <= 1'b1; + end + 32'h4: + bsx_regs_reset_we_buf <= 1'b0; + endcase + 8'he7: + case (spi_byte_cnt) + 32'h2: begin + srtc_reset_buf <= 1'b1; + end + 32'h3: begin + srtc_reset_buf <= 1'b0; + end + endcase + 8'he8: begin // set BRAM address + case (spi_byte_cnt) + 32'h2: mcu_bram_addr[12:8] <= param_data[4:0]; + 32'h3: mcu_bram_addr[7:0] <= param_data[7:0]; + endcase + end + 8'he9: begin // write BRAM + case (spi_byte_cnt) + 32'h2: begin + mcu_bram_data_out <= param_data; + mcu_bram_we <= 1'b1; + end + 32'h3: mcu_bram_we <= 1'b0; + 32'h4: mcu_bram_addr <= mcu_bram_addr + 1; + endcase + end + 8'hee: + ramsel_out <= param_data[0]; + 8'hf5: + if (spi_byte_cnt == 32'h3) mcu_bram_addr <= mcu_bram_addr + 1; + endcase + end +end + +always @(posedge clk) begin + if(param_ready && cmd_data[7:4] == 4'h0) begin + case (cmd_data[1:0]) + 2'b01: begin + case (spi_byte_cnt) + 32'h2: begin + DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0]; + DAC_ADDR_OUT_BUF[7:0] <= 8'b0; + end + 32'h3: + DAC_ADDR_OUT_BUF[7:0] <= param_data; + endcase + end + 2'b10: begin + case (spi_byte_cnt) + 32'h2: begin + MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0]; + MSU_ADDR_OUT_BUF[7:0] <= 8'b0; + end + 32'h3: + MSU_ADDR_OUT_BUF[7:0] <= param_data; + endcase + end + default: + case (spi_byte_cnt) + 32'h2: begin + ADDR_OUT_BUF[23:16] <= param_data; + ADDR_OUT_BUF[15:0] <= 16'b0; + end + 32'h3: + ADDR_OUT_BUF[15:8] <= param_data; + 32'h4: + ADDR_OUT_BUF[7:0] <= param_data; + endcase + endcase + end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) + && (cmd_data[3]) + && (spi_byte_cnt >= (32'h1+cmd_data[4]))) + ) + begin + case (SD_DMA_TGTr) + 2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1; + 2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1; + 2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1; + endcase + end +end + +// value fetch during last SPI bit +always @(posedge clk) begin + if (cmd_data[7:4] == 4'h8 && mcu_nextaddr_buf == 2'b01) + MCU_DATA_IN_BUF <= mcu_data_in; + else if (spi_bit_cnt == 3'h7) begin + if (cmd_data[7:0] == 8'hF0) + MCU_DATA_IN_BUF <= 8'hA5; + else if (cmd_data[7:0] == 8'hF1) + case (spi_byte_cnt[0]) + 1'b1: // buffer status (1st byte) + MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0}; + 1'b0: // control status (2nd byte) + MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]}; + endcase + else if (cmd_data[7:0] == 8'hF2) + case (spi_byte_cnt) + 32'h1: + MCU_DATA_IN_BUF <= msu_addressrq[31:24]; + 32'h2: + MCU_DATA_IN_BUF <= msu_addressrq[23:16]; + 32'h3: + MCU_DATA_IN_BUF <= msu_addressrq[15:8]; + 32'h4: + MCU_DATA_IN_BUF <= msu_addressrq[7:0]; + endcase + else if (cmd_data[7:0] == 8'hF3) + case (spi_byte_cnt) + 32'h1: + MCU_DATA_IN_BUF <= msu_trackrq[15:8]; + 32'h2: + MCU_DATA_IN_BUF <= msu_trackrq[7:0]; + endcase + else if (cmd_data[7:0] == 8'hF4) + MCU_DATA_IN_BUF <= msu_volumerq; + else if (cmd_data[7:0] == 8'hF5) + MCU_DATA_IN_BUF <= mcu_bram_data_in; + else if (cmd_data[7:0] == 8'hF7) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_romsel_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hF8) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_cpuclk_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hF9) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_read_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFA) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_write_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFB) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_pard_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFC) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_pawr_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFD) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_refresh_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFE) + case (spi_byte_cnt) + 32'h1: + SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq; + 32'h2: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24]; + 32'h3: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16]; + 32'h4: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8]; + 32'h5: + MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0]; + endcase + else if (cmd_data[7:0] == 8'hFF) + MCU_DATA_IN_BUF <= param_data; + end +end + +// nextaddr pulse generation +always @(posedge clk) begin + mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy}; +end + +parameter ST_RQ = 2'b01; +parameter ST_IDLE = 2'b10; + +reg [1:0] rrq_state; +initial rrq_state = ST_IDLE; +reg mcu_rrq_r; + +reg [1:0] wrq_state; +initial wrq_state = ST_IDLE; +reg mcu_wrq_r; + +always @(posedge clk) begin + case(rrq_state) + ST_IDLE: begin + if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin + mcu_rrq_r <= 1'b1; + rrq_state <= ST_RQ; + end else + rrq_state <= ST_IDLE; + end + ST_RQ: begin + mcu_rrq_r <= 1'b0; + rrq_state <= ST_IDLE; + end + endcase +end + +always @(posedge clk) begin + case(wrq_state) + ST_IDLE: begin + if(param_ready && cmd_data[7:4] == 4'h9) begin + mcu_wrq_r <= 1'b1; + wrq_state <= ST_RQ; + end else + wrq_state <= ST_IDLE; + end + ST_RQ: begin + mcu_wrq_r <= 1'b0; + wrq_state <= ST_IDLE; + end + endcase +end + +// trigger for nextaddr +assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01; + +assign mcu_rrq = mcu_rrq_r; +assign mcu_wrq = mcu_wrq_r; +assign mcu_write = SD_DMA_STATUS + ?(SD_DMA_TGTr == 2'b00 + ?SD_DMA_SRAM_WE + :1'b1 + ) + : 1'b1; + +assign addr_out = ADDR_OUT_BUF; +assign dac_addr_out = DAC_ADDR_OUT_BUF; +assign msu_addr_out = MSU_ADDR_OUT_BUF; +assign dac_play_out = DAC_PLAY_OUT_BUF; +assign dac_reset_out = DAC_RESET_OUT_BUF; +assign msu_status_reset_we = msu_status_reset_we_buf; +assign msu_status_reset_out = msu_status_reset_out_buf; +assign msu_status_set_out = msu_status_set_out_buf; +assign msu_reset_out = MSU_RESET_OUT_BUF; +assign msu_ptr_out = MSU_PTR_OUT_BUF; + +assign bsx_regs_reset_we = bsx_regs_reset_we_buf; +assign bsx_regs_reset_out = bsx_regs_reset_out_buf; +assign bsx_regs_set_out = bsx_regs_set_out_buf; + +assign rtc_data_out = rtc_data_out_buf; +assign rtc_pgm_we = rtc_pgm_we_buf; + +assign srtc_reset = srtc_reset_buf; + +assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF; +assign mcu_mapper = MAPPER_BUF; +assign rom_mask_out = ROM_MASK; +assign saveram_mask_out = SAVERAM_MASK; + +endmodule diff --git a/verilog/sd2snes_test/sd2snes_test.xise b/verilog/sd2snes_test/sd2snes_test.xise new file mode 100644 index 0000000..6c66fb1 --- /dev/null +++ b/verilog/sd2snes_test/sd2snes_test.xise @@ -0,0 +1,432 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_test/sd_dma.v b/verilog/sd2snes_test/sd_dma.v new file mode 100644 index 0000000..2137370 --- /dev/null +++ b/verilog/sd2snes_test/sd_dma.v @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:19:08 12/01/2010 +// Design Name: +// Module Name: sd_dma +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module sd_dma( + input [3:0] SD_DAT, + inout SD_CLK, + input CLK, + input SD_DMA_EN, + output SD_DMA_STATUS, + output SD_DMA_SRAM_WE, + output SD_DMA_NEXTADDR, + output [7:0] SD_DMA_SRAM_DATA, + input SD_DMA_PARTIAL, + input [10:0] SD_DMA_PARTIAL_START, + input [10:0] SD_DMA_PARTIAL_END +); + +reg [10:0] SD_DMA_STARTr; +reg [10:0] SD_DMA_ENDr; +reg SD_DMA_PARTIALr; +always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL; + +reg SD_DMA_DONEr; +reg[1:0] SD_DMA_DONEr2; +initial begin + SD_DMA_DONEr2 = 2'b00; + SD_DMA_DONEr = 1'b0; +end +always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr}; +wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01); + +reg [1:0] SD_DMA_ENr; +initial SD_DMA_ENr = 2'b00; +always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN}; +wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01); + +reg SD_DMA_STATUSr; +assign SD_DMA_STATUS = SD_DMA_STATUSr; + +// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit) +reg [10:0] cyclecnt; +initial cyclecnt = 11'd0; + +reg SD_DMA_SRAM_WEr; +initial SD_DMA_SRAM_WEr = 1'b1; +assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1; + +reg SD_DMA_NEXTADDRr; +assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0; + +reg[7:0] SD_DMA_SRAM_DATAr; +assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; + +// we have 4 internal cycles per SD clock, 8 per RAM byte write +reg [2:0] clkcnt; +initial clkcnt = 3'b000; +reg [1:0] SD_CLKr; +always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]}; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ; + +always @(posedge CLK) begin + if(SD_DMA_EN_rising) begin + SD_DMA_STATUSr <= 1'b1; + SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0); + SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024); + end + else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0; +end + +always @(posedge CLK) begin + if(cyclecnt == 1042) SD_DMA_DONEr <= 1; + else SD_DMA_DONEr <= 0; +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin + clkcnt <= 0; + end else begin + if(SD_DMA_STATUSr) begin + clkcnt <= clkcnt + 1; + end + end +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0; + else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1; +end + +// we have 8 clk cycles to complete one RAM write +// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte) +always @(posedge CLK) begin + if(SD_DMA_STATUSr) begin + case(clkcnt[2:0]) + 3'h0: begin + SD_DMA_SRAM_WEr <= 1'b1; + SD_DMA_SRAM_DATAr[7:4] <= SD_DAT; + if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1; + end + 3'h1: + SD_DMA_NEXTADDRr <= 1'b0; +// 3'h2: + 3'h3: + if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0; + 3'h4: + SD_DMA_SRAM_DATAr[3:0] <= SD_DAT; +// 3'h5: +// 3'h6: +// 3'h7: + endcase + end +end + +endmodule + diff --git a/verilog/sd2snes_test/spi.v b/verilog/sd2snes_test/spi.v new file mode 100644 index 0000000..cb6bf79 --- /dev/null +++ b/verilog/sd2snes_test/spi.v @@ -0,0 +1,113 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:16:09 07/10/2009 +// Design Name: +// Module Name: spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// + +////////////////////////////////////////////////////////////////////////////////// +module spi( + input clk, + input SCK, + input MOSI, + inout MISO, + input SSEL, + output cmd_ready, + output param_ready, + output [7:0] cmd_data, + output [7:0] param_data, + output endmessage, + output startmessage, + input [7:0] input_data, + output [31:0] byte_cnt, + output [2:0] bit_cnt +); + +reg [7:0] cmd_data_r; +reg [7:0] param_data_r; + +reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL}; +wire SSEL_active = ~SSELr[1]; // SSEL is active low +wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge +wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge +assign endmessage = SSEL_endmessage; +assign startmessage = SSEL_startmessage; + +// bit count for one SPI byte + byte count for the message +reg [2:0] bitcnt; +reg [31:0] byte_cnt_r; + +reg byte_received; // high when a byte has been received +reg [7:0] byte_data_received; + +assign bit_cnt = bitcnt; + +always @(posedge SCK) begin + if(SSEL) bitcnt <= 3'b000; + else begin + bitcnt <= bitcnt + 3'b001; + byte_data_received <= {byte_data_received[6:0], MOSI}; + end + if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1; + else byte_received <= 1'b0; +end + +reg [1:0] byte_received_r; +always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received}; +wire byte_received_sync = (byte_received_r == 2'b01); + +always @(posedge clk) begin + if(~SSEL_active) + byte_cnt_r <= 16'h0000; + else if(byte_received_sync) begin + byte_cnt_r <= byte_cnt_r + 16'h0001; + end +end + +reg [7:0] byte_data_sent; + +assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first + +reg cmd_ready_r; +reg param_ready_r; +reg cmd_ready_r2; +reg param_ready_r2; +assign cmd_ready = cmd_ready_r; +assign param_ready = param_ready_r; +assign cmd_data = cmd_data_r; +assign param_data = param_data_r; +assign byte_cnt = byte_cnt_r; + +always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0; +always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0; + +// fill registers +always @(posedge clk) begin + if (SSEL_startmessage) + cmd_data_r <= 8'h00; + else if(cmd_ready_r2) + cmd_data_r <= byte_data_received; + else if(param_ready_r2) + param_data_r <= byte_data_received; +end + +// delay ready signals by one clock +always @(posedge clk) begin + cmd_ready_r <= cmd_ready_r2; + param_ready_r <= param_ready_r2; +end + +endmodule From 20c2cdb961353d1475b582e51d710646524d1101 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 19 Dec 2011 22:29:19 +0100 Subject: [PATCH 38/66] Firmware/bootloader: add 'fresh' Makefile target (erase+program) --- src/bootldr/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/bootldr/Makefile b/src/bootldr/Makefile index aae0385..0788ac5 100644 --- a/src/bootldr/Makefile +++ b/src/bootldr/Makefile @@ -213,6 +213,8 @@ sym: $(TARGET).sym # utils/lpcchksum $(TARGET).bin +fresh: erase program + program: bin openocd -f openocd-usb.cfg -f lpc1754.cfg -f flash.cfg From 90b91583a12bbd210a97acfd754e8c9c0901b73f Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 19 Dec 2011 22:32:27 +0100 Subject: [PATCH 39/66] Firmware: use FatFS FASTSEEK option for MSU1 file access --- src/config | 6 +++--- src/config.h | 2 +- src/ffconf.h | 2 +- src/msu1.c | 11 +++++++++++ 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/config b/src/config index f1319e4..aa88b57 100644 --- a/src/config +++ b/src/config @@ -1,4 +1,4 @@ -CONFIG_VERSION=0.1.0 -#FWVER=000100 -CONFIG_FWVER=256 +CONFIG_VERSION=0.1.1 +#FWVER=000101 +CONFIG_FWVER=257 CONFIG_MCU_FOSC=12000000 diff --git a/src/config.h b/src/config.h index 6900ac2..03d5d0c 100644 --- a/src/config.h +++ b/src/config.h @@ -66,7 +66,7 @@ #define FPGA_MCU_RDY_BIT 9 #define QSORT_MAXELEM 2048 - +#define CLTBL_SIZE 100 #define SSP_REGS LPC_SSP0 #define SSP_PCLKREG PCLKSEL1 // 1: PCLKSEL0 diff --git a/src/ffconf.h b/src/ffconf.h index fb2757c..14551ed 100644 --- a/src/ffconf.h +++ b/src/ffconf.h @@ -48,7 +48,7 @@ /* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ -#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +#define _USE_FASTSEEK 1 /* 0:Disable or 1:Enable */ /* To enable fast seek feature, set _USE_FASTSEEK to 1. */ diff --git a/src/msu1.c b/src/msu1.c index 6dc298f..3e1e884 100644 --- a/src/msu1.c +++ b/src/msu1.c @@ -13,6 +13,9 @@ #include "smc.h" FIL msufile; +DWORD msu_cltbl[CLTBL_SIZE] IN_AHBRAM; +DWORD pcm_cltbl[CLTBL_SIZE] IN_AHBRAM; + extern snes_romprops_t romprops; int msu1_check_reset(void) { @@ -40,6 +43,11 @@ int msu1_check(uint8_t* filename) { printf("MSU datafile not found\n"); return 0; } + msufile.cltbl = msu_cltbl; + msu_cltbl[0] = CLTBL_SIZE; + if(f_lseek(&msufile, CREATE_LINKMAP)) { + printf("Error creating FF linkmap for MSU file!\n"); + } romprops.fpga_features |= FEAT_MSU1; return 1; } @@ -128,6 +136,9 @@ int msu1_loop() { strcpy(strrchr((char*)file_buf, (int)'.'), suffix); printf("filename: %s\n", file_buf); f_open(&file_handle, (const TCHAR*)file_buf, FA_READ); + file_handle.cltbl = pcm_cltbl; + pcm_cltbl[0] = CLTBL_SIZE; + f_lseek(&file_handle, CREATE_LINKMAP); f_lseek(&file_handle, 4L); f_read(&file_handle, &msu_loop_point, 4, &bytes_read); printf("loop point: %ld samples\n", msu_loop_point); From a7c1a29f109dcea12a0a62fc2eef1019bf323d52 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 24 Dec 2011 23:06:28 +0100 Subject: [PATCH 40/66] add changelog --- CHANGELOG | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 CHANGELOG diff --git a/CHANGELOG b/CHANGELOG new file mode 100644 index 0000000..1cbc8fc --- /dev/null +++ b/CHANGELOG @@ -0,0 +1,13 @@ +v0.1.1 +====== + + * initial public release + + +v0.1.1a (bugfix release) +======================== + + * Fixes: + - SuperCIC pair mode was erroneously enabled in firmware binary + - SNES menu crashed on empty database + From 1585032c5a4129f32ceab5c8e6f150cc768574ac Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 27 Dec 2011 01:56:24 +0100 Subject: [PATCH 41/66] PCB: Rev.E2 (replace elusive Micrel regulator) --- pcb/kicad/RevE/fpga.sch | 4 +- pcb/kicad/RevE/mcu.sch | 4 +- pcb/kicad/RevE/memory.sch | 6 +- pcb/kicad/RevE/pwr_misc.sch | 4 +- pcb/kicad/RevE/sd2snes.brd | 38 +- pcb/kicad/RevE/sd2snes.net | 6 +- pcb/kicad/RevE/sd2snes.sch | 4 +- pcb/kicad/RevE/snesslot.sch | 6 +- pcb/kicad/RevE2/fpga.sch | 1321 ++ pcb/kicad/RevE2/mcu.sch | 1193 ++ pcb/kicad/RevE2/memory.sch | 806 + pcb/kicad/RevE2/pwr_misc.sch | 1246 ++ pcb/kicad/RevE2/sd2snes.brd | 35370 ++++++++++++++++++++++++++++++++ pcb/kicad/RevE2/sd2snes.cmp | 1067 + pcb/kicad/RevE2/sd2snes.net | 3218 +++ pcb/kicad/RevE2/sd2snes.pro | 116 + pcb/kicad/RevE2/sd2snes.sch | 93 + pcb/kicad/RevE2/snesslot.sch | 2058 ++ pcb/kicad/libs/mypackages.mod | 676 +- pcb/kicad/libs/sdcard.bak | 27 +- pcb/kicad/libs/sdcard.mod | 21 +- 21 files changed, 47201 insertions(+), 83 deletions(-) create mode 100644 pcb/kicad/RevE2/fpga.sch create mode 100644 pcb/kicad/RevE2/mcu.sch create mode 100644 pcb/kicad/RevE2/memory.sch create mode 100644 pcb/kicad/RevE2/pwr_misc.sch create mode 100644 pcb/kicad/RevE2/sd2snes.brd create mode 100644 pcb/kicad/RevE2/sd2snes.cmp create mode 100644 pcb/kicad/RevE2/sd2snes.net create mode 100644 pcb/kicad/RevE2/sd2snes.pro create mode 100644 pcb/kicad/RevE2/sd2snes.sch create mode 100644 pcb/kicad/RevE2/snesslot.sch diff --git a/pcb/kicad/RevE/fpga.sch b/pcb/kicad/RevE/fpga.sch index 4cb6667..74ae85d 100644 --- a/pcb/kicad/RevE/fpga.sch +++ b/pcb/kicad/RevE/fpga.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:06 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A3 16535 11700 encoding utf-8 Sheet 6 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/mcu.sch b/pcb/kicad/RevE/mcu.sch index d1b28ad..2a84cdd 100644 --- a/pcb/kicad/RevE/mcu.sch +++ b/pcb/kicad/RevE/mcu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:06 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 4 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/memory.sch b/pcb/kicad/RevE/memory.sch index 664ae4d..44bc725 100644 --- a/pcb/kicad/RevE/memory.sch +++ b/pcb/kicad/RevE/memory.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:05 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 3 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" @@ -322,7 +322,7 @@ L R R513 U 1 1 4BF2FDAC P 9150 5700 F 0 "R513" V 9230 5700 50 0000 C CNN -F 1 "1k" V 9150 5700 50 0000 C CNN +F 1 "100k" V 9150 5700 50 0000 C CNN F 2 "SM0805_FIXEDMASK" H 9150 5700 60 0001 C CNN 1 9150 5700 1 0 0 -1 diff --git a/pcb/kicad/RevE/pwr_misc.sch b/pcb/kicad/RevE/pwr_misc.sch index babba70..858fa01 100644 --- a/pcb/kicad/RevE/pwr_misc.sch +++ b/pcb/kicad/RevE/pwr_misc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:06 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 5 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/sd2snes.brd b/pcb/kicad/RevE/sd2snes.brd index 00cff02..8a5401a 100644 --- a/pcb/kicad/RevE/sd2snes.brd +++ b/pcb/kicad/RevE/sd2snes.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Sat 12 Nov 2011 04:56:02 PM CET +PCBNEW-BOARD Version 1 date Fri 02 Dec 2011 02:55:43 PM CET # Created by Pcbnew(2011-07-02 BZR 2664)-stable @@ -9,8 +9,8 @@ Ly 1FFF8001 EnabledLayers 1FFF8001 Links 668 NoConn 0 -Di 36595 16630 77260 64790 -Ndraw 239 +Di 36595 16630 83771 64790 +Ndraw 241 Ntrack 4007 Nzone 0 BoardThickness 630 @@ -21,7 +21,7 @@ $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "sd2snes Mark II" -Date "12 nov 2011" +Date "2 dec 2011" Rev "C2" Comp "Maximilian Rehkopf" Comment1 "" @@ -7484,7 +7484,7 @@ AR /4B6ED75B/4BEECBCD Op 0 0 0 At SMD T0 0 600 320 320 2700 70 N V 21 N "C408" -T1 0 0 320 320 2700 70 N I 21 N "22p" +T1 0 0 320 320 2700 70 N I 21 N "10p" DS 200 350 650 350 75 21 DS -650 350 -200 350 75 21 DS 650 -350 200 -350 75 21 @@ -8708,7 +8708,7 @@ AR /4B6ED75B/4BEECBD1 Op 0 0 0 At SMD T0 -25 -600 320 320 900 70 N V 21 N "C409" -T1 0 0 320 320 900 70 N I 21 N "22p" +T1 0 0 320 320 900 70 N I 21 N "10p" DS 200 350 650 350 75 21 DS -650 350 -200 350 75 21 DS 650 -350 200 -350 75 21 @@ -12481,6 +12481,32 @@ Ne 0 "" Po 14331 3780 $EndPAD $EndMODULE SNESCART_EXT2 +$COTATION +Ge 0 24 0 +Va 32677 +Te "83.000 mm" +Po 81111 38031 600 800 120 2701 1 +Sb 0 80471 21693 80471 54370 120 +Sd 0 65630 54370 81751 54370 120 +Sg 0 65630 21693 81751 21693 120 +S1 0 80471 54370 80241 53927 120 +S2 0 80471 54370 80701 53927 120 +S3 0 80471 21693 80241 22136 120 +S4 0 80471 21693 80701 22136 120 +$endCOTATION +$COTATION +Ge 0 24 0 +Va 40000 +Te "101.600 mm" +Po 57165 59419 600 800 120 0 1 +Sb 0 37165 58779 77165 58779 120 +Sd 0 77165 34606 77165 60059 120 +Sg 0 37165 34606 37165 60059 120 +S1 0 77165 58779 76722 59009 120 +S2 0 77165 58779 76722 58549 120 +S3 0 37165 58779 37608 59009 120 +S4 0 37165 58779 37608 58549 120 +$endCOTATION $TEXTPCB Te "USE_BATT" Po 46575 27525 320 320 80 0 diff --git a/pcb/kicad/RevE/sd2snes.net b/pcb/kicad/RevE/sd2snes.net index 4505e7b..ee7ae04 100644 --- a/pcb/kicad/RevE/sd2snes.net +++ b/pcb/kicad/RevE/sd2snes.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Fri 02 Dec 2011 09:50:17 AM CET +# EESchema Netlist Version 1.1 created Fri 09 Dec 2011 10:46:12 PM CET ( ( /4B6E16F2/4D97B45F $noname RA114 100 {Lib=R_PACK4} ( 1 N-000108 ) @@ -176,7 +176,7 @@ ( 1 SNES_IRQ_EN ) ( 2 N-000036 ) ) - ( /4B6E16F2/4C7EAEBF $noname R102 1k {Lib=R} + ( /4B6E16F2/4C7EAEBF $noname R102 100k {Lib=R} ( 1 N-000036 ) ( 2 GND ) ) @@ -489,7 +489,7 @@ ( 1 /Memory/SRAM_Vcc ) ( 2 /Memory/RAM_/CE ) ) - ( /4BAA6ABD/4BF2FDAC SM0805_FIXEDMASK R513 1k {Lib=R} + ( /4BAA6ABD/4BF2FDAC SM0805_FIXEDMASK R513 100k {Lib=R} ( 1 N-000344 ) ( 2 GND ) ) diff --git a/pcb/kicad/RevE/sd2snes.sch b/pcb/kicad/RevE/sd2snes.sch index e6ce0e2..731b674 100644 --- a/pcb/kicad/RevE/sd2snes.sch +++ b/pcb/kicad/RevE/sd2snes.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:05 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A4 11700 8267 encoding utf-8 Sheet 1 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "E" Comp "Maximilian Rehkopf" Comment1 "" diff --git a/pcb/kicad/RevE/snesslot.sch b/pcb/kicad/RevE/snesslot.sch index a487e76..e53e4d2 100644 --- a/pcb/kicad/RevE/snesslot.sch +++ b/pcb/kicad/RevE/snesslot.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 02 Dec 2011 09:50:04 AM CET +EESchema Schematic File Version 2 date Fri 09 Dec 2011 10:46:05 PM CET LIBS:power LIBS:device LIBS:transistors @@ -47,7 +47,7 @@ $Descr A3 16535 11700 encoding utf-8 Sheet 2 6 Title "sd2snes Mark II" -Date "2 dec 2011" +Date "9 dec 2011" Rev "C" Comp "Maximilian Rehkopf" Comment1 "" @@ -1125,7 +1125,7 @@ L R R102 U 1 1 4C7EAEBF P 6850 8600 F 0 "R102" V 6930 8600 50 0000 C CNN -F 1 "1k" V 6850 8600 50 0000 C CNN +F 1 "100k" V 6850 8600 50 0000 C CNN 1 6850 8600 1 0 0 -1 $EndComp diff --git a/pcb/kicad/RevE2/fpga.sch b/pcb/kicad/RevE2/fpga.sch new file mode 100644 index 0000000..d741da2 --- /dev/null +++ b/pcb/kicad/RevE2/fpga.sch @@ -0,0 +1,1321 @@ +EESchema Schematic File Version 2 date Mon 26 Dec 2011 09:56:14 PM CET +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:snescart +LIBS:misc-74 +LIBS:vreg +LIBS:lpc1754 +LIBS:sd_card +LIBS:cy62148ev30 +LIBS:mt45w8mw16 +LIBS:cs4344 +LIBS:double_sch_kcom +LIBS:usb_minib +LIBS:mic23250 +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11700 +encoding utf-8 +Sheet 6 6 +Title "sd2snes Mark II" +Date "26 dec 2011" +Rev "E2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 3400 10950 +Wire Wire Line + 3650 10850 3650 10950 +Wire Wire Line + 3650 10950 650 10950 +Wire Wire Line + 6400 10850 6400 10950 +Connection ~ 3150 10950 +Wire Wire Line + 3400 10950 3400 10850 +Connection ~ 2900 10950 +Wire Wire Line + 3150 10950 3150 10850 +Connection ~ 5100 10950 +Wire Wire Line + 5350 10850 5350 10950 +Wire Wire Line + 5350 10950 4100 10950 +Connection ~ 2650 10950 +Wire Wire Line + 2900 10950 2900 10850 +Connection ~ 2400 10950 +Wire Wire Line + 2650 10950 2650 10850 +Connection ~ 4850 10950 +Wire Wire Line + 5100 10950 5100 10850 +Wire Wire Line + 12000 9350 10500 9350 +Wire Wire Line + 6200 7100 4600 7100 +Connection ~ 6150 10950 +Wire Wire Line + 6400 10950 5650 10950 +Connection ~ 6150 10350 +Wire Wire Line + 6150 10350 6150 10450 +Wire Wire Line + 5800 3800 6200 3800 +Wire Wire Line + 10500 5650 10900 5650 +Wire Wire Line + 10500 5550 10900 5550 +Wire Wire Line + 10500 5450 10900 5450 +Wire Wire Line + 10500 5350 10900 5350 +Wire Wire Line + 10500 5250 10900 5250 +Wire Wire Line + 10500 5150 10900 5150 +Wire Wire Line + 10500 5050 10900 5050 +Wire Wire Line + 10500 4950 10900 4950 +Wire Wire Line + 10500 4850 10900 4850 +Wire Wire Line + 10500 4750 10900 4750 +Wire Wire Line + 10500 4650 10900 4650 +Wire Wire Line + 10500 4550 10900 4550 +Wire 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Line + 6400 10350 6400 10450 +Wire Wire Line + 650 10350 3650 10350 +Wire Wire Line + 3650 10350 3650 10450 +Connection ~ 3400 10350 +$Comp +L C C234 +U 1 1 4D2F566A +P 3650 10650 +F 0 "C234" H 3700 10750 50 0000 L CNN +F 1 "100n" H 3700 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3650 10650 60 0001 C CNN + 1 3650 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C233 +U 1 1 4D2F497B +P 3400 10650 +F 0 "C233" H 3450 10750 50 0000 L CNN +F 1 "100n" H 3450 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3400 10650 60 0001 C CNN + 1 3400 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C232 +U 1 1 4D2F4979 +P 3150 10650 +F 0 "C232" H 3200 10750 50 0000 L CNN +F 1 "100n" H 3200 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3150 10650 60 0001 C CNN + 1 3150 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C215 +U 1 1 4D2F4480 +P 5350 10650 +F 0 "C215" H 5400 10750 50 0000 L CNN +F 1 "100n" H 5400 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 5350 10650 60 0001 C CNN + 1 5350 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C231 +U 1 1 4D2F4344 +P 2900 10650 +F 0 "C231" H 2950 10750 50 0000 L CNN +F 1 "100n" H 2950 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 2900 10650 60 0001 C CNN + 1 2900 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C209 +U 1 1 4D2F4312 +P 2650 10650 +F 0 "C209" H 2700 10750 50 0000 L CNN +F 1 "100n" H 2700 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 2650 10650 60 0001 C CNN + 1 2650 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C214 +U 1 1 4D252B5C +P 5100 10650 +F 0 "C214" H 5150 10750 50 0000 L CNN +F 1 "100n" H 5150 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 5100 10650 60 0001 C CNN + 1 5100 10650 + 1 0 0 -1 +$EndComp +$Comp +L CONN_1 P113 +U 1 1 4C7FF87E +P 12150 9350 +F 0 "P113" H 12230 9350 40 0000 L CNN +F 1 "CONN_1" H 12150 9405 30 0001 C CNN + 1 12150 9350 + 1 0 0 -1 +$EndComp +Text GLabel 11350 9250 2 50 Output ~ 0 +SNES_IRQ_EN +Text GLabel 4600 8400 0 50 BiDi ~ 0 +SD_DAT1 +Text GLabel 4600 7100 0 50 BiDi ~ 0 +SD_DAT2 +Text Notes 11850 10450 0 500 ~ 100 +FPGA +Text Notes 12800 8150 1 50 ~ 0 +SNES A+B bus +Text Notes 11800 4500 1 50 ~ 0 +70ns PSRAM bus +Text Notes 4000 5600 1 50 ~ 0 +45ns SRAM bus +Text Notes 2900 7400 0 50 ~ 0 +SD bus; shared with MCU +Text Notes 3100 7800 0 50 ~ 0 +SPI (MCU interface) +Text Notes 3700 8150 0 50 ~ 0 +DAC +$Comp +L C C224 +U 1 1 4BF5A441 +P 6400 10650 +F 0 "C224" H 6450 10750 50 0000 L CNN +F 1 "100n" H 6450 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 6400 10650 60 0001 C CNN + 1 6400 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C223 +U 1 1 4BF5A43F +P 6150 10650 +F 0 "C223" H 6200 10750 50 0000 L CNN +F 1 "100n" H 6200 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 6150 10650 60 0001 C CNN + 1 6150 10650 + 1 0 0 -1 +$EndComp +Text GLabel 5650 2200 0 50 Input ~ 0 +CCLK +Text GLabel 5650 2100 0 50 Output ~ 0 +DONE +Text GLabel 5650 1900 0 50 Input ~ 0 +PROG_B +Text GLabel 5800 6000 0 50 Output ~ 0 +RAM_A8 +Text GLabel 5800 4500 0 50 BiDi ~ 0 +RAM_DQ0 +Text GLabel 5800 5900 0 50 Output ~ 0 +RAM_A6 +Text GLabel 5800 6100 0 50 Output ~ 0 +RAM_A7 +Text GLabel 5800 5300 0 50 Output ~ 0 +RAM_A3 +Text GLabel 5800 5500 0 50 Output ~ 0 +RAM_A4 +Text GLabel 5800 6400 0 50 Output ~ 0 +RAM_/WE +Text GLabel 5800 5000 0 50 Output ~ 0 +RAM_A1 +Text GLabel 5800 5100 0 50 Output ~ 0 +RAM_A2 +Text GLabel 5800 4800 0 50 Output ~ 0 +RAM_A0 +Text GLabel 5800 4300 0 50 BiDi ~ 0 +RAM_DQ1 +Text GLabel 5800 4200 0 50 BiDi ~ 0 +RAM_DQ4 +Text GLabel 5800 4400 0 50 BiDi ~ 0 +RAM_DQ5 +Text GLabel 5800 5700 0 50 Output ~ 0 +RAM_A5 +Text GLabel 5800 7000 0 50 Output ~ 0 +RAM_A17 +Text GLabel 5800 4600 0 50 BiDi ~ 0 +RAM_DQ6 +Text GLabel 5800 6600 0 50 Output ~ 0 +RAM_A18 +Text GLabel 5800 4900 0 50 BiDi ~ 0 +RAM_DQ7 +Text GLabel 5800 4100 0 50 BiDi ~ 0 +RAM_DQ2 +Text GLabel 5800 5800 0 50 Output ~ 0 +RAM_A9 +Text GLabel 5800 5400 0 50 Output ~ 0 +RAM_/OE +Text GLabel 5800 5200 0 50 Output ~ 0 +RAM_A10 +Text GLabel 5800 5600 0 50 Output ~ 0 +RAM_A11 +Text GLabel 5800 6800 0 50 Output ~ 0 +RAM_A16 +Text GLabel 5800 6300 0 50 Output ~ 0 +RAM_A12 +Text GLabel 5800 6900 0 50 Output ~ 0 +RAM_A15 +Text GLabel 5800 6200 0 50 Output ~ 0 +RAM_A13 +Text GLabel 5800 4000 0 50 BiDi ~ 0 +RAM_DQ3 +Text GLabel 5800 6500 0 50 Output ~ 0 +RAM_A14 +Text GLabel 5800 3900 0 50 Output ~ 0 +ROM_A5 +Text GLabel 5800 3800 0 50 BiDi ~ 0 +ROM_DQ8 +Text GLabel 5800 3700 0 50 BiDi ~ 0 +ROM_DQ10 +Text GLabel 5800 3600 0 50 BiDi ~ 0 +ROM_DQ9 +Text GLabel 5800 3500 0 50 BiDi ~ 0 +ROM_DQ11 +Text GLabel 5800 3400 0 50 Output ~ 0 +ROM_A17 +Text GLabel 5800 3300 0 50 BiDi ~ 0 +ROM_DQ12 +Text GLabel 5800 3200 0 50 BiDi ~ 0 +ROM_DQ14 +Text GLabel 5800 3100 0 50 BiDi ~ 0 +ROM_DQ13 +Text GLabel 5800 3000 0 50 BiDi ~ 0 +ROM_DQ15 +Text GLabel 5800 2900 0 50 Output ~ 0 +ROM_A19 +Text GLabel 5800 2800 0 50 Output ~ 0 +ROM_A18 +Text GLabel 5800 2700 0 50 Output ~ 0 +ROM_A12 +Text GLabel 10900 2650 2 50 Output ~ 0 +ROM_A8 +Text GLabel 10900 2750 2 50 Output ~ 0 +ROM_A9 +Text GLabel 10900 2850 2 50 Output ~ 0 +ROM_A21 +Text GLabel 10900 2950 2 50 Output ~ 0 +ROM_A14 +Text GLabel 10900 3050 2 50 Output ~ 0 +ROM_A16 +Text GLabel 10900 3150 2 50 Output ~ 0 +ROM_A22 +Text GLabel 10900 3250 2 50 Output ~ 0 +ROM_A10 +Text GLabel 10900 3350 2 50 Output ~ 0 +ROM_A11 +Text GLabel 10900 3450 2 50 Output ~ 0 +ROM_A13 +Text GLabel 10900 3550 2 50 Output ~ 0 +ROM_A20 +Text GLabel 10900 3650 2 50 Output ~ 0 +ROM_/WE +Text GLabel 10900 3750 2 50 BiDi ~ 0 +ROM_DQ7 +Text GLabel 10900 3850 2 50 BiDi ~ 0 +ROM_DQ5 +Text GLabel 10900 3950 2 50 BiDi ~ 0 +ROM_DQ6 +Text GLabel 10900 4050 2 50 Output ~ 0 +ROM_A15 +Text GLabel 10900 4150 2 50 BiDi ~ 0 +ROM_DQ4 +Text GLabel 10900 4350 2 50 BiDi ~ 0 +ROM_DQ3 +Text GLabel 10900 4450 2 50 BiDi ~ 0 +ROM_DQ2 +Text GLabel 10900 4650 2 50 BiDi ~ 0 +ROM_DQ1 +Text GLabel 10900 4750 2 50 BiDi ~ 0 +ROM_DQ0 +Text GLabel 10900 4850 2 50 Output ~ 0 +ROM_A6 +Text GLabel 10900 4950 2 50 Output ~ 0 +ROM_/CE +Text GLabel 10900 5050 2 50 Output ~ 0 +ROM_A2 +Text GLabel 10900 5150 2 50 Output ~ 0 +ROM_A4 +Text GLabel 10900 5250 2 50 Output ~ 0 +ROM_A1 +Text GLabel 10900 5350 2 50 Output ~ 0 +ROM_A7 +Text GLabel 10900 5450 2 50 Output ~ 0 +ROM_A0 +Text GLabel 10900 5550 2 50 Output ~ 0 +ROM_A3 +Text GLabel 10900 5650 2 50 Output ~ 0 +ROM_/OE +Text GLabel 10900 5750 2 50 Output ~ 0 +ROM_/UB +Text GLabel 11350 5950 2 50 Output ~ 0 +ROM_/LB +Text GLabel 4600 7400 0 50 BiDi ~ 0 +SD_DAT0 +Text GLabel 4600 7500 0 50 Output ~ 0 +SD_CMD +Text GLabel 4600 7300 0 50 Output ~ 0 +SD_CLK +Text GLabel 4600 7200 0 50 Output ~ 0 +SD_DAT3 +Text GLabel 4600 7800 0 50 Output ~ 0 +MCU_SPI_MISO +Text GLabel 4600 7900 0 50 Input ~ 0 +MCU_SPI_MOSI +Text GLabel 4600 7700 0 50 Input ~ 0 +MCU_SPI_SCK +Text GLabel 4600 7600 0 50 Input ~ 0 +MCU_SPI_SS +Text GLabel 4600 8000 0 50 Output ~ 0 +DAC_MCLK +Text GLabel 4600 8100 0 50 Output ~ 0 +DAC_LRCK +Text GLabel 4600 8200 0 50 Output ~ 0 +DAC_SDIN +Text GLabel 4600 9200 0 50 Input ~ 0 +DIN+MCU_/OVR +Text GLabel 4600 8700 0 50 Output ~ 0 +INIT_B+MCU_IRQ +Text GLabel 4600 8500 0 50 Input ~ 0 +FPGA_CLK +Text GLabel 5350 8600 0 50 Input ~ 0 +SNES_PA4 +Text GLabel 5350 8800 0 50 Input ~ 0 +SNES_PA5 +Text GLabel 5350 8900 0 50 Input ~ 0 +SNES_PA2 +Text GLabel 5350 9000 0 50 Input ~ 0 +SNES_PA3 +Text GLabel 5350 9100 0 50 Input ~ 0 +SNES_PA0 +Text GLabel 5350 9300 0 50 Input ~ 0 +SNES_PA1 +Text GLabel 5350 9500 0 50 Input ~ 0 +SNES_CPU_CLK +Text GLabel 5350 9400 0 50 Input ~ 0 +SNES_/WR +Text GLabel 5350 9600 0 50 BiDi ~ 0 +SNES_D3 +Text GLabel 5350 9700 0 50 BiDi ~ 0 +SNES_D7 +Text GLabel 5350 9800 0 50 BiDi ~ 0 +SNES_D2 +Text GLabel 5350 9900 0 50 BiDi ~ 0 +SNES_D6 +Text GLabel 5350 10000 0 50 BiDi ~ 0 +SNES_D1 +Text GLabel 11350 9850 2 50 BiDi ~ 0 +SNES_D5 +Text GLabel 11350 9750 2 50 BiDi ~ 0 +SNES_D0 +Text GLabel 11350 9650 2 50 BiDi ~ 0 +SNES_D4 +Text GLabel 11350 9450 2 50 Output ~ 0 +DATABUS_DIR +Text GLabel 11350 9550 2 50 Output ~ 0 +DATABUS_/OE +Text GLabel 11350 9150 2 50 Input ~ 0 +SNES_/RD +Text GLabel 11350 9050 2 50 Input ~ 0 +SNES_/ROMSEL +Text GLabel 11350 8950 2 50 Input ~ 0 +SNES_A23 +Text GLabel 11350 8850 2 50 Input ~ 0 +SNES_A0 +Text GLabel 11350 8750 2 50 Input ~ 0 +SNES_A22 +Text GLabel 11350 8650 2 50 Input ~ 0 +SNES_A1 +Text GLabel 11350 8550 2 50 Input ~ 0 +SNES_A21 +Text GLabel 11350 8450 2 50 Input ~ 0 +SNES_A2 +Text GLabel 11350 8350 2 50 Input ~ 0 +SNES_A20 +Text GLabel 11350 8250 2 50 Input ~ 0 +SNES_A3 +Text GLabel 11350 8150 2 50 Input ~ 0 +SNES_A19 +Text GLabel 11350 8050 2 50 Input ~ 0 +SNES_A4 +Text GLabel 11350 7950 2 50 Input ~ 0 +SNES_A18 +Text GLabel 11350 7750 2 50 Input ~ 0 +SNES_A5 +Text GLabel 11350 7650 2 50 Input ~ 0 +SNES_A17 +Text GLabel 11350 7550 2 50 Input ~ 0 +SNES_A6 +Text GLabel 11350 7450 2 50 Input ~ 0 +SNES_A16 +Text GLabel 11350 7350 2 50 Input ~ 0 +SNES_A7 +Text GLabel 11350 7250 2 50 Input ~ 0 +SNES_A15 +Text GLabel 11350 7150 2 50 Input ~ 0 +SNES_A8 +Text GLabel 11350 7050 2 50 Input ~ 0 +SNES_A14 +Text GLabel 11350 6950 2 50 Input ~ 0 +SNES_A9 +Text GLabel 11350 6850 2 50 Input ~ 0 +SNES_A13 +Text GLabel 11350 6750 2 50 Input ~ 0 +SNES_A10 +Text GLabel 11350 6650 2 50 Input ~ 0 +SNES_A12 +Text GLabel 11350 6550 2 50 Input ~ 0 +SNES_A11 +Text GLabel 11350 6450 2 50 Input ~ 0 +SNES_/PARD +Text GLabel 11350 6350 2 50 Input ~ 0 +SNES_/PAWR +Text GLabel 11350 6250 2 50 Input ~ 0 +SNES_PA6 +Text GLabel 11350 6150 2 50 Input ~ 0 +SNES_PA7 +Text GLabel 11350 6050 2 50 Input ~ 0 +SNES_REFRESH +Text GLabel 10900 4550 2 50 Input ~ 0 +SNES_SYS_CLK +$Comp +L GND #PWR0113 +U 1 1 4BADE94E +P 5800 2000 +F 0 "#PWR0113" H 5800 2000 30 0001 C CNN +F 1 "GND" H 5800 1930 30 0001 C CNN + 1 5800 2000 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR0114 +U 1 1 4BADE8CE +P 8450 10900 +F 0 "#PWR0114" H 8450 10900 30 0001 C CNN +F 1 "GND" H 8450 10830 30 0001 C CNN + 1 8450 10900 + 1 0 0 -1 +$EndComp +$Comp +L +1.2V #PWR0115 +U 1 1 4BADD09D +P 5650 10200 +F 0 "#PWR0115" H 5650 10340 20 0001 C CNN +F 1 "+1.2V" H 5650 10310 30 0000 C CNN + 1 5650 10200 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR0116 +U 1 1 4BADD090 +P 4100 10200 +F 0 "#PWR0116" H 4100 10150 20 0001 C CNN +F 1 "+2.5V" H 4100 10300 30 0000 C CNN + 1 4100 10200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0117 +U 1 1 4BADD08B +P 5650 11100 +F 0 "#PWR0117" H 5650 11100 30 0001 C CNN +F 1 "GND" H 5650 11030 30 0001 C CNN + 1 5650 11100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0118 +U 1 1 4BADD089 +P 4100 11100 +F 0 "#PWR0118" H 4100 11100 30 0001 C CNN +F 1 "GND" H 4100 11030 30 0001 C CNN + 1 4100 11100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0119 +U 1 1 4BADD072 +P 650 11100 +F 0 "#PWR0119" H 650 11100 30 0001 C CNN +F 1 "GND" H 650 11030 30 0001 C CNN + 1 650 11100 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR0120 +U 1 1 4BADD05C +P 650 10200 +F 0 "#PWR0120" H 650 10160 30 0001 C CNN +F 1 "+3.3V" H 650 10310 30 0000 C CNN + 1 650 10200 + 1 0 0 -1 +$EndComp +$Comp +L C C222 +U 1 1 4BADCE85 +P 5900 10650 +F 0 "C222" H 5950 10750 50 0000 L CNN +F 1 "100n" H 5950 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 5900 10650 60 0001 C CNN + 1 5900 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C221 +U 1 1 4BADCE7D +P 5650 10650 +F 0 "C221" H 5700 10750 50 0000 L CNN +F 1 "100n" H 5700 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 5650 10650 60 0001 C CNN + 1 5650 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C213 +U 1 1 4BADCE7B +P 4850 10650 +F 0 "C213" H 4900 10750 50 0000 L CNN +F 1 "100n" H 4900 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 4850 10650 60 0001 C CNN + 1 4850 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C212 +U 1 1 4BADCE7A +P 4600 10650 +F 0 "C212" H 4650 10750 50 0000 L CNN +F 1 "100n" H 4650 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 4600 10650 60 0001 C CNN + 1 4600 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C211 +U 1 1 4BADCE78 +P 4350 10650 +F 0 "C211" H 4400 10750 50 0000 L CNN +F 1 "100n" H 4400 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 4350 10650 60 0001 C CNN + 1 4350 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C210 +U 1 1 4BADCE74 +P 4100 10650 +F 0 "C210" H 4150 10750 50 0000 L CNN +F 1 "100n" H 4150 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 4100 10650 60 0001 C CNN + 1 4100 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C208 +U 1 1 4BADCE6D +P 2400 10650 +F 0 "C208" H 2450 10750 50 0000 L CNN +F 1 "100n" H 2450 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 2400 10650 60 0001 C CNN + 1 2400 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C207 +U 1 1 4BADCE6B +P 2150 10650 +F 0 "C207" H 2200 10750 50 0000 L CNN +F 1 "100n" H 2200 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 2150 10650 60 0001 C CNN + 1 2150 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C206 +U 1 1 4BADCE6A +P 1900 10650 +F 0 "C206" H 1950 10750 50 0000 L CNN +F 1 "100n" H 1950 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1900 10650 60 0001 C CNN + 1 1900 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C205 +U 1 1 4BADCE67 +P 1650 10650 +F 0 "C205" H 1700 10750 50 0000 L CNN +F 1 "100n" H 1700 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1650 10650 60 0001 C CNN + 1 1650 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C204 +U 1 1 4BADCE65 +P 1400 10650 +F 0 "C204" H 1450 10750 50 0000 L CNN +F 1 "100n" H 1450 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1400 10650 60 0001 C CNN + 1 1400 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C203 +U 1 1 4BADCE64 +P 1150 10650 +F 0 "C203" H 1200 10750 50 0000 L CNN +F 1 "100n" H 1200 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1150 10650 60 0001 C CNN + 1 1150 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C202 +U 1 1 4BADCE62 +P 900 10650 +F 0 "C202" H 950 10750 50 0000 L CNN +F 1 "100n" H 950 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 900 10650 60 0001 C CNN + 1 900 10650 + 1 0 0 -1 +$EndComp +$Comp +L C C201 +U 1 1 4BADCE47 +P 650 10650 +F 0 "C201" H 700 10750 50 0000 L CNN +F 1 "100n" H 700 10550 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 650 10650 60 0001 C CNN + 1 650 10650 + 1 0 0 -1 +$EndComp +$Comp +L XC3S400-PQ208 U201 +U 1 1 4B6E1931 +P 8350 5850 +F 0 "U201" H 10000 10450 60 0000 L CNN +F 1 "XC3S400-PQ208" H 10050 1200 60 0000 L CNN +F 2 "PQFP208" H 8350 5850 60 0001 C CNN + 1 8350 5850 + 1 0 0 -1 +$EndComp +Text Notes 6550 1300 0 50 ~ 0 +JTAG +$Comp +L +3.3V #PWR0121 +U 1 1 4BAD12D2 +P 7650 800 +F 0 "#PWR0121" H 7650 760 30 0001 C CNN +F 1 "+3.3V" H 7650 910 30 0000 C CNN + 1 7650 800 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR0122 +U 1 1 4BAD12BE +P 9050 800 +F 0 "#PWR0122" H 9050 750 20 0001 C CNN +F 1 "+2.5V" H 9050 900 30 0000 C CNN + 1 9050 800 + 1 0 0 -1 +$EndComp +$Comp +L +1.2V #PWR0123 +U 1 1 4BAD12B4 +P 9650 800 +F 0 "#PWR0123" H 9650 940 20 0001 C CNN +F 1 "+1.2V" H 9650 910 30 0000 C CNN + 1 9650 800 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/pcb/kicad/RevE2/mcu.sch b/pcb/kicad/RevE2/mcu.sch new file mode 100644 index 0000000..4b4fe13 --- /dev/null +++ b/pcb/kicad/RevE2/mcu.sch @@ -0,0 +1,1193 @@ +EESchema Schematic File Version 2 date Mon 26 Dec 2011 09:56:13 PM CET +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:snescart +LIBS:misc-74 +LIBS:vreg +LIBS:lpc1754 +LIBS:sd_card +LIBS:cy62148ev30 +LIBS:mt45w8mw16 +LIBS:cs4344 +LIBS:double_sch_kcom +LIBS:usb_minib +LIBS:mic23250 +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 4 6 +Title "sd2snes Mark II" +Date "26 dec 2011" +Rev "E2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4200 7400 4200 7200 +Wire Wire Line + 4200 7200 4400 7200 +Wire Wire Line + 5000 7200 5100 7200 +Wire Wire Line + 6700 5100 7200 5100 +Wire Wire Line + 6700 4900 7300 4900 +Wire Wire Line + 9450 6850 9200 6850 +Wire Wire Line + 10250 6650 10500 6650 +Wire Wire Line + 9200 6750 9450 6750 +Wire Wire Line + 7300 4700 6700 4700 +Wire Wire Line + 7300 4500 6700 4500 +Wire Wire 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+ 10500 6750 10250 6750 +Wire Wire Line + 6700 5000 7950 5000 +$Comp +L GND #PWR045 +U 1 1 4E2C17DC +P 4200 7400 +F 0 "#PWR045" H 4200 7400 30 0001 C CNN +F 1 "GND" H 4200 7330 30 0001 C CNN + 1 4200 7400 + -1 0 0 -1 +$EndComp +Text GLabel 5100 7200 2 50 Output ~ 0 +/USEBATT +$Comp +L JUMPER JP402 +U 1 1 4E2C1796 +P 4700 7200 +F 0 "JP402" H 4700 7100 60 0000 C CNN +F 1 "JUMPER" H 4700 7000 40 0000 C CNN + 1 4700 7200 + 1 0 0 -1 +$EndComp +Text GLabel 7950 5000 2 50 Input ~ 0 +/USEBATT +Text GLabel 10500 6750 2 50 BiDi ~ 0 +MCU_SPARE +Text GLabel 7300 4700 2 50 BiDi ~ 0 +MCU_SPARE +Text GLabel 9200 6850 0 50 Output ~ 0 +P2_CLK +Text GLabel 10500 6850 2 50 Input ~ 0 +P2_D0 +Text GLabel 9200 6750 0 50 Output ~ 0 +P_LATCH +Text GLabel 10500 6650 2 50 Output ~ 0 +P1_CLK +Text GLabel 9200 6650 0 50 Input ~ 0 +P1_D0 +Text GLabel 7300 4800 2 50 Input ~ 0 +P2_CLK +Text GLabel 7300 4900 2 50 Output ~ 0 +P2_D0 +Text GLabel 7300 4600 2 50 Input ~ 0 +P_LATCH +Text GLabel 7300 4500 2 50 Input ~ 0 +P1_CLK +Text GLabel 7300 4400 2 50 Output ~ 0 +P1_D0 +$Comp +L CONN_3X2 P404 +U 1 1 4DF9F6C8 +P 9850 6800 +F 0 "P404" H 9850 7050 50 0000 C CNN +F 1 "CONN_3X2" V 9850 6850 40 0000 C CNN + 1 9850 6800 + 1 0 0 -1 +$EndComp +Text Notes 6400 6250 0 50 ~ 0 +open in case of in-circuit PIC programming +$Comp +L JUMPER JP401 +U 1 1 4C86265B +P 7300 5950 +F 0 "JP401" H 7300 5850 60 0000 C CNN +F 1 "JUMPER" H 7300 5750 40 0000 C CNN + 1 7300 5950 + 1 0 0 -1 +$EndComp +$Comp +L R R407 +U 1 1 4C814430 +P 1400 3700 +F 0 "R407" V 1300 3700 50 0000 C CNN +F 1 "10k" V 1400 3700 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 1400 3700 60 0001 C CNN + 1 1400 3700 + -1 0 0 1 +$EndComp +$Comp +L +3.3V #PWR046 +U 1 1 4C814422 +P 1400 3400 +F 0 "#PWR046" H 1400 3360 30 0001 C CNN +F 1 "+3.3V" H 1400 3510 30 0000 C CNN + 1 1400 3400 + -1 0 0 -1 +$EndComp +Text GLabel 2700 4500 0 50 Input ~ 0 +EXT_TDO +Text GLabel 9200 5350 0 50 Input ~ 0 +USB_SWCONN +Text GLabel 2700 4200 0 50 Output ~ 0 +USB_SWCONN +Text Notes 750 1700 0 50 ~ 0 +or 3000mcd LEDs (10k for R401-403) +NoConn ~ 6700 5500 +NoConn ~ 6700 5400 +NoConn ~ 6700 5300 +NoConn ~ 3200 5100 +NoConn ~ 3200 4300 +NoConn ~ 3200 3700 +NoConn ~ 3200 2800 +NoConn ~ 3200 2500 +$Comp +L R R422 +U 1 1 4C5608C9 +P 7450 4200 +F 0 "R422" V 7400 4450 50 0000 C CNN +F 1 "33" V 7450 4200 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 7450 4200 60 0001 C CNN + 1 7450 4200 + 0 1 1 0 +$EndComp +$Comp +L R R421 +U 1 1 4C5608C6 +P 7450 4100 +F 0 "R421" V 7400 4350 50 0000 C CNN +F 1 "33" V 7450 4100 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 7450 4100 60 0001 C CNN + 1 7450 4100 + 0 1 1 0 +$EndComp +Text GLabel 10600 1050 2 50 BiDi ~ 0 +SD_DAT1 +$Comp +L CONN_2 P403 +U 1 1 4C4A0B6F +P 8500 6400 +F 0 "P403" V 8450 6400 40 0000 C CNN +F 1 "CONN_2" V 8550 6400 40 0000 C CNN +F 2 "PIN_ARRAY_2X1" H 8500 6400 60 0001 C CNN + 1 8500 6400 + 1 0 0 1 +$EndComp +$Comp +L GND #PWR047 +U 1 1 4C4A0B6E +P 7950 6700 +F 0 "#PWR047" H 7950 6700 30 0001 C CNN +F 1 "GND" H 7950 6630 30 0001 C CNN + 1 7950 6700 + -1 0 0 -1 +$EndComp +Text Notes 8232 6200 0 50 ~ 0 +Freeze button +Text GLabel 10600 1150 2 50 BiDi ~ 0 +SD_DAT2 +Text GLabel 7000 5700 2 50 Output ~ 0 +DAC_/DEM +Text GLabel 2700 3800 0 50 Output ~ 0 +DIN+MCU_/OVR +$Comp +L C C412 +U 1 1 4C1286D5 +P 10950 3100 +F 0 "C412" H 11000 3200 50 0000 L CNN +F 1 "100n" H 11000 3000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10950 3100 60 0001 C CNN + 1 10950 3100 + 1 0 0 -1 +$EndComp +$Comp +L LED D403 +U 1 1 4C0DA78D +P 800 2500 +F 0 "D403" H 800 2600 50 0000 C CNN +F 1 "LED 2mA 1.7V, red" H 800 2400 50 0000 C CNN +F 2 "LED-3MM-FIXED" H 800 2500 60 0001 C CNN + 1 800 2500 + 0 -1 1 0 +$EndComp +$Comp +L R R403 +U 1 1 4C0DA785 +P 2000 3200 +F 0 "R403" V 2050 2950 50 0000 C CNN +F 1 "680" V 2000 3200 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 2000 3200 60 0001 C CNN + 1 2000 3200 + 0 1 1 0 +$EndComp +$Comp +L CONN_7X2 P401 +U 1 1 4C0943CA +P 9850 6050 +F 0 "P401" H 9850 6450 60 0000 C CNN +F 1 "CONN_7X2" V 9850 6050 60 0000 C CNN +F 2 "pin_array_7x2" H 9850 6050 60 0001 C CNN + 1 9850 6050 + 1 0 0 -1 +$EndComp +Text Notes 500 7700 0 250 ~ 50 +MCU, SD, debug +Text Notes 700 5050 0 50 ~ 0 +Reset button +Text Notes 750 1600 0 50 ~ 0 +2mA low current LEDs +$Comp +L C C405 +U 1 1 4C063C47 +P 1400 5600 +F 0 "C405" H 1400 5700 50 0000 L CNN +F 1 "100n" H 1400 5500 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1400 5600 60 0001 C CNN + 1 1400 5600 + 1 0 0 -1 +$EndComp +$Comp +L R R404 +U 1 1 4C063C2F +P 1400 4900 +F 0 "R404" V 1300 4900 50 0000 C CNN +F 1 "10k" V 1400 4900 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 1400 4900 60 0001 C CNN + 1 1400 4900 + -1 0 0 1 +$EndComp +$Comp +L +3.3V #PWR048 +U 1 1 4C063C16 +P 1400 4600 +F 0 "#PWR048" H 1400 4560 30 0001 C CNN +F 1 "+3.3V" H 1400 4710 30 0000 C CNN + 1 1400 4600 + -1 0 0 -1 +$EndComp +$Comp +L R R423 +U 1 1 4C01596A +P 9300 5000 +F 0 "R423" V 9250 5250 50 0000 C CNN +F 1 "1.5k" V 9300 5000 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 9300 5000 60 0001 C CNN + 1 9300 5000 + 1 0 0 -1 +$EndComp +Text GLabel 2700 5100 0 50 Input ~ 0 +/RESET +$Comp +L +5V #PWR049 +U 1 1 4BFBFF63 +P 10500 5750 +F 0 "#PWR049" H 10500 5840 20 0001 C CNN +F 1 "+5V" H 10500 5840 30 0000 C CNN + 1 10500 5750 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR050 +U 1 1 4BFBFF50 +P 9200 5750 +F 0 "#PWR050" H 9200 5710 30 0001 C CNN +F 1 "+3.3V" H 9200 5860 30 0000 C CNN + 1 9200 5750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR051 +U 1 1 4BFBFF44 +P 8850 5850 +F 0 "#PWR051" H 8850 5850 30 0001 C CNN +F 1 "GND" H 8850 5780 30 0001 C CNN + 1 8850 5850 + 0 1 1 0 +$EndComp +Text GLabel 9200 5950 0 50 Output ~ 0 +/RESET +Text GLabel 10500 5850 2 50 Input ~ 0 +P2.10 +Text GLabel 1000 4000 0 50 Input ~ 0 +P2.10 +Text GLabel 10500 5950 2 50 Input ~ 0 +TX3 +Text GLabel 9200 6050 0 50 Output ~ 0 +RX3 +Text GLabel 10500 6050 2 50 Output ~ 0 +TCK +Text GLabel 9200 6150 0 50 Output ~ 0 +/TRST +Text GLabel 10500 6150 2 50 Output ~ 0 +TMS +Text GLabel 9200 6250 0 50 Output ~ 0 +EXT_TDI +Text GLabel 10500 6250 2 50 Input ~ 0 +EXT_TDO +Text GLabel 10500 6350 2 50 Input ~ 0 +TX0 +Text GLabel 9200 6350 0 50 Output ~ 0 +RX0 +Text GLabel 7000 4000 2 50 Input ~ 0 +RX3 +Text GLabel 7000 3900 2 50 Output ~ 0 +TX3 +$Comp +L R R405 +U 1 1 4BF850D1 +P 7250 3300 +F 0 "R405" V 7200 3550 50 0000 C CNN +F 1 "100" V 7250 3300 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 7250 3300 60 0001 C CNN + 1 7250 3300 + 0 1 1 0 +$EndComp +$Comp +L R R406 +U 1 1 4BF850A9 +P 7450 5100 +F 0 "R406" V 7400 4850 50 0000 C CNN +F 1 "100" V 7450 5100 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 7450 5100 60 0001 C CNN + 1 7450 5100 + 0 -1 1 0 +$EndComp +$Comp +L +3.3V #PWR052 +U 1 1 4BF84ABB +P 1100 1900 +F 0 "#PWR052" H 1100 1860 30 0001 C CNN +F 1 "+3.3V" H 1100 2010 30 0000 C CNN + 1 1100 1900 + -1 0 0 -1 +$EndComp +$Comp +L R R402 +U 1 1 4BF847B1 +P 2000 3100 +F 0 "R402" V 2050 2850 50 0000 C CNN +F 1 "680" V 2000 3100 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 2000 3100 60 0001 C CNN + 1 2000 3100 + 0 1 1 0 +$EndComp +$Comp +L R R401 +U 1 1 4BF847A7 +P 2000 3000 +F 0 "R401" V 2050 2750 50 0000 C CNN +F 1 "680" V 2000 3000 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 2000 3000 60 0001 C CNN + 1 2000 3000 + 0 1 1 0 +$EndComp +$Comp +L LED D401 +U 1 1 4BF8328D +P 1400 2500 +F 0 "D401" H 1400 2600 50 0000 C CNN +F 1 "LED 2mA 1.9V, green" H 1400 2400 50 0000 C CNN +F 2 "LED-3MM-FIXED" H 1400 2500 60 0001 C CNN + 1 1400 2500 + 0 -1 1 0 +$EndComp +$Comp +L LED D402 +U 1 1 4BF8324A +P 1100 2500 +F 0 "D402" H 1100 2600 50 0000 C CNN +F 1 "LED 2mA 1.8V, yellow" H 1100 2400 50 0000 C CNN +F 2 "LED-3MM-FIXED" H 1100 2500 60 0001 C CNN + 1 1100 2500 + 0 -1 1 0 +$EndComp +$Comp +L GND #PWR053 +U 1 1 4BF6C1FC +P 5850 7600 +F 0 "#PWR053" H 5850 7600 30 0001 C CNN +F 1 "GND" H 5850 7530 30 0001 C CNN + 1 5850 7600 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR054 +U 1 1 4BF6C1F7 +P 5850 6800 +F 0 "#PWR054" H 5850 6760 30 0001 C CNN +F 1 "+3.3V" H 5850 6910 30 0000 C CNN + 1 5850 6800 + -1 0 0 -1 +$EndComp +$Comp +L C C404 +U 1 1 4BF6BFE6 +P 6600 7200 +F 0 "C404" H 6650 7300 50 0000 L CNN +F 1 "100n" H 6650 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 6600 7200 60 0001 C CNN + 1 6600 7200 + 1 0 0 -1 +$EndComp +$Comp +L C C403 +U 1 1 4BF6BFE5 +P 6350 7200 +F 0 "C403" H 6400 7300 50 0000 L CNN +F 1 "100n" H 6400 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 6350 7200 60 0001 C CNN + 1 6350 7200 + 1 0 0 -1 +$EndComp +$Comp +L C C402 +U 1 1 4BF6BFE2 +P 6100 7200 +F 0 "C402" H 6150 7300 50 0000 L CNN +F 1 "100n" H 6150 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 6100 7200 60 0001 C CNN + 1 6100 7200 + 1 0 0 -1 +$EndComp +$Comp +L C C401 +U 1 1 4BF6BFE1 +P 5850 7200 +F 0 "C401" H 5900 7300 50 0000 L CNN +F 1 "100n" H 5900 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 5850 7200 60 0001 C CNN + 1 5850 7200 + 1 0 0 -1 +$EndComp +$Comp +L C C411 +U 1 1 4BF6BFBB +P 10700 3100 +F 0 "C411" H 10750 3200 50 0000 L CNN +F 1 "10u" H 10750 3000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10700 3100 60 0001 C CNN + 1 10700 3100 + 1 0 0 -1 +$EndComp +Text GLabel 2700 4800 0 50 Input ~ 0 +/TRST +Text GLabel 7000 2700 2 50 Input ~ 0 +RX0 +Text GLabel 7000 2600 2 50 Output ~ 0 +TX0 +Text GLabel 7000 2500 2 50 3State ~ 0 +CIC_DATA0 +Text GLabel 7000 2400 2 50 3State ~ 0 +CIC_DATA1 +$Comp +L GND #PWR055 +U 1 1 4BF0021F +P 9600 5200 +F 0 "#PWR055" H 9600 5200 30 0001 C CNN +F 1 "GND" H 9600 5130 30 0001 C CNN + 1 9600 5200 + 1 0 0 -1 +$EndComp +$Comp +L USB_MINIB J421 +U 1 1 4BF00175 +P 10100 4700 +F 0 "J421" H 10100 5100 60 0000 C CNN +F 1 "Molex 54819" H 10250 4300 60 0000 C CNN +F 2 "USB-MINIB-THT" H 10100 4700 60 0001 C CNN +F 4 "Molex" H 10100 4700 60 0001 C CNN "Manufacturer" +F 5 "Assmann A-USBB-M5" H 10100 4700 60 0001 C CNN "Value" + 1 10100 4700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR056 +U 1 1 4BEFBCAA +P 1200 6850 +F 0 "#PWR056" H 1200 6850 30 0001 C CNN +F 1 "GND" H 1200 6780 30 0001 C CNN + 1 1200 6850 + -1 0 0 -1 +$EndComp +$Comp +L CONN_2 P402 +U 1 1 4BEFBC73 +P 850 5300 +F 0 "P402" V 800 5300 40 0000 C CNN +F 1 "CONN_2" V 900 5300 40 0000 C CNN +F 2 "PIN_ARRAY_2X1" H 850 5300 60 0001 C CNN + 1 850 5300 + -1 0 0 1 +$EndComp +Text GLabel 2700 4900 0 50 Input ~ 0 +TCK +Text GLabel 2700 4700 0 50 Input ~ 0 +TMS +Text GLabel 2700 4600 0 50 Input ~ 0 +EXT_TDI +Text GLabel 7950 5100 2 50 Output ~ 0 +PROG_B +Text GLabel 7000 3200 2 50 Output ~ 0 +FPGA_CLK +Text GLabel 7750 3300 2 50 Output ~ 0 +CCLK +Text GLabel 7000 3800 2 50 Input ~ 0 +DONE +$Comp +L SD_CARD J411 +U 1 1 4BAA6A9C +P 9650 3250 +F 0 "J411" H 9350 3750 60 0000 C CNN +F 1 "Hirose DM1AA" H 9850 2700 60 0000 C CNN + 1 9650 3250 + 1 0 0 -1 +$EndComp +Text GLabel 2550 2400 0 50 3State ~ 0 +SNES_/RESET +Text GLabel 7650 5950 2 50 Output ~ 0 +CIC_MCLR +$Comp +L GND #PWR057 +U 1 1 4BEECBF1 +P 3100 6850 +F 0 "#PWR057" H 3100 6850 30 0001 C CNN +F 1 "GND" H 3100 6780 30 0001 C CNN + 1 3100 6850 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR058 +U 1 1 4BEECBEF +P 2500 6850 +F 0 "#PWR058" H 2500 6850 30 0001 C CNN +F 1 "GND" H 2500 6780 30 0001 C CNN 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1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/pcb/kicad/RevE2/pwr_misc.sch b/pcb/kicad/RevE2/pwr_misc.sch new file mode 100644 index 0000000..3f84cea --- /dev/null +++ b/pcb/kicad/RevE2/pwr_misc.sch @@ -0,0 +1,1246 @@ +EESchema Schematic File Version 2 date Mon 26 Dec 2011 09:56:13 PM CET +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:snescart +LIBS:misc-74 +LIBS:vreg +LIBS:lpc1754 +LIBS:sd_card +LIBS:cy62148ev30 +LIBS:mt45w8mw16 +LIBS:cs4344 +LIBS:double_sch_kcom +LIBS:usb_minib +LIBS:mic23250 +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 5 6 +Title "sd2snes Mark II" +Date "26 dec 2011" +Rev "E2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L FILTER FB342 +U 1 1 4EF8DF53 +P 5450 5500 +F 0 "FB342" H 5450 5650 60 0000 C CNN +F 1 "FILTER" H 5450 5400 60 0000 C CNN + 1 5450 5500 + 1 0 0 -1 +$EndComp +Connection ~ 4000 2600 +Wire Wire Line + 3250 2800 4000 2800 +Wire Wire Line + 4000 2800 4000 2600 +Wire Wire Line + 3250 4250 4000 4250 +Wire Wire Line + 3250 4050 3350 4050 +Connection ~ 1750 4050 +Wire Wire Line + 1850 4250 1750 4250 +Wire Wire Line + 1750 4250 1750 4050 +Connection ~ 4100 2600 +Wire Wire Line + 4100 2800 4100 2600 +Wire Wire Line + 4100 2600 4100 2400 +Wire Wire Line + 3250 2600 3350 2600 +Wire Wire Line + 1600 3200 1600 3450 +Wire Wire Line + 1850 2600 1750 2600 +Wire Wire Line + 1750 2600 1600 2600 +Wire Wire Line + 1600 2600 1000 2600 +Wire Wire Line + 1000 2600 1000 2400 +Wire Wire Line + 2550 4750 2550 4900 +Wire Wire Line + 5100 5500 5000 5500 +Wire Wire Line + 5100 5100 5000 5100 +Wire Wire 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0000 C CNN + 1 2550 2700 + 1 0 0 -1 +$EndComp +$Comp +L MCP1603-SOT23-FIXED U302 +U 1 1 4EF3AD9A +P 2550 4150 +F 0 "U302" H 2550 4150 60 0000 C CNN +F 1 "MCP1603T-330I/OS" H 2550 4500 60 0000 C CNN + 1 2550 4150 + 1 0 0 -1 +$EndComp +$Comp +L +3.3VDAC #PWR071 +U 1 1 4DB2EA88 +P 5900 4900 +F 0 "#PWR071" H 5900 5020 20 0001 C CNN +F 1 "+3.3VDAC" H 5900 4990 30 0000 C CNN + 1 5900 4900 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR072 +U 1 1 4DB2EA61 +P 5000 4900 +F 0 "#PWR072" H 5000 4860 30 0001 C CNN +F 1 "+3.3V" H 5000 5010 30 0000 C CNN + 1 5000 4900 + 1 0 0 -1 +$EndComp +$Comp +L FILTER FB341 +U 1 1 4DB2EA56 +P 5450 5100 +F 0 "FB341" H 5450 5250 60 0000 C CNN +F 1 "FILTER" H 5450 5000 60 0000 C CNN + 1 5450 5100 + 1 0 0 -1 +$EndComp +$Comp +L +3.3VDAC #PWR073 +U 1 1 4DB2E9FC +P 10150 5750 +F 0 "#PWR073" H 10150 5870 20 0001 C CNN +F 1 "+3.3VDAC" H 10150 5840 30 0000 C CNN + 1 10150 5750 + 1 0 0 -1 +$EndComp +$Comp +L +3.3VDAC #PWR074 +U 1 1 4DB2E9D7 +P 6550 3050 +F 0 "#PWR074" H 6550 3170 20 0001 C CNN +F 1 "+3.3VDAC" H 6550 3140 30 0000 C CNN + 1 6550 3050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR075 +U 1 1 4DB21FAD +P 5000 5700 +F 0 "#PWR075" H 5000 5700 30 0001 C CNN +F 1 "GND" H 5000 5630 30 0001 C CNN + 1 5000 5700 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR076 +U 1 1 4DB21FA9 +P 5900 5700 +F 0 "#PWR076" H 5900 5700 40 0001 C CNN +F 1 "AGND" H 5900 5630 50 0000 C CNN + 1 5900 5700 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR077 +U 1 1 4DB21531 +P 10350 4500 +F 0 "#PWR077" H 10350 4500 40 0001 C CNN +F 1 "AGND" H 10350 4430 50 0000 C CNN + 1 10350 4500 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR078 +U 1 1 4DB2152E +P 9650 4500 +F 0 "#PWR078" H 9650 4500 40 0001 C CNN +F 1 "AGND" H 9650 4430 50 0000 C CNN + 1 9650 4500 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR079 +U 1 1 4DB2152B +P 10150 6550 +F 0 "#PWR079" H 10150 6550 40 0001 C CNN +F 1 "AGND" H 10150 6480 50 0000 C CNN + 1 10150 6550 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR080 +U 1 1 4DB2152A +P 9750 5500 +F 0 "#PWR080" H 9750 5500 40 0001 C CNN +F 1 "AGND" H 9750 5430 50 0000 C CNN + 1 9750 5500 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR081 +U 1 1 4DB21528 +P 9150 5500 +F 0 "#PWR081" H 9150 5500 40 0001 C CNN +F 1 "AGND" H 9150 5430 50 0000 C CNN + 1 9150 5500 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR082 +U 1 1 4DB21526 +P 8300 5500 +F 0 "#PWR082" H 8300 5500 40 0001 C CNN +F 1 "AGND" H 8300 5430 50 0000 C CNN + 1 8300 5500 + 1 0 0 -1 +$EndComp +$Comp +L AGND #PWR083 +U 1 1 4DB21524 +P 7700 5500 +F 0 "#PWR083" H 7700 5500 40 0001 C CNN +F 1 "AGND" H 7700 5430 50 0000 C CNN + 1 7700 5500 + 1 0 0 -1 +$EndComp +Text Notes 7000 7000 0 250 ~ 50 +Power, DAC, CIC, Batt +$Comp +L AGND #PWR084 +U 1 1 4DB214E8 +P 6550 4800 +F 0 "#PWR084" H 6550 4800 40 0001 C CNN +F 1 "AGND" H 6550 4730 50 0000 C CNN + 1 6550 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R301 +U 1 1 4D4BE786 +P 2550 1700 +F 0 "R301" V 2630 1700 50 0000 C CNN +F 1 "20k" V 2550 1700 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 2550 1700 60 0001 C CNN + 1 2550 1700 + -1 0 0 1 +$EndComp +Text Notes 2050 800 0 50 ~ 0 +inverse polarity protection +$Comp +L MOSFET_P Q301 +U 1 1 4D4BCF29 +P 2550 1150 +F 0 "Q301" V 2800 1150 60 0000 R CNN +F 1 "IRLML6402PbF" V 2500 650 60 0000 R CNN + 1 2550 1150 + 0 -1 -1 0 +$EndComp +$Comp +L +5V #PWR085 +U 1 1 4D4BC990 +P 3300 900 +F 0 "#PWR085" H 3300 990 20 0001 C CNN +F 1 "+5V" H 3300 990 30 0000 C CNN + 1 3300 900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR086 +U 1 1 4D4BC92F +P 2550 2100 +F 0 "#PWR086" H 2550 2100 30 0001 C CNN +F 1 "GND" H 2550 2030 30 0001 C CNN + 1 2550 2100 + 1 0 0 -1 +$EndComp +$Comp +L +5VL #PWR49 +U 1 1 4D4BC926 +P 1800 900 +F 0 "#PWR49" H 1800 1030 20 0001 C CNN +F 1 "+5VL" H 1800 1000 30 0000 C CNN + 1 1800 900 + 1 0 0 -1 +$EndComp +Text GLabel 9000 1200 1 50 3State ~ 0 +CIC_DATA1 +Text GLabel 9200 1200 1 50 3State ~ 0 +CIC_DATA0 +$Comp +L GND #PWR087 +U 1 1 4CA65604 +P 9350 2400 +F 0 "#PWR087" H 9350 2400 30 0001 C CNN +F 1 "GND" H 9350 2330 30 0001 C CNN + 1 9350 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR088 +U 1 1 4CA655FE +P 9600 2400 +F 0 "#PWR088" H 9600 2400 30 0001 C CNN +F 1 "GND" H 9600 2330 30 0001 C CNN + 1 9600 2400 + 1 0 0 -1 +$EndComp +$Comp +L C C332 +U 1 1 4CA655D4 +P 9350 2100 +F 0 "C332" H 9400 2200 50 0000 L CNN +F 1 "100p" H 9400 2000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 9350 2100 60 0001 C CNN + 1 9350 2100 + 1 0 0 -1 +$EndComp +$Comp +L C C333 +U 1 1 4CA65597 +P 9600 2100 +F 0 "C333" H 9650 2200 50 0000 L CNN +F 1 "100p" H 9650 2000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 9600 2100 60 0001 C CNN + 1 9600 2100 + 1 0 0 -1 +$EndComp +$Comp +L R R333 +U 1 1 4CA65577 +P 9850 1800 +F 0 "R333" V 9930 1800 50 0000 C CNN +F 1 "680" V 9850 1800 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 9850 1800 60 0001 C CNN + 1 9850 1800 + 0 1 1 0 +$EndComp +$Comp +L R R332 +U 1 1 4CA6556E +P 9850 1400 +F 0 "R332" V 9930 1400 50 0000 C CNN +F 1 "680" V 9850 1400 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 9850 1400 60 0001 C CNN + 1 9850 1400 + 0 -1 1 0 +$EndComp +$Comp +L R R331 +U 1 1 4C42D578 +P 6150 1400 +F 0 "R331" V 6230 1400 50 0000 C CNN +F 1 "680" V 6150 1400 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 6150 1400 60 0001 C CNN + 1 6150 1400 + 0 1 1 0 +$EndComp +Text GLabel 5550 3900 0 50 Input ~ 0 +DAC_/DEM +$Comp +L C C342 +U 1 1 4C17DE31 +P 10500 6150 +F 0 "C342" H 10550 6250 50 0000 L CNN +F 1 "1u" H 10550 6050 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10500 6150 60 0001 C CNN + 1 10500 6150 + 1 0 0 -1 +$EndComp +Text Notes 5000 6700 0 100 ~ 0 +Battery (SRAM + RTC) +Text Notes 2400 6550 0 50 ~ 0 +2.5V LDO +Text Notes 2400 5200 0 50 ~ 0 +1.8V LDO +Text Notes 2250 2300 0 50 ~ 0 +1.2V Step-Down +$Comp +L +1.2V #PWR089 +U 1 1 4C05BAEC +P 4100 2400 +F 0 "#PWR089" H 4100 2540 20 0001 C CNN +F 1 "+1.2V" H 4100 2510 30 0000 C CNN + 1 4100 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR090 +U 1 1 4C05AF72 +P 1600 3450 +F 0 "#PWR090" H 1600 3450 30 0001 C CNN +F 1 "GND" H 1600 3380 30 0001 C CNN + 1 1600 3450 + 1 0 0 -1 +$EndComp +$Comp +L C C301 +U 1 1 4C05ACA2 +P 1600 3000 +F 0 "C301" H 1450 3100 50 0000 L CNN +F 1 "4.7u" H 1400 2900 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1600 3000 60 0001 C CNN + 1 1600 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR091 +U 1 1 4C05ADCE +P 4100 4900 +F 0 "#PWR091" H 4100 4900 30 0001 C CNN +F 1 "GND" H 4100 4830 30 0001 C CNN + 1 4100 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR092 +U 1 1 4C05ADC9 +P 1600 4900 +F 0 "#PWR092" H 1600 4900 30 0001 C CNN +F 1 "GND" H 1600 4830 30 0001 C CNN + 1 1600 4900 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR093 +U 1 1 4C05AD31 +P 1000 2400 +F 0 "#PWR093" H 1000 2490 20 0001 C CNN +F 1 "+5V" H 1000 2490 30 0000 C CNN + 1 1000 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR094 +U 1 1 4C05AD0F +P 4100 3450 +F 0 "#PWR094" H 4100 3450 30 0001 C CNN +F 1 "GND" H 4100 3380 30 0001 C CNN + 1 4100 3450 + 1 0 0 -1 +$EndComp +$Comp +L C C302 +U 1 1 4C05AC9D +P 4100 3000 +F 0 "C302" H 4150 3100 50 0000 L CNN +F 1 "4.7u" H 4150 2900 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 4100 3000 60 0001 C CNN + 1 4100 3000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR095 +U 1 1 4C05A4CA +P 2550 4900 +F 0 "#PWR095" H 2550 4900 30 0001 C CNN +F 1 "GND" H 2550 4830 30 0001 C CNN + 1 2550 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR096 +U 1 1 4C05A4C3 +P 2550 3450 +F 0 "#PWR096" H 2550 3450 30 0001 C CNN +F 1 "GND" H 2550 3380 30 0001 C CNN + 1 2550 3450 + 1 0 0 -1 +$EndComp +Text GLabel 9800 4750 2 50 Output ~ 0 +AUDIO_L +Text GLabel 8350 4750 2 50 Output ~ 0 +AUDIO_R +$Comp +L R R341 +U 1 1 4BF98EC6 +P 8000 4750 +F 0 "R341" V 8080 4750 50 0000 C CNN +F 1 "470" V 8000 4750 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 8000 4750 60 0001 C CNN + 1 8000 4750 + 0 1 1 0 +$EndComp +$Comp +L R R342 +U 1 1 4BF98EC4 +P 7700 5150 +F 0 "R342" V 7780 5150 50 0000 C CNN +F 1 "10k" V 7700 5150 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 7700 5150 60 0001 C CNN + 1 7700 5150 + 1 0 0 -1 +$EndComp +$Comp +L C C349 +U 1 1 4BF98EBF +P 9750 5200 +F 0 "C349" H 9800 5300 50 0000 L CNN +F 1 "10n" H 9800 5100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 9750 5200 60 0001 C CNN + 1 9750 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C346 +U 1 1 4BF98EBE +P 7700 4400 +F 0 "C346" H 7750 4500 50 0000 L CNN +F 1 "3.3u" H 7750 4300 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 7700 4400 60 0001 C CNN + 1 7700 4400 + 1 0 0 1 +$EndComp +$Comp +L C C348 +U 1 1 4BF98EBB +P 9150 4400 +F 0 "C348" H 9200 4500 50 0000 L CNN +F 1 "3.3u" H 9200 4300 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 9150 4400 60 0001 C CNN + 1 9150 4400 + 1 0 0 1 +$EndComp +$Comp +L R R344 +U 1 1 4BF98EB9 +P 9150 5150 +F 0 "R344" V 9230 5150 50 0000 C CNN +F 1 "10k" V 9150 5150 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 9150 5150 60 0001 C CNN + 1 9150 5150 + 1 0 0 -1 +$EndComp +$Comp +L R R343 +U 1 1 4BF98EB4 +P 9450 4750 +F 0 "R343" V 9530 4750 50 0000 C CNN +F 1 "470" V 9450 4750 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 9450 4750 60 0001 C CNN + 1 9450 4750 + 0 1 1 0 +$EndComp +$Comp +L C C347 +U 1 1 4BF98E9E +P 8300 5200 +F 0 "C347" H 8350 5300 50 0000 L CNN +F 1 "10n" H 8350 5100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 8300 5200 60 0001 C CNN + 1 8300 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C345 +U 1 1 4BF98AAB +P 9650 4100 +F 0 "C345" H 9700 4200 50 0000 L CNN +F 1 "10u" H 9700 4000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 9650 4100 60 0001 C CNN + 1 9650 4100 + 1 0 0 -1 +$EndComp +$Comp +L C C344 +U 1 1 4BF98AA5 +P 10050 4100 +F 0 "C344" H 10100 4200 50 0000 L CNN +F 1 "10u" H 10100 4000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10050 4100 60 0001 C CNN + 1 10050 4100 + 1 0 0 -1 +$EndComp +$Comp +L C C343 +U 1 1 4BF98AA2 +P 10350 4100 +F 0 "C343" H 10400 4200 50 0000 L CNN +F 1 "100n" H 10400 4000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10350 4100 60 0001 C CNN + 1 10350 4100 + 1 0 0 -1 +$EndComp +Text GLabel 5550 4100 0 50 Input ~ 0 +DAC_MCLK +Text GLabel 5550 4000 0 50 Input ~ 0 +DAC_LRCK +Text GLabel 5550 3700 0 50 Input ~ 0 +DAC_SDIN +Text Label 8200 2100 0 50 ~ 0 +CIC_RESET +Text Label 8200 1800 0 50 ~ 0 +CIC_DATA1 +Text Label 8200 1400 0 50 ~ 0 +CIC_DATA0 +Text Label 6450 2100 0 50 ~ 0 +CIC_MCLR +Text Label 6450 1800 0 50 ~ 0 +CIC_STATUS +Text Label 5650 1400 0 50 ~ 0 +CIC_CLK +$Comp +L +BATT #PWR097 +U 1 1 4BAF2EDB +P 5300 6900 +F 0 "#PWR097" H 5300 6850 20 0001 C CNN +F 1 "+BATT" H 5300 7000 30 0000 C CNN + 1 5300 6900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR098 +U 1 1 4BAF2ED2 +P 6300 7100 +F 0 "#PWR098" H 6300 7100 30 0001 C CNN +F 1 "GND" H 6300 7030 30 0001 C CNN + 1 6300 7100 + 1 0 0 -1 +$EndComp +$Comp +L BATTERY BT351 +U 1 1 4BAF2EAF +P 5800 7000 +F 0 "BT351" H 5800 7200 50 0000 C CNN +F 1 "Keystone 1059 / KZH20PCB" H 5800 6810 50 0000 C CNN +F 2 "BT_KEYSTONE_1059_20MM" H 5800 7000 60 0001 C CNN + 1 5800 7000 + 1 0 0 -1 +$EndComp +$Comp +L C C341 +U 1 1 4BADC720 +P 10150 6150 +F 0 "C341" H 10200 6250 50 0000 L CNN +F 1 "100n" H 10200 6050 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10150 6150 60 0001 C CNN + 1 10150 6150 + 1 0 0 -1 +$EndComp +Text Notes 6150 2850 0 100 ~ 0 +Audio DAC +$Comp +L CS4344 U341 +U 1 1 4BAA9331 +P 6550 3900 +F 0 "U341" H 6200 4300 60 0000 C CNN +F 1 "CS4344" H 6900 3500 60 0000 C CNN +F 2 "TSSOP10" H 6550 3900 60 0001 C CNN + 1 6550 3900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR099 +U 1 1 4BADC745 +P 11100 2400 +F 0 "#PWR099" H 11100 2400 30 0001 C CNN +F 1 "GND" H 11100 2330 30 0001 C CNN + 1 11100 2400 + 1 0 0 -1 +$EndComp +$Comp +L C C331 +U 1 1 4BADC719 +P 11100 2100 +F 0 "C331" H 10900 2200 50 0000 L CNN +F 1 "100n" H 10900 2000 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 11100 2100 60 0001 C CNN + 1 11100 2100 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR0100 +U 1 1 4BADC709 +P 11100 1800 +F 0 "#PWR0100" H 11100 1890 20 0001 C CNN +F 1 "+5V" H 11100 1890 30 0000 C CNN + 1 11100 1800 + 1 0 0 -1 +$EndComp +Text GLabel 8600 2100 2 60 Input ~ 0 +CIC_RESET +Text GLabel 10200 1800 2 60 BiDi ~ 0 +EXT_CIC_DATA1 +Text GLabel 10200 1400 2 60 BiDi ~ 0 +EXT_CIC_DATA0 +Text GLabel 6350 2100 0 60 Input ~ 0 +CIC_MCLR +Text GLabel 6350 1800 0 60 Output ~ 0 +CIC_STATUS +Text GLabel 5650 1400 0 60 Input ~ 0 +CIC_CLK +$Comp +L GND #PWR0101 +U 1 1 4BAD0C41 +P 8500 1200 +F 0 "#PWR0101" H 8500 1200 30 0001 C CNN +F 1 "GND" H 8500 1130 30 0001 C CNN + 1 8500 1200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0102 +U 1 1 4BABCB69 +P 3500 6200 +F 0 "#PWR0102" H 3500 6200 30 0001 C CNN +F 1 "GND" H 3500 6130 30 0001 C CNN + 1 3500 6200 + 1 0 0 -1 +$EndComp +$Comp +L C C312 +U 1 1 4BABCB68 +P 3500 5850 +F 0 "C312" H 3550 5950 50 0000 L CNN +F 1 "4.7u" H 3550 5750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3500 5850 60 0001 C CNN + 1 3500 5850 + 1 0 0 -1 +$EndComp +$Comp +L C C311 +U 1 1 4BABCB5C +P 1600 5850 +F 0 "C311" H 1650 5950 50 0000 L CNN +F 1 "4.7u" H 1650 5750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1600 5850 60 0001 C CNN + 1 1600 5850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0103 +U 1 1 4BABCB5B +P 1600 6200 +F 0 "#PWR0103" H 1600 6200 30 0001 C CNN +F 1 "GND" H 1600 6130 30 0001 C CNN + 1 1600 6200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0104 +U 1 1 4BABCAF4 +P 1600 7550 +F 0 "#PWR0104" H 1600 7550 30 0001 C CNN +F 1 "GND" H 1600 7480 30 0001 C CNN + 1 1600 7550 + 1 0 0 -1 +$EndComp +$Comp +L C C322 +U 1 1 4BABCAD2 +P 3500 7200 +F 0 "C322" H 3550 7300 50 0000 L CNN +F 1 "4.7u" H 3550 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3500 7200 60 0001 C CNN + 1 3500 7200 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0105 +U 1 1 4BABCA9D +P 3500 7550 +F 0 "#PWR0105" H 3500 7550 30 0001 C CNN +F 1 "GND" H 3500 7480 30 0001 C CNN + 1 3500 7550 + 1 0 0 -1 +$EndComp +$Comp +L C C321 +U 1 1 4BABCA9C +P 1600 7200 +F 0 "C321" H 1650 7300 50 0000 L CNN +F 1 "4.7u" H 1650 7100 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 1600 7200 60 0001 C CNN + 1 1600 7200 + 1 0 0 -1 +$EndComp +Text Notes 2050 650 0 100 ~ 0 +Power Supply +Text Notes 6950 700 0 100 ~ 0 +SuperCIC Key +$Comp +L +5V #PWR0106 +U 1 1 4BABC073 +P 6350 1000 +F 0 "#PWR0106" H 6350 1090 20 0001 C CNN +F 1 "+5V" H 6350 1090 30 0000 C CNN + 1 6350 1000 + 1 0 0 -1 +$EndComp +$Comp +L PIC12F629 U331 +U 1 1 4BAA92DB +P 7450 1600 +F 0 "U331" H 7400 1600 60 0000 C CNN +F 1 "PIC12F629-I/P" H 7450 2350 60 0000 C CNN +F 2 "SO8N" H 7450 1600 60 0001 C CNN + 1 7450 1600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0107 +U 1 1 4B6ED41C +P 2550 7550 +F 0 "#PWR0107" H 2550 7550 30 0001 C CNN +F 1 "GND" H 2550 7480 30 0001 C CNN + 1 2550 7550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR0108 +U 1 1 4B6ED418 +P 2550 6200 +F 0 "#PWR0108" H 2550 6200 30 0001 C CNN +F 1 "GND" H 2550 6130 30 0001 C CNN + 1 2550 6200 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR0109 +U 1 1 4B6ED26C +P 1150 6650 +F 0 "#PWR0109" H 1150 6610 30 0001 C CNN +F 1 "+3.3V" H 1150 6760 30 0000 C CNN + 1 1150 6650 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR0110 +U 1 1 4B6ED268 +P 1150 5300 +F 0 "#PWR0110" H 1150 5260 30 0001 C CNN +F 1 "+3.3V" H 1150 5410 30 0000 C CNN + 1 1150 5300 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR0111 +U 1 1 4B6ED246 +P 3950 6650 +F 0 "#PWR0111" H 3950 6600 20 0001 C CNN +F 1 "+2.5V" H 3950 6750 30 0000 C CNN + 1 3950 6650 + 1 0 0 -1 +$EndComp +$Comp +L +1.8V #PWR0112 +U 1 1 4B6ED23A +P 3950 5300 +F 0 "#PWR0112" H 3950 5440 20 0001 C CNN +F 1 "+1.8V" H 3950 5410 30 0000 C CNN + 1 3950 5300 + 1 0 0 -1 +$EndComp +$Comp +L MCP1824-SOT23-Fixed U311 +U 1 1 4B6ED144 +P 2550 5600 +F 0 "U311" H 2550 5600 60 0000 C CNN +F 1 "MCP1824-1802E/OT" H 2550 5950 60 0000 C CNN +F 2 "SOT23-5" H 2550 5600 60 0001 C CNN + 1 2550 5600 + 1 0 0 -1 +$EndComp +$Comp +L MCP1824-SOT23-Fixed U321 +U 1 1 4B6ED134 +P 2550 6950 +F 0 "U321" H 2550 6950 60 0000 C CNN +F 1 "MCP1824-2502E/OT" H 2550 7300 60 0000 C CNN +F 2 "SOT23-5" H 2550 6950 60 0001 C CNN + 1 2550 6950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/pcb/kicad/RevE2/sd2snes.brd b/pcb/kicad/RevE2/sd2snes.brd new file mode 100644 index 0000000..7708f9f --- /dev/null +++ b/pcb/kicad/RevE2/sd2snes.brd @@ -0,0 +1,35370 @@ +PCBNEW-BOARD Version 1 date Tue 27 Dec 2011 01:32:38 AM CET + +# Created by Pcbnew(2011-07-02 BZR 2664)-stable + +$GENERAL +encoding utf-8 +LayerCount 2 +Ly 1FFF8001 +EnabledLayers 1FFF8001 +Links 668 +NoConn 0 +Di 36595 17005 83771 64790 +Ndraw 240 +Ntrack 3996 +Nzone 0 +BoardThickness 630 +Nmodule 153 +Nnets 326 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "sd2snes Mark II" +Date "27 dec 2011" +Rev "C2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +Layers 2 +Layer[0] Copper signal +Layer[15] Component signal +TrackWidth 400 +TrackWidthList 59 +TrackWidthList 60 +TrackWidthList 80 +TrackWidthList 160 +TrackWidthList 320 +TrackWidthList 400 +TrackWidthList 640 +TrackClearence 60 +ZoneClearence 75 +TrackMinWidth 2 +DrawSegmWidth 70 +EdgeSegmWidth 40 +ViaSize 218 +ViaDrill 118 +ViaMinSize 3 +ViaMinDrill 39 +ViaSizeList 118 39 +ViaSizeList 157 79 +ViaSizeList 157 118 +ViaSizeList 218 118 +ViaSizeList 350 236 +MicroViaSize 200 +MicroViaDrill 50 +MicroViasAllowed 0 +MicroViaMinSize 8 +MicroViaMinDrill 50 +TextPcbWidth 120 +TextPcbSize 600 800 +EdgeModWidth 79 +TextModSize 600 600 +TextModWidth 120 +PadSize 512 512 +PadDrill 512 +Pad2MaskClearance 40 +AuxiliaryAxisOrg 0 0 +PcbPlotParams (pcbplotparams (layerselection 284983297) (usegerberextensions true) (excludeedgelayer true) (linewidth 79) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 0) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue false) (plotothertext false) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk true) (outputformat 1) (mirror false) (drillshape 2) (scaleselection 1) (outputdirectory "")) +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "+1.2V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "+1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "+2.5V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "+3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 5 "+3.3VDAC" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 6 "+5V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 7 "+5VL" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 8 "+BATT" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 9 "/Memory/RAM_/CE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 10 "/Memory/SRAM_Vcc" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 11 "/Power_Supply_/_Misc./LX12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 12 "/Power_Supply_/_Misc./LX33" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 13 "/RESET" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 14 "/SNES_Slot/SNES_EXT_/IRQ" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 15 "/SNES_Slot/SNES_EXT_/PARD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 16 "/SNES_Slot/SNES_EXT_/PAWR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 17 "/SNES_Slot/SNES_EXT_/RD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 18 "/SNES_Slot/SNES_EXT_/ROMSEL" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 19 "/SNES_Slot/SNES_EXT_/WR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 20 "/SNES_Slot/SNES_EXT_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 21 "/SNES_Slot/SNES_EXT_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 22 "/SNES_Slot/SNES_EXT_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 23 "/SNES_Slot/SNES_EXT_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 24 "/SNES_Slot/SNES_EXT_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 25 "/SNES_Slot/SNES_EXT_A13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 26 "/SNES_Slot/SNES_EXT_A14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 27 "/SNES_Slot/SNES_EXT_A15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 28 "/SNES_Slot/SNES_EXT_A16" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 29 "/SNES_Slot/SNES_EXT_A17" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 30 "/SNES_Slot/SNES_EXT_A18" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 31 "/SNES_Slot/SNES_EXT_A19" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 32 "/SNES_Slot/SNES_EXT_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 33 "/SNES_Slot/SNES_EXT_A20" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 34 "/SNES_Slot/SNES_EXT_A21" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 35 "/SNES_Slot/SNES_EXT_A22" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 36 "/SNES_Slot/SNES_EXT_A23" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 37 "/SNES_Slot/SNES_EXT_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 38 "/SNES_Slot/SNES_EXT_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 39 "/SNES_Slot/SNES_EXT_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 40 "/SNES_Slot/SNES_EXT_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 41 "/SNES_Slot/SNES_EXT_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 42 "/SNES_Slot/SNES_EXT_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 43 "/SNES_Slot/SNES_EXT_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 44 "/SNES_Slot/SNES_EXT_CPU_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 45 "/SNES_Slot/SNES_EXT_D0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 46 "/SNES_Slot/SNES_EXT_D1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 47 "/SNES_Slot/SNES_EXT_D2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 48 "/SNES_Slot/SNES_EXT_D3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 49 "/SNES_Slot/SNES_EXT_D4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 50 "/SNES_Slot/SNES_EXT_D5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 51 "/SNES_Slot/SNES_EXT_D6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 52 "/SNES_Slot/SNES_EXT_D7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 53 "/SNES_Slot/SNES_EXT_PA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 54 "/SNES_Slot/SNES_EXT_PA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 55 "/SNES_Slot/SNES_EXT_PA2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 56 "/SNES_Slot/SNES_EXT_PA3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 57 "/SNES_Slot/SNES_EXT_PA4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 58 "/SNES_Slot/SNES_EXT_PA5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 59 "/SNES_Slot/SNES_EXT_PA6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 60 "/SNES_Slot/SNES_EXT_PA7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 61 "/SNES_Slot/SNES_EXT_REFRESH" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 62 "/SNES_Slot/SNES_EXT_SYS_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 63 "/TRST" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 64 "/USEBATT" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 65 "AGND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 66 "AUDIO_L" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 67 "AUDIO_R" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 68 "CCLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 69 "CIC_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 70 "CIC_DATA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 71 "CIC_DATA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 72 "CIC_MCLR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 73 "CIC_RESET" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 74 "CIC_STATUS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 75 "DAC_/DEM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 76 "DAC_LRCK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 77 "DAC_MCLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 78 "DAC_SDIN" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 79 "DATABUS_/OE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 80 "DATABUS_DIR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 81 "DIN+MCU_/OVR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 82 "DONE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 83 "EXT_CIC_DATA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 84 "EXT_CIC_DATA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 85 "EXT_TDI" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 86 "EXT_TDO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 87 "FPGA_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 88 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 89 "INIT_B+MCU_IRQ" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 90 "MCU_SPARE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 91 "MCU_SPI_MISO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 92 "MCU_SPI_MOSI" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 93 "MCU_SPI_SCK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 94 "MCU_SPI_SS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 95 "N-000012" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 96 "N-000013" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 97 "N-000036" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 98 "N-000037" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 99 "N-000038" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 100 "N-000039" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 101 "N-000040" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 102 "N-000041" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 103 "N-000042" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 104 "N-000045" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 105 "N-000047" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 106 "N-000049" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 107 "N-000050" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 108 "N-000053" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 109 "N-000056" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 110 "N-000071" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 111 "N-000072" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 112 "N-000073" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 113 "N-000074" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 114 "N-000075" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 115 "N-000076" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 116 "N-000078" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 117 "N-000082" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 118 "N-000083" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 119 "N-000084" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 120 "N-000086" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 121 "N-000087" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 122 "N-000091" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 123 "N-000092" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 124 "N-000095" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 125 "N-000100" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 126 "N-000102" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 127 "N-000103" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 128 "N-000104" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 129 "N-000105" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 130 "N-000106" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 131 "N-000107" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 132 "N-000108" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 133 "N-000120" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 134 "N-000125" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 135 "N-000127" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 136 "N-000137" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 137 "N-000143" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 138 "N-000144" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 139 "N-000145" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 140 "N-000146" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 141 "N-000147" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 142 "N-000151" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 143 "N-000152" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 144 "N-000153" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 145 "N-000154" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 146 "N-000156" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 147 "N-000157" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 148 "N-000158" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 149 "N-000159" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 150 "N-000160" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 151 "N-000161" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 152 "N-000193" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 153 "N-000275" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 154 "N-000277" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 155 "N-000278" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 156 "N-000279" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 157 "N-000281" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 158 "N-000284" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 159 "N-000285" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 160 "N-000286" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 161 "N-000294" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 162 "N-000295" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 163 "N-000300" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 164 "N-000305" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 165 "N-000309" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 166 "N-000310" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 167 "N-000311" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 168 "N-000313" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 169 "N-000314" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 170 "N-000315" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 171 "N-000316" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 172 "N-000318" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 173 "N-000322" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 174 "N-000323" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 175 "N-000324" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 176 "N-000327" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 177 "N-000328" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 178 "N-000337" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 179 "N-000338" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 180 "N-000339" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 181 "N-000340" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 182 "N-000344" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 183 "P1_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 184 "P1_D0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 185 "P2.10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 186 "P2_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 187 "P2_D0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 188 "PROG_B" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 189 "P_LATCH" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 190 "RAM_/OE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 191 "RAM_/WE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 192 "RAM_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 193 "RAM_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 194 "RAM_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 195 "RAM_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 196 "RAM_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 197 "RAM_A13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 198 "RAM_A14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 199 "RAM_A15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 200 "RAM_A16" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 201 "RAM_A17" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 202 "RAM_A18" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 203 "RAM_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 204 "RAM_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 205 "RAM_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 206 "RAM_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 207 "RAM_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 208 "RAM_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 209 "RAM_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 210 "RAM_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 211 "RAM_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 212 "RAM_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 213 "RAM_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 214 "RAM_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 215 "RAM_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 216 "RAM_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 217 "RAM_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 218 "RAM_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 219 "ROM_/CE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 220 "ROM_/LB" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 221 "ROM_/OE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 222 "ROM_/UB" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 223 "ROM_/WE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 224 "ROM_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 225 "ROM_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 226 "ROM_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 227 "ROM_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 228 "ROM_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 229 "ROM_A13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 230 "ROM_A14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 231 "ROM_A15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 232 "ROM_A16" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 233 "ROM_A17" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 234 "ROM_A18" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 235 "ROM_A19" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 236 "ROM_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 237 "ROM_A20" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 238 "ROM_A21" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 239 "ROM_A22" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 240 "ROM_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 241 "ROM_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 242 "ROM_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 243 "ROM_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 244 "ROM_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 245 "ROM_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 246 "ROM_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 247 "ROM_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 248 "ROM_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 249 "ROM_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 250 "ROM_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 251 "ROM_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 252 "ROM_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 253 "ROM_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 254 "ROM_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 255 "ROM_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 256 "ROM_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 257 "ROM_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 258 "ROM_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 259 "ROM_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 260 "ROM_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 261 "ROM_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 262 "ROM_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 263 "RX0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 264 "RX3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 265 "SD_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 266 "SD_CMD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 267 "SD_DAT0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 268 "SD_DAT1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 269 "SD_DAT2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 270 "SD_DAT3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 271 "SNES_/PARD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 272 "SNES_/PAWR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 273 "SNES_/RD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 274 "SNES_/RESET" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 275 "SNES_/ROMSEL" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 276 "SNES_/WR" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 277 "SNES_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 278 "SNES_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 279 "SNES_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 280 "SNES_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 281 "SNES_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 282 "SNES_A13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 283 "SNES_A14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 284 "SNES_A15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 285 "SNES_A16" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 286 "SNES_A17" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 287 "SNES_A18" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 288 "SNES_A19" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 289 "SNES_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 290 "SNES_A20" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 291 "SNES_A21" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 292 "SNES_A22" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 293 "SNES_A23" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 294 "SNES_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 295 "SNES_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 296 "SNES_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 297 "SNES_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 298 "SNES_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 299 "SNES_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 300 "SNES_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 301 "SNES_CPU_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 302 "SNES_D0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 303 "SNES_D1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 304 "SNES_D2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 305 "SNES_D3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 306 "SNES_D4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 307 "SNES_D5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 308 "SNES_D6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 309 "SNES_D7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 310 "SNES_IRQ_EN" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 311 "SNES_PA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 312 "SNES_PA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 313 "SNES_PA2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 314 "SNES_PA3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 315 "SNES_PA4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 316 "SNES_PA5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 317 "SNES_PA6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 318 "SNES_PA7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 319 "SNES_REFRESH" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 320 "SNES_SYS_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 321 "TCK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 322 "TMS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 323 "TX0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 324 "TX3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 325 "USB_SWCONN" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 60 +TrackWidth 60 +ViaDia 218 +ViaDrill 118 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "+1.2V" +AddNet "+1.8V" +AddNet "+2.5V" +AddNet "+3.3V" +AddNet "+3.3VDAC" +AddNet "+5V" +AddNet "+5VL" +AddNet "+BATT" +AddNet "/Memory/RAM_/CE" +AddNet "/Memory/SRAM_Vcc" +AddNet "/Power_Supply_/_Misc./LX12" +AddNet "/Power_Supply_/_Misc./LX33" +AddNet "/RESET" +AddNet "/SNES_Slot/SNES_EXT_/IRQ" +AddNet "/SNES_Slot/SNES_EXT_/PARD" +AddNet "/SNES_Slot/SNES_EXT_/PAWR" +AddNet "/SNES_Slot/SNES_EXT_/RD" +AddNet "/SNES_Slot/SNES_EXT_/ROMSEL" +AddNet "/SNES_Slot/SNES_EXT_/WR" +AddNet "/SNES_Slot/SNES_EXT_A0" +AddNet "/SNES_Slot/SNES_EXT_A1" +AddNet "/SNES_Slot/SNES_EXT_A10" +AddNet "/SNES_Slot/SNES_EXT_A11" +AddNet "/SNES_Slot/SNES_EXT_A12" +AddNet "/SNES_Slot/SNES_EXT_A13" +AddNet "/SNES_Slot/SNES_EXT_A14" +AddNet "/SNES_Slot/SNES_EXT_A15" +AddNet "/SNES_Slot/SNES_EXT_A16" +AddNet "/SNES_Slot/SNES_EXT_A17" +AddNet "/SNES_Slot/SNES_EXT_A18" +AddNet "/SNES_Slot/SNES_EXT_A19" +AddNet "/SNES_Slot/SNES_EXT_A2" +AddNet "/SNES_Slot/SNES_EXT_A20" +AddNet "/SNES_Slot/SNES_EXT_A21" +AddNet "/SNES_Slot/SNES_EXT_A22" +AddNet "/SNES_Slot/SNES_EXT_A23" +AddNet "/SNES_Slot/SNES_EXT_A3" +AddNet "/SNES_Slot/SNES_EXT_A4" +AddNet "/SNES_Slot/SNES_EXT_A5" +AddNet "/SNES_Slot/SNES_EXT_A6" +AddNet "/SNES_Slot/SNES_EXT_A7" +AddNet "/SNES_Slot/SNES_EXT_A8" +AddNet "/SNES_Slot/SNES_EXT_A9" +AddNet "/SNES_Slot/SNES_EXT_CPU_CLK" +AddNet "/SNES_Slot/SNES_EXT_D0" +AddNet "/SNES_Slot/SNES_EXT_D1" +AddNet "/SNES_Slot/SNES_EXT_D2" +AddNet "/SNES_Slot/SNES_EXT_D3" +AddNet "/SNES_Slot/SNES_EXT_D4" +AddNet "/SNES_Slot/SNES_EXT_D5" +AddNet "/SNES_Slot/SNES_EXT_D6" +AddNet "/SNES_Slot/SNES_EXT_D7" +AddNet "/SNES_Slot/SNES_EXT_PA0" +AddNet "/SNES_Slot/SNES_EXT_PA1" +AddNet "/SNES_Slot/SNES_EXT_PA2" +AddNet "/SNES_Slot/SNES_EXT_PA3" +AddNet "/SNES_Slot/SNES_EXT_PA4" +AddNet "/SNES_Slot/SNES_EXT_PA5" +AddNet "/SNES_Slot/SNES_EXT_PA6" +AddNet "/SNES_Slot/SNES_EXT_PA7" +AddNet "/SNES_Slot/SNES_EXT_REFRESH" +AddNet "/SNES_Slot/SNES_EXT_SYS_CLK" +AddNet "/TRST" +AddNet "/USEBATT" +AddNet "AGND" +AddNet "AUDIO_L" +AddNet "AUDIO_R" +AddNet "CCLK" +AddNet "CIC_CLK" +AddNet "CIC_DATA0" +AddNet "CIC_DATA1" +AddNet "CIC_MCLR" +AddNet "CIC_RESET" +AddNet "CIC_STATUS" +AddNet "DAC_/DEM" +AddNet "DAC_LRCK" +AddNet "DAC_MCLK" +AddNet "DAC_SDIN" +AddNet "DATABUS_/OE" +AddNet "DATABUS_DIR" +AddNet "DIN+MCU_/OVR" +AddNet "DONE" +AddNet "EXT_CIC_DATA0" +AddNet "EXT_CIC_DATA1" +AddNet "EXT_TDI" +AddNet "EXT_TDO" +AddNet "FPGA_CLK" +AddNet "GND" +AddNet "INIT_B+MCU_IRQ" +AddNet "MCU_SPARE" +AddNet "MCU_SPI_MISO" +AddNet "MCU_SPI_MOSI" +AddNet "MCU_SPI_SCK" +AddNet "MCU_SPI_SS" +AddNet "N-000012" +AddNet "N-000013" +AddNet "N-000036" +AddNet "N-000037" +AddNet "N-000038" +AddNet "N-000039" +AddNet "N-000040" +AddNet "N-000041" +AddNet "N-000042" +AddNet "N-000045" +AddNet "N-000047" +AddNet "N-000049" +AddNet "N-000050" +AddNet "N-000053" +AddNet "N-000056" +AddNet "N-000071" +AddNet "N-000072" +AddNet "N-000073" +AddNet "N-000074" +AddNet "N-000075" +AddNet "N-000076" +AddNet "N-000078" +AddNet "N-000082" +AddNet "N-000083" +AddNet "N-000084" +AddNet "N-000086" +AddNet "N-000087" +AddNet "N-000091" +AddNet "N-000092" +AddNet "N-000095" +AddNet "N-000100" +AddNet "N-000102" +AddNet "N-000103" +AddNet "N-000104" +AddNet "N-000105" +AddNet "N-000106" +AddNet "N-000107" +AddNet "N-000108" +AddNet "N-000120" +AddNet "N-000125" +AddNet "N-000127" +AddNet "N-000137" +AddNet "N-000143" +AddNet "N-000144" +AddNet "N-000145" +AddNet "N-000146" +AddNet "N-000147" +AddNet "N-000151" +AddNet "N-000152" +AddNet "N-000153" +AddNet "N-000154" +AddNet "N-000156" +AddNet "N-000157" +AddNet "N-000158" +AddNet "N-000159" +AddNet "N-000160" +AddNet "N-000161" +AddNet "N-000193" +AddNet "N-000275" +AddNet "N-000277" +AddNet "N-000278" +AddNet "N-000279" +AddNet "N-000281" +AddNet "N-000284" +AddNet "N-000285" +AddNet "N-000286" +AddNet "N-000294" +AddNet "N-000295" +AddNet "N-000300" +AddNet "N-000305" +AddNet "N-000309" +AddNet "N-000310" +AddNet "N-000311" +AddNet "N-000313" +AddNet "N-000314" +AddNet "N-000315" +AddNet "N-000316" +AddNet "N-000318" +AddNet "N-000322" +AddNet "N-000323" +AddNet "N-000324" +AddNet "N-000327" +AddNet "N-000328" +AddNet "N-000337" +AddNet "N-000338" +AddNet "N-000339" +AddNet "N-000340" +AddNet "N-000344" +AddNet "P1_CLK" +AddNet "P1_D0" +AddNet "P2.10" +AddNet "P2_CLK" +AddNet "P2_D0" +AddNet "PROG_B" +AddNet "P_LATCH" +AddNet "RAM_/OE" +AddNet "RAM_/WE" +AddNet "RAM_A0" +AddNet "RAM_A1" +AddNet "RAM_A10" +AddNet "RAM_A11" +AddNet "RAM_A12" +AddNet "RAM_A13" +AddNet "RAM_A14" +AddNet "RAM_A15" +AddNet "RAM_A16" +AddNet "RAM_A17" +AddNet "RAM_A18" +AddNet "RAM_A2" +AddNet "RAM_A3" +AddNet "RAM_A4" +AddNet "RAM_A5" +AddNet "RAM_A6" +AddNet "RAM_A7" +AddNet "RAM_A8" +AddNet "RAM_A9" +AddNet "RAM_DQ0" +AddNet "RAM_DQ1" +AddNet "RAM_DQ2" +AddNet "RAM_DQ3" +AddNet "RAM_DQ4" +AddNet "RAM_DQ5" +AddNet "RAM_DQ6" +AddNet "RAM_DQ7" +AddNet "ROM_/CE" +AddNet "ROM_/LB" +AddNet "ROM_/OE" +AddNet "ROM_/UB" +AddNet "ROM_/WE" +AddNet "ROM_A0" +AddNet "ROM_A1" +AddNet "ROM_A10" +AddNet "ROM_A11" +AddNet "ROM_A12" +AddNet "ROM_A13" +AddNet "ROM_A14" +AddNet "ROM_A15" +AddNet "ROM_A16" +AddNet "ROM_A17" +AddNet "ROM_A18" +AddNet "ROM_A19" +AddNet "ROM_A2" +AddNet "ROM_A20" +AddNet "ROM_A21" +AddNet "ROM_A22" +AddNet "ROM_A3" +AddNet "ROM_A4" +AddNet "ROM_A5" +AddNet "ROM_A6" +AddNet "ROM_A7" +AddNet "ROM_A8" +AddNet "ROM_A9" +AddNet "ROM_DQ0" +AddNet "ROM_DQ1" +AddNet "ROM_DQ10" +AddNet "ROM_DQ11" +AddNet "ROM_DQ12" +AddNet "ROM_DQ13" +AddNet "ROM_DQ14" +AddNet "ROM_DQ15" +AddNet "ROM_DQ2" +AddNet "ROM_DQ3" +AddNet "ROM_DQ4" +AddNet "ROM_DQ5" +AddNet "ROM_DQ6" +AddNet "ROM_DQ7" +AddNet "ROM_DQ8" +AddNet "ROM_DQ9" +AddNet "RX0" +AddNet "RX3" +AddNet "SD_CLK" +AddNet "SD_CMD" +AddNet "SD_DAT0" +AddNet "SD_DAT1" +AddNet "SD_DAT2" +AddNet "SD_DAT3" +AddNet "SNES_/PARD" +AddNet "SNES_/PAWR" +AddNet "SNES_/RD" +AddNet "SNES_/RESET" +AddNet "SNES_/ROMSEL" +AddNet "SNES_/WR" +AddNet "SNES_A0" +AddNet "SNES_A1" +AddNet "SNES_A10" +AddNet "SNES_A11" +AddNet "SNES_A12" +AddNet "SNES_A13" +AddNet "SNES_A14" +AddNet "SNES_A15" +AddNet "SNES_A16" +AddNet "SNES_A17" +AddNet "SNES_A18" +AddNet "SNES_A19" +AddNet "SNES_A2" +AddNet "SNES_A20" +AddNet "SNES_A21" +AddNet "SNES_A22" +AddNet "SNES_A23" +AddNet "SNES_A3" +AddNet "SNES_A4" +AddNet "SNES_A5" +AddNet "SNES_A6" +AddNet "SNES_A7" +AddNet "SNES_A8" +AddNet "SNES_A9" +AddNet "SNES_CPU_CLK" +AddNet "SNES_D0" +AddNet "SNES_D1" +AddNet "SNES_D2" +AddNet "SNES_D3" +AddNet "SNES_D4" +AddNet "SNES_D5" +AddNet "SNES_D6" +AddNet "SNES_D7" +AddNet "SNES_IRQ_EN" +AddNet "SNES_PA0" +AddNet "SNES_PA1" +AddNet "SNES_PA2" +AddNet "SNES_PA3" +AddNet "SNES_PA4" +AddNet "SNES_PA5" +AddNet "SNES_PA6" +AddNet "SNES_PA7" +AddNet "SNES_REFRESH" +AddNet "SNES_SYS_CLK" +AddNet "TCK" +AddNet "TMS" +AddNet "TX0" +AddNet "TX3" +AddNet "USB_SWCONN" +$EndNCLASS +$NCLASS +Name "Power" +Desc "" +Clearance 80 +TrackWidth 320 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +$EndNCLASS +$NCLASS +Name "Small" +Desc "" +Clearance 60 +TrackWidth 60 +ViaDia 218 +ViaDrill 118 +uViaDia 200 +uViaDrill 50 +$EndNCLASS +$MODULE GS2 +Po 48250 27475 0 15 4E2C1983 4E2C1883 ~~ +Li GS2 +Cd Pontet Goute de soudure +Sc 4E2C1883 +AR /4B6ED75B/4E2C1796 +Op 0 0 0 +At VIRTUAL +T0 725 -400 320 320 900 70 N V 21 N "JP402" +T1 600 0 300 300 900 50 N I 21 N "JUMPER" +DS -350 -500 -350 500 80 21 +DS 350 500 350 -500 80 21 +DS 350 500 -350 500 80 21 +DS -350 -500 350 -500 80 21 +$PAD +Sh "1" R 500 380 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 -250 +$EndPAD +$PAD +Sh "2" R 500 380 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 64 "/USEBATT" +Po 0 250 +$EndPAD +$EndMODULE GS2 +$MODULE SOT23-5_LARGEPADS +Po 73645 39358 900 15 4EF902D7 4B6ED33B ~~ +Li SOT23-5_LARGEPADS +Cd SOT23-5 +Sc 4B6ED33B +AR /4B6EC9C3/4B6ED134 +Op 0 0 0 +At SMD +T0 -1367 55 300 320 1800 70 N V 21 N "U321" +T1 972 95 300 320 1800 70 N I 21 N "MCP1824-2502E/OT" +DS 600 -350 600 350 80 21 +DS 600 350 -600 350 80 21 +DS -600 350 -600 -350 80 21 +DS -600 -350 600 -350 80 21 +$PAD +Sh "1" R 272 390 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 272 390 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 272 390 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 272 390 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 272 390 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5_LARGEPADS +$MODULE SOT23-5_LARGEPADS +Po 74980 28135 0 15 4E2AAECC 4B6ED33D ~~ +Li SOT23-5_LARGEPADS +Cd SOT23-5 +Sc 4B6ED33D +AR /4B6EC9C3/4B6ED144 +Op 0 0 0 +At SMD +T0 926 -25 300 320 900 70 N V 21 N "U311" +T1 -3169 290 300 320 0 70 N I 21 N "MCP1824-1802E/OT" +DS 600 -350 600 350 80 21 +DS 600 350 -600 350 80 21 +DS -600 350 -600 -350 80 21 +DS -600 -350 600 -350 80 21 +$PAD +Sh "1" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "+1.8V" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5_LARGEPADS +$MODULE pin_array_3x2 +Po 40615 24860 0 15 4E13735B 4DF9FBE1 ~~ +Li pin_array_3x2 +Cd Double rangee de contacts 2 x 4 pins +Kw CONN +Sc 4DF9FBE1 +AR /4B6ED75B/4DF9F6C8 +Op 0 0 0 +T0 2225 905 320 320 0 70 N V 21 N "P404" +T1 10 1965 400 400 0 80 N I 21 N "CONN_3X2" +DS -1500 -1000 -1610 -1000 118 21 +DS -1610 -1000 -1610 1000 118 21 +DS -1610 1000 -1490 1000 118 21 +DS -1496 0 -472 0 118 21 +DS -472 0 -472 984 118 21 +DS 1500 1000 -1500 1000 118 21 +DS -1500 -1000 1500 -1000 118 21 +DS 1500 -1000 1500 1000 118 21 +DS -1500 1000 -1500 -1000 118 21 +$PAD +Sh "1" R 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 184 "P1_D0" +Po -1000 500 +$EndPAD +$PAD +Sh "2" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 183 "P1_CLK" +Po -1000 -500 +$EndPAD +$PAD +Sh "3" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 189 "P_LATCH" +Po 0 500 +$EndPAD +$PAD +Sh "4" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 90 "MCU_SPARE" +Po 0 -500 +$EndPAD +$PAD +Sh "5" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 186 "P2_CLK" +Po 1000 500 +$EndPAD +$PAD +Sh "6" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 187 "P2_D0" +Po 1000 -500 +$EndPAD +$SHAPE3D +Na "pin_array/pins_array_3x2.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE pin_array_3x2 +$MODULE TSSOP48 +Po 54050 46100 0 15 4C5931A1 4BEDD157 ~~ +Li TSSOP48 +Sc 4BEDD157 +AR /4B6E16F2/4B6E1740 +Op 0 0 0 +T0 1800 2250 320 320 0 70 N V 21 N "U101" +T1 5 435 320 320 0 70 N V 21 N "74ALVC164245DGG" +DC -2205 945 -2087 945 75 21 +DS -2460 -1200 2460 -1200 75 21 +DS 2460 -1200 2460 1200 75 21 +DS -2460 1200 2460 1200 75 21 +DS -2460 -1200 -2460 1200 75 21 +$PAD +Sh "1" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 1535 +$EndPAD +$PAD +Sh "2" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 126 "N-000102" +Po -2066 1535 +$EndPAD +$PAD +Sh "3" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 123 "N-000092" +Po -1870 1535 +$EndPAD +$PAD +Sh "4" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 1535 +$EndPAD +$PAD +Sh "5" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 127 "N-000103" +Po -1476 1535 +$EndPAD +$PAD +Sh "6" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 128 "N-000104" +Po -1279 1535 +$EndPAD +$PAD +Sh "7" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -1082 1535 +$EndPAD +$PAD +Sh "8" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 129 "N-000105" +Po -885 1535 +$EndPAD +$PAD +Sh "9" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 130 "N-000106" +Po -688 1535 +$EndPAD +$PAD +Sh "10" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 1535 +$EndPAD +$PAD +Sh "11" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 96 "N-000013" +Po -295 1535 +$EndPAD +$PAD +Sh "12" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 138 "N-000144" +Po -98 1535 +$EndPAD +$PAD +Sh "13" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000074" +Po 98 1535 +$EndPAD +$PAD +Sh "14" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 116 "N-000078" +Po 295 1535 +$EndPAD +$PAD +Sh "15" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 1535 +$EndPAD +$PAD +Sh "16" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 110 "N-000071" +Po 688 1535 +$EndPAD +$PAD +Sh "17" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 120 "N-000086" +Po 885 1535 +$EndPAD +$PAD +Sh "18" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po 1082 1535 +$EndPAD +$PAD +Sh "19" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 122 "N-000091" +Po 1279 1535 +$EndPAD +$PAD +Sh "20" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 131 "N-000107" +Po 1476 1535 +$EndPAD +$PAD +Sh "21" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 1535 +$EndPAD +$PAD +Sh "22" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "N-000072" +Po 1870 1535 +$EndPAD +$PAD +Sh "23" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000075" +Po 2066 1535 +$EndPAD +$PAD +Sh "24" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 80 "DATABUS_DIR" +Po 2263 1535 +$EndPAD +$PAD +Sh "25" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 79 "DATABUS_/OE" +Po 2263 -1535 +$EndPAD +$PAD +Sh "26" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 118 "N-000083" +Po 2066 -1535 +$EndPAD +$PAD +Sh "27" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 121 "N-000087" +Po 1870 -1535 +$EndPAD +$PAD +Sh "28" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 -1535 +$EndPAD +$PAD +Sh "29" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 139 "N-000145" +Po 1476 -1535 +$EndPAD +$PAD +Sh "30" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 132 "N-000108" +Po 1279 -1535 +$EndPAD +$PAD +Sh "31" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1082 -1535 +$EndPAD +$PAD +Sh "32" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 112 "N-000073" +Po 885 -1535 +$EndPAD +$PAD +Sh "33" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 115 "N-000076" +Po 688 -1535 +$EndPAD +$PAD +Sh "34" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 -1535 +$EndPAD +$PAD +Sh "35" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 117 "N-000082" +Po 295 -1535 +$EndPAD +$PAD +Sh "36" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 119 "N-000084" +Po 98 -1535 +$EndPAD +$PAD +Sh "37" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 301 "SNES_CPU_CLK" +Po -98 -1535 +$EndPAD +$PAD +Sh "38" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 276 "SNES_/WR" +Po -295 -1535 +$EndPAD +$PAD +Sh "39" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 -1535 +$EndPAD +$PAD +Sh "40" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 312 "SNES_PA1" +Po -688 -1535 +$EndPAD +$PAD +Sh "41" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 311 "SNES_PA0" +Po -885 -1535 +$EndPAD +$PAD +Sh "42" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1082 -1535 +$EndPAD +$PAD +Sh "43" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 314 "SNES_PA3" +Po -1279 -1535 +$EndPAD +$PAD +Sh "44" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 313 "SNES_PA2" +Po -1476 -1535 +$EndPAD +$PAD +Sh "45" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 -1535 +$EndPAD +$PAD +Sh "46" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "SNES_PA5" +Po -1870 -1535 +$EndPAD +$PAD +Sh "47" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 315 "SNES_PA4" +Po -2066 -1535 +$EndPAD +$PAD +Sh "48" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 -1535 +$EndPAD +$EndMODULE TSSOP48 +$MODULE TSSOP48 +Po 65550 44850 0 15 4C59321C 4BEDD1A3 ~~ +Li TSSOP48 +Sc 4BEDD1A3 +AR /4B6E16F2/4B6E1748 +Op 0 0 0 +T0 3125 1775 320 320 0 70 N V 21 N "U103" +T1 1 386 320 320 0 70 N V 21 N "74ALVC164245DGG" +DC -2205 945 -2087 945 75 21 +DS -2460 -1200 2460 -1200 75 21 +DS 2460 -1200 2460 1200 75 21 +DS -2460 1200 2460 1200 75 21 +DS -2460 -1200 -2460 1200 75 21 +$PAD +Sh "1" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 1535 +$EndPAD +$PAD +Sh "2" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 134 "N-000125" +Po -2066 1535 +$EndPAD +$PAD +Sh "3" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 133 "N-000120" +Po -1870 1535 +$EndPAD +$PAD +Sh "4" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 1535 +$EndPAD +$PAD +Sh "5" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "N-000127" +Po -1476 1535 +$EndPAD +$PAD +Sh "6" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 136 "N-000137" +Po -1279 1535 +$EndPAD +$PAD +Sh "7" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -1082 1535 +$EndPAD +$PAD +Sh "8" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "N-000161" +Po -885 1535 +$EndPAD +$PAD +Sh "9" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 150 "N-000160" +Po -688 1535 +$EndPAD +$PAD +Sh "10" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 1535 +$EndPAD +$PAD +Sh "11" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 149 "N-000159" +Po -295 1535 +$EndPAD +$PAD +Sh "12" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 140 "N-000146" +Po -98 1535 +$EndPAD +$PAD +Sh "13" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 148 "N-000158" +Po 98 1535 +$EndPAD +$PAD +Sh "14" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 147 "N-000157" +Po 295 1535 +$EndPAD +$PAD +Sh "15" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 1535 +$EndPAD +$PAD +Sh "16" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 146 "N-000156" +Po 688 1535 +$EndPAD +$PAD +Sh "17" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 142 "N-000151" +Po 885 1535 +$EndPAD +$PAD +Sh "18" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po 1082 1535 +$EndPAD +$PAD +Sh "19" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 143 "N-000152" +Po 1279 1535 +$EndPAD +$PAD +Sh "20" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 144 "N-000153" +Po 1476 1535 +$EndPAD +$PAD +Sh "21" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 1535 +$EndPAD +$PAD +Sh "22" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 145 "N-000154" +Po 1870 1535 +$EndPAD +$PAD +Sh "23" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" +Po 2066 1535 +$EndPAD +$PAD +Sh "24" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2263 1535 +$EndPAD +$PAD +Sh "25" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2263 -1535 +$EndPAD +$PAD +Sh "26" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 320 "SNES_SYS_CLK" +Po 2066 -1535 +$EndPAD +$PAD +Sh "27" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 319 "SNES_REFRESH" +Po 1870 -1535 +$EndPAD +$PAD +Sh "28" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 -1535 +$EndPAD +$PAD +Sh "29" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "SNES_PA7" +Po 1476 -1535 +$EndPAD +$PAD +Sh "30" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "SNES_PA6" +Po 1279 -1535 +$EndPAD +$PAD +Sh "31" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1082 -1535 +$EndPAD +$PAD +Sh "32" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 272 "SNES_/PAWR" +Po 885 -1535 +$EndPAD +$PAD +Sh "33" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 271 "SNES_/PARD" +Po 688 -1535 +$EndPAD +$PAD +Sh "34" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 -1535 +$EndPAD +$PAD +Sh "35" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 280 "SNES_A11" +Po 295 -1535 +$EndPAD +$PAD +Sh "36" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 281 "SNES_A12" +Po 98 -1535 +$EndPAD +$PAD +Sh "37" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 279 "SNES_A10" +Po -98 -1535 +$EndPAD +$PAD +Sh "38" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 282 "SNES_A13" +Po -295 -1535 +$EndPAD +$PAD +Sh "39" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 -1535 +$EndPAD +$PAD +Sh "40" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 300 "SNES_A9" +Po -688 -1535 +$EndPAD +$PAD +Sh "41" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 283 "SNES_A14" +Po -885 -1535 +$EndPAD +$PAD +Sh "42" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1082 -1535 +$EndPAD +$PAD +Sh "43" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 299 "SNES_A8" +Po -1279 -1535 +$EndPAD +$PAD +Sh "44" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 284 "SNES_A15" +Po -1476 -1535 +$EndPAD +$PAD +Sh "45" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 -1535 +$EndPAD +$PAD +Sh "46" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 298 "SNES_A7" +Po -1870 -1535 +$EndPAD +$PAD +Sh "47" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 285 "SNES_A16" +Po -2066 -1535 +$EndPAD +$PAD +Sh "48" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 -1535 +$EndPAD +$EndMODULE TSSOP48 +$MODULE TSSOP48 +Po 59850 46100 0 15 4C5931C0 4BEDD19A ~~ +Li TSSOP48 +Sc 4BEDD19A +AR /4B6E16F2/4B6E1744 +Op 0 0 0 +T0 1825 2250 320 320 0 70 N V 21 N "U102" +T1 -7 435 320 320 0 70 N V 21 N "74ALVC164245DGG" +DC -2205 945 -2087 945 75 21 +DS -2460 -1200 2460 -1200 75 21 +DS 2460 -1200 2460 1200 75 21 +DS -2460 1200 2460 1200 75 21 +DS -2460 -1200 -2460 1200 75 21 +$PAD +Sh "1" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 1535 +$EndPAD +$PAD +Sh "2" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 95 "N-000012" +Po -2066 1535 +$EndPAD +$PAD +Sh "3" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 137 "N-000143" +Po -1870 1535 +$EndPAD +$PAD +Sh "4" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 1535 +$EndPAD +$PAD +Sh "5" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 99 "N-000038" +Po -1476 1535 +$EndPAD +$PAD +Sh "6" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 100 "N-000039" +Po -1279 1535 +$EndPAD +$PAD +Sh "7" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -1082 1535 +$EndPAD +$PAD +Sh "8" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 101 "N-000040" +Po -885 1535 +$EndPAD +$PAD +Sh "9" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 102 "N-000041" +Po -688 1535 +$EndPAD +$PAD +Sh "10" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 1535 +$EndPAD +$PAD +Sh "11" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 104 "N-000045" +Po -295 1535 +$EndPAD +$PAD +Sh "12" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 105 "N-000047" +Po -98 1535 +$EndPAD +$PAD +Sh "13" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 106 "N-000049" +Po 98 1535 +$EndPAD +$PAD +Sh "14" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 108 "N-000053" +Po 295 1535 +$EndPAD +$PAD +Sh "15" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 1535 +$EndPAD +$PAD +Sh "16" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 109 "N-000056" +Po 688 1535 +$EndPAD +$PAD +Sh "17" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 124 "N-000095" +Po 885 1535 +$EndPAD +$PAD +Sh "18" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po 1082 1535 +$EndPAD +$PAD +Sh "19" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 125 "N-000100" +Po 1279 1535 +$EndPAD +$PAD +Sh "20" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "N-000042" +Po 1476 1535 +$EndPAD +$PAD +Sh "21" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 1535 +$EndPAD +$PAD +Sh "22" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 98 "N-000037" +Po 1870 1535 +$EndPAD +$PAD +Sh "23" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 107 "N-000050" +Po 2066 1535 +$EndPAD +$PAD +Sh "24" R 118 472 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2263 1535 +$EndPAD +$PAD +Sh "25" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2263 -1535 +$EndPAD +$PAD +Sh "26" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 297 "SNES_A6" +Po 2066 -1535 +$EndPAD +$PAD +Sh "27" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 286 "SNES_A17" +Po 1870 -1535 +$EndPAD +$PAD +Sh "28" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1673 -1535 +$EndPAD +$PAD +Sh "29" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 296 "SNES_A5" +Po 1476 -1535 +$EndPAD +$PAD +Sh "30" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 287 "SNES_A18" +Po 1279 -1535 +$EndPAD +$PAD +Sh "31" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1082 -1535 +$EndPAD +$PAD +Sh "32" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 295 "SNES_A4" +Po 885 -1535 +$EndPAD +$PAD +Sh "33" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 288 "SNES_A19" +Po 688 -1535 +$EndPAD +$PAD +Sh "34" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 492 -1535 +$EndPAD +$PAD +Sh "35" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 294 "SNES_A3" +Po 295 -1535 +$EndPAD +$PAD +Sh "36" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "SNES_A20" +Po 98 -1535 +$EndPAD +$PAD +Sh "37" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 289 "SNES_A2" +Po -98 -1535 +$EndPAD +$PAD +Sh "38" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 291 "SNES_A21" +Po -295 -1535 +$EndPAD +$PAD +Sh "39" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -492 -1535 +$EndPAD +$PAD +Sh "40" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 278 "SNES_A1" +Po -688 -1535 +$EndPAD +$PAD +Sh "41" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "SNES_A22" +Po -885 -1535 +$EndPAD +$PAD +Sh "42" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1082 -1535 +$EndPAD +$PAD +Sh "43" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 277 "SNES_A0" +Po -1279 -1535 +$EndPAD +$PAD +Sh "44" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 293 "SNES_A23" +Po -1476 -1535 +$EndPAD +$PAD +Sh "45" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1673 -1535 +$EndPAD +$PAD +Sh "46" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 275 "SNES_/ROMSEL" +Po -1870 -1535 +$EndPAD +$PAD +Sh "47" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 273 "SNES_/RD" +Po -2066 -1535 +$EndPAD +$PAD +Sh "48" R 118 472 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2263 -1535 +$EndPAD +$EndMODULE TSSOP48 +$MODULE LQFP80-.5 +Po 48075 33300 2700 15 4C5944B7 4BF3E245 ~~ +Li LQFP80-.5 +Sc 4BF3E245 +AR /4B6ED75B/4B6F321A +Op 0 0 0 +T0 2950 -2700 320 320 3600 70 N V 21 N "U401" +T1 0 0 320 320 2700 70 N V 21 N "LPC1754" +DC -2047 2047 -1929 2008 75 21 +DS -2263 -2263 2263 -2263 75 21 +DS 2263 -2263 2263 2263 75 21 +DS -2263 2263 2263 2263 75 21 +DS -2263 -2263 -2263 2263 75 21 +$PAD +Sh "1" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "EXT_TDO" +Po -1870 2755 +$EndPAD +$PAD +Sh "2" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 85 "EXT_TDI" +Po -1673 2755 +$EndPAD +$PAD +Sh "3" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 322 "TMS" +Po -1476 2755 +$EndPAD +$PAD +Sh "4" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 63 "/TRST" +Po -1279 2755 +$EndPAD +$PAD +Sh "5" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 321 "TCK" +Po -1082 2755 +$EndPAD +$PAD +Sh "6" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 264 "RX3" +Po -885 2755 +$EndPAD +$PAD +Sh "7" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 324 "TX3" +Po -688 2755 +$EndPAD +$PAD +Sh "8" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -492 2755 +$EndPAD +$PAD +Sh "9" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -295 2755 +$EndPAD +$PAD +Sh "10" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -98 2755 +$EndPAD +$PAD +Sh "11" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 2755 +$EndPAD +$PAD +Sh "12" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 295 2755 +$EndPAD +$PAD +Sh "13" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 178 "N-000337" +Po 492 2755 +$EndPAD +$PAD +Sh "14" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/RESET" +Po 688 2755 +$EndPAD +$PAD +Sh "15" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 179 "N-000338" +Po 885 2755 +$EndPAD +$PAD +Sh "16" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "+BATT" +Po 1082 2755 +$EndPAD +$PAD +Sh "17" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1279 2755 +$EndPAD +$PAD +Sh "18" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 177 "N-000328" +Po 1476 2755 +$EndPAD +$PAD +Sh "19" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 180 "N-000339" +Po 1673 2755 +$EndPAD +$PAD +Sh "20" R 98 590 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 181 "N-000340" +Po 1870 2755 +$EndPAD +$PAD +Sh "21" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 2755 1870 +$EndPAD +$PAD +Sh "22" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 165 "N-000309" +Po 2755 1673 +$EndPAD +$PAD +Sh "23" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 169 "N-000314" +Po 2755 1476 +$EndPAD +$PAD +Sh "24" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2755 1279 +$EndPAD +$PAD +Sh "25" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 168 "N-000313" +Po 2755 1082 +$EndPAD +$PAD +Sh "26" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2755 885 +$EndPAD +$PAD +Sh "27" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2755 688 +$EndPAD +$PAD +Sh "28" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2755 492 +$EndPAD +$PAD +Sh "29" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 174 "N-000323" +Po 2755 295 +$EndPAD +$PAD +Sh "30" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 75 "DAC_/DEM" +Po 2755 98 +$EndPAD +$PAD +Sh "31" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 163 "N-000300" +Po 2755 -98 +$EndPAD +$PAD +Sh "32" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 274 "SNES_/RESET" +Po 2755 -295 +$EndPAD +$PAD +Sh "33" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2755 -492 +$EndPAD +$PAD +Sh "34" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 2755 -688 +$EndPAD +$PAD +Sh "35" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2755 -885 +$EndPAD +$PAD +Sh "36" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 74 "CIC_STATUS" +Po 2755 -1082 +$EndPAD +$PAD +Sh "37" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 71 "CIC_DATA1" +Po 2755 -1279 +$EndPAD +$PAD +Sh "38" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 70 "CIC_DATA0" +Po 2755 -1476 +$EndPAD +$PAD +Sh "39" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "FPGA_CLK" +Po 2755 -1673 +$EndPAD +$PAD +Sh "40" R 98 590 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 176 "N-000327" +Po 2755 -1870 +$EndPAD +$PAD +Sh "41" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "P2.10" +Po 1870 -2755 +$EndPAD +$PAD +Sh "42" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1673 -2755 +$EndPAD +$PAD +Sh "43" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1476 -2755 +$EndPAD +$PAD +Sh "44" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 82 "DONE" +Po 1279 -2755 +$EndPAD +$PAD +Sh "45" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 92 "MCU_SPI_MOSI" +Po 1082 -2755 +$EndPAD +$PAD +Sh "46" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 91 "MCU_SPI_MISO" +Po 885 -2755 +$EndPAD +$PAD +Sh "47" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 93 "MCU_SPI_SCK" +Po 688 -2755 +$EndPAD +$PAD +Sh "48" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 94 "MCU_SPI_SS" +Po 492 -2755 +$EndPAD +$PAD +Sh "49" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 89 "INIT_B+MCU_IRQ" +Po 295 -2755 +$EndPAD +$PAD +Sh "50" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 81 "DIN+MCU_/OVR" +Po 98 -2755 +$EndPAD +$PAD +Sh "51" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 -2755 +$EndPAD +$PAD +Sh "52" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -295 -2755 +$EndPAD +$PAD +Sh "53" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 173 "N-000322" +Po -492 -2755 +$EndPAD +$PAD +Sh "54" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 161 "N-000294" +Po -688 -2755 +$EndPAD +$PAD +Sh "55" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 270 "SD_DAT3" +Po -885 -2755 +$EndPAD +$PAD +Sh "56" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1082 -2755 +$EndPAD +$PAD +Sh "57" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1279 -2755 +$EndPAD +$PAD +Sh "58" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "SD_DAT2" +Po -1476 -2755 +$EndPAD +$PAD +Sh "59" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 268 "SD_DAT1" +Po -1673 -2755 +$EndPAD +$PAD +Sh "60" R 98 590 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 267 "SD_DAT0" +Po -1870 -2755 +$EndPAD +$PAD +Sh "61" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 266 "SD_CMD" +Po -2755 -1870 +$EndPAD +$PAD +Sh "62" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 172 "N-000318" +Po -2755 -1673 +$EndPAD +$PAD +Sh "63" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 265 "SD_CLK" +Po -2755 -1476 +$EndPAD +$PAD +Sh "64" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 162 "N-000295" +Po -2755 -1279 +$EndPAD +$PAD +Sh "65" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 325 "USB_SWCONN" +Po -2755 -1082 +$EndPAD +$PAD +Sh "66" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2755 -885 +$EndPAD +$PAD +Sh "67" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -2755 -688 +$EndPAD +$PAD +Sh "68" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2755 -492 +$EndPAD +$PAD +Sh "69" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 175 "N-000324" +Po -2755 -295 +$EndPAD +$PAD +Sh "70" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 64 "/USEBATT" +Po -2755 -98 +$EndPAD +$PAD +Sh "71" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 187 "P2_D0" +Po -2755 98 +$EndPAD +$PAD +Sh "72" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 186 "P2_CLK" +Po -2755 295 +$EndPAD +$PAD +Sh "73" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 90 "MCU_SPARE" +Po -2755 492 +$EndPAD +$PAD +Sh "74" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 189 "P_LATCH" +Po -2755 688 +$EndPAD +$PAD +Sh "75" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 183 "P1_CLK" +Po -2755 885 +$EndPAD +$PAD +Sh "76" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 184 "P1_D0" +Po -2755 1082 +$EndPAD +$PAD +Sh "77" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -2755 1279 +$EndPAD +$PAD +Sh "78" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2755 1476 +$EndPAD +$PAD +Sh "79" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 323 "TX0" +Po -2755 1673 +$EndPAD +$PAD +Sh "80" R 98 590 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 263 "RX0" +Po -2755 1870 +$EndPAD +$EndMODULE LQFP80-.5 +$MODULE PQFP208 +Po 62400 34950 0 15 4EF8EF11 4B6E26C2 ~~ +Li PQFP208 +Cd Module cms PQFP 208 pins +Kw PQFP CMS +Sc 4B6E26C2 +AR /4B6E18FC/4B6E1931 +Op 0 0 0 +At SMD +T0 6000 6225 320 320 0 70 N V 21 N "U201" +T1 2 11 320 320 0 70 N V 21 N "XC3S400-PQ208" +DS 0 -5512 -5512 -5512 75 21 +DS -5512 -5512 -5512 0 75 21 +DS -5512 0 -5512 5512 75 21 +DS -5512 5512 0 5512 75 21 +DS 0 5512 5512 5512 75 21 +DS 5512 5512 5512 0 75 21 +DS 5512 0 5512 -5512 75 21 +DS 5512 -5512 0 -5512 75 21 +T2 5350 -6100 600 400 0 80 N V 21 N "1" +DC 4750 -4700 4750 -5050 75 21 +$PAD +Sh "1" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 5023 -6100 +$EndPAD +$PAD +Sh "2" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 228 "ROM_A12" +Po 4826 -6100 +$EndPAD +$PAD +Sh "3" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 234 "ROM_A18" +Po 4629 -6100 +$EndPAD +$PAD +Sh "4" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "ROM_A19" +Po 4432 -6100 +$EndPAD +$PAD +Sh "5" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 254 "ROM_DQ15" +Po 4235 -6100 +$EndPAD +$PAD +Sh "6" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 4038 -6100 +$EndPAD +$PAD +Sh "7" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 252 "ROM_DQ13" +Po 3841 -6100 +$EndPAD +$PAD +Sh "8" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 3644 -6100 +$EndPAD +$PAD +Sh "9" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 253 "ROM_DQ14" +Po 3447 -6100 +$EndPAD +$PAD +Sh "10" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 251 "ROM_DQ12" +Po 3250 -6100 +$EndPAD +$PAD +Sh "11" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 233 "ROM_A17" +Po 3053 -6100 +$EndPAD +$PAD +Sh "12" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 250 "ROM_DQ11" +Po 2856 -6100 +$EndPAD +$PAD +Sh "13" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 262 "ROM_DQ9" +Po 2659 -6100 +$EndPAD +$PAD +Sh "14" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2462 -6100 +$EndPAD +$PAD +Sh "15" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "ROM_DQ10" +Po 2265 -6100 +$EndPAD +$PAD +Sh "16" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 261 "ROM_DQ8" +Po 2068 -6100 +$EndPAD +$PAD +Sh "17" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1871 -6100 +$EndPAD +$PAD +Sh "18" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 242 "ROM_A5" +Po 1674 -6100 +$EndPAD +$PAD +Sh "19" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 214 "RAM_DQ3" +Po 1477 -6100 +$EndPAD +$PAD +Sh "20" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 213 "RAM_DQ2" +Po 1280 -6100 +$EndPAD +$PAD +Sh "21" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 215 "RAM_DQ4" +Po 1083 -6100 +$EndPAD +$PAD +Sh "22" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 212 "RAM_DQ1" +Po 886 -6100 +$EndPAD +$PAD +Sh "23" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 689 -6100 +$EndPAD +$PAD +Sh "24" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 216 "RAM_DQ5" +Po 492 -6100 +$EndPAD +$PAD +Sh "25" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 295 -6100 +$EndPAD +$PAD +Sh "26" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 211 "RAM_DQ0" +Po 98 -6100 +$EndPAD +$PAD +Sh "27" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 217 "RAM_DQ6" +Po -99 -6100 +$EndPAD +$PAD +Sh "28" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 192 "RAM_A0" +Po -296 -6100 +$EndPAD +$PAD +Sh "29" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 218 "RAM_DQ7" +Po -493 -6100 +$EndPAD +$PAD +Sh "30" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -690 -6100 +$EndPAD +$PAD +Sh "31" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 193 "RAM_A1" +Po -887 -6100 +$EndPAD +$PAD +Sh "32" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1084 -6100 +$EndPAD +$PAD +Sh "33" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 203 "RAM_A2" +Po -1281 -6100 +$EndPAD +$PAD +Sh "34" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 194 "RAM_A10" +Po -1478 -6100 +$EndPAD +$PAD +Sh "35" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 204 "RAM_A3" +Po -1675 -6100 +$EndPAD +$PAD +Sh "36" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 190 "RAM_/OE" +Po -1872 -6100 +$EndPAD +$PAD +Sh "37" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 205 "RAM_A4" +Po -2069 -6100 +$EndPAD +$PAD +Sh "38" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2266 -6100 +$EndPAD +$PAD +Sh "39" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 195 "RAM_A11" +Po -2463 -6100 +$EndPAD +$PAD +Sh "40" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 206 "RAM_A5" +Po -2660 -6100 +$EndPAD +$PAD +Sh "41" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2857 -6100 +$EndPAD +$PAD +Sh "42" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 210 "RAM_A9" +Po -3054 -6100 +$EndPAD +$PAD +Sh "43" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 207 "RAM_A6" +Po -3251 -6100 +$EndPAD +$PAD +Sh "44" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 209 "RAM_A8" +Po -3448 -6100 +$EndPAD +$PAD +Sh "45" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 208 "RAM_A7" +Po -3645 -6100 +$EndPAD +$PAD +Sh "46" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 197 "RAM_A13" +Po -3842 -6100 +$EndPAD +$PAD +Sh "47" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -4039 -6100 +$EndPAD +$PAD +Sh "48" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 196 "RAM_A12" +Po -4236 -6100 +$EndPAD +$PAD +Sh "49" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -4433 -6100 +$EndPAD +$PAD +Sh "50" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 191 "RAM_/WE" +Po -4630 -6100 +$EndPAD +$PAD +Sh "51" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 198 "RAM_A14" +Po -4827 -6100 +$EndPAD +$PAD +Sh "52" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 202 "RAM_A18" +Po -5024 -6100 +$EndPAD +$PAD +Sh "53" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 -5023 +$EndPAD +$PAD +Sh "54" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -6130 -4826 +$EndPAD +$PAD +Sh "55" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -6130 -4629 +$EndPAD +$PAD +Sh "56" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -6130 -4432 +$EndPAD +$PAD +Sh "57" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 200 "RAM_A16" +Po -6130 -4235 +$EndPAD +$PAD +Sh "58" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 199 "RAM_A15" +Po -6130 -4038 +$EndPAD +$PAD +Sh "59" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 -3841 +$EndPAD +$PAD +Sh "60" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -6130 -3644 +$EndPAD +$PAD +Sh "61" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 201 "RAM_A17" +Po -6130 -3447 +$EndPAD +$PAD +Sh "62" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "SD_DAT2" +Po -6130 -3250 +$EndPAD +$PAD +Sh "63" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 270 "SD_DAT3" +Po -6130 -3053 +$EndPAD +$PAD +Sh "64" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 265 "SD_CLK" +Po -6130 -2856 +$EndPAD +$PAD +Sh "65" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 267 "SD_DAT0" +Po -6130 -2659 +$EndPAD +$PAD +Sh "66" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 -2462 +$EndPAD +$PAD +Sh "67" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 266 "SD_CMD" +Po -6130 -2265 +$EndPAD +$PAD +Sh "68" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 94 "MCU_SPI_SS" +Po -6130 -2068 +$EndPAD +$PAD +Sh "69" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -6130 -1871 +$EndPAD +$PAD +Sh "70" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -6130 -1674 +$EndPAD +$PAD +Sh "71" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 93 "MCU_SPI_SCK" +Po -6130 -1477 +$EndPAD +$PAD +Sh "72" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 91 "MCU_SPI_MISO" +Po -6130 -1280 +$EndPAD +$PAD +Sh "73" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -6130 -1083 +$EndPAD +$PAD +Sh "74" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 92 "MCU_SPI_MOSI" +Po -6130 -886 +$EndPAD +$PAD +Sh "75" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 -689 +$EndPAD +$PAD +Sh "76" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 77 "DAC_MCLK" +Po -6130 -492 +$EndPAD +$PAD +Sh "77" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 76 "DAC_LRCK" +Po -6130 -295 +$EndPAD +$PAD +Sh "78" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 78 "DAC_SDIN" +Po -6130 -98 +$EndPAD +$PAD +Sh "79" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 268 "SD_DAT1" +Po -6130 99 +$EndPAD +$PAD +Sh "80" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "FPGA_CLK" +Po -6130 296 +$EndPAD +$PAD +Sh "81" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 315 "SNES_PA4" +Po -6130 493 +$EndPAD +$PAD +Sh "82" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 690 +$EndPAD +$PAD +Sh "83" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 89 "INIT_B+MCU_IRQ" +Po -6130 887 +$EndPAD +$PAD +Sh "84" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -6130 1084 +$EndPAD +$PAD +Sh "85" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "SNES_PA5" +Po -6130 1281 +$EndPAD +$PAD +Sh "86" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 313 "SNES_PA2" +Po -6130 1478 +$EndPAD +$PAD +Sh "87" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 314 "SNES_PA3" +Po -6130 1675 +$EndPAD +$PAD +Sh "88" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -6130 1872 +$EndPAD +$PAD +Sh "89" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -6130 2069 +$EndPAD +$PAD +Sh "90" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 311 "SNES_PA0" +Po -6130 2266 +$EndPAD +$PAD +Sh "91" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 2463 +$EndPAD +$PAD +Sh "92" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 81 "DIN+MCU_/OVR" +Po -6130 2660 +$EndPAD +$PAD +Sh "93" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 312 "SNES_PA1" +Po -6130 2857 +$EndPAD +$PAD +Sh "94" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 276 "SNES_/WR" +Po -6130 3054 +$EndPAD +$PAD +Sh "95" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 301 "SNES_CPU_CLK" +Po -6130 3251 +$EndPAD +$PAD +Sh "96" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 305 "SNES_D3" +Po -6130 3448 +$EndPAD +$PAD +Sh "97" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 309 "SNES_D7" +Po -6130 3645 +$EndPAD +$PAD +Sh "98" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -6130 3842 +$EndPAD +$PAD +Sh "99" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -6130 4039 +$EndPAD +$PAD +Sh "100" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 304 "SNES_D2" +Po -6130 4236 +$EndPAD +$PAD +Sh "101" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 308 "SNES_D6" +Po -6130 4433 +$EndPAD +$PAD +Sh "102" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 303 "SNES_D1" +Po -6130 4630 +$EndPAD +$PAD +Sh "103" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 82 "DONE" +Po -6130 4827 +$EndPAD +$PAD +Sh "104" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 68 "CCLK" +Po -6130 5024 +$EndPAD +$PAD +Sh "105" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -5023 6180 +$EndPAD +$PAD +Sh "106" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "SNES_D5" +Po -4826 6180 +$EndPAD +$PAD +Sh "107" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 302 "SNES_D0" +Po -4629 6180 +$EndPAD +$PAD +Sh "108" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 306 "SNES_D4" +Po -4432 6180 +$EndPAD +$PAD +Sh "109" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 79 "DATABUS_/OE" +Po -4235 6180 +$EndPAD +$PAD +Sh "110" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -4038 6180 +$EndPAD +$PAD +Sh "111" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 80 "DATABUS_DIR" +Po -3841 6180 +$EndPAD +$PAD +Sh "112" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -3644 6180 +$EndPAD +$PAD +Sh "113" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 152 "N-000193" +Po -3447 6180 +$EndPAD +$PAD +Sh "114" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 310 "SNES_IRQ_EN" +Po -3250 6180 +$EndPAD +$PAD +Sh "115" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 273 "SNES_/RD" +Po -3053 6180 +$EndPAD +$PAD +Sh "116" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 275 "SNES_/ROMSEL" +Po -2856 6180 +$EndPAD +$PAD +Sh "117" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 293 "SNES_A23" +Po -2659 6180 +$EndPAD +$PAD +Sh "118" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -2462 6180 +$EndPAD +$PAD +Sh "119" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 277 "SNES_A0" +Po -2265 6180 +$EndPAD +$PAD +Sh "120" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "SNES_A22" +Po -2068 6180 +$EndPAD +$PAD +Sh "121" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1871 6180 +$EndPAD +$PAD +Sh "122" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 278 "SNES_A1" +Po -1674 6180 +$EndPAD +$PAD +Sh "123" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 291 "SNES_A21" +Po -1477 6180 +$EndPAD +$PAD +Sh "124" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 289 "SNES_A2" +Po -1280 6180 +$EndPAD +$PAD +Sh "125" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "SNES_A20" +Po -1083 6180 +$EndPAD +$PAD +Sh "126" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 294 "SNES_A3" +Po -886 6180 +$EndPAD +$PAD +Sh "127" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -689 6180 +$EndPAD +$PAD +Sh "128" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 288 "SNES_A19" +Po -492 6180 +$EndPAD +$PAD +Sh "129" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -295 6180 +$EndPAD +$PAD +Sh "130" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 295 "SNES_A4" +Po -98 6180 +$EndPAD +$PAD +Sh "131" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 287 "SNES_A18" +Po 99 6180 +$EndPAD +$PAD +Sh "132" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 296 "SNES_A5" +Po 296 6180 +$EndPAD +$PAD +Sh "133" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 286 "SNES_A17" +Po 493 6180 +$EndPAD +$PAD +Sh "134" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 690 6180 +$EndPAD +$PAD +Sh "135" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 297 "SNES_A6" +Po 887 6180 +$EndPAD +$PAD +Sh "136" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1084 6180 +$EndPAD +$PAD +Sh "137" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 285 "SNES_A16" +Po 1281 6180 +$EndPAD +$PAD +Sh "138" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 298 "SNES_A7" +Po 1478 6180 +$EndPAD +$PAD +Sh "139" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 284 "SNES_A15" +Po 1675 6180 +$EndPAD +$PAD +Sh "140" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 299 "SNES_A8" +Po 1872 6180 +$EndPAD +$PAD +Sh "141" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 283 "SNES_A14" +Po 2069 6180 +$EndPAD +$PAD +Sh "142" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 2266 6180 +$EndPAD +$PAD +Sh "143" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 300 "SNES_A9" +Po 2463 6180 +$EndPAD +$PAD +Sh "144" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 282 "SNES_A13" +Po 2660 6180 +$EndPAD +$PAD +Sh "145" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 2857 6180 +$EndPAD +$PAD +Sh "146" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 279 "SNES_A10" +Po 3054 6180 +$EndPAD +$PAD +Sh "147" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 281 "SNES_A12" +Po 3251 6180 +$EndPAD +$PAD +Sh "148" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 280 "SNES_A11" +Po 3448 6180 +$EndPAD +$PAD +Sh "149" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 271 "SNES_/PARD" +Po 3645 6180 +$EndPAD +$PAD +Sh "150" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 272 "SNES_/PAWR" +Po 3842 6180 +$EndPAD +$PAD +Sh "151" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 4039 6180 +$EndPAD +$PAD +Sh "152" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "SNES_PA6" +Po 4236 6180 +$EndPAD +$PAD +Sh "153" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 4433 6180 +$EndPAD +$PAD +Sh "154" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "SNES_PA7" +Po 4630 6180 +$EndPAD +$PAD +Sh "155" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 319 "SNES_REFRESH" +Po 4827 6180 +$EndPAD +$PAD +Sh "156" R 1000 100 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 220 "ROM_/LB" +Po 5024 6180 +$EndPAD +$PAD +Sh "157" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 5023 +$EndPAD +$PAD +Sh "158" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 6150 4826 +$EndPAD +$PAD +Sh "159" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 6150 4629 +$EndPAD +$PAD +Sh "160" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 6150 4432 +$EndPAD +$PAD +Sh "161" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 222 "ROM_/UB" +Po 6150 4235 +$EndPAD +$PAD +Sh "162" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 221 "ROM_/OE" +Po 6150 4038 +$EndPAD +$PAD +Sh "163" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 3841 +$EndPAD +$PAD +Sh "164" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 6150 3644 +$EndPAD +$PAD +Sh "165" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 240 "ROM_A3" +Po 6150 3447 +$EndPAD +$PAD +Sh "166" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "ROM_A0" +Po 6150 3250 +$EndPAD +$PAD +Sh "167" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 244 "ROM_A7" +Po 6150 3053 +$EndPAD +$PAD +Sh "168" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 225 "ROM_A1" +Po 6150 2856 +$EndPAD +$PAD +Sh "169" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "ROM_A4" +Po 6150 2659 +$EndPAD +$PAD +Sh "170" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 2462 +$EndPAD +$PAD +Sh "171" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 236 "ROM_A2" +Po 6150 2265 +$EndPAD +$PAD +Sh "172" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 219 "ROM_/CE" +Po 6150 2068 +$EndPAD +$PAD +Sh "173" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 6150 1871 +$EndPAD +$PAD +Sh "174" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 6150 1674 +$EndPAD +$PAD +Sh "175" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 243 "ROM_A6" +Po 6150 1477 +$EndPAD +$PAD +Sh "176" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "ROM_DQ0" +Po 6150 1280 +$EndPAD +$PAD +Sh "177" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 6150 1083 +$EndPAD +$PAD +Sh "178" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "ROM_DQ1" +Po 6150 886 +$EndPAD +$PAD +Sh "179" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 689 +$EndPAD +$PAD +Sh "180" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 320 "SNES_SYS_CLK" +Po 6150 492 +$EndPAD +$PAD +Sh "181" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 255 "ROM_DQ2" +Po 6150 295 +$EndPAD +$PAD +Sh "182" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "ROM_DQ3" +Po 6150 98 +$EndPAD +$PAD +Sh "183" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 257 "ROM_DQ4" +Po 6150 -99 +$EndPAD +$PAD +Sh "184" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 231 "ROM_A15" +Po 6150 -296 +$EndPAD +$PAD +Sh "185" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 259 "ROM_DQ6" +Po 6150 -493 +$EndPAD +$PAD +Sh "186" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 -690 +$EndPAD +$PAD +Sh "187" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 258 "ROM_DQ5" +Po 6150 -887 +$EndPAD +$PAD +Sh "188" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 6150 -1084 +$EndPAD +$PAD +Sh "189" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 260 "ROM_DQ7" +Po 6150 -1281 +$EndPAD +$PAD +Sh "190" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 223 "ROM_/WE" +Po 6150 -1478 +$EndPAD +$PAD +Sh "191" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 237 "ROM_A20" +Po 6150 -1675 +$EndPAD +$PAD +Sh "192" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 6150 -1872 +$EndPAD +$PAD +Sh "193" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 6150 -2069 +$EndPAD +$PAD +Sh "194" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 229 "ROM_A13" +Po 6150 -2266 +$EndPAD +$PAD +Sh "195" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 -2463 +$EndPAD +$PAD +Sh "196" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 227 "ROM_A11" +Po 6150 -2660 +$EndPAD +$PAD +Sh "197" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 226 "ROM_A10" +Po 6150 -2857 +$EndPAD +$PAD +Sh "198" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 239 "ROM_A22" +Po 6150 -3054 +$EndPAD +$PAD +Sh "199" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 232 "ROM_A16" +Po 6150 -3251 +$EndPAD +$PAD +Sh "200" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 230 "ROM_A14" +Po 6150 -3448 +$EndPAD +$PAD +Sh "201" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 6150 -3645 +$EndPAD +$PAD +Sh "202" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 -3842 +$EndPAD +$PAD +Sh "203" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 238 "ROM_A21" +Po 6150 -4039 +$EndPAD +$PAD +Sh "204" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "ROM_A9" +Po 6150 -4236 +$EndPAD +$PAD +Sh "205" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "ROM_A8" +Po 6150 -4433 +$EndPAD +$PAD +Sh "206" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 6150 -4630 +$EndPAD +$PAD +Sh "207" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 188 "PROG_B" +Po 6150 -4827 +$EndPAD +$PAD +Sh "208" R 1000 100 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 6150 -5024 +$EndPAD +$SHAPE3D +Na "smd/pqfp208.wrl" +Sc 0.393000 0.393000 0.400000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE PQFP208 +$MODULE SOT23EBC +Po 53200 24475 1800 15 4D4BE4E0 4BEE66BC ~~ +Li SOT23EBC +Cd Module CMS SOT23 Transistore EBC +Kw CMS SOT +Sc 4BEE66BC +AR /4BAA6ABD/4BF19DCA +Op 0 0 0 +At SMD +T0 1250 -525 320 320 1800 70 N V 21 N "D511" +T1 125 475 320 320 1800 70 N I 21 N "BAT54C" +DS -600 -150 600 -150 75 21 +DS 600 -150 600 150 75 21 +DS 600 150 -600 150 75 21 +DS -600 150 -600 -150 75 21 +$PAD +Sh "1" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -350 -400 +$EndPAD +$PAD +Sh "2" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "+BATT" +Po 350 -400 +$EndPAD +$PAD +Sh "3" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/Memory/SRAM_Vcc" +Po 0 400 +$EndPAD +$SHAPE3D +Na "smd/cms_sot23.wrl" +Sc 0.130000 0.150000 0.150000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23EBC +$MODULE XTAL_SMD_05019 +Po 43550 34350 2700 15 4C593100 4C13969B ~~ +Li XTAL_SMD_05019 +Sc 4C13969B +AR /4B6ED75B/4BC243CB +Op 0 0 0 +T0 -1175 -950 320 320 2700 70 N V 21 N "X402" +T1 0 0 320 320 2700 70 N V 21 N "32.768kHz" +DS -1220 -591 1220 -591 75 21 +DS 1220 -591 1220 591 75 21 +DS 1220 591 -1220 591 75 21 +DS -1220 591 -1220 -591 75 21 +$PAD +Sh "1" R 512 866 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 178 "N-000337" +Po -827 0 +$EndPAD +$PAD +Sh "2" R 512 866 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 179 "N-000338" +Po 827 0 +$EndPAD +$EndMODULE XTAL_SMD_05019 +$MODULE PIN_ARRAY_2X1 +Po 38500 38000 900 15 4C5944CA 4BEFC8C5 ~~ +Li PIN_ARRAY_2X1 +Cd Connecteurs 2 pins +Kw CONN DEV +Sc 4BEFC8C5 +AR /4B6ED75B/4BEFBC73 +Op 0 0 0 +T0 0 -750 320 320 900 70 N V 21 N "P402" +T1 8 4 320 320 900 70 N I 21 N "CONN_2" +DS -1000 500 -1000 -500 75 21 +DS -1000 -500 1000 -500 75 21 +DS 1000 -500 1000 500 75 21 +DS 1000 500 -1000 500 75 21 +$PAD +Sh "1" R 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 88 "GND" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 13 "/RESET" +Po 500 0 +$EndPAD +$SHAPE3D +Na "pin_array/pins_array_2x1.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE PIN_ARRAY_2X1 +$MODULE USB-MINIB-THT +Po 50450 24100 2700 0 4D2F12DF 4BEFB152 ~~ +Li USB-MINIB-THT +Sc 4BEFB152 +AR /4B6ED75B/4BF00175 +Op 0 0 0 +T0 -475 2500 320 320 3600 70 M V 20 N "J421" +T1 -1600 0 320 320 3600 70 M V 20 N "Molex_54819" +DS -2146 -1220 -1988 -1063 75 24 +DS -2539 -1220 -1988 -669 75 24 +DS -1988 -276 -2933 -1220 75 24 +DS -1988 118 -3248 -1142 75 24 +DS -3248 -748 -1988 512 75 24 +DS -3248 -354 -1988 906 75 24 +DS -2067 1220 -3248 39 75 24 +DS -3248 433 -2461 1220 75 24 +DS -2854 1220 -3248 827 75 24 +DS -3248 1220 -1988 1220 75 24 +DS -1988 1220 -1988 -1220 75 24 +DS -1988 -1220 -3248 -1220 75 24 +DS -3248 -1220 -3248 1220 75 24 +DS -39 -807 -39 -1220 75 24 +DS -39 -1220 79 -1220 75 24 +DS 79 -1220 79 -1417 75 24 +DS 79 -1417 256 -1417 75 24 +DS 256 -1417 256 -1535 75 24 +DS 256 -1535 -1220 -1535 75 24 +DS -1220 -1535 -3091 -1535 75 24 +DS -3091 -1535 -3091 1535 75 24 +DS -3091 1535 256 1535 75 24 +DS 256 1535 256 1417 75 24 +DS 256 1417 79 1417 75 24 +DS 79 1417 79 1220 75 24 +DS 79 1220 -39 1220 75 24 +DS -39 1220 -39 807 75 24 +DS -39 -571 236 -571 75 24 +DS 236 -571 236 -689 75 24 +DS 236 -689 -39 -689 75 24 +DS -39 59 236 59 75 24 +DS 236 59 236 -59 75 24 +DS 236 -59 -39 -59 75 24 +DS -39 689 236 689 75 24 +DS 236 689 236 571 75 24 +DS 236 571 -39 571 75 24 +DS -39 807 -39 -807 75 24 +DS -39 -1220 -39 -807 75 20 +DS -39 1220 -39 807 75 20 +DS 256 1535 -1220 1535 75 20 +DS -3091 1535 -2323 1535 75 20 +DS 256 -1535 -1220 -1535 75 20 +DS -3091 -1535 -2323 -1535 75 20 +DS 139 -1417 80 -1417 75 20 +DS 80 -1417 80 -1220 75 20 +DS 80 -1220 -39 -1220 75 20 +DS -40 1220 79 1220 75 20 +DS 79 1220 79 1398 75 20 +DS 79 1398 79 1417 75 20 +DS 79 1417 256 1417 75 20 +DS 256 1417 256 1535 75 20 +DS -3091 1535 -3091 -1535 75 20 +DS 257 -1535 257 -1417 75 20 +DS 257 -1417 139 -1417 75 20 +DS -492 -1181 492 -1181 75 24 +DS 492 -1181 492 -1732 75 24 +DS 492 -1732 -492 -1732 75 24 +DS -492 -1732 -492 -1181 75 24 +DS -492 1181 492 1181 75 24 +DS 492 1181 492 1732 75 24 +DS 492 1732 -492 1732 75 24 +DS -492 1732 -492 1181 75 24 +$PAD +Sh "2" C 394 394 0 0 2700 +Dr 276 0 0 +At STD N 00D0FFFF +Ne 166 "N-000310" +Po -236 315 +$EndPAD +$PAD +Sh "3" C 394 394 0 0 2700 +Dr 276 0 0 +At STD N 00D0FFFF +Ne 170 "N-000315" +Po 236 0 +$EndPAD +$PAD +Sh "4" C 394 394 0 0 2700 +Dr 276 0 0 +At STD N 00D0FFFF +Ne 0 "" +Po -236 -315 +$EndPAD +$PAD +Sh "5" C 394 394 0 0 2700 +Dr 276 0 0 +At STD N 00D0FFFF +Ne 88 "GND" +Po 236 -630 +$EndPAD +$PAD +Sh "1" C 394 394 0 0 2700 +Dr 276 0 0 +At STD N 00D0FFFF +Ne 177 "N-000328" +Po 236 630 +$EndPAD +$PAD +Sh "6" O 866 394 0 0 2700 +Dr 748 0 0 O 748 276 +At STD N 00D0FFFF +Ne 88 "GND" +Po -1772 1437 +$EndPAD +$PAD +Sh "7" O 866 394 0 0 2700 +Dr 748 0 0 O 748 276 +At STD N 00D0FFFF +Ne 88 "GND" +Po -1772 -1437 +$EndPAD +$EndMODULE USB-MINIB-THT +$MODULE SOT23EBC +Po 54600 24475 1800 15 4D4BE2D6 4BF2FF04 ~~ +Li SOT23EBC +Cd Module CMS SOT23 Transistore EBC +Kw CMS SOT +Sc 4BF2FF04 +AR /4BAA6ABD/4BF2FD9F +Op 0 0 0 +At SMD +T0 -950 -325 320 320 2700 70 N V 21 N "Q511" +T1 -1525 -75 320 320 2700 70 N I 21 N "2N2222A" +DS -600 -150 600 -150 75 21 +DS 600 -150 600 150 75 21 +DS 600 150 -600 150 75 21 +DS -600 150 -600 -150 75 21 +$PAD +Sh "1" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -350 -400 +$EndPAD +$PAD +Sh "2" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 182 "N-000344" +Po 350 -400 +$EndPAD +$PAD +Sh "3" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/Memory/RAM_/CE" +Po 0 400 +$EndPAD +$SHAPE3D +Na "smd/cms_sot23.wrl" +Sc 0.130000 0.150000 0.150000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23EBC +$MODULE PIN_ARRAY_2X1 +Po 38500 40000 2700 15 4C5944D6 4BF3D1C4 ~~ +Li PIN_ARRAY_2X1 +Cd Connecteurs 2 pins +Kw CONN DEV +Sc 4BF3D1C4 +AR /4B6ED75B/4C4A0B6F +Op 0 0 0 +T0 0 750 320 320 2700 70 N V 21 N "P403" +T1 0 -4 320 320 2700 70 N I 21 N "CONN_2" +DS -1000 500 -1000 -500 75 21 +DS -1000 -500 1000 -500 75 21 +DS 1000 -500 1000 500 75 21 +DS 1000 500 -1000 500 75 21 +$PAD +Sh "1" R 600 600 0 0 2700 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 88 "GND" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 600 600 0 0 2700 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 168 "N-000313" +Po 500 0 +$EndPAD +$SHAPE3D +Na "pin_array/pins_array_2x1.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE PIN_ARRAY_2X1 +$MODULE BT_KEYSTONE_1059_20MM +Po 44000 35500 900 0 4DB238EB 4BEE7B7D ~~ +Li BT_KEYSTONE_1059_20MM +Sc 4BEE7B7D +AR /4B6EC9C3/4BAF2EAF +Op 0 0 0 +T0 -4850 -2300 320 320 1800 70 M V 20 N "BT351" +T1 0 0 320 320 900 70 M V 20 N "Keystone_1059_/_KZH20PCB" +DS 3583 -2677 4134 -2677 75 20 +DS 3858 -2402 3858 -2953 75 20 +DS -3858 2953 -3858 2402 75 20 +DC 3858 -2677 4134 -2953 75 20 +DC -3858 2677 -3465 2677 75 20 +DC 0 0 3976 0 75 20 +DS -5591 -1339 -4331 -1339 75 20 +DS -4331 -1339 -4331 -3150 75 20 +DS -4331 -3150 4331 -3150 75 20 +DS 4331 -3150 4331 -1339 75 20 +DS 4331 -1339 5591 -1339 75 20 +DS 5591 -1339 5591 1339 75 20 +DS 5591 1339 4331 1339 75 20 +DS 4331 1339 4331 2756 75 20 +DS 4331 2756 3937 3150 75 20 +DS 3937 3150 -4331 3150 75 20 +DS -4331 3150 -4331 1339 75 20 +DS -4331 1339 -5591 1339 75 20 +DS -5591 1339 -5591 -1339 75 20 +$PAD +Sh "2" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00F0FFFF +Ne 88 "GND" +Po -5300 0 +$EndPAD +$PAD +Sh "1" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00F0FFFF +Ne 8 "+BATT" +Po 5300 500 +$EndPAD +$PAD +Sh "1" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00F0FFFF +Ne 8 "+BATT" +Po 5300 -500 +$EndPAD +$EndMODULE BT_KEYSTONE_1059_20MM +$MODULE VFBGA54 +Po 72079 31670 1800 15 4C13975F 4BF2734A ~~ +Li VFBGA54 +Sc 4BF2734A +AR /4BAA6ABD/4B868602 +Op 0 0 0 +T0 1519 1910 320 320 1800 70 N V 21 N "U501" +T1 71 16 320 320 1800 70 N V 21 N "MT45W8MW16" +DC -1693 1299 -1535 1299 75 21 +DS -1968 -1574 1968 -1574 75 21 +DS 1968 -1574 1968 1574 75 21 +DS -1968 1574 1968 1574 75 21 +DS -1968 -1574 -1968 1574 75 21 +$PAD +Sh "A1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 220 "ROM_/LB" +Po -1181 738 +$EndPAD +$PAD +Sh "B1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 261 "ROM_DQ8" +Po -885 738 +$EndPAD +$PAD +Sh "C1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 262 "ROM_DQ9" +Po -590 738 +$EndPAD +$PAD +Sh "D1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -295 738 +$EndPAD +$PAD +Sh "E1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 0 738 +$EndPAD +$PAD +Sh "F1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 253 "ROM_DQ14" +Po 295 738 +$EndPAD +$PAD +Sh "G1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 254 "ROM_DQ15" +Po 590 738 +$EndPAD +$PAD +Sh "H1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 234 "ROM_A18" +Po 885 738 +$EndPAD +$PAD +Sh "J1" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1181 738 +$EndPAD +$PAD +Sh "A2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 221 "ROM_/OE" +Po -1181 442 +$EndPAD +$PAD +Sh "B2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 222 "ROM_/UB" +Po -885 442 +$EndPAD +$PAD +Sh "C2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "ROM_DQ10" +Po -590 442 +$EndPAD +$PAD +Sh "D2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 250 "ROM_DQ11" +Po -295 442 +$EndPAD +$PAD +Sh "E2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 251 "ROM_DQ12" +Po 0 442 +$EndPAD +$PAD +Sh "F2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 252 "ROM_DQ13" +Po 295 442 +$EndPAD +$PAD +Sh "G2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "ROM_A19" +Po 590 442 +$EndPAD +$PAD +Sh "H2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "ROM_A8" +Po 885 442 +$EndPAD +$PAD +Sh "J2" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1181 442 +$EndPAD +$PAD +Sh "A3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "ROM_A0" +Po -1181 147 +$EndPAD +$PAD +Sh "B3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 240 "ROM_A3" +Po -885 147 +$EndPAD +$PAD +Sh "C3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 242 "ROM_A5" +Po -590 147 +$EndPAD +$PAD +Sh "D3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 233 "ROM_A17" +Po -295 147 +$EndPAD +$PAD +Sh "E3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 238 "ROM_A21" +Po 0 147 +$EndPAD +$PAD +Sh "F3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 230 "ROM_A14" +Po 295 147 +$EndPAD +$PAD +Sh "G3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 228 "ROM_A12" +Po 590 147 +$EndPAD +$PAD +Sh "H3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "ROM_A9" +Po 885 147 +$EndPAD +$PAD +Sh "J3" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 1181 147 +$EndPAD +$PAD +Sh "A4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 225 "ROM_A1" +Po -1181 -147 +$EndPAD +$PAD +Sh "B4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "ROM_A4" +Po -885 -147 +$EndPAD +$PAD +Sh "C4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 243 "ROM_A6" +Po -590 -147 +$EndPAD +$PAD +Sh "D4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 244 "ROM_A7" +Po -295 -147 +$EndPAD +$PAD +Sh "E4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 232 "ROM_A16" +Po 0 -147 +$EndPAD +$PAD +Sh "F4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 231 "ROM_A15" +Po 295 -147 +$EndPAD +$PAD +Sh "G4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 229 "ROM_A13" +Po 590 -147 +$EndPAD +$PAD +Sh "H4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 226 "ROM_A10" +Po 885 -147 +$EndPAD +$PAD +Sh "J4" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 239 "ROM_A22" +Po 1181 -147 +$EndPAD +$PAD +Sh "A5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 236 "ROM_A2" +Po -1181 -442 +$EndPAD +$PAD +Sh "B5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 219 "ROM_/CE" +Po -885 -442 +$EndPAD +$PAD +Sh "C5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "ROM_DQ1" +Po -590 -442 +$EndPAD +$PAD +Sh "D5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "ROM_DQ3" +Po -295 -442 +$EndPAD +$PAD +Sh "E5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 257 "ROM_DQ4" +Po 0 -442 +$EndPAD +$PAD +Sh "F5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 258 "ROM_DQ5" +Po 295 -442 +$EndPAD +$PAD +Sh "G5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 223 "ROM_/WE" +Po 590 -442 +$EndPAD +$PAD +Sh "H5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 227 "ROM_A11" +Po 885 -442 +$EndPAD +$PAD +Sh "J5" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1181 -442 +$EndPAD +$PAD +Sh "A6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -1181 -738 +$EndPAD +$PAD +Sh "B6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "ROM_DQ0" +Po -885 -738 +$EndPAD +$PAD +Sh "C6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 255 "ROM_DQ2" +Po -590 -738 +$EndPAD +$PAD +Sh "D6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "+1.8V" +Po -295 -738 +$EndPAD +$PAD +Sh "E6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 -738 +$EndPAD +$PAD +Sh "F6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 259 "ROM_DQ6" +Po 295 -738 +$EndPAD +$PAD +Sh "G6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 260 "ROM_DQ7" +Po 590 -738 +$EndPAD +$PAD +Sh "H6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 237 "ROM_A20" +Po 885 -738 +$EndPAD +$PAD +Sh "J6" O 114 114 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1181 -738 +$EndPAD +$EndMODULE VFBGA54 +$MODULE TSSOP10 +Po 41050 41500 1800 15 4D2A0F06 4BAA93D8 ~~ +Li TSSOP10 +Sc 4BAA93D8 +AR /4B6EC9C3/4BAA9331 +Op 0 0 0 +T0 0 -1475 320 320 1800 70 N V 21 N "U341" +T1 250 825 320 320 1800 70 N V 21 N "CS4344" +DC -394 394 -315 394 75 21 +DS -590 -590 590 -590 75 21 +DS 590 -590 590 590 75 21 +DS -590 590 590 590 75 21 +DS -590 -590 -590 590 75 21 +$PAD +Sh "1" R 118 393 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 78 "DAC_SDIN" +Po -393 885 +$EndPAD +$PAD +Sh "2" R 118 393 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 75 "DAC_/DEM" +Po -196 885 +$EndPAD +$PAD +Sh "3" R 118 393 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 76 "DAC_LRCK" +Po 0 885 +$EndPAD +$PAD +Sh "4" R 118 393 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 77 "DAC_MCLK" +Po 196 885 +$EndPAD +$PAD +Sh "5" R 118 393 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 156 "N-000279" +Po 393 885 +$EndPAD +$PAD +Sh "6" R 118 393 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 157 "N-000281" +Po 393 -885 +$EndPAD +$PAD +Sh "7" R 118 393 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 155 "N-000278" +Po 196 -885 +$EndPAD +$PAD +Sh "8" R 118 393 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 0 -885 +$EndPAD +$PAD +Sh "9" R 118 393 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+3.3VDAC" +Po -196 -885 +$EndPAD +$PAD +Sh "10" R 118 393 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 160 "N-000286" +Po -393 -885 +$EndPAD +$EndMODULE TSSOP10 +$MODULE pin_array_7x2 +Po 39016 32992 900 15 4D4AAE76 4C09447D ~~ +Li pin_array_7x2 +Cd Double rangee de contacts 2 x 7 pins +Kw CONN +Sc 4C09447D +AR /4B6ED75B/4C0943CA +Op 0 0 0 +T0 2942 -1291 320 320 900 70 N V 21 N "P401" +T1 0 0 320 320 900 70 N V 21 N "CONN_7X2" +DS -3600 -1000 -3700 -1000 120 21 +DS -3700 -1000 -3700 1000 120 21 +DS -3700 1000 -3625 1000 120 21 +DS -3550 0 -2500 0 120 21 +DS -2500 0 -2500 1000 120 21 +DS -3500 -1000 -3600 -1000 120 21 +DS -3600 -1000 -3600 1000 120 21 +DS -3600 1000 -3500 1000 120 21 +DS -3500 1000 3500 1000 120 21 +DS -3500 -1000 3500 -1000 120 21 +DS 3500 -1000 3500 1000 120 21 +DS -3500 1000 -3500 -1000 120 21 +$PAD +Sh "1" R 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 4 "+3.3V" +Po -3000 500 +$EndPAD +$PAD +Sh "2" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 6 "+5V" +Po -3000 -500 +$EndPAD +$PAD +Sh "3" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 88 "GND" +Po -2000 500 +$EndPAD +$PAD +Sh "4" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 185 "P2.10" +Po -2000 -500 +$EndPAD +$PAD +Sh "5" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 13 "/RESET" +Po -1000 500 +$EndPAD +$PAD +Sh "6" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 324 "TX3" +Po -1000 -500 +$EndPAD +$PAD +Sh "7" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 264 "RX3" +Po 0 500 +$EndPAD +$PAD +Sh "8" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 321 "TCK" +Po 0 -500 +$EndPAD +$PAD +Sh "9" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 63 "/TRST" +Po 1000 500 +$EndPAD +$PAD +Sh "10" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 322 "TMS" +Po 1000 -500 +$EndPAD +$PAD +Sh "11" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 85 "EXT_TDI" +Po 2000 500 +$EndPAD +$PAD +Sh "12" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 86 "EXT_TDO" +Po 2000 -500 +$EndPAD +$PAD +Sh "13" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 263 "RX0" +Po 3000 500 +$EndPAD +$PAD +Sh "14" C 600 600 0 0 900 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 323 "TX0" +Po 3000 -500 +$EndPAD +$EndMODULE pin_array_7x2 +$MODULE SM0805_FIXEDMASK +Po 49050 48575 2700 15 4DB454D6 4C8642EF ~~ +Li SM0805_FIXEDMASK +Sc 4C8642EF +AR /4B6EC9C3/4C42D578 +Op 0 0 0 +At SMD +T0 25 2025 320 320 2700 70 N V 21 N "R331" +T1 0 0 320 320 2700 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 158 "N-000284" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 69 "CIC_CLK" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 42900 41750 900 15 4C592F23 4C1A7291 ~~ +Li SM0805_FIXEDMASK +Sc 4C1A7291 +AR /4B6EC9C3/4C17DE31 +Op 0 0 0 +At SMD +T0 1335 -13 320 320 900 70 N V 21 N "C342" +T1 0 0 320 320 900 70 N I 21 N "1u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+3.3VDAC" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 59213 34370 0 0 4D2F5E34 4C12872B ~~ +Li SM0805_FIXEDMASK +Sc 4C12872B +AR /4B6ED75B/4C1286D5 +Op 0 0 0 +At SMD +T0 -1338 5 320 320 0 70 M V 20 N "C412" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 70075 25425 900 15 4C594445 4C0DA806 ~~ +Li SM0805_FIXEDMASK +Sc 4C0DA806 +AR /4B6ED75B/4C0DA785 +Op 0 0 0 +At SMD +T0 0 -625 320 320 900 70 N V 21 N "R403" +T1 0 0 320 320 900 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 174 "N-000323" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 167 "N-000311" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 39475 38975 2700 15 4C5930D1 4C063CEB ~~ +Li SM0805_FIXEDMASK +Sc 4C063CEB +AR /4B6ED75B/4C063C47 +Op 0 0 0 +At SMD +T0 1325 -25 320 320 2700 70 N V 21 N "C405" +T1 0 0 320 320 2700 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/RESET" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 39488 37520 900 15 4C5930DE 4C063CE9 ~~ +Li SM0805_FIXEDMASK +Sc 4C063CE9 +AR /4B6ED75B/4C063C2F +Op 0 0 0 +At SMD +T0 -455 712 320 320 900 70 N V 21 N "R404" +T1 0 0 320 320 900 70 N I 21 N "10k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/RESET" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 73075 45825 900 15 4EF8DC60 4C05B204 ~~ +Li SM0805_FIXEDMASK +Sc 4C05B204 +AR /4B6EC9C3/4C05ACA2 +Op 0 0 0 +At SMD +T0 -1375 25 320 320 900 70 N V 21 N "C301" +T1 0 0 320 320 900 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 69700 45825 900 15 4EF8DC73 4C05B202 ~~ +Li SM0805_FIXEDMASK +Sc 4C05B202 +AR /4B6EC9C3/4EF3B15E +Op 0 0 0 +At SMD +T0 -1650 -125 320 320 900 70 N V 21 N "C303" +T1 0 0 320 320 900 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 73075 44250 2700 15 4EF8DC52 4C05B200 ~~ +Li SM0805_FIXEDMASK +Sc 4C05B200 +AR /4B6EC9C3/4C05AC9D +Op 0 0 0 +At SMD +T0 -1350 -25 320 320 2700 70 N V 21 N "C302" +T1 0 0 320 320 2700 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 69700 44250 2700 15 4EF8EFD7 4C05B1FE ~~ +Li SM0805_FIXEDMASK +Sc 4C05B1FE +AR /4B6EC9C3/4EF3B181 +Op 0 0 0 +At SMD +T0 -1350 -25 320 320 2700 70 N V 21 N "C304" +T1 0 0 320 320 2700 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 50875 26025 0 0 4C5945DB 4C017B5E ~~ +Li SM0805_FIXEDMASK +Sc 4C017B5E +AR /4B6ED75B/4C01596A +Op 0 0 0 +At SMD +T0 1300 0 320 320 0 70 M V 20 N "R423" +T1 0 0 320 320 0 70 M I 20 N "1.5k" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 170 "N-000315" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 325 "USB_SWCONN" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 72245 39308 900 15 4C5943FA 4BABDA69 ~~ +Li SM0805_FIXEDMASK +Sc 4BABDA69 +AR /4B6EC9C3/4BABCAD2 +Op 0 0 0 +At SMD +T0 -192 -670 320 320 900 70 N V 21 N "C322" +T1 0 0 320 320 900 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 74980 26985 0 15 4C59441E 4BABDA6B ~~ +Li SM0805_FIXEDMASK +Sc 4BABDA6B +AR /4B6EC9C3/4BABCB68 +Op 0 0 0 +At SMD +T0 -1355 15 320 320 0 70 N V 21 N "C312" +T1 0 0 320 320 0 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "+1.8V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 75051 39360 900 15 4C594403 4BABDA6D ~~ +Li SM0805_FIXEDMASK +Sc 4BABDA6D +AR /4B6EC9C3/4BABCA9C +Op 0 0 0 +At SMD +T0 10 699 320 320 900 70 N V 21 N "C321" +T1 0 0 320 320 900 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 74970 29295 0 15 4C594416 4BABDA6F ~~ +Li SM0805_FIXEDMASK +Sc 4BABDA6F +AR /4B6EC9C3/4BABCB5C +Op 0 0 0 +At SMD +T0 1330 5 320 320 0 70 N V 21 N "C311" +T1 0 0 320 320 0 70 N I 21 N "4.7u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 72200 33600 1800 0 4C59467D 4BAD47FF ~~ +Li SM0805_FIXEDMASK +Sc 4BAD47FF +AR /4BAA6ABD/4BAD3D55 +Op 0 0 0 +At SMD +T0 1350 -225 320 320 1800 70 M V 20 N "C502" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+1.8V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 55300 23100 2700 15 4D4BE509 4BEDCF0C ~~ +Li SM0805_FIXEDMASK +Sc 4BEDCF0C +AR /4BAA6ABD/4BAD3D53 +Op 0 0 0 +At SMD +T0 -125 1475 320 320 2700 70 N V 21 N "C511" +T1 0 0 320 320 2700 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/Memory/SRAM_Vcc" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 72050 29475 0 0 4C5946A5 4D2528F3 ~~ +Li SM0805_FIXEDMASK +Sc 4D2528F3 +AR /4BAA6ABD/4BAD3D47 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 0 70 M V 20 N "C501" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 64475 45775 900 0 4C5946F0 4BAD4805 ~~ +Li SM0805_FIXEDMASK +Sc 4BAD4805 +AR /4B6E16F2/4BAD42E2 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 900 70 M V 20 N "C116" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 58775 47025 900 0 4DB49853 4BAD4807 ~~ +Li SM0805_FIXEDMASK +Sc 4BAD4807 +AR /4B6E16F2/4BAD42E0 +Op 0 0 0 +At SMD +T0 -1350 25 320 320 900 70 M V 20 N "C115" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 52975 47025 900 0 4E136369 4BAD4809 ~~ +Li SM0805_FIXEDMASK +Sc 4BAD4809 +AR /4B6E16F2/4BAD42DF +Op 0 0 0 +At SMD +T0 25 -650 320 320 900 70 M V 20 N "C114" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 64475 43925 2700 0 4C5946E1 4BEDD15D ~~ +Li SM0805_FIXEDMASK +Sc 4BEDD15D +AR /4B6E16F2/4BAD42DA +Op 0 0 0 +At SMD +T0 -1325 0 320 320 2700 70 M V 20 N "C103" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 58775 45175 2700 0 4C594726 4BEDD15A ~~ +Li SM0805_FIXEDMASK +Sc 4BEDD15A +AR /4B6E16F2/4BAD42D8 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 2700 70 M V 20 N "C102" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 52975 45175 2700 0 4C594741 4BAD480F ~~ +Li SM0805_FIXEDMASK +Sc 4BAD480F +AR /4B6E16F2/4BAD42D5 +Op 0 0 0 +At SMD +T0 -1325 -25 320 320 2700 70 M V 20 N "C101" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 42125 41750 900 15 4C592F1B 4BAE3C6B ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C6B +AR /4B6EC9C3/4BADC720 +Op 0 0 0 +At SMD +T0 1335 24 320 320 900 70 N V 21 N "C341" +T1 0 0 320 320 900 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+3.3VDAC" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 50550 45600 2700 0 4D20DC20 4C8642E9 ~~ +Li SM0805_FIXEDMASK +Sc 4C8642E9 +AR /4B6EC9C3/4BADC719 +Op 0 0 0 +At SMD +T0 25 -650 320 320 2700 70 M V 20 N "C331" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 70100 33100 0 0 4C59466E 4BAE3C6F ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C6F +AR /4B6E18FC/4BADCE85 +Op 0 0 0 +At SMD +T0 -1500 0 320 320 0 70 M V 20 N "C222" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54375 33050 1800 15 4C59317D 4C06E5AC ~~ +Li SM0805_FIXEDMASK +Sc 4C06E5AC +AR /4B6E18FC/4BADCE7D +Op 0 0 0 +At SMD +T0 -195 -685 320 320 1800 70 N V 21 N "C221" +T1 0 0 320 320 1800 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 61850 27725 1800 15 4D4BE244 4BAE3C73 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C73 +AR /4B6E18FC/4BADCE7B +Op 0 0 0 +At SMD +T0 -1450 -25 320 320 1800 70 N V 21 N "C213" +T1 0 0 320 320 1800 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66900 34800 1800 0 4C59465C 4BAE3C75 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C75 +AR /4B6E18FC/4BADCE7A +Op 0 0 0 +At SMD +T0 1325 0 320 320 1800 70 M V 20 N "C212" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 62700 39500 900 0 4D2F5C81 4BAE3C77 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C77 +AR /4B6E18FC/4BADCE78 +Op 0 0 0 +At SMD +T0 1400 0 320 320 900 70 M V 20 N "C211" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 57835 35118 0 0 4C5945F6 4BAE3C79 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C79 +AR /4B6E18FC/4BADCE74 +Op 0 0 0 +At SMD +T0 -1335 157 320 320 0 70 M V 20 N "C210" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 59275 39500 900 0 4C594614 4BAE3C7B ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C7B +AR /4B6E18FC/4BADCE6D +Op 0 0 0 +At SMD +T0 -1325 0 320 320 900 70 M V 20 N "C208" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66825 40275 2700 0 4D2F5C6A 4BAE3C7D ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C7D +AR /4B6E18FC/4BADCE6B +Op 0 0 0 +At SMD +T0 -725 600 320 320 2700 70 M V 20 N "C207" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 67475 38600 1800 0 4D2F5C6F 4BAE3C7F ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C7F +AR /4B6E18FC/4BADCE6A +Op 0 0 0 +At SMD +T0 0 650 320 320 1800 70 M V 20 N "C206" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 67475 33850 1800 0 4D2F5C4D 4BAE3C81 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C81 +AR /4B6E18FC/4BADCE67 +Op 0 0 0 +At SMD +T0 1325 200 320 320 1800 70 M V 20 N "C205" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66425 29925 2700 0 4C594694 4BAE3C83 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C83 +AR /4B6E18FC/4BADCE65 +Op 0 0 0 +At SMD +T0 -1300 0 320 320 2700 70 M V 20 N "C204" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 58125 27725 0 15 4D4BE254 4BAE3C85 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C85 +AR /4B6E18FC/4BADCE64 +Op 0 0 0 +At SMD +T0 1325 -275 320 320 0 70 N V 21 N "C203" +T1 0 0 320 320 0 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 56300 33875 1800 0 4D2F5C39 4BF5AE0A ~~ +Li SM0805_FIXEDMASK +Sc 4BF5AE0A +AR /4B6E18FC/4BADCE62 +Op 0 0 0 +At SMD +T0 1325 -50 320 320 1800 70 M V 20 N "C202" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 56300 36025 1800 0 4D2F5C2B 4BAE3C89 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE3C89 +AR /4B6E18FC/4BADCE47 +Op 0 0 0 +At SMD +T0 25 -700 320 320 1800 70 M V 20 N "C201" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 73825 49000 2700 0 4D2596E5 4BAE5213 ~~ +Li SM0805_FIXEDMASK +Sc 4BAE5213 +AR /4B6E16F2/4BAE51CA +Op 0 0 0 +At SMD +T0 -1400 -25 320 320 2700 70 M V 20 N "R101" +T1 0 0 320 320 2700 70 M I 20 N "270" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 42550 33650 2700 15 4C593120 4C1396A7 ~~ +Li SM0805_FIXEDMASK +Sc 4C1396A7 +AR /4B6ED75B/4BEECBCD +Op 0 0 0 +At SMD +T0 0 600 320 320 2700 70 N V 21 N "C408" +T1 0 0 320 320 2700 70 N I 21 N "10p" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 178 "N-000337" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 44125 38275 1800 15 4D2539EE 4BEEE8BE ~~ +Li SM0805_FIXEDMASK +Sc 4BEEE8BE +AR /4B6ED75B/4BEECBCA +Op 0 0 0 +At SMD +T0 0 -700 320 320 1800 70 N V 21 N "C407" +T1 0 0 320 320 1800 70 N I 21 N "33p" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 181 "N-000340" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 42575 38275 0 15 4D2539F3 4BEEE8C0 ~~ +Li SM0805_FIXEDMASK +Sc 4BEEE8C0 +AR /4B6ED75B/4BEECBC1 +Op 0 0 0 +At SMD +T0 0 700 320 320 0 70 N V 21 N "C406" +T1 0 0 320 320 0 70 N I 21 N "33p" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 180 "N-000339" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54600 26250 1800 15 4D4BE27B 4BF2FEFF ~~ +Li SM0805_FIXEDMASK +Sc 4BF2FEFF +AR /4BAA6ABD/4BF2FDA9 +Op 0 0 0 +At SMD +T0 1400 -25 320 320 1800 70 N V 21 N "R512" +T1 0 0 320 320 1800 70 N I 21 N "4k7" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 182 "N-000344" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54600 25550 0 15 4D4BE273 4BF2FF01 ~~ +Li SM0805_FIXEDMASK +Sc 4BF2FF01 +AR /4BAA6ABD/4BF2FDAC +Op 0 0 0 +At SMD +T0 -1400 25 320 320 0 70 N V 21 N "R513" +T1 0 0 320 320 0 70 N I 21 N "100k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 182 "N-000344" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54600 23100 2700 15 4D4BE500 4BF2FF03 ~~ +Li SM0805_FIXEDMASK +Sc 4BF2FF03 +AR /4BAA6ABD/4BF2FDAF +Op 0 0 0 +At SMD +T0 -125 1325 320 320 2700 70 N V 21 N "R511" +T1 0 0 320 320 2700 70 N I 21 N "20k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/Memory/SRAM_Vcc" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/Memory/RAM_/CE" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54375 36825 1800 0 4C5945EA 4BF5A49C ~~ +Li SM0805_FIXEDMASK +Sc 4BF5A49C +AR /4B6E18FC/4BF5A43F +Op 0 0 0 +At SMD +T0 0 -700 320 320 1800 70 M V 20 N "C223" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 70100 36600 0 0 4C594654 4BF5A49E ~~ +Li SM0805_FIXEDMASK +Sc 4BF5A49E +AR /4B6E18FC/4BF5A441 +Op 0 0 0 +At SMD +T0 -1525 50 320 320 0 70 M V 20 N "C224" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 59213 35118 0 0 4C594605 4BF6C25D ~~ +Li SM0805_FIXEDMASK +Sc 4BF6C25D +AR /4B6ED75B/4BF6BFBB +Op 0 0 0 +At SMD +T0 1312 32 320 320 0 70 M V 20 N "C411" +T1 0 0 320 320 0 70 M I 20 N "10u" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 48000 33450 0 0 4D2A0FA5 4C139698 ~~ +Li SM0805_FIXEDMASK +Sc 4C139698 +AR /4B6ED75B/4BF6BFE1 +Op 0 0 0 +At SMD +T0 0 -600 320 320 0 70 M V 20 N "C401" +T1 -1525 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 47800 31800 2700 0 4C5945AD 4BF6C261 ~~ +Li SM0805_FIXEDMASK +Sc 4BF6C261 +AR /4B6ED75B/4BF6BFE2 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 2700 70 M V 20 N "C402" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 49600 33450 1800 0 4C59459D 4BF6C263 ~~ +Li SM0805_FIXEDMASK +Sc 4BF6C263 +AR /4B6ED75B/4BF6BFE5 +Op 0 0 0 +At SMD +T0 0 -675 320 320 1800 70 M V 20 N "C403" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 47975 34750 900 0 4D2A0FBB 4BF6C265 ~~ +Li SM0805_FIXEDMASK +Sc 4BF6C265 +AR /4B6ED75B/4BF6BFE6 +Op 0 0 0 +At SMD +T0 -1375 350 320 320 900 70 M V 20 N "C404" +T1 0 650 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 74525 25425 900 15 4C594435 4C59442F ~~ +Li SM0805_FIXEDMASK +Sc 4C59442F +AR /4B6ED75B/4BF847A7 +Op 0 0 0 +At SMD +T0 0 -600 320 320 900 70 N V 21 N "R401" +T1 0 0 320 320 900 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 161 "N-000294" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 171 "N-000316" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 72300 25425 900 15 4C59443D 4BF851B9 ~~ +Li SM0805_FIXEDMASK +Sc 4BF851B9 +AR /4B6ED75B/4BF847B1 +Op 0 0 0 +At SMD +T0 0 -625 320 320 900 70 N V 21 N "R402" +T1 0 0 320 320 900 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 173 "N-000322" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 164 "N-000305" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 51725 29700 0 15 4C593160 4BF851BB ~~ +Li SM0805_FIXEDMASK +Sc 4BF851BB +AR /4B6ED75B/4BF850A9 +Op 0 0 0 +At SMD +T0 1311 8 320 320 0 70 N V 21 N "R406" +T1 0 0 320 320 0 70 N I 21 N "100" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 175 "N-000324" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 188 "PROG_B" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 50000 39300 900 15 4C59318C 4BF851BD ~~ +Li SM0805_FIXEDMASK +Sc 4BF851BD +AR /4B6ED75B/4BF850D1 +Op 0 0 0 +At SMD +T0 0 -600 320 320 900 70 N V 21 N "R405" +T1 0 0 320 320 900 70 N I 21 N "100" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 68 "CCLK" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 176 "N-000327" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 39450 41450 1800 15 4C592C70 4BF99039 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99039 +AR /4B6EC9C3/4BF98AA2 +Op 0 0 0 +At SMD +T0 1350 0 320 320 1800 70 N V 21 N "C343" +T1 0 0 320 320 1800 70 N I 21 N "100n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 156 "N-000279" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 39450 42200 1800 15 4C592C7A 4BF9903B ~~ +Li SM0805_FIXEDMASK +Sc 4BF9903B +AR /4B6EC9C3/4BF98AA5 +Op 0 0 0 +At SMD +T0 1350 0 320 320 1800 70 N V 21 N "C344" +T1 0 0 320 320 1800 70 N I 21 N "10u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 156 "N-000279" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 39450 42950 1800 15 4C592C85 4BF9903D ~~ +Li SM0805_FIXEDMASK +Sc 4BF9903D +AR /4B6EC9C3/4BF98AAB +Op 0 0 0 +At SMD +T0 1325 0 320 320 1800 70 N V 21 N "C345" +T1 0 0 320 320 1800 70 N I 21 N "10u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 157 "N-000281" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 41950 45925 0 15 4C592E73 4BF9903F ~~ +Li SM0805_FIXEDMASK +Sc 4BF9903F +AR /4B6EC9C3/4BF98E9E +Op 0 0 0 +At SMD +T0 675 675 320 320 0 70 N V 21 N "C347" +T1 0 0 320 320 0 70 N I 21 N "10n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 67 "AUDIO_R" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 40325 45225 1800 15 4E0FB3F3 4BF99041 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99041 +AR /4B6EC9C3/4BF98EB4 +Op 0 0 0 +At SMD +T0 25 -2675 320 320 1800 70 N V 21 N "R343" +T1 0 0 320 320 1800 70 N I 21 N "470" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 66 "AUDIO_L" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 159 "N-000285" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 40325 44525 0 15 4E0FB3F7 4BF99043 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99043 +AR /4B6EC9C3/4BF98EB9 +Op 0 0 0 +At SMD +T0 -25 2775 320 320 0 70 N V 21 N "R344" +T1 0 0 320 320 0 70 N I 21 N "10k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 159 "N-000285" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 40325 43825 0 15 4E0FB3E3 4BF99045 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99045 +AR /4B6EC9C3/4BF98EBB +Op 0 0 0 +At SMD +T0 -25 2875 320 320 0 70 N V 21 N "C348" +T1 0 0 320 320 0 70 N I 21 N "3.3u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 159 "N-000285" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 155 "N-000278" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 41950 43825 1800 15 4DB42F0A 4BF99047 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99047 +AR /4B6EC9C3/4BF98EBE +Op 0 0 0 +At SMD +T0 -1350 650 320 320 1800 70 N V 21 N "C346" +T1 0 0 320 320 1800 70 N I 21 N "3.3u" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "N-000277" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 160 "N-000286" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 40325 45925 1800 15 4E0FB3EF 4BF99049 ~~ +Li SM0805_FIXEDMASK +Sc 4BF99049 +AR /4B6EC9C3/4BF98EBF +Op 0 0 0 +At SMD +T0 25 -2575 320 320 1800 70 N V 21 N "C349" +T1 0 0 320 320 1800 70 N I 21 N "10n" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 66 "AUDIO_L" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 41950 44525 1800 15 4C592E8F 4BF9904B ~~ +Li SM0805_FIXEDMASK +Sc 4BF9904B +AR /4B6EC9C3/4BF98EC4 +Op 0 0 0 +At SMD +T0 -1350 0 320 320 1800 70 N V 21 N "R342" +T1 0 0 320 320 1800 70 N I 21 N "10k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "N-000277" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 41950 45225 0 15 4C592E86 4BF9904D ~~ +Li SM0805_FIXEDMASK +Sc 4BF9904D +AR /4B6EC9C3/4BF98EC6 +Op 0 0 0 +At SMD +T0 1350 0 320 320 0 70 N V 21 N "R341" +T1 0 0 320 320 0 70 N I 21 N "470" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 67 "AUDIO_R" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "N-000277" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 55125 45175 2700 0 4D20F37A 4BFB12D0 ~~ +Li SM0805_FIXEDMASK +Sc 4BFB12D0 +AR /4B6E16F2/4BFB1190 +Op 0 0 0 +At SMD +T0 -1325 -25 320 320 2700 70 M V 20 N "C104" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 60925 45175 2700 0 4C5946FA 4BFB12D2 ~~ +Li SM0805_FIXEDMASK +Sc 4BFB12D2 +AR /4B6E16F2/4BFB1192 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 2700 70 M V 20 N "C105" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66625 43925 2700 0 4C5946D9 4BFB12D4 ~~ +Li SM0805_FIXEDMASK +Sc 4BFB12D4 +AR /4B6E16F2/4BFB1194 +Op 0 0 0 +At SMD +T0 -1325 0 320 320 2700 70 M V 20 N "C106" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66625 45775 900 0 4C5946CC 4BFF8E85 ~~ +Li SM0805_FIXEDMASK +Sc 4BFF8E85 +AR /4B6E16F2/4BFB1197 +Op 0 0 0 +At SMD +T0 0 675 320 320 900 70 M V 20 N "C113" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 60925 47025 900 0 4DB4983C 4BFB12D8 ~~ +Li SM0805_FIXEDMASK +Sc 4BFB12D8 +AR /4B6E16F2/4BFB1199 +Op 0 0 0 +At SMD +T0 -1350 0 320 320 900 70 M V 20 N "C112" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 55125 47025 900 0 4DB497AF 4BFB12DA ~~ +Li SM0805_FIXEDMASK +Sc 4BFB12DA +AR /4B6E16F2/4BFB119A +Op 0 0 0 +At SMD +T0 -1375 275 320 320 900 70 M V 20 N "C111" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 42550 35050 900 15 4C593112 4C1396A1 ~~ +Li SM0805_FIXEDMASK +Sc 4C1396A1 +AR /4B6ED75B/4BEECBD1 +Op 0 0 0 +At SMD +T0 -25 -600 320 320 900 70 N V 21 N "C409" +T1 0 0 320 320 900 70 N I 21 N "10p" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 179 "N-000338" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 50575 27025 2700 0 4C5945D1 4C5608E7 ~~ +Li SM0805_FIXEDMASK +Sc 4C5608E7 +AR /4B6ED75B/4C5608C6 +Op 0 0 0 +At SMD +T0 1300 -25 320 320 2700 70 M V 20 N "R421" +T1 0 0 320 320 2700 70 M I 20 N "33" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 170 "N-000315" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 165 "N-000309" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 49875 27025 2700 0 4C5945CB 4C5608E9 ~~ +Li SM0805_FIXEDMASK +Sc 4C5608E9 +AR /4B6ED75B/4C5608C9 +Op 0 0 0 +At SMD +T0 1275 25 320 320 2700 70 M V 20 N "R422" +T1 0 0 320 320 2700 70 M I 20 N "33" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 166 "N-000310" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 169 "N-000314" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SOT23EBC +Po 56075 47125 1800 0 4E137307 4C7EAD87 ~~ +Li SOT23EBC +Cd Module CMS SOT23 Transistore EBC +Kw CMS SOT +Sc 4C7EAD87 +AR /4B6E16F2/4C7EAD01 +Op 0 0 0 +At SMD +T0 -225 1775 320 320 2700 70 M V 20 N "Q101" +T1 100 975 320 320 1800 70 M I 20 N "2N2222A" +DS -600 150 600 150 75 20 +DS 600 150 600 -150 75 20 +DS 600 -150 -600 -150 75 20 +DS -600 -150 -600 150 75 20 +$PAD +Sh "1" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -350 400 +$EndPAD +$PAD +Sh "2" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 97 "N-000036" +Po 350 400 +$EndPAD +$PAD +Sh "3" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 141 "N-000147" +Po 0 -400 +$EndPAD +$SHAPE3D +Na "smd/cms_sot23.wrl" +Sc 0.130000 0.150000 0.150000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23EBC +$MODULE SM0805_FIXEDMASK +Po 56950 46650 2700 15 4D20DBD3 4C7EAF70 ~~ +Li SM0805_FIXEDMASK +Sc 4C7EAF70 +AR /4B6E16F2/4C7EAEBF +Op 0 0 0 +At SMD +T0 1375 -175 320 320 2700 70 N V 21 N "R102" +T1 0 0 320 320 2700 70 N I 21 N "100k" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 97 "N-000036" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 56950 45100 2700 15 4D20DBDD 4C7EAF72 ~~ +Li SM0805_FIXEDMASK +Sc 4C7EAF72 +AR /4B6E16F2/4C7EAF13 +Op 0 0 0 +At SMD +T0 -1300 0 320 320 2700 70 N V 21 N "R103" +T1 0 0 320 320 2700 70 N I 21 N "4k7" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 310 "SNES_IRQ_EN" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 97 "N-000036" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE PAD_1x1mm +Po 58825 42275 0 15 4C814406 4C7FF8C4 ~~ +Li PAD_1x1mm +Sc 4C7FF8C4 +AR /4B6E18FC/4C7FF87E +Op 0 0 0 +T0 1025 25 320 320 0 70 N V 21 N "P113" +T1 50 575 320 320 0 70 N V 21 N "CONN_1" +DS -315 -315 315 -315 75 21 +DS 315 -315 315 315 75 21 +DS 315 315 -315 315 75 21 +DS -315 315 -315 -315 75 21 +$PAD +Sh "1" R 394 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 152 "N-000193" +Po 0 0 +$EndPAD +$EndMODULE PAD_1x1mm +$MODULE SM0805_FIXEDMASK +Po 49525 35925 900 0 4D20DD62 4C829461 ~~ +Li SM0805_FIXEDMASK +Sc 4C829461 +AR /4B6ED75B/4C814430 +Op 0 0 0 +At SMD +T0 0 -625 320 320 900 70 M V 20 N "R407" +T1 0 0 320 320 900 70 M I 20 N "10k" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 185 "P2.10" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE GS2 +Po 47925 42275 0 15 4D20F05A 4C863298 ~~ +Li GS2 +Cd Pontet Goute de soudure +Sc 4C863298 +AR /4B6ED75B/4C86265B +Op 0 0 0 +At VIRTUAL +T0 700 0 320 320 900 70 N V 21 N "JP401" +T1 -700 0 320 320 900 70 N I 21 N "JUMPER" +DS -350 -500 -350 500 75 21 +DS 350 500 350 -500 75 21 +DS 350 500 -350 500 75 21 +DS -350 -500 350 -500 75 21 +$PAD +Sh "1" R 500 380 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 163 "N-000300" +Po 0 -250 +$EndPAD +$PAD +Sh "2" R 500 380 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 72 "CIC_MCLR" +Po 0 250 +$EndPAD +$EndMODULE GS2 +$MODULE DIP-8__300 +Po 49050 46075 1800 15 4E2BF7AC 4BAA9371 ~~ +Li DIP-8__300 +Cd 8 pins DIL package, round pads +Kw DIL +Sc 4BAA9371 +AR /4B6EC9C3/4BAA92DB +Op 0 0 0 +T0 2350 -525 320 320 2700 70 N V 21 N "U331" +T1 -75 -1400 320 320 1800 70 N V 21 N "PIC12F629-I/P" +DS -2000 -500 -1500 -500 100 21 +DS -1500 -500 -1500 500 100 21 +DS -1500 500 -2000 500 100 21 +DS -2000 -1000 2000 -1000 100 21 +DS 2000 -1000 2000 1000 100 21 +DS 2000 1000 -2000 1000 100 21 +DS -2000 1000 -2000 -1000 100 21 +$PAD +Sh "1" R 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 6 "+5V" +Po -1500 1500 +$EndPAD +$PAD +Sh "2" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 158 "N-000284" +Po -500 1500 +$EndPAD +$PAD +Sh "3" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 74 "CIC_STATUS" +Po 500 1500 +$EndPAD +$PAD +Sh "4" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 72 "CIC_MCLR" +Po 1500 1500 +$EndPAD +$PAD +Sh "5" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 73 "CIC_RESET" +Po 1500 -1500 +$EndPAD +$PAD +Sh "6" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 71 "CIC_DATA1" +Po 500 -1500 +$EndPAD +$PAD +Sh "7" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 70 "CIC_DATA0" +Po -500 -1500 +$EndPAD +$PAD +Sh "8" C 550 550 0 0 1800 +Dr 320 0 0 +At STD N 00E0FFFF +Ne 88 "GND" +Po -1500 -1500 +$EndPAD +$SHAPE3D +Na "dil/dil_8.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE DIP-8__300 +$MODULE SM0805_FIXEDMASK +Po 49800 48575 2700 15 4DB454C7 4D0BC965 ~~ +Li SM0805_FIXEDMASK +Sc 4D0BC965 +AR /4B6EC9C3/4CA6556E +Op 0 0 0 +At SMD +T0 25 2250 320 320 2700 70 N V 21 N "R332" +T1 0 0 320 320 2700 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 70 "CIC_DATA0" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 83 "EXT_CIC_DATA0" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 48300 48575 900 15 4DB454DC 4D0BC967 ~~ +Li SM0805_FIXEDMASK +Sc 4D0BC967 +AR /4B6EC9C3/4CA65577 +Op 0 0 0 +At SMD +T0 -25 -1800 320 320 900 70 N V 21 N "R333" +T1 0 0 320 320 900 70 N I 21 N "680" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 84 "EXT_CIC_DATA1" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 71 "CIC_DATA1" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 48550 46550 900 0 4D20DD25 4D0BC969 ~~ +Li SM0805_FIXEDMASK +Sc 4D0BC969 +AR /4B6EC9C3/4CA65597 +Op 0 0 0 +At SMD +T0 0 -1275 320 320 900 70 M V 20 N "C333" +T1 0 0 320 320 900 70 M I 20 N "100p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 71 "CIC_DATA1" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 49550 46550 900 0 4D20DD2A 4D0BC96B ~~ +Li SM0805_FIXEDMASK +Sc 4D0BC96B +AR /4B6EC9C3/4CA655D4 +Op 0 0 0 +At SMD +T0 0 -1675 320 320 900 70 M V 20 N "C332" +T1 0 0 320 320 900 70 M I 20 N "100p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 70 "CIC_DATA0" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66225 49025 900 0 4D20DDB3 4D1787CE ~~ +Li SM0805_FIXEDMASK +Sc 4D1787CE +AR /4B6E16F2/4D115250 +Op 0 0 0 +At SMD +T0 0 -825 320 320 900 70 M V 20 N "C128" +T1 0 0 320 320 900 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 146 "N-000156" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 66225 47675 2700 0 4D96E90A 4D1787D0 ~~ +Li SM0805_FIXEDMASK +Sc 4D1787D0 +AR /4B6E16F2/4D11524F +Op 0 0 0 +At SMD +T0 0 825 320 320 2700 70 M V 20 N "C127" +T1 0 0 320 320 2700 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 142 "N-000151" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 71400 47900 2700 15 4DB5B204 4D1787D2 ~~ +Li SM0805_FIXEDMASK +Sc 4D1787D2 +AR /4B6E16F2/4D11524E +Op 0 0 0 +At SMD +T0 0 625 320 320 2700 70 N V 21 N "C126" +T1 0 0 320 320 2700 70 N I 21 N "10p" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 61 "/SNES_Slot/SNES_EXT_REFRESH" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 57375 47025 900 0 4DB497E0 4D1787D4 ~~ +Li SM0805_FIXEDMASK +Sc 4D1787D4 +AR /4B6E16F2/4D113CAF +Op 0 0 0 +At SMD +T0 1350 -125 320 320 900 70 M V 20 N "C125" +T1 0 0 320 320 900 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 95 "N-000012" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 53700 47025 900 0 4E136363 4D1787D6 ~~ +Li SM0805_FIXEDMASK +Sc 4D1787D6 +AR /4B6E16F2/4D113CAC +Op 0 0 0 +At SMD +T0 1400 0 320 320 900 70 M V 20 N "C124" +T1 0 0 320 320 900 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 96 "N-000013" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 56800 48825 0 0 4D20DD7C 4D1787D8 ~~ +Li SM0805_FIXEDMASK +Sc 4D1787D8 +AR /4B6E16F2/4D113CAA +Op 0 0 0 +At SMD +T0 0 -650 320 320 0 70 M V 20 N "C123" +T1 0 0 320 320 0 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 141 "N-000147" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 58075 47025 900 0 4DB49837 4D1787DA ~~ +Li SM0805_FIXEDMASK +Sc 4D1787DA +AR /4B6E16F2/4D113C9C +Op 0 0 0 +At SMD +T0 -1350 25 320 320 900 70 M V 20 N "C122" +T1 0 0 320 320 900 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 137 "N-000143" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 54425 47025 900 0 4E136350 4D1787DC ~~ +Li SM0805_FIXEDMASK +Sc 4D1787DC +AR /4B6E16F2/4D113C55 +Op 0 0 0 +At SMD +T0 1400 0 320 320 900 70 M V 20 N "C121" +T1 0 0 320 320 900 70 M I 20 N "10p" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 138 "N-000144" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 65225 32150 0 0 4D252E94 4D252B91 ~~ +Li SM0805_FIXEDMASK +Sc 4D252B91 +AR /4B6E18FC/4D252B5C +Op 0 0 0 +At SMD +T0 0 675 320 320 0 70 M V 20 N "C214" +T1 0 0 320 320 0 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE HC49US +Po 43175 36900 0 15 4D2592DD 4C13968F ~~ +Li HC49US +Sc 4C13968F +AR /4B6ED75B/4BC243C8 +Op 0 0 0 +T0 2700 1250 320 320 0 70 N V 21 N "X401" +T1 0 0 320 320 0 70 N V 21 N "12MHz" +DS -1181 807 1181 807 80 21 +DS -1181 -807 1181 -807 80 21 +DA 1181 0 1988 0 900 80 21 +DA 1181 0 1181 -807 900 80 21 +DA -1181 0 -1181 807 900 80 21 +DA -1181 0 -1988 0 900 80 21 +DS -2244 -925 2244 -925 80 21 +DS 2244 -925 2244 925 80 21 +DS 2244 925 -2244 925 80 21 +DS -2244 925 -2244 -925 80 21 +$PAD +Sh "1" R 2166 787 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 180 "N-000339" +Po -1673 0 +$EndPAD +$PAD +Sh "2" R 2166 787 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 181 "N-000340" +Po 1673 0 +$EndPAD +$EndMODULE HC49US +$MODULE SM0805_FIXEDMASK +Po 61725 39500 900 0 4D2F5DE4 4D2F4360 ~~ +Li SM0805_FIXEDMASK +Sc 4D2F4360 +AR /4B6E18FC/4D2F4312 +Op 0 0 0 +At SMD +T0 1400 25 320 320 900 70 M V 20 N "C209" +T1 0 0 320 320 900 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 57150 38550 1800 0 4D2F5CBD 4D2F4362 ~~ +Li SM0805_FIXEDMASK +Sc 4D2F4362 +AR /4B6E18FC/4D2F4344 +Op 0 0 0 +At SMD +T0 1325 -25 320 320 1800 70 M V 20 N "C231" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 59000 36875 2700 0 4D2F5CC6 4D2F4494 ~~ +Li SM0805_FIXEDMASK +Sc 4D2F4494 +AR /4B6E18FC/4D2F4480 +Op 0 0 0 +At SMD +T0 1300 -25 320 320 2700 70 M V 20 N "C215" +T1 0 0 320 320 2700 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 63100 40750 1800 0 4D2F5C95 4D2F499D ~~ +Li SM0805_FIXEDMASK +Sc 4D2F499D +AR /4B6E18FC/4D2F4979 +Op 0 0 0 +At SMD +T0 -1375 -25 320 320 1800 70 M V 20 N "C232" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 67475 36025 1800 0 4D2F5C55 4D2F499F ~~ +Li SM0805_FIXEDMASK +Sc 4D2F499F +AR /4B6E18FC/4D2F497B +Op 0 0 0 +At SMD +T0 1325 -25 320 320 1800 70 M V 20 N "C233" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SM0805_FIXEDMASK +Po 67475 31300 1800 0 4D2F5CA5 4D2F5753 ~~ +Li SM0805_FIXEDMASK +Sc 4D2F5753 +AR /4B6E18FC/4D2F566A +Op 0 0 0 +At SMD +T0 -1325 -25 320 320 1800 70 M V 20 N "C234" +T1 0 0 320 320 1800 70 M I 20 N "100n" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE TSOPII-32 +Po 59975 24500 0 15 4D4BAF03 4BAA892D ~~ +Li TSOPII-32 +Sc 4BAA892D +AR /4BAA6ABD/4D49598F +Op 0 0 0 +T0 4925 1725 320 320 0 70 N V 21 N "U511" +T1 0 0 320 320 0 70 N V 21 N "CY62148EV30-ZSXI" +DC -3760 1398 -3524 1417 80 21 +DS -4153 -1850 4153 -1850 75 21 +DS 4153 -1850 4153 1850 75 21 +DS -4153 1850 4153 1850 75 21 +DS -4153 -1850 -4153 1850 75 21 +$PAD +Sh "1" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 201 "RAM_A17" +Po -3749 2249 +$EndPAD +$PAD +Sh "2" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 200 "RAM_A16" +Po -3249 2249 +$EndPAD +$PAD +Sh "3" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 198 "RAM_A14" +Po -2749 2249 +$EndPAD +$PAD +Sh "4" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 196 "RAM_A12" +Po -2249 2249 +$EndPAD +$PAD +Sh "5" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 208 "RAM_A7" +Po -1749 2249 +$EndPAD +$PAD +Sh "6" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 207 "RAM_A6" +Po -1249 2249 +$EndPAD +$PAD +Sh "7" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 206 "RAM_A5" +Po -749 2249 +$EndPAD +$PAD +Sh "8" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 205 "RAM_A4" +Po -249 2249 +$EndPAD +$PAD +Sh "9" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 204 "RAM_A3" +Po 249 2249 +$EndPAD +$PAD +Sh "10" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 203 "RAM_A2" +Po 749 2249 +$EndPAD +$PAD +Sh "11" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 193 "RAM_A1" +Po 1249 2249 +$EndPAD +$PAD +Sh "12" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 192 "RAM_A0" +Po 1749 2249 +$EndPAD +$PAD +Sh "13" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 211 "RAM_DQ0" +Po 2249 2249 +$EndPAD +$PAD +Sh "14" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 212 "RAM_DQ1" +Po 2749 2249 +$EndPAD +$PAD +Sh "15" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 213 "RAM_DQ2" +Po 3249 2249 +$EndPAD +$PAD +Sh "16" R 295 499 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 3749 2249 +$EndPAD +$PAD +Sh "17" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 214 "RAM_DQ3" +Po 3749 -2249 +$EndPAD +$PAD +Sh "18" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 215 "RAM_DQ4" +Po 3249 -2249 +$EndPAD +$PAD +Sh "19" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 216 "RAM_DQ5" +Po 2749 -2249 +$EndPAD +$PAD +Sh "20" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 217 "RAM_DQ6" +Po 2249 -2249 +$EndPAD +$PAD +Sh "21" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 218 "RAM_DQ7" +Po 1749 -2249 +$EndPAD +$PAD +Sh "22" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/Memory/RAM_/CE" +Po 1249 -2249 +$EndPAD +$PAD +Sh "23" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 194 "RAM_A10" +Po 749 -2249 +$EndPAD +$PAD +Sh "24" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 190 "RAM_/OE" +Po 249 -2249 +$EndPAD +$PAD +Sh "25" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 195 "RAM_A11" +Po -249 -2249 +$EndPAD +$PAD +Sh "26" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 210 "RAM_A9" +Po -749 -2249 +$EndPAD +$PAD +Sh "27" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 209 "RAM_A8" +Po -1249 -2249 +$EndPAD +$PAD +Sh "28" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 197 "RAM_A13" +Po -1749 -2249 +$EndPAD +$PAD +Sh "29" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 191 "RAM_/WE" +Po -2249 -2249 +$EndPAD +$PAD +Sh "30" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 202 "RAM_A18" +Po -2749 -2249 +$EndPAD +$PAD +Sh "31" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 199 "RAM_A15" +Po -3249 -2249 +$EndPAD +$PAD +Sh "32" R 295 499 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/Memory/SRAM_Vcc" +Po -3749 -2249 +$EndPAD +$EndMODULE TSOPII-32 +$MODULE SOT23GDS +Po 54450 48875 1800 0 4DB497C3 4D4BCAFC ~~ +Li SOT23GDS +Cd Module CMS SOT23 Transistore EBC +Kw CMS SOT +Sc 4D4BCAFC +AR /4B6EC9C3/4D4BCF29 +Op 0 0 0 +At SMD +T0 0 875 320 320 1800 70 M V 20 N "Q301" +T1 -25 -1150 320 320 1800 70 M V 20 N "IRLML6402PbF" +DS -600 150 600 150 75 20 +DS 600 150 600 -150 75 20 +DS 600 -150 -600 -150 75 20 +DS -600 -150 -600 150 75 20 +$PAD +Sh "S" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "+5V" +Po -350 400 +$EndPAD +$PAD +Sh "G" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 153 "N-000275" +Po 350 400 +$EndPAD +$PAD +Sh "D" R 360 360 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 7 "+5VL" +Po 0 -400 +$EndPAD +$SHAPE3D +Na "smd/cms_sot23.wrl" +Sc 0.130000 0.150000 0.150000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23GDS +$MODULE SM0805_FIXEDMASK +Po 53125 48475 0 0 4DB4304F 4D4BEB99 ~~ +Li SM0805_FIXEDMASK +Sc 4D4BEB99 +AR /4B6EC9C3/4D4BE786 +Op 0 0 0 +At SMD +T0 -1350 -150 320 320 0 70 M V 20 N "R301" +T1 0 0 300 300 0 60 M I 20 N "20k" +DS 200 -350 650 -350 75 20 +DS -650 -350 -200 -350 75 20 +DS 650 350 200 350 75 20 +DS -650 350 -200 350 75 20 +DS 650 350 650 -350 75 20 +DS -650 -350 -650 350 75 20 +$PAD +Sh "1" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 153 "N-000275" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE R_PACK_0804 +Po 51450 48450 2700 15 4D983205 4D96383B ~~ +Li R_PACK_0804 +Sc 4D96383B +AR /4B6E16F2/4D9630F0 +Op 0 0 0 +T0 875 -25 320 320 3600 70 N V 21 N "RA101" +T1 0 0 320 320 2700 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 123 "N-000092" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 127 "N-000103" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 58 "/SNES_Slot/SNES_EXT_PA5" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 55 "/SNES_Slot/SNES_EXT_PA2" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 126 "N-000102" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 128 "N-000104" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 56 "/SNES_Slot/SNES_EXT_PA3" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 57 "/SNES_Slot/SNES_EXT_PA4" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 53450 49075 0 15 4D96E870 4D963839 ~~ +Li R_PACK_0804 +Sc 4D963839 +AR /4B6E16F2/4D9630F4 +Op 0 0 0 +T0 -475 750 320 320 0 70 N V 21 N "RA102" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 130 "N-000106" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 96 "N-000013" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 54 "/SNES_Slot/SNES_EXT_PA1" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 19 "/SNES_Slot/SNES_EXT_/WR" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 129 "N-000105" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 138 "N-000144" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 44 "/SNES_Slot/SNES_EXT_CPU_CLK" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 53 "/SNES_Slot/SNES_EXT_PA0" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 57400 49075 0 15 4D96E8A1 4D963837 ~~ +Li R_PACK_0804 +Sc 4D963837 +AR /4B6E16F2/4D96310E +Op 0 0 0 +T0 325 750 320 320 0 70 N V 21 N "RA105" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 95 "N-000012" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 137 "N-000143" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "/SNES_Slot/SNES_EXT_/RD" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 18 "/SNES_Slot/SNES_EXT_/ROMSEL" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 141 "N-000147" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 99 "N-000038" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 36 "/SNES_Slot/SNES_EXT_A23" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/SNES_Slot/SNES_EXT_/IRQ" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 58925 49075 0 15 4D96E8C8 4D963835 ~~ +Li R_PACK_0804 +Sc 4D963835 +AR /4B6E16F2/4D963115 +Op 0 0 0 +T0 0 -675 320 320 0 70 N V 21 N "RA106" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 101 "N-000040" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 102 "N-000041" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 35 "/SNES_Slot/SNES_EXT_A22" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 21 "/SNES_Slot/SNES_EXT_A1" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 100 "N-000039" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 104 "N-000045" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 34 "/SNES_Slot/SNES_EXT_A21" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 20 "/SNES_Slot/SNES_EXT_A0" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 60050 49075 0 15 4D96E8CD 4D963833 ~~ +Li R_PACK_0804 +Sc 4D963833 +AR /4B6E16F2/4D963117 +Op 0 0 0 +T0 0 750 320 320 0 70 N V 21 N "RA107" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 106 "N-000049" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 108 "N-000053" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 33 "/SNES_Slot/SNES_EXT_A20" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 37 "/SNES_Slot/SNES_EXT_A3" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 105 "N-000047" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 109 "N-000056" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 31 "/SNES_Slot/SNES_EXT_A19" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 32 "/SNES_Slot/SNES_EXT_A2" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 61225 49075 0 15 4D96E8D2 4D963831 ~~ +Li R_PACK_0804 +Sc 4D963831 +AR /4B6E16F2/4D963119 +Op 0 0 0 +T0 325 750 320 320 0 70 N V 21 N "RA108" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 125 "N-000100" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "N-000042" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 30 "/SNES_Slot/SNES_EXT_A18" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 39 "/SNES_Slot/SNES_EXT_A5" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 124 "N-000095" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 98 "N-000037" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 29 "/SNES_Slot/SNES_EXT_A17" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 38 "/SNES_Slot/SNES_EXT_A4" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 62875 49075 0 15 4D96E8D6 4D96382F ~~ +Li R_PACK_0804 +Sc 4D96382F +AR /4B6E16F2/4D963103 +Op 0 0 0 +T0 175 750 320 320 0 70 N V 21 N "RA109" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 134 "N-000125" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 133 "N-000120" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 28 "/SNES_Slot/SNES_EXT_A16" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 41 "/SNES_Slot/SNES_EXT_A7" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 107 "N-000050" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "N-000127" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 27 "/SNES_Slot/SNES_EXT_A15" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 40 "/SNES_Slot/SNES_EXT_A6" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 64050 49075 0 15 4D96E8DD 4D96382D ~~ +Li R_PACK_0804 +Sc 4D96382D +AR /4B6E16F2/4D963107 +Op 0 0 0 +T0 0 -725 320 320 0 70 N V 21 N "RA110" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "N-000161" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 150 "N-000160" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 26 "/SNES_Slot/SNES_EXT_A14" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 43 "/SNES_Slot/SNES_EXT_A9" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 136 "N-000137" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 149 "N-000159" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 25 "/SNES_Slot/SNES_EXT_A13" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 42 "/SNES_Slot/SNES_EXT_A8" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 65225 49075 0 15 4D96E8E6 4D96382B ~~ +Li R_PACK_0804 +Sc 4D96382B +AR /4B6E16F2/4D96310A +Op 0 0 0 +T0 0 750 320 320 0 70 N V 21 N "RA111" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 148 "N-000158" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 147 "N-000157" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 24 "/SNES_Slot/SNES_EXT_A12" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 23 "/SNES_Slot/SNES_EXT_A11" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 140 "N-000146" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 146 "N-000156" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "/SNES_Slot/SNES_EXT_/PARD" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 22 "/SNES_Slot/SNES_EXT_A10" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 68875 47700 900 0 4D96E851 4D963829 ~~ +Li R_PACK_0804 +Sc 4D963829 +AR /4B6E16F2/4D96310C +Op 0 0 0 +T0 0 775 320 320 900 70 M V 20 N "RA112" +T1 0 0 320 320 900 70 M V 20 N "100" +DS -551 394 551 394 75 20 +DS 551 394 551 -394 75 20 +DS 551 -394 -551 -394 75 20 +DS -551 -394 -551 394 75 20 +$PAD +Sh "7" R 118 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 59 "/SNES_Slot/SNES_EXT_PA6" +Po -98 197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 60 "/SNES_Slot/SNES_EXT_PA7" +Po 98 197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 143 "N-000152" +Po -98 -197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 144 "N-000153" +Po 98 -197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 16 "/SNES_Slot/SNES_EXT_/PAWR" +Po -335 197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 61 "/SNES_Slot/SNES_EXT_REFRESH" +Po 335 197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 145 "N-000154" +Po 335 -197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 142 "N-000151" +Po -335 -197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 54550 49075 0 15 4EBE961A 4D95D318 ~~ +Li R_PACK_0804 +Sc 4D95D318 +AR /4B6E16F2/4D95CDCD +Op 0 0 0 +T0 0 750 320 320 0 70 N V 21 N "RA103" +T1 0 0 320 320 0 70 N V 21 N "FB" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 116 "N-000078" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 110 "N-000071" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 52 "/SNES_Slot/SNES_EXT_D7" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 47 "/SNES_Slot/SNES_EXT_D2" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000074" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 120 "N-000086" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 51 "/SNES_Slot/SNES_EXT_D6" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 48 "/SNES_Slot/SNES_EXT_D3" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 55700 49075 0 15 4EBE961F 4D95D316 ~~ +Li R_PACK_0804 +Sc 4D95D316 +AR /4B6E16F2/4D95CDD4 +Op 0 0 0 +T0 350 750 320 320 0 70 N V 21 N "RA104" +T1 0 0 320 320 0 70 N V 21 N "FB" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 131 "N-000107" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "N-000072" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 50 "/SNES_Slot/SNES_EXT_D5" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 45 "/SNES_Slot/SNES_EXT_D0" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 122 "N-000091" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000075" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 49 "/SNES_Slot/SNES_EXT_D4" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 46 "/SNES_Slot/SNES_EXT_D1" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 55950 42925 0 15 4D9F94A2 4D97B6C6 ~~ +Li R_PACK_0804 +Sc 4D97B6C6 +AR /4B6E16F2/4D97B45F +Op 0 0 0 +T0 -75 725 320 320 0 70 N V 21 N "RA114" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "SNES_D5" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 302 "SNES_D0" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 139 "N-000145" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 121 "N-000087" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 303 "SNES_D1" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 306 "SNES_D4" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 118 "N-000083" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 132 "N-000108" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE R_PACK_0804 +Po 54850 42925 0 15 4D9F94AA 4D97B6C8 ~~ +Li R_PACK_0804 +Sc 4D97B6C8 +AR /4B6E16F2/4D97B45C +Op 0 0 0 +T0 -600 725 320 320 0 70 N V 21 N "RA113" +T1 0 0 320 320 0 70 N V 21 N "100" +DS -551 -394 551 -394 75 21 +DS 551 -394 551 394 75 21 +DS 551 394 -551 394 75 21 +DS -551 394 -551 -394 75 21 +$PAD +Sh "7" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 309 "SNES_D7" +Po -98 -197 +$EndPAD +$PAD +Sh "6" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 304 "SNES_D2" +Po 98 -197 +$EndPAD +$PAD +Sh "2" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 117 "N-000082" +Po -98 197 +$EndPAD +$PAD +Sh "3" R 118 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 115 "N-000076" +Po 98 197 +$EndPAD +$PAD +Sh "8" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 305 "SNES_D3" +Po -335 -197 +$EndPAD +$PAD +Sh "5" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 308 "SNES_D6" +Po 335 -197 +$EndPAD +$PAD +Sh "4" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 112 "N-000073" +Po 335 197 +$EndPAD +$PAD +Sh "1" R 197 197 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 119 "N-000084" +Po -335 197 +$EndPAD +$EndMODULE R_PACK_0804 +$MODULE SM0805_FIXEDMASK +Po 44025 43825 1800 15 4DB42EDA 4DB2EAF2 ~~ +Li SM0805_FIXEDMASK +Sc 4DB2EAF2 +AR /4B6EC9C3/4DB2EA56 +Op 0 0 0 +At SMD +T0 -1450 -50 320 320 1800 70 N V 21 N "FB341" +T1 0 0 300 300 1800 60 N I 21 N "FILTER" +DS 200 350 650 350 75 21 +DS -650 350 -200 350 75 21 +DS 650 -350 200 -350 75 21 +DS -650 -350 -200 -350 75 21 +DS 650 -350 650 350 75 21 +DS -650 350 -650 -350 75 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+3.3VDAC" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE SNESCART_EXT2 +Po 57100 52400 1800 0 4E10EF0E 4B6D9041 ~~ +Li SNESCART_EXT2 +Sc 4B6D9041 +AR /4B6E16F2/4B6E1766 +Op 0 0 0 +.SolderMask 4 +.SolderPaste -4 +T0 -4134 -2953 600 600 1800 120 M V 20 N "J101" +T1 0 -2953 600 600 1800 120 M V 20 N "SNESCART_EXT" +DS -20039 24409 -20039 12244 39 28 +DS -19488 27087 -19488 24409 39 28 +DC 1142 11378 1929 11378 79 21 +DC 1142 11378 1929 11339 79 20 +DS 19921 24409 19921 8976 39 28 +DS 19291 27087 19291 24409 39 28 +DS 19291 24409 19921 24409 39 28 +DS 18307 6890 19291 6890 39 28 +DS 19291 8189 19291 6890 39 28 +DS 18307 8189 19291 8189 39 28 +DS 18307 8976 18307 8189 39 28 +DS 19921 8976 18307 8976 39 28 +DS -20039 4803 -20039 8898 39 28 +DS -18465 12244 -20039 12244 39 28 +DS -18465 11457 -18465 12244 39 28 +DS -19449 11457 -18465 11457 39 28 +DS -19449 8898 -19449 11457 39 28 +DS -20039 8898 -19449 8898 39 28 +DA -17441 -1693 -17441 -1969 -900 39 28 +DA -13071 -1693 -12795 -1693 -900 39 28 +DA -11535 -1693 -11535 -1969 -900 39 28 +DA 11535 -1693 11811 -1693 -900 39 28 +DA 13071 -1693 13071 -1969 -900 39 28 +DA 17441 -1693 17717 -1693 -900 39 28 +DS 8622 29331 19291 29331 40 28 +DS -8524 30709 8622 30709 40 28 +DS -19488 29331 -8524 29331 40 28 +DC 2796 17047 3583 17047 75 21 +DC 2795 17047 3582 17047 75 20 +DS 8622 29331 8622 30709 40 28 +DS -8524 30709 -8524 29331 40 28 +DS -19488 29331 -19488 27756 40 28 +DS -19488 27756 -18504 27756 40 28 +DS -18504 27756 -18504 27087 40 28 +DS -18504 27087 -19488 27087 40 28 +DS -19488 24409 -20039 24409 40 28 +DS -20039 4803 -18465 4803 40 28 +DS -18465 4803 -18465 4016 40 28 +DS -18465 4016 -19449 4016 40 28 +DS -19449 4016 -19449 2205 40 28 +DS -19449 2205 -17717 2205 40 28 +DS -17717 2205 -17717 2165 40 28 +DS 19291 27087 18307 27087 40 28 +DS 18307 27087 18307 27756 40 28 +DS 18307 27756 19291 27756 40 28 +DS 19291 27756 19291 29331 40 28 +DS 17717 -1693 17717 2165 40 28 +DS 17717 2165 17717 2205 40 28 +DS 17717 2205 19921 2205 40 28 +DS 19921 2205 19921 4094 40 28 +DS 19921 4094 19291 4094 40 28 +DS 19291 4094 19291 6102 40 28 +DS 19291 6102 18307 6102 40 28 +DS 18307 6102 18307 6890 40 28 +DS 13071 -1969 17441 -1969 40 28 +DS 11811 -1693 11811 2480 40 28 +DS 11811 2480 12795 2480 40 28 +DS 12795 2480 12795 -1693 40 28 +DS -17717 -1693 -17717 2165 40 28 +DS -13071 -1969 -17441 -1969 40 28 +DS -11811 -1693 -11811 2480 40 28 +DS -11811 2480 -12795 2480 40 28 +DS -12795 2480 -12795 -1693 40 28 +DS -11535 -1969 11535 -1969 40 28 +$PAD +Sh "1" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 62 "/SNES_Slot/SNES_EXT_SYS_CLK" +Po -16732 -197 +$EndPAD +$PAD +Sh "2" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 0 "" +Po -15748 -197 +$EndPAD +$PAD +Sh "3" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 59 "/SNES_Slot/SNES_EXT_PA6" +Po -14764 -197 +$EndPAD +$PAD +Sh "4" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 15 "/SNES_Slot/SNES_EXT_/PARD" +Po -13780 -197 +$EndPAD +$PAD +Sh "5" R 787 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 88 "GND" +Po -10925 -197 +$EndPAD +$PAD +Sh "6" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 23 "/SNES_Slot/SNES_EXT_A11" +Po -9843 -197 +$EndPAD +$PAD +Sh "7" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 22 "/SNES_Slot/SNES_EXT_A10" +Po -8858 -197 +$EndPAD +$PAD +Sh "8" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 43 "/SNES_Slot/SNES_EXT_A9" +Po -7874 -197 +$EndPAD +$PAD +Sh "9" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 42 "/SNES_Slot/SNES_EXT_A8" +Po -6890 -197 +$EndPAD +$PAD +Sh "10" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 41 "/SNES_Slot/SNES_EXT_A7" +Po -5906 -197 +$EndPAD +$PAD +Sh "11" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 40 "/SNES_Slot/SNES_EXT_A6" +Po -4921 -197 +$EndPAD +$PAD +Sh "12" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 39 "/SNES_Slot/SNES_EXT_A5" +Po -3937 -197 +$EndPAD +$PAD +Sh "13" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 38 "/SNES_Slot/SNES_EXT_A4" +Po -2953 -197 +$EndPAD +$PAD +Sh "14" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 37 "/SNES_Slot/SNES_EXT_A3" +Po -1969 -197 +$EndPAD +$PAD +Sh "15" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 32 "/SNES_Slot/SNES_EXT_A2" +Po -984 -197 +$EndPAD +$PAD +Sh "16" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 21 "/SNES_Slot/SNES_EXT_A1" +Po 0 -197 +$EndPAD +$PAD +Sh "17" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 20 "/SNES_Slot/SNES_EXT_A0" +Po 984 -197 +$EndPAD +$PAD +Sh "18" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 14 "/SNES_Slot/SNES_EXT_/IRQ" +Po 1969 -197 +$EndPAD +$PAD +Sh "19" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 45 "/SNES_Slot/SNES_EXT_D0" +Po 2953 -197 +$EndPAD +$PAD +Sh "20" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 46 "/SNES_Slot/SNES_EXT_D1" +Po 3937 -197 +$EndPAD +$PAD +Sh "21" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 47 "/SNES_Slot/SNES_EXT_D2" +Po 4921 -197 +$EndPAD +$PAD +Sh "22" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 48 "/SNES_Slot/SNES_EXT_D3" +Po 5906 -197 +$EndPAD +$PAD +Sh "23" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 17 "/SNES_Slot/SNES_EXT_/RD" +Po 6890 -197 +$EndPAD +$PAD +Sh "24" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 84 "EXT_CIC_DATA1" +Po 7874 -197 +$EndPAD +$PAD +Sh "25" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 73 "CIC_RESET" +Po 8858 -197 +$EndPAD +$PAD +Sh "26" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 274 "SNES_/RESET" +Po 9843 -197 +$EndPAD +$PAD +Sh "27" R 787 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 7 "+5VL" +Po 10925 -197 +$EndPAD +$PAD +Sh "28" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 53 "/SNES_Slot/SNES_EXT_PA0" +Po 13780 -197 +$EndPAD +$PAD +Sh "29" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 55 "/SNES_Slot/SNES_EXT_PA2" +Po 14764 -197 +$EndPAD +$PAD +Sh "30" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 57 "/SNES_Slot/SNES_EXT_PA4" +Po 15748 -197 +$EndPAD +$PAD +Sh "31" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00000001 +Ne 66 "AUDIO_L" +Po 16732 -197 +$EndPAD +$PAD +Sh "32" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 0 "" +Po -16732 -197 +$EndPAD +$PAD +Sh "33" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 61 "/SNES_Slot/SNES_EXT_REFRESH" +Po -15748 -197 +$EndPAD +$PAD +Sh "34" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 60 "/SNES_Slot/SNES_EXT_PA7" +Po -14764 -197 +$EndPAD +$PAD +Sh "35" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 16 "/SNES_Slot/SNES_EXT_/PAWR" +Po -13780 -197 +$EndPAD +$PAD +Sh "36" R 787 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 88 "GND" +Po -10925 -197 +$EndPAD +$PAD +Sh "37" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 24 "/SNES_Slot/SNES_EXT_A12" +Po -9843 -197 +$EndPAD +$PAD +Sh "38" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 25 "/SNES_Slot/SNES_EXT_A13" +Po -8858 -197 +$EndPAD +$PAD +Sh "39" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 26 "/SNES_Slot/SNES_EXT_A14" +Po -7874 -197 +$EndPAD +$PAD +Sh "40" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 27 "/SNES_Slot/SNES_EXT_A15" +Po -6890 -197 +$EndPAD +$PAD +Sh "41" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 28 "/SNES_Slot/SNES_EXT_A16" +Po -5906 -197 +$EndPAD +$PAD +Sh "42" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 29 "/SNES_Slot/SNES_EXT_A17" +Po -4921 -197 +$EndPAD +$PAD +Sh "43" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 30 "/SNES_Slot/SNES_EXT_A18" +Po -3937 -197 +$EndPAD +$PAD +Sh "44" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 31 "/SNES_Slot/SNES_EXT_A19" +Po -2953 -197 +$EndPAD +$PAD +Sh "45" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 33 "/SNES_Slot/SNES_EXT_A20" +Po -1969 -197 +$EndPAD +$PAD +Sh "46" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 34 "/SNES_Slot/SNES_EXT_A21" +Po -984 -197 +$EndPAD +$PAD +Sh "47" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 35 "/SNES_Slot/SNES_EXT_A22" +Po 0 -197 +$EndPAD +$PAD +Sh "48" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 36 "/SNES_Slot/SNES_EXT_A23" +Po 984 -197 +$EndPAD +$PAD +Sh "49" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 18 "/SNES_Slot/SNES_EXT_/ROMSEL" +Po 1969 -197 +$EndPAD +$PAD +Sh "50" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 49 "/SNES_Slot/SNES_EXT_D4" +Po 2953 -197 +$EndPAD +$PAD +Sh "51" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 50 "/SNES_Slot/SNES_EXT_D5" +Po 3937 -197 +$EndPAD +$PAD +Sh "52" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 51 "/SNES_Slot/SNES_EXT_D6" +Po 4921 -197 +$EndPAD +$PAD +Sh "53" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 52 "/SNES_Slot/SNES_EXT_D7" +Po 5906 -197 +$EndPAD +$PAD +Sh "54" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 19 "/SNES_Slot/SNES_EXT_/WR" +Po 6890 -197 +$EndPAD +$PAD +Sh "55" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 83 "EXT_CIC_DATA0" +Po 7874 -197 +$EndPAD +$PAD +Sh "56" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 69 "CIC_CLK" +Po 8858 -197 +$EndPAD +$PAD +Sh "57" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 44 "/SNES_Slot/SNES_EXT_CPU_CLK" +Po 9843 -197 +$EndPAD +$PAD +Sh "58" R 787 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 7 "+5VL" +Po 10925 -197 +$EndPAD +$PAD +Sh "59" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 54 "/SNES_Slot/SNES_EXT_PA1" +Po 13780 -197 +$EndPAD +$PAD +Sh "60" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 56 "/SNES_Slot/SNES_EXT_PA3" +Po 14764 -197 +$EndPAD +$PAD +Sh "61" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 58 "/SNES_Slot/SNES_EXT_PA5" +Po 15748 -197 +$EndPAD +$PAD +Sh "62" R 591 2756 0 0 1800 +Dr 0 0 0 +At CONN N 00008000 +Ne 67 "AUDIO_R" +Po 16732 -197 +$EndPAD +$PAD +Sh "" R 4921 3150 0 0 1800 +Dr 0 0 0 +At CONN N 00C00000 +Ne 0 "" +Po -15256 -394 +$EndPAD +$PAD +Sh "" R 4921 3150 0 0 1800 +Dr 0 0 0 +At CONN N 00C00000 +Ne 0 "" +Po 15256 -394 +$EndPAD +$PAD +Sh "" R 23622 3150 0 0 1800 +Dr 0 0 0 +At CONN N 00C00000 +Ne 0 "" +Po 0 -394 +$EndPAD +$PAD +Sh "" R 2362 1969 0 0 1800 +Dr 0 0 0 +At CONN N 00800000 +Ne 0 "" +Po -10945 3819 +$EndPAD +$PAD +Sh "" R 2283 2362 0 0 1800 +Dr 0 0 0 +At CONN N 00800000 +Ne 0 "" +Po 14331 3780 +$EndPAD +$EndMODULE SNESCART_EXT2 +$MODULE SOT23-5_LARGEPADS +Po 70975 45725 0 15 4EF8DC25 4EF654C2 ~~ +Li SOT23-5_LARGEPADS +Cd SOT23-5 +Sc 4EF654C2 +AR /4B6EC9C3/4EF3AD9A +Op 0 0 0 +At SMD +T0 625 1075 300 320 0 70 N V 21 N "U302" +T1 0 150 300 250 0 50 N I 21 N "MCP1603T-330I/OS" +DS 600 -350 600 350 80 21 +DS 600 350 -600 350 80 21 +DS -600 350 -600 -350 80 21 +DS -600 -350 600 -350 80 21 +$PAD +Sh "1" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/Power_Supply_/_Misc./LX33" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5_LARGEPADS +$MODULE SOT23-5_LARGEPADS +Po 74375 45725 0 15 4EF8DC17 4C05889D ~~ +Li SOT23-5_LARGEPADS +Cd SOT23-5 +Sc 4C05889D +AR /4B6EC9C3/4EF3ADA3 +Op 0 0 0 +At SMD +T0 725 1075 300 320 0 70 N V 21 N "U301" +T1 0 150 300 250 0 50 N I 21 N "MCP1603T-120I/OS" +DS 600 -350 600 350 80 21 +DS 600 350 -600 350 80 21 +DS -600 350 -600 -350 80 21 +DS -600 -350 600 -350 80 21 +$PAD +Sh "1" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "+5V" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/Power_Supply_/_Misc./LX12" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 272 390 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5_LARGEPADS +$MODULE L_4.2X4.2 +Po 74700 43275 900 15 4EF8DCC9 4C05B209 ~~ +Li L_4.2X4.2 +Sc 4C05B209 +AR /4B6EC9C3/4EF3AFF2 +Op 0 0 0 +T0 1450 -25 320 320 1800 70 N V 21 N "L301" +T1 0 0 600 600 900 120 N V 21 N "4.7uH" +DS -1024 -984 1024 -984 79 21 +DS 1024 -984 1024 984 79 21 +DS 1024 984 -1024 984 79 21 +DS -1024 984 -1024 -984 79 21 +$PAD +Sh "1" R 591 1654 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/Power_Supply_/_Misc./LX12" +Po -571 0 +$EndPAD +$PAD +Sh "2" R 591 1654 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 571 0 +$EndPAD +$EndMODULE L_4.2X4.2 +$MODULE L_4.2X4.2 +Po 71300 43275 900 15 4EF8DCD1 4EF7AF5A ~~ +Li L_4.2X4.2 +Sc 4EF7AF5A +AR /4B6EC9C3/4EF3B17C +Op 0 0 0 +T0 1450 -50 320 320 1800 70 N V 21 N "L302" +T1 0 0 600 600 900 120 N V 21 N "4.7uH" +DS -1024 -984 1024 -984 79 21 +DS 1024 -984 1024 984 79 21 +DS 1024 984 -1024 984 79 21 +DS -1024 984 -1024 -984 79 21 +$PAD +Sh "1" R 591 1654 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/Power_Supply_/_Misc./LX33" +Po -571 0 +$EndPAD +$PAD +Sh "2" R 591 1654 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 571 0 +$EndPAD +$EndMODULE L_4.2X4.2 +$MODULE SM0805_FIXEDMASK +Po 44650 48900 1800 15 4EF8E036 4EF8DFA6 ~~ +Li SM0805_FIXEDMASK +Sc 4EF8DFA6 +AR /4B6EC9C3/4EF8DF53 +Op 0 0 0 +At SMD +T0 0 600 320 320 1800 70 N V 21 N "FB342" +T1 0 0 300 300 1800 60 N I 21 N "FILTER" +DS 200 350 650 350 60 21 +DS -650 350 -200 350 60 21 +DS 650 -350 200 -350 60 21 +DS -650 -350 -200 -350 60 21 +DS 650 -350 650 350 60 21 +DS -650 350 -650 -350 60 21 +$PAD +Sh "1" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "GND" +Po -375 0 +$EndPAD +$PAD +Sh "2" R 350 550 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "AGND" +Po 375 0 +$EndPAD +$SHAPE3D +Na "smd/chip_cms.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SM0805_FIXEDMASK +$MODULE +Po 72825 43625 0 0 00000000 4EF8E0DF ~~ +Li +Sc 4EF8E0DF +AR +Op 0 0 0 +T0 0 -2000 600 600 0 120 M I 20 N "G***" +T1 0 2000 600 600 0 120 M I 20 N "LOGO" +DP 0 0 0 0 361 1 20 +Dl -2918 1325 +Dl -2888 1306 +Dl -2888 1199 +Dl -2899 1157 +Dl -2883 1038 +Dl -2848 900 +Dl -2805 799 +Dl -2729 641 +Dl -2681 407 +Dl -2667 76 +Dl -2667 -13 +Dl -2681 -258 +Dl -2721 -422 +Dl -2795 -541 +Dl -2809 -560 +Dl -2826 -618 +Dl -2786 -593 +Dl -2704 -495 +Dl -2654 -423 +Dl -2607 -322 +Dl -2576 -183 +Dl -2549 41 +Dl -2526 175 +Dl -2498 233 +Dl -2469 215 +Dl -2392 128 +Dl -2343 74 +Dl -2195 -26 +Dl -2023 -100 +Dl -1871 -130 +Dl -1783 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-2272 -111 +Dl -2411 -16 +Dl -2436 5 +Dl -2461 -3 +Dl -2466 -115 +Dl -2474 -221 +Dl -2512 -378 +Dl -2531 -414 +Dl -2622 -537 +Dl -2745 -674 +Dl -2861 -787 +Dl -2934 -833 +Dl -2940 -832 +Dl -2967 -772 +Dl -2937 -638 +Dl -2859 -469 +Dl -2810 -379 +Dl -2771 -274 +Dl -2755 -144 +Dl -2753 66 +Dl -2759 249 +Dl -2782 477 +Dl -2817 638 +Dl -2859 699 +Dl -2903 747 +Dl -2950 895 +Dl -2984 1108 +Dl -2991 1187 +Dl -2982 1313 +Dl -2918 1325 +$EndMODULE +$MODULE LED-3MM-FIXED +Po 69575 24250 0 0 4EF9035D 4C0DA805 ~~ +Li LED-3MM-FIXED +Cd LED 3mm - Lead pitch 100mil (2,54mm) +Kw LED led 3mm 3MM 100mil 2,54mm +Sc 4C0DA805 +AR /4B6ED75B/4C0DA78D +Op 0 0 0 +At VIRTUAL +T0 -300 2125 320 320 0 70 M V 20 N "D403" +T1 25 -3575 320 320 900 70 M V 20 N "LED_2mA_1.7V,_red" +DS 669 -669 669 -394 80 20 +DS 669 669 669 394 80 20 +DA 0 0 669 -669 -2700 80 20 +$PAD +Sh "1" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 4 "+3.3V" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 167 "N-000311" +Po 500 0 +$EndPAD +$SHAPE3D +Na "libs/led3_vertical_red.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE LED-3MM-FIXED +$MODULE LED-3MM-FIXED +Po 74025 24250 0 0 4EF9035D 4BF851B6 ~~ +Li LED-3MM-FIXED +Cd LED 3mm - Lead pitch 100mil (2,54mm) +Kw LED led 3mm 3MM 100mil 2,54mm +Sc 4BF851B6 +AR /4B6ED75B/4BF8328D +Op 0 0 0 +At VIRTUAL +T0 -300 2125 320 320 0 70 M V 20 N "D401" +T1 25 -3575 320 320 900 70 M V 20 N "LED_2mA_1.9V,_green" +DS 669 -669 669 -394 80 20 +DS 669 669 669 394 80 20 +DA 0 0 669 -669 -2700 80 20 +$PAD +Sh "1" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 4 "+3.3V" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 171 "N-000316" +Po 500 0 +$EndPAD +$SHAPE3D +Na "libs/led3_vertical_red.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE LED-3MM-FIXED +$MODULE LED-3MM-FIXED +Po 71800 24250 0 0 4EF9035D 4BF851B4 ~~ +Li LED-3MM-FIXED +Cd LED 3mm - Lead pitch 100mil (2,54mm) +Kw LED led 3mm 3MM 100mil 2,54mm +Sc 4BF851B4 +AR /4B6ED75B/4BF8324A +Op 0 0 0 +At VIRTUAL +T0 -300 2125 320 320 0 70 M V 20 N "D402" +T1 25 -3575 320 320 900 70 M V 20 N "LED_2mA_1.8V,_yellow" +DS 669 -669 669 -394 80 20 +DS 669 669 669 394 80 20 +DA 0 0 669 -669 -2700 80 20 +$PAD +Sh "1" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 4 "+3.3V" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00D0FFFF +Ne 164 "N-000305" +Po 500 0 +$EndPAD +$SHAPE3D +Na "libs/led3_vertical_red.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE LED-3MM-FIXED +$MODULE HRS-DM1AA +Po 59000 27050 0 0 4EF91222 4BFDB494 ~~ +Li HRS-DM1AA +Sc 4BFDB494 +AR /4B6ED75B/4BAA6A9C +Op 0 0 0 +T0 -4975 6425 320 320 0 70 M V 20 N "J411" +T1 0 0 300 300 0 60 M V 20 N "Hirose_DM1AA" +DS 4134 5984 5512 5984 120 20 +DS 5512 -6024 -5512 -6024 120 20 +DS -5512 5984 -4685 5984 120 20 +DS -5512 -4685 -5512 -6024 120 20 +DS 5511 -6025 5511 -4686 120 20 +DS 5511 2637 5511 -3584 120 20 +DS 5511 5983 5511 3779 120 20 +DS 4133 5511 3779 5511 120 20 +DS -4686 5511 -4529 5511 120 20 +DS -5512 -2521 -5512 -2796 120 20 +DS -5512 983 -5512 -1773 120 20 +DS -5512 2637 -5512 1731 120 20 +DS -5512 5983 -5512 3779 120 20 +DS -4686 5983 -4686 5511 120 20 +DS 4133 5511 4133 5983 120 20 +$PAD +Sh "~" C 510 510 0 0 0 +Dr 512 0 0 +At STD N 0000FFFF +Ne 0 "" +Po -4686 4999 +$EndPAD +$PAD +Sh "~" C 510 510 0 0 0 +Dr 512 0 0 +At STD N 0000FFFF +Ne 0 "" +Po 4133 4999 +$EndPAD +$PAD +Sh "1" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 270 "SD_DAT3" +Po 2391 5865 +$EndPAD +$PAD +Sh "2" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 266 "SD_CMD" +Po 1407 5865 +$EndPAD +$PAD +Sh "3" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 422 5865 +$EndPAD +$PAD +Sh "4" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -562 5865 +$EndPAD +$PAD +Sh "5" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 265 "SD_CLK" +Po -1546 5865 +$EndPAD +$PAD +Sh "6" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -2530 5865 +$EndPAD +$PAD +Sh "7" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 267 "SD_DAT0" +Po -3485 5865 +$EndPAD +$PAD +Sh "8" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 268 "SD_DAT1" +Po -4155 5865 +$EndPAD +$PAD +Sh "9" R 433 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 269 "SD_DAT2" +Po 3375 5865 +$EndPAD +$PAD +Sh "GND1" R 787 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 5708 3208 +$EndPAD +$PAD +Sh "GND1" R 787 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po 5708 -4135 +$EndPAD +$PAD +Sh "GND1" R 787 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -5710 3208 +$EndPAD +$PAD +Sh "GND1" R 787 787 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -5710 -4135 +$EndPAD +$PAD +Sh "DT" R 787 394 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 172 "N-000318" +Po -5552 1377 +$EndPAD +$PAD +Sh "WP" R 787 394 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 162 "N-000295" +Po -5552 -2147 +$EndPAD +$PAD +Sh "GND2" R 787 394 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 88 "GND" +Po -5552 -3170 +$EndPAD +$EndMODULE HRS-DM1AA +$COTATION +Ge 0 24 0 +Va 32677 +Te "83.000 mm" +Po 81111 38031 600 800 120 2701 1 +Sb 0 80471 21693 80471 54370 120 +Sd 0 65630 54370 81751 54370 120 +Sg 0 65630 21693 81751 21693 120 +S1 0 80471 54370 80241 53927 120 +S2 0 80471 54370 80701 53927 120 +S3 0 80471 21693 80241 22136 120 +S4 0 80471 21693 80701 22136 120 +$endCOTATION +$COTATION +Ge 0 24 0 +Va 40000 +Te "101.600 mm" +Po 57165 59419 600 800 120 0 1 +Sb 0 37165 58779 77165 58779 120 +Sd 0 77165 34606 77165 60059 120 +Sg 0 37165 34606 37165 60059 120 +S1 0 77165 58779 76722 59009 120 +S2 0 77165 58779 76722 58549 120 +S3 0 37165 58779 37608 59009 120 +S4 0 37165 58779 37608 58549 120 +$endCOTATION +$TEXTPCB +Te "USE_BATT" +Po 46575 27525 320 320 80 0 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "GPIO" +Po 42775 26225 320 320 70 0 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "6" +Po 47559 24409 300 300 60 900 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "5" +Po 47559 26575 300 300 60 900 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "2" +Po 45472 24409 300 300 60 900 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "1" +Po 45472 26575 300 300 60 900 +De 21 1 0 Normal C +$EndTEXTPCB +$TEXTPCB +Te "P404" +Po 46496 23780 300 300 60 0 +De 21 1 0 Normal C +$EndTEXTPCB +$DRAWSEGMENT +Po 0 45728 25452 47263 25452 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 46751 26712 46751 24035 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 46239 26712 46239 24035 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 47263 26712 45728 26712 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 47263 24035 47263 26712 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 45728 24035 47263 24035 60 +De 21 0 900 0 0 +$EndDRAWSEGMENT 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0 +37425 43249 0 0 +37425 41225 0 0 +42870 41225 0 0 +42870 44175 0 0 +42886 44253 0 0 +42930 44320 0 0 +43479 44869 0 0 +43480 44870 0 0 +43719 45109 0 0 +43475 45354 0 0 +43475 47371 0 0 +43850 47746 0 0 +43850 47835 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4E12CFA5 3 "+2.5V" +ZLayer 15 +ZAux 11 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 66125 38925 0 +ZCorner 66125 38050 0 +ZCorner 64450 36375 0 +ZCorner 64450 35900 0 +ZCorner 64200 35650 0 +ZCorner 63300 35650 0 +ZCorner 63050 35900 0 +ZCorner 63050 36800 0 +ZCorner 63300 37050 0 +ZCorner 63875 37050 0 +ZCorner 65750 38925 1 +$POLYSCORNERS +66075 38875 0 0 +65771 38875 0 0 +63896 37000 0 0 +63321 37000 0 0 +63100 36779 0 0 +63100 35921 0 0 +63321 35700 0 0 +64179 35700 0 0 +64400 35921 0 0 +64400 36396 0 0 +66075 38071 0 0 +66075 38875 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4E130811 7 "+5VL" +ZLayer 0 +ZAux 10 E +ZClearance 75 I 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0 +46750 50729 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4EF7AF74 12 "/Power_Supply_/_Misc./LX33" +ZLayer 15 +ZAux 7 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 70775 45450 0 +ZCorner 70775 45025 0 +ZCorner 71525 44275 0 +ZCorner 72125 44275 0 +ZCorner 72125 43575 0 +ZCorner 70425 43575 0 +ZCorner 70425 45450 1 +$POLYSCORNERS +72075 44225 0 0 +71504 44225 0 0 +70725 45004 0 0 +70725 45400 0 0 +70475 45400 0 0 +70475 43625 0 0 +72075 43625 0 0 +72075 44225 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4EF7B0E4 11 "/Power_Supply_/_Misc./LX12" +ZLayer 15 +ZAux 7 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 74175 45450 0 +ZCorner 74175 45025 0 +ZCorner 74925 44275 0 +ZCorner 75525 44275 0 +ZCorner 75525 43550 0 +ZCorner 73825 43550 0 +ZCorner 73825 45450 1 +$POLYSCORNERS +75475 44225 0 0 +74904 44225 0 0 +74125 45004 0 0 +74125 45400 0 0 +73875 45400 0 0 +73875 43600 0 0 +75475 43600 0 0 +75475 44225 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4EF8B056 4 "+3.3V" +ZLayer 15 +ZAux 11 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 70050 44075 0 +ZCorner 70050 43400 0 +ZCorner 70450 43000 0 +ZCorner 72225 43000 0 +ZCorner 72225 42150 0 +ZCorner 70250 42150 0 +ZCorner 70250 41175 0 +ZCorner 68350 41175 0 +ZCorner 68350 43850 0 +ZCorner 69350 43850 0 +ZCorner 69350 44075 1 +$POLYSCORNERS +72175 42950 0 0 +70429 42950 0 0 +70000 43379 0 0 +70000 44025 0 0 +69400 44025 0 0 +69400 43800 0 0 +68400 43800 0 0 +68400 41225 0 0 +70200 41225 0 0 +70200 41437 0 0 +70139 41530 0 0 +70105 41700 0 0 +70139 41870 0 0 +70200 41962 0 0 +70200 42200 0 0 +72175 42200 0 0 +72175 42950 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4EF8B325 1 "+1.2V" +ZLayer 15 +ZAux 7 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 73425 44075 0 +ZCorner 73425 43400 0 +ZCorner 73825 43000 0 +ZCorner 75625 43000 0 +ZCorner 75625 42150 0 +ZCorner 72600 42150 0 +ZCorner 72600 44075 1 +$POLYSCORNERS +75575 42950 0 0 +73804 42950 0 0 +73375 43379 0 0 +73375 44025 0 0 +72650 44025 0 0 +72650 42200 0 0 +75575 42200 0 0 +75575 42950 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$CZONE_OUTLINE +ZInfo 4EF8BCCF 6 "+5V" +ZLayer 15 +ZAux 8 E +ZClearance 75 I +ZMinThickness 100 +ZOptions 0 16 F 118 118 +ZSmoothing 0 0 +ZCorner 74150 46900 0 +ZCorner 74150 45975 0 +ZCorner 71200 45975 0 +ZCorner 71200 46475 0 +ZCorner 70750 46475 0 +ZCorner 70750 45975 0 +ZCorner 69375 45975 0 +ZCorner 69375 46900 1 +$POLYSCORNERS +74100 46850 0 0 +69425 46850 0 0 +69425 46025 0 0 +69650 46025 0 0 +69700 46035 0 0 +70690 46035 0 0 +70690 46225 0 0 +70700 46274 0 0 +70700 46525 0 0 +70767 46525 0 0 +70768 46526 0 0 +70814 46545 0 0 +70864 46545 0 0 +71136 46545 0 0 +71182 46526 0 0 +71183 46525 0 0 +71250 46525 0 0 +71250 46274 0 0 +71260 46225 0 0 +71260 46025 0 0 +72946 46025 0 0 +72966 46038 0 0 +73075 46060 0 0 +74090 46060 0 0 +74090 46225 0 0 +74100 46274 0 0 +74100 46850 1 0 +$endPOLYSCORNERS +$endCZONE_OUTLINE +$EndBOARD diff --git a/pcb/kicad/RevE2/sd2snes.cmp b/pcb/kicad/RevE2/sd2snes.cmp new file mode 100644 index 0000000..51676c5 --- /dev/null +++ b/pcb/kicad/RevE2/sd2snes.cmp @@ -0,0 +1,1067 @@ +Cmp-Mod V01 Created by CvPCB (2011-07-02 BZR 2664)-stable date = Mon 26 Dec 2011 09:56:51 PM CET + +BeginCmp +TimeStamp = /4B6EC9C3/4BAF2EAF; +Reference = BT351; +ValeurCmp = Keystone_1059_/_KZH20PCB; +IdModule = BT_KEYSTONE_1059_20MM; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42D5; +Reference = C101; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42D8; +Reference = C102; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42DA; +Reference = C103; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB1190; +Reference = C104; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB1192; +Reference = C105; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB1194; +Reference = C106; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB119A; +Reference = C111; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB1199; +Reference = C112; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BFB1197; +Reference = C113; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42DF; +Reference = C114; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42E0; +Reference = C115; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAD42E2; +Reference = C116; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D113C55; +Reference = C121; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D113C9C; +Reference = C122; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D113CAA; +Reference = C123; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D113CAC; +Reference = C124; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D113CAF; +Reference = C125; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D11524E; +Reference = C126; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D11524F; +Reference = C127; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D115250; +Reference = C128; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE47; +Reference = C201; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE62; +Reference = C202; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE64; +Reference = C203; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE65; +Reference = C204; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE67; +Reference = C205; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE6A; +Reference = C206; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE6B; +Reference = C207; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE6D; +Reference = C208; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F4312; +Reference = C209; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE74; +Reference = C210; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE78; +Reference = C211; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE7A; +Reference = C212; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE7B; +Reference = C213; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D252B5C; +Reference = C214; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F4480; +Reference = C215; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE7D; +Reference = C221; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BADCE85; +Reference = C222; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BF5A43F; +Reference = C223; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4BF5A441; +Reference = C224; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F4344; +Reference = C231; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F4979; +Reference = C232; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F497B; +Reference = C233; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4D2F566A; +Reference = C234; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4C05ACA2; +Reference = C301; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4C05AC9D; +Reference = C302; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3B15E; +Reference = C303; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3B181; +Reference = C304; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BABCB5C; +Reference = C311; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BABCB68; +Reference = C312; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BABCA9C; +Reference = C321; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BABCAD2; +Reference = C322; +ValeurCmp = 4.7u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BADC719; +Reference = C331; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4CA655D4; +Reference = C332; +ValeurCmp = 100p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4CA65597; +Reference = C333; +ValeurCmp = 100p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BADC720; +Reference = C341; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4C17DE31; +Reference = C342; +ValeurCmp = 1u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98AA2; +Reference = C343; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98AA5; +Reference = C344; +ValeurCmp = 10u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98AAB; +Reference = C345; +ValeurCmp = 10u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EBE; +Reference = C346; +ValeurCmp = 3.3u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98E9E; +Reference = C347; +ValeurCmp = 10n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EBB; +Reference = C348; +ValeurCmp = 3.3u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EBF; +Reference = C349; +ValeurCmp = 10n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF6BFE1; +Reference = C401; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF6BFE2; +Reference = C402; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF6BFE5; +Reference = C403; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF6BFE6; +Reference = C404; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C063C47; +Reference = C405; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BEECBC1; +Reference = C406; +ValeurCmp = 33p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BEECBCA; +Reference = C407; +ValeurCmp = 33p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BEECBCD; +Reference = C408; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BEECBD1; +Reference = C409; +ValeurCmp = 10p; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF6BFBB; +Reference = C411; +ValeurCmp = 10u; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C1286D5; +Reference = C412; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BAD3D47; +Reference = C501; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BAD3D55; +Reference = C502; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BAD3D53; +Reference = C511; +ValeurCmp = 100n; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF8328D; +Reference = D401; +ValeurCmp = LED_2mA_1.9V,_green; +IdModule = LED-3MM-FIXED; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF8324A; +Reference = D402; +ValeurCmp = LED_2mA_1.8V,_yellow; +IdModule = LED-3MM-FIXED; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C0DA78D; +Reference = D403; +ValeurCmp = LED_2mA_1.7V,_red; +IdModule = LED-3MM-FIXED; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BF19DCA; +Reference = D511; +ValeurCmp = BAT54C; +IdModule = SOT23EBC; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4DB2EA56; +Reference = FB341; +ValeurCmp = FILTER; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF8DF53; +Reference = FB342; +ValeurCmp = FILTER; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4B6E1766; +Reference = J101; +ValeurCmp = SNESCART_EXT; +IdModule = SNESCART_EXT2; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BAA6A9C; +Reference = J411; +ValeurCmp = Hirose_DM1AA; +IdModule = HRS-DM1AA; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF00175; +Reference = J421; +ValeurCmp = Molex_54819; +IdModule = USB-MINIB-THT; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C86265B; +Reference = JP401; +ValeurCmp = JUMPER; +IdModule = GS2; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4E2C1796; +Reference = JP402; +ValeurCmp = JUMPER; +IdModule = GS2; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3AFF2; +Reference = L301; +ValeurCmp = 4.7uH; +IdModule = L_4.2X4.2; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3B17C; +Reference = L302; +ValeurCmp = 4.7uH; +IdModule = L_4.2X4.2; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4C7FF87E; +Reference = P113; +ValeurCmp = CONN_1; +IdModule = PAD_1x1mm; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C0943CA; +Reference = P401; +ValeurCmp = CONN_7X2; +IdModule = pin_array_7x2; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BEFBC73; +Reference = P402; +ValeurCmp = CONN_2; +IdModule = PIN_ARRAY_2X1; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C4A0B6F; +Reference = P403; +ValeurCmp = CONN_2; +IdModule = PIN_ARRAY_2X1; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4DF9F6C8; +Reference = P404; +ValeurCmp = CONN_3X2; +IdModule = pin_array_3x2; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4C7EAD01; +Reference = Q101; +ValeurCmp = 2N2222A; +IdModule = SOT23EBC; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4D4BCF29; +Reference = Q301; +ValeurCmp = IRLML6402PbF; +IdModule = SOT23GDS; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BF2FD9F; +Reference = Q511; +ValeurCmp = 2N2222A; +IdModule = SOT23EBC; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4BAE51CA; +Reference = R101; +ValeurCmp = 270; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4C7EAEBF; +Reference = R102; +ValeurCmp = 100k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4C7EAF13; +Reference = R103; +ValeurCmp = 4k7; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4D4BE786; +Reference = R301; +ValeurCmp = 20k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4C42D578; +Reference = R331; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4CA6556E; +Reference = R332; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4CA65577; +Reference = R333; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EC6; +Reference = R341; +ValeurCmp = 470; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EC4; +Reference = R342; +ValeurCmp = 10k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EB4; +Reference = R343; +ValeurCmp = 470; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BF98EB9; +Reference = R344; +ValeurCmp = 10k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF847A7; +Reference = R401; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF847B1; +Reference = R402; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C0DA785; +Reference = R403; +ValeurCmp = 680; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C063C2F; +Reference = R404; +ValeurCmp = 10k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF850D1; +Reference = R405; +ValeurCmp = 100; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BF850A9; +Reference = R406; +ValeurCmp = 100; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C814430; +Reference = R407; +ValeurCmp = 10k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C5608C6; +Reference = R421; +ValeurCmp = 33; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C5608C9; +Reference = R422; +ValeurCmp = 33; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4C01596A; +Reference = R423; +ValeurCmp = 1.5k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BF2FDAF; +Reference = R511; +ValeurCmp = 20k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BF2FDA9; +Reference = R512; +ValeurCmp = 4k7; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4BF2FDAC; +Reference = R513; +ValeurCmp = 100k; +IdModule = SM0805_FIXEDMASK; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D9630F0; +Reference = RA101; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D9630F4; +Reference = RA102; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D95CDCD; +Reference = RA103; +ValeurCmp = FB; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D95CDD4; +Reference = RA104; +ValeurCmp = FB; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D96310E; +Reference = RA105; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D963115; +Reference = RA106; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D963117; +Reference = RA107; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D963119; +Reference = RA108; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D963103; +Reference = RA109; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D963107; +Reference = RA110; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D96310A; +Reference = RA111; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D96310C; +Reference = RA112; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D97B45C; +Reference = RA113; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4D97B45F; +Reference = RA114; +ValeurCmp = 100; +IdModule = R_PACK_0804; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4B6E1740; +Reference = U101; +ValeurCmp = 74ALVC164245DGG; +IdModule = TSSOP48; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4B6E1744; +Reference = U102; +ValeurCmp = 74ALVC164245DGG; +IdModule = TSSOP48; +EndCmp + +BeginCmp +TimeStamp = /4B6E16F2/4B6E1748; +Reference = U103; +ValeurCmp = 74ALVC164245DGG; +IdModule = TSSOP48; +EndCmp + +BeginCmp +TimeStamp = /4B6E18FC/4B6E1931; +Reference = U201; +ValeurCmp = XC3S400-PQ208; +IdModule = PQFP208; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3ADA3; +Reference = U301; +ValeurCmp = MCP1603T-120I/OS; +IdModule = SOT23-5_LARGEPADS; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4EF3AD9A; +Reference = U302; +ValeurCmp = MCP1603T-330I/OS; +IdModule = SOT23-5_LARGEPADS; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4B6ED144; +Reference = U311; +ValeurCmp = MCP1824-1802E/OT; +IdModule = SOT23-5_LARGEPADS; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4B6ED134; +Reference = U321; +ValeurCmp = MCP1824-2502E/OT; +IdModule = SOT23-5_LARGEPADS; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BAA92DB; +Reference = U331; +ValeurCmp = PIC12F629-I/P; +IdModule = DIP-8__300; +EndCmp + +BeginCmp +TimeStamp = /4B6EC9C3/4BAA9331; +Reference = U341; +ValeurCmp = CS4344; +IdModule = TSSOP10; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4B6F321A; +Reference = U401; +ValeurCmp = LPC1754; +IdModule = LQFP80-.5; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4B868602; +Reference = U501; +ValeurCmp = MT45W8MW16; +IdModule = VFBGA54; +EndCmp + +BeginCmp +TimeStamp = /4BAA6ABD/4D49598F; +Reference = U511; +ValeurCmp = CY62148EV30-ZSXI; +IdModule = TSOPII-32; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BC243C8; +Reference = X401; +ValeurCmp = 12MHz; +IdModule = HC49US; +EndCmp + +BeginCmp +TimeStamp = /4B6ED75B/4BC243CB; +Reference = X402; +ValeurCmp = 32.768kHz; +IdModule = XTAL_SMD_05019; +EndCmp + +EndListe diff --git a/pcb/kicad/RevE2/sd2snes.net b/pcb/kicad/RevE2/sd2snes.net new file mode 100644 index 0000000..6a67162 --- /dev/null +++ b/pcb/kicad/RevE2/sd2snes.net @@ -0,0 +1,3218 @@ +# EESchema Netlist Version 1.1 created Mon 26 Dec 2011 09:57:01 PM CET +( + ( /4B6E16F2/4D97B45F $noname RA114 100 {Lib=R_PACK4} + ( 1 N-000108 ) + ( 2 N-000145 ) + ( 3 N-000087 ) + ( 4 N-000083 ) + ( 5 SNES_D4 ) + ( 6 SNES_D0 ) + ( 7 SNES_D5 ) + ( 8 SNES_D1 ) + ) + ( /4B6E16F2/4D97B45C $noname RA113 100 {Lib=R_PACK4} + ( 1 N-000084 ) + ( 2 N-000082 ) + ( 3 N-000076 ) + ( 4 N-000073 ) + ( 5 SNES_D6 ) + ( 6 SNES_D2 ) + ( 7 SNES_D7 ) + ( 8 SNES_D3 ) + ) + ( /4B6E16F2/4D963119 $noname RA108 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A4 ) + ( 2 /SNES_Slot/SNES_EXT_A18 ) + ( 3 /SNES_Slot/SNES_EXT_A5 ) + ( 4 /SNES_Slot/SNES_EXT_A17 ) + ( 5 N-000037 ) + ( 6 N-000042 ) + ( 7 N-000100 ) + ( 8 N-000095 ) + ) + ( /4B6E16F2/4D963117 $noname RA107 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A2 ) + ( 2 /SNES_Slot/SNES_EXT_A20 ) + ( 3 /SNES_Slot/SNES_EXT_A3 ) + ( 4 /SNES_Slot/SNES_EXT_A19 ) + ( 5 N-000056 ) + ( 6 N-000053 ) + ( 7 N-000049 ) + ( 8 N-000047 ) + ) + ( /4B6E16F2/4D963115 $noname RA106 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A0 ) + ( 2 /SNES_Slot/SNES_EXT_A22 ) + ( 3 /SNES_Slot/SNES_EXT_A1 ) + ( 4 /SNES_Slot/SNES_EXT_A21 ) + ( 5 N-000045 ) + ( 6 N-000041 ) + ( 7 N-000040 ) + ( 8 N-000039 ) + ) + ( /4B6E16F2/4D96310E $noname RA105 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_/IRQ ) + ( 2 /SNES_Slot/SNES_EXT_/RD ) + ( 3 /SNES_Slot/SNES_EXT_/ROMSEL ) + ( 4 /SNES_Slot/SNES_EXT_A23 ) + ( 5 N-000038 ) + ( 6 N-000143 ) + ( 7 N-000012 ) + ( 8 N-000147 ) + ) + ( /4B6E16F2/4D96310C $noname RA112 100 {Lib=R_PACK4} + ( 1 N-000151 ) + ( 2 N-000152 ) + ( 3 N-000153 ) + ( 4 N-000154 ) + ( 5 /SNES_Slot/SNES_EXT_REFRESH ) + ( 6 /SNES_Slot/SNES_EXT_PA7 ) + ( 7 /SNES_Slot/SNES_EXT_PA6 ) + ( 8 /SNES_Slot/SNES_EXT_/PAWR ) + ) + ( /4B6E16F2/4D96310A $noname RA111 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A10 ) + ( 2 /SNES_Slot/SNES_EXT_A12 ) + ( 3 /SNES_Slot/SNES_EXT_A11 ) + ( 4 /SNES_Slot/SNES_EXT_/PARD ) + ( 5 N-000156 ) + ( 6 N-000157 ) + ( 7 N-000158 ) + ( 8 N-000146 ) + ) + ( /4B6E16F2/4D963107 $noname RA110 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A8 ) + ( 2 /SNES_Slot/SNES_EXT_A14 ) + ( 3 /SNES_Slot/SNES_EXT_A9 ) + ( 4 /SNES_Slot/SNES_EXT_A13 ) + ( 5 N-000159 ) + ( 6 N-000160 ) + ( 7 N-000161 ) + ( 8 N-000137 ) + ) + ( /4B6E16F2/4D963103 $noname RA109 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_A6 ) + ( 2 /SNES_Slot/SNES_EXT_A16 ) + ( 3 /SNES_Slot/SNES_EXT_A7 ) + ( 4 /SNES_Slot/SNES_EXT_A15 ) + ( 5 N-000127 ) + ( 6 N-000120 ) + ( 7 N-000125 ) + ( 8 N-000050 ) + ) + ( /4B6E16F2/4D9630F4 $noname RA102 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_PA0 ) + ( 2 /SNES_Slot/SNES_EXT_PA1 ) + ( 3 /SNES_Slot/SNES_EXT_/WR ) + ( 4 /SNES_Slot/SNES_EXT_CPU_CLK ) + ( 5 N-000144 ) + ( 6 N-000013 ) + ( 7 N-000106 ) + ( 8 N-000105 ) + ) + ( /4B6E16F2/4D9630F0 $noname RA101 100 {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_PA4 ) + ( 2 /SNES_Slot/SNES_EXT_PA5 ) + ( 3 /SNES_Slot/SNES_EXT_PA2 ) + ( 4 /SNES_Slot/SNES_EXT_PA3 ) + ( 5 N-000104 ) + ( 6 N-000103 ) + ( 7 N-000092 ) + ( 8 N-000102 ) + ) + ( /4B6E16F2/4D95CDD4 $noname RA104 FB {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_D1 ) + ( 2 /SNES_Slot/SNES_EXT_D5 ) + ( 3 /SNES_Slot/SNES_EXT_D0 ) + ( 4 /SNES_Slot/SNES_EXT_D4 ) + ( 5 N-000075 ) + ( 6 N-000072 ) + ( 7 N-000107 ) + ( 8 N-000091 ) + ) + ( /4B6E16F2/4D95CDCD $noname RA103 FB {Lib=R_PACK4} + ( 1 /SNES_Slot/SNES_EXT_D3 ) + ( 2 /SNES_Slot/SNES_EXT_D7 ) + ( 3 /SNES_Slot/SNES_EXT_D2 ) + ( 4 /SNES_Slot/SNES_EXT_D6 ) + ( 5 N-000086 ) + ( 6 N-000071 ) + ( 7 N-000078 ) + ( 8 N-000074 ) + ) + ( /4B6E16F2/4D115250 SM0805_FIXEDMASK C128 10p {Lib=C} + ( 1 N-000156 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D11524F SM0805_FIXEDMASK C127 10p {Lib=C} + ( 1 N-000151 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D11524E SM0805_FIXEDMASK C126 10p {Lib=C} + ( 1 /SNES_Slot/SNES_EXT_REFRESH ) + ( 2 GND ) + ) + ( /4B6E16F2/4D113CAF SM0805_FIXEDMASK C125 10p {Lib=C} + ( 1 N-000012 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D113CAC SM0805_FIXEDMASK C124 10p {Lib=C} + ( 1 N-000013 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D113CAA SM0805_FIXEDMASK C123 10p {Lib=C} + ( 1 N-000147 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D113C9C SM0805_FIXEDMASK C122 10p {Lib=C} + ( 1 N-000143 ) + ( 2 GND ) + ) + ( /4B6E16F2/4D113C55 SM0805_FIXEDMASK C121 10p {Lib=C} + ( 1 N-000144 ) + ( 2 GND ) + ) + ( /4B6E16F2/4C7EAF13 $noname R103 4k7 {Lib=R} + ( 1 SNES_IRQ_EN ) + ( 2 N-000036 ) + ) + ( /4B6E16F2/4C7EAEBF $noname R102 100k {Lib=R} + ( 1 N-000036 ) + ( 2 GND ) + ) + ( /4B6E16F2/4C7EAD01 $noname Q101 2N2222A {Lib=NPN} + ( 1 GND ) + ( 2 N-000036 ) + ( 3 N-000147 ) + ) + ( /4B6E16F2/4BFB119A SM0805_FIXEDMASK C111 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BFB1199 SM0805_FIXEDMASK C112 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BFB1197 SM0805_FIXEDMASK C113 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BFB1194 SM0805_FIXEDMASK C106 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BFB1192 SM0805_FIXEDMASK C105 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BFB1190 SM0805_FIXEDMASK C104 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAE51CA SM0805_FIXEDMASK R101 270 {Lib=R} + ( 1 GND ) + ( 2 /SNES_Slot/SNES_EXT_SYS_CLK ) + ) + ( /4B6E16F2/4BAD42E2 SM0805_FIXEDMASK C116 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAD42E0 SM0805_FIXEDMASK C115 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAD42DF SM0805_FIXEDMASK C114 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAD42DA SM0805_FIXEDMASK C103 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAD42D8 SM0805_FIXEDMASK C102 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4BAD42D5 SM0805_FIXEDMASK C101 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E16F2/4B6E1766 SNESCART_EXT J101 SNESCART_EXT {Lib=SNESCART_EXT} + ( 1 /SNES_Slot/SNES_EXT_SYS_CLK ) + ( 2 ? ) + ( 3 /SNES_Slot/SNES_EXT_PA6 ) + ( 4 /SNES_Slot/SNES_EXT_/PARD ) + ( 5 GND ) + ( 6 /SNES_Slot/SNES_EXT_A11 ) + ( 7 /SNES_Slot/SNES_EXT_A10 ) + ( 8 /SNES_Slot/SNES_EXT_A9 ) + ( 9 /SNES_Slot/SNES_EXT_A8 ) + ( 10 /SNES_Slot/SNES_EXT_A7 ) + ( 11 /SNES_Slot/SNES_EXT_A6 ) + ( 12 /SNES_Slot/SNES_EXT_A5 ) + ( 13 /SNES_Slot/SNES_EXT_A4 ) + ( 14 /SNES_Slot/SNES_EXT_A3 ) + ( 15 /SNES_Slot/SNES_EXT_A2 ) + ( 16 /SNES_Slot/SNES_EXT_A1 ) + ( 17 /SNES_Slot/SNES_EXT_A0 ) + ( 18 /SNES_Slot/SNES_EXT_/IRQ ) + ( 19 /SNES_Slot/SNES_EXT_D0 ) + ( 20 /SNES_Slot/SNES_EXT_D1 ) + ( 21 /SNES_Slot/SNES_EXT_D2 ) + ( 22 /SNES_Slot/SNES_EXT_D3 ) + ( 23 /SNES_Slot/SNES_EXT_/RD ) + ( 24 EXT_CIC_DATA1 ) + ( 25 CIC_RESET ) + ( 26 SNES_/RESET ) + ( 27 +5VL ) + ( 28 /SNES_Slot/SNES_EXT_PA0 ) + ( 29 /SNES_Slot/SNES_EXT_PA2 ) + ( 30 /SNES_Slot/SNES_EXT_PA4 ) + ( 31 AUDIO_L ) + ( 32 ? ) + ( 33 /SNES_Slot/SNES_EXT_REFRESH ) + ( 34 /SNES_Slot/SNES_EXT_PA7 ) + ( 35 /SNES_Slot/SNES_EXT_/PAWR ) + ( 36 GND ) + ( 37 /SNES_Slot/SNES_EXT_A12 ) + ( 38 /SNES_Slot/SNES_EXT_A13 ) + ( 39 /SNES_Slot/SNES_EXT_A14 ) + ( 40 /SNES_Slot/SNES_EXT_A15 ) + ( 41 /SNES_Slot/SNES_EXT_A16 ) + ( 42 /SNES_Slot/SNES_EXT_A17 ) + ( 43 /SNES_Slot/SNES_EXT_A18 ) + ( 44 /SNES_Slot/SNES_EXT_A19 ) + ( 45 /SNES_Slot/SNES_EXT_A20 ) + ( 46 /SNES_Slot/SNES_EXT_A21 ) + ( 47 /SNES_Slot/SNES_EXT_A22 ) + ( 48 /SNES_Slot/SNES_EXT_A23 ) + ( 49 /SNES_Slot/SNES_EXT_/ROMSEL ) + ( 50 /SNES_Slot/SNES_EXT_D4 ) + ( 51 /SNES_Slot/SNES_EXT_D5 ) + ( 52 /SNES_Slot/SNES_EXT_D6 ) + ( 53 /SNES_Slot/SNES_EXT_D7 ) + ( 54 /SNES_Slot/SNES_EXT_/WR ) + ( 55 EXT_CIC_DATA0 ) + ( 56 CIC_CLK ) + ( 57 /SNES_Slot/SNES_EXT_CPU_CLK ) + ( 58 +5VL ) + ( 59 /SNES_Slot/SNES_EXT_PA1 ) + ( 60 /SNES_Slot/SNES_EXT_PA3 ) + ( 61 /SNES_Slot/SNES_EXT_PA5 ) + ( 62 AUDIO_R ) + ) + ( /4B6E16F2/4B6E1748 TSSOP48 U103 74ALVC164245DGG {Lib=74ALVC164245} + ( 1 GND ) + ( 2 N-000125 ) + ( 3 N-000120 ) + ( 4 GND ) + ( 5 N-000127 ) + ( 6 N-000137 ) + ( 7 +5V ) + ( 8 N-000161 ) + ( 9 N-000160 ) + ( 10 GND ) + ( 11 N-000159 ) + ( 12 N-000146 ) + ( 13 N-000158 ) + ( 14 N-000157 ) + ( 15 GND ) + ( 16 N-000156 ) + ( 17 N-000151 ) + ( 18 +5V ) + ( 19 N-000152 ) + ( 20 N-000153 ) + ( 21 GND ) + ( 22 N-000154 ) + ( 23 /SNES_Slot/SNES_EXT_SYS_CLK ) + ( 24 GND ) + ( 25 GND ) + ( 26 SNES_SYS_CLK ) + ( 27 SNES_REFRESH ) + ( 28 GND ) + ( 29 SNES_PA7 ) + ( 30 SNES_PA6 ) + ( 31 +3.3V ) + ( 32 SNES_/PAWR ) + ( 33 SNES_/PARD ) + ( 34 GND ) + ( 35 SNES_A11 ) + ( 36 SNES_A12 ) + ( 37 SNES_A10 ) + ( 38 SNES_A13 ) + ( 39 GND ) + ( 40 SNES_A9 ) + ( 41 SNES_A14 ) + ( 42 +3.3V ) + ( 43 SNES_A8 ) + ( 44 SNES_A15 ) + ( 45 GND ) + ( 46 SNES_A7 ) + ( 47 SNES_A16 ) + ( 48 GND ) + ) + ( /4B6E16F2/4B6E1744 TSSOP48 U102 74ALVC164245DGG {Lib=74ALVC164245} + ( 1 GND ) + ( 2 N-000012 ) + ( 3 N-000143 ) + ( 4 GND ) + ( 5 N-000038 ) + ( 6 N-000039 ) + ( 7 +5V ) + ( 8 N-000040 ) + ( 9 N-000041 ) + ( 10 GND ) + ( 11 N-000045 ) + ( 12 N-000047 ) + ( 13 N-000049 ) + ( 14 N-000053 ) + ( 15 GND ) + ( 16 N-000056 ) + ( 17 N-000095 ) + ( 18 +5V ) + ( 19 N-000100 ) + ( 20 N-000042 ) + ( 21 GND ) + ( 22 N-000037 ) + ( 23 N-000050 ) + ( 24 GND ) + ( 25 GND ) + ( 26 SNES_A6 ) + ( 27 SNES_A17 ) + ( 28 GND ) + ( 29 SNES_A5 ) + ( 30 SNES_A18 ) + ( 31 +3.3V ) + ( 32 SNES_A4 ) + ( 33 SNES_A19 ) + ( 34 GND ) + ( 35 SNES_A3 ) + ( 36 SNES_A20 ) + ( 37 SNES_A2 ) + ( 38 SNES_A21 ) + ( 39 GND ) + ( 40 SNES_A1 ) + ( 41 SNES_A22 ) + ( 42 +3.3V ) + ( 43 SNES_A0 ) + ( 44 SNES_A23 ) + ( 45 GND ) + ( 46 SNES_/ROMSEL ) + ( 47 SNES_/RD ) + ( 48 GND ) + ) + ( /4B6E16F2/4B6E1740 TSSOP48 U101 74ALVC164245DGG {Lib=74ALVC164245} + ( 1 GND ) + ( 2 N-000102 ) + ( 3 N-000092 ) + ( 4 GND ) + ( 5 N-000103 ) + ( 6 N-000104 ) + ( 7 +5V ) + ( 8 N-000105 ) + ( 9 N-000106 ) + ( 10 GND ) + ( 11 N-000013 ) + ( 12 N-000144 ) + ( 13 N-000074 ) + ( 14 N-000078 ) + ( 15 GND ) + ( 16 N-000071 ) + ( 17 N-000086 ) + ( 18 +5V ) + ( 19 N-000091 ) + ( 20 N-000107 ) + ( 21 GND ) + ( 22 N-000072 ) + ( 23 N-000075 ) + ( 24 DATABUS_DIR ) + ( 25 DATABUS_/OE ) + ( 26 N-000083 ) + ( 27 N-000087 ) + ( 28 GND ) + ( 29 N-000145 ) + ( 30 N-000108 ) + ( 31 +3.3V ) + ( 32 N-000073 ) + ( 33 N-000076 ) + ( 34 GND ) + ( 35 N-000082 ) + ( 36 N-000084 ) + ( 37 SNES_CPU_CLK ) + ( 38 SNES_/WR ) + ( 39 GND ) + ( 40 SNES_PA1 ) + ( 41 SNES_PA0 ) + ( 42 +3.3V ) + ( 43 SNES_PA3 ) + ( 44 SNES_PA2 ) + ( 45 GND ) + ( 46 SNES_PA5 ) + ( 47 SNES_PA4 ) + ( 48 GND ) + ) + ( /4BAA6ABD/4D49598F $noname U511 CY62148EV30-ZSXI {Lib=CY62148EV30-ZSXI} + ( 1 RAM_A17 ) + ( 2 RAM_A16 ) + ( 3 RAM_A14 ) + ( 4 RAM_A12 ) + ( 5 RAM_A7 ) + ( 6 RAM_A6 ) + ( 7 RAM_A5 ) + ( 8 RAM_A4 ) + ( 9 RAM_A3 ) + ( 10 RAM_A2 ) + ( 11 RAM_A1 ) + ( 12 RAM_A0 ) + ( 13 RAM_DQ0 ) + ( 14 RAM_DQ1 ) + ( 15 RAM_DQ2 ) + ( 16 GND ) + ( 17 RAM_DQ3 ) + ( 18 RAM_DQ4 ) + ( 19 RAM_DQ5 ) + ( 20 RAM_DQ6 ) + ( 21 RAM_DQ7 ) + ( 22 /Memory/RAM_/CE ) + ( 23 RAM_A10 ) + ( 24 RAM_/OE ) + ( 25 RAM_A11 ) + ( 26 RAM_A9 ) + ( 27 RAM_A8 ) + ( 28 RAM_A13 ) + ( 29 RAM_/WE ) + ( 30 RAM_A18 ) + ( 31 RAM_A15 ) + ( 32 /Memory/SRAM_Vcc ) + ) + ( /4BAA6ABD/4BF2FDAF SM0805_FIXEDMASK R511 20k {Lib=R} + ( 1 /Memory/SRAM_Vcc ) + ( 2 /Memory/RAM_/CE ) + ) + ( /4BAA6ABD/4BF2FDAC SM0805_FIXEDMASK R513 100k {Lib=R} + ( 1 N-000344 ) + ( 2 GND ) + ) + ( /4BAA6ABD/4BF2FDA9 SM0805_FIXEDMASK R512 4k7 {Lib=R} + ( 1 N-000344 ) + ( 2 +3.3V ) + ) + ( /4BAA6ABD/4BF2FD9F SOT23EBC Q511 2N2222A {Lib=NPN} + ( 1 GND ) + ( 2 N-000344 ) + ( 3 /Memory/RAM_/CE ) + ) + ( /4BAA6ABD/4BF19DCA SOT23EBC D511 BAT54C {Lib=DOUBLE_SCH_KCOM2} + ( 1 +3.3V ) + ( 2 +BATT ) + ( 3 /Memory/SRAM_Vcc ) + ) + ( /4BAA6ABD/4BAD3D55 SM0805_FIXEDMASK C502 100n {Lib=C} + ( 1 +1.8V ) + ( 2 GND ) + ) + ( /4BAA6ABD/4BAD3D53 SM0805_FIXEDMASK C511 100n {Lib=C} + ( 1 /Memory/SRAM_Vcc ) + ( 2 GND ) + ) + ( /4BAA6ABD/4BAD3D47 SM0805_FIXEDMASK C501 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4BAA6ABD/4B868602 VFBGA54 U501 MT45W8MW16 {Lib=MT45W8MW16} + ( A1 ROM_/LB ) + ( A2 ROM_/OE ) + ( A3 ROM_A0 ) + ( A4 ROM_A1 ) + ( A5 ROM_A2 ) + ( A6 GND ) + ( B1 ROM_DQ8 ) + ( B2 ROM_/UB ) + ( B3 ROM_A3 ) + ( B4 ROM_A4 ) + ( B5 ROM_/CE ) + ( B6 ROM_DQ0 ) + ( C1 ROM_DQ9 ) + ( C2 ROM_DQ10 ) + ( C3 ROM_A5 ) + ( C4 ROM_A6 ) + ( C5 ROM_DQ1 ) + ( C6 ROM_DQ2 ) + ( D1 GND ) + ( D2 ROM_DQ11 ) + ( D3 ROM_A17 ) + ( D4 ROM_A7 ) + ( D5 ROM_DQ3 ) + ( D6 +1.8V ) + ( E1 +3.3V ) + ( E2 ROM_DQ12 ) + ( E3 ROM_A21 ) + ( E4 ROM_A16 ) + ( E5 ROM_DQ4 ) + ( E6 GND ) + ( F1 ROM_DQ14 ) + ( F2 ROM_DQ13 ) + ( F3 ROM_A14 ) + ( F4 ROM_A15 ) + ( F5 ROM_DQ5 ) + ( F6 ROM_DQ6 ) + ( G1 ROM_DQ15 ) + ( G2 ROM_A19 ) + ( G3 ROM_A12 ) + ( G4 ROM_A13 ) + ( G5 ROM_/WE ) + ( G6 ROM_DQ7 ) + ( H1 ROM_A18 ) + ( H2 ROM_A8 ) + ( H3 ROM_A9 ) + ( H4 ROM_A10 ) + ( H5 ROM_A11 ) + ( H6 ROM_A20 ) + ( J1 ? ) + ( J2 GND ) + ( J3 GND ) + ( J4 ROM_A22 ) + ) + ( /4B6ED75B/4E2C1796 $noname JP402 JUMPER {Lib=JUMPER} + ( 1 GND ) + ( 2 /USEBATT ) + ) + ( /4B6ED75B/4DF9F6C8 $noname P404 CONN_3X2 {Lib=CONN_3X2} + ( 1 P1_D0 ) + ( 2 P1_CLK ) + ( 3 P_LATCH ) + ( 4 MCU_SPARE ) + ( 5 P2_CLK ) + ( 6 P2_D0 ) + ) + ( /4B6ED75B/4C86265B $noname JP401 JUMPER {Lib=JUMPER} + ( 1 N-000300 ) + ( 2 CIC_MCLR ) + ) + ( /4B6ED75B/4C814430 SM0805_FIXEDMASK R407 10k {Lib=R} + ( 1 P2.10 ) + ( 2 +3.3V ) + ) + ( /4B6ED75B/4C5608C9 SM0805_FIXEDMASK R422 33 {Lib=R} + ( 1 N-000310 ) + ( 2 N-000314 ) + ) + ( /4B6ED75B/4C5608C6 SM0805_FIXEDMASK R421 33 {Lib=R} + ( 1 N-000315 ) + ( 2 N-000309 ) + ) + ( /4B6ED75B/4C4A0B6F PIN_ARRAY_2X1 P403 CONN_2 {Lib=CONN_2} + ( 1 GND ) + ( 2 N-000313 ) + ) + ( /4B6ED75B/4C1286D5 SM0805_FIXEDMASK C412 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4C0DA78D LED-3MM-FIXED D403 LED_2mA_1.7V,_red {Lib=LED} + ( 1 +3.3V ) + ( 2 N-000311 ) + ) + ( /4B6ED75B/4C0DA785 SM0805_FIXEDMASK R403 680 {Lib=R} + ( 1 N-000323 ) + ( 2 N-000311 ) + ) + ( /4B6ED75B/4C0943CA pin_array_7x2 P401 CONN_7X2 {Lib=CONN_7X2} + ( 1 +3.3V ) + ( 2 +5V ) + ( 3 GND ) + ( 4 P2.10 ) + ( 5 /RESET ) + ( 6 TX3 ) + ( 7 RX3 ) + ( 8 TCK ) + ( 9 /TRST ) + ( 10 TMS ) + ( 11 EXT_TDI ) + ( 12 EXT_TDO ) + ( 13 RX0 ) + ( 14 TX0 ) + ) + ( /4B6ED75B/4C063C47 SM0805_FIXEDMASK C405 100n {Lib=C} + ( 1 /RESET ) + ( 2 GND ) + ) + ( /4B6ED75B/4C063C2F SM0805_FIXEDMASK R404 10k {Lib=R} + ( 1 /RESET ) + ( 2 +3.3V ) + ) + ( /4B6ED75B/4C01596A SM0805_FIXEDMASK R423 1.5k {Lib=R} + ( 1 N-000315 ) + ( 2 USB_SWCONN ) + ) + ( /4B6ED75B/4BF850D1 SM0805_FIXEDMASK R405 100 {Lib=R} + ( 1 CCLK ) + ( 2 N-000327 ) + ) + ( /4B6ED75B/4BF850A9 SM0805_FIXEDMASK R406 100 {Lib=R} + ( 1 N-000324 ) + ( 2 PROG_B ) + ) + ( /4B6ED75B/4BF847B1 SM0805_FIXEDMASK R402 680 {Lib=R} + ( 1 N-000322 ) + ( 2 N-000305 ) + ) + ( /4B6ED75B/4BF847A7 SM0805_FIXEDMASK R401 680 {Lib=R} + ( 1 N-000294 ) + ( 2 N-000316 ) + ) + ( /4B6ED75B/4BF8328D LED-3MM-FIXED D401 LED_2mA_1.9V,_green {Lib=LED} + ( 1 +3.3V ) + ( 2 N-000316 ) + ) + ( /4B6ED75B/4BF8324A LED-3MM-FIXED D402 LED_2mA_1.8V,_yellow {Lib=LED} + ( 1 +3.3V ) + ( 2 N-000305 ) + ) + ( /4B6ED75B/4BF6BFE6 SM0805_FIXEDMASK C404 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4BF6BFE5 SM0805_FIXEDMASK C403 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4BF6BFE2 SM0805_FIXEDMASK C402 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4BF6BFE1 SM0805_FIXEDMASK C401 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4BF6BFBB SM0805_FIXEDMASK C411 10u {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6ED75B/4BF00175 USB-MINIB-THT J421 Molex_54819 {Lib=USB_MINIB} + ( 1 N-000328 ) + ( 2 N-000310 ) + ( 3 N-000315 ) + ( 5 GND ) + ( 6 GND ) + ( 7 GND ) + ) + ( /4B6ED75B/4BEFBC73 PIN_ARRAY_2X1 P402 CONN_2 {Lib=CONN_2} + ( 1 GND ) + ( 2 /RESET ) + ) + ( /4B6ED75B/4BAA6A9C $noname J411 Hirose_DM1AA {Lib=SD_CARD} + ( 1 SD_DAT3 ) + ( 2 SD_CMD ) + ( 3 GND ) + ( 4 +3.3V ) + ( 5 SD_CLK ) + ( 6 GND ) + ( 7 SD_DAT0 ) + ( 8 SD_DAT1 ) + ( 9 SD_DAT2 ) + ( DT N-000318 ) + ( GND1 GND ) + ( GND2 GND ) + ( WP N-000295 ) + ) + ( /4B6ED75B/4BEECBD1 SM0805_FIXEDMASK C409 10p {Lib=C} + ( 1 N-000338 ) + ( 2 GND ) + ) + ( /4B6ED75B/4BEECBCD SM0805_FIXEDMASK C408 10p {Lib=C} + ( 1 N-000337 ) + ( 2 GND ) + ) + ( /4B6ED75B/4BEECBCA SM0805_FIXEDMASK C407 33p {Lib=C} + ( 1 N-000340 ) + ( 2 GND ) + ) + ( /4B6ED75B/4BEECBC1 SM0805_FIXEDMASK C406 33p {Lib=C} + ( 1 N-000339 ) + ( 2 GND ) + ) + ( /4B6ED75B/4BC243CB XTAL_SMD_05019 X402 32.768kHz {Lib=CRYSTAL} + ( 1 N-000337 ) + ( 2 N-000338 ) + ) + ( /4B6ED75B/4BC243C8 XTAL_SMD_05032 X401 12MHz {Lib=CRYSTAL} + ( 1 N-000339 ) + ( 2 N-000340 ) + ) + ( /4B6ED75B/4B6F321A LQFP80-.5 U401 LPC1754 {Lib=LPC1754} + ( 1 EXT_TDO ) + ( 2 EXT_TDI ) + ( 3 TMS ) + ( 4 /TRST ) + ( 5 TCK ) + ( 6 RX3 ) + ( 7 TX3 ) + ( 8 +3.3V ) + ( 9 GND ) + ( 10 +3.3V ) + ( 11 ? ) + ( 12 GND ) + ( 13 N-000337 ) + ( 14 /RESET ) + ( 15 N-000338 ) + ( 16 +BATT ) + ( 17 ? ) + ( 18 N-000328 ) + ( 19 N-000339 ) + ( 20 N-000340 ) + ( 21 +3.3V ) + ( 22 N-000309 ) + ( 23 N-000314 ) + ( 24 GND ) + ( 25 N-000313 ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 N-000323 ) + ( 30 DAC_/DEM ) + ( 31 N-000300 ) + ( 32 SNES_/RESET ) + ( 33 GND ) + ( 34 +3.3V ) + ( 35 ? ) + ( 36 CIC_STATUS ) + ( 37 CIC_DATA1 ) + ( 38 CIC_DATA0 ) + ( 39 FPGA_CLK ) + ( 40 N-000327 ) + ( 41 P2.10 ) + ( 42 +3.3V ) + ( 43 GND ) + ( 44 DONE ) + ( 45 MCU_SPI_MOSI ) + ( 46 MCU_SPI_MISO ) + ( 47 MCU_SPI_SCK ) + ( 48 MCU_SPI_SS ) + ( 49 INIT_B+MCU_IRQ ) + ( 50 DIN+MCU_/OVR ) + ( 51 ? ) + ( 52 ? ) + ( 53 N-000322 ) + ( 54 N-000294 ) + ( 55 SD_DAT3 ) + ( 56 +3.3V ) + ( 57 GND ) + ( 58 SD_DAT2 ) + ( 59 SD_DAT1 ) + ( 60 SD_DAT0 ) + ( 61 SD_CMD ) + ( 62 N-000318 ) + ( 63 SD_CLK ) + ( 64 N-000295 ) + ( 65 USB_SWCONN ) + ( 66 GND ) + ( 67 +3.3V ) + ( 68 ? ) + ( 69 N-000324 ) + ( 70 /USEBATT ) + ( 71 P2_D0 ) + ( 72 P2_CLK ) + ( 73 MCU_SPARE ) + ( 74 P_LATCH ) + ( 75 P1_CLK ) + ( 76 P1_D0 ) + ( 77 +3.3V ) + ( 78 GND ) + ( 79 TX0 ) + ( 80 RX0 ) + ) + ( /4B6EC9C3/4EF8DF53 $noname FB342 FILTER {Lib=FILTER} + ( 1 GND ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4EF3B181 SM0805_FIXEDMASK C304 4.7u {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4EF3B17C $noname L302 4.7uH {Lib=INDUCTOR} + ( 1 /Power_Supply_/_Misc./LX33 ) + ( 2 +3.3V ) + ) + ( /4B6EC9C3/4EF3B15E SM0805_FIXEDMASK C303 4.7u {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4EF3AFF2 $noname L301 4.7uH {Lib=INDUCTOR} + ( 1 /Power_Supply_/_Misc./LX12 ) + ( 2 +1.2V ) + ) + ( /4B6EC9C3/4EF3ADA3 $noname U301 MCP1603T-120I/OS {Lib=MCP1603-SOT23-FIXED} + ( 1 +5V ) + ( 2 GND ) + ( 3 +5V ) + ( 4 +1.2V ) + ( 5 /Power_Supply_/_Misc./LX12 ) + ) + ( /4B6EC9C3/4EF3AD9A $noname U302 MCP1603T-330I/OS {Lib=MCP1603-SOT23-FIXED} + ( 1 +5V ) + ( 2 GND ) + ( 3 +5V ) + ( 4 +3.3V ) + ( 5 /Power_Supply_/_Misc./LX33 ) + ) + ( /4B6EC9C3/4DB2EA56 $noname FB341 FILTER {Lib=FILTER} + ( 1 +3.3V ) + ( 2 +3.3VDAC ) + ) + ( /4B6EC9C3/4D4BE786 SM0805_FIXEDMASK R301 20k {Lib=R} + ( 1 GND ) + ( 2 N-000275 ) + ) + ( /4B6EC9C3/4D4BCF29 $noname Q301 IRLML6402PbF {Lib=MOSFET_P} + ( D +5VL ) + ( G N-000275 ) + ( S +5V ) + ) + ( /4B6EC9C3/4CA655D4 SM0805_FIXEDMASK C332 100p {Lib=C} + ( 1 CIC_DATA0 ) + ( 2 GND ) + ) + ( /4B6EC9C3/4CA65597 SM0805_FIXEDMASK C333 100p {Lib=C} + ( 1 CIC_DATA1 ) + ( 2 GND ) + ) + ( /4B6EC9C3/4CA65577 SM0805_FIXEDMASK R333 680 {Lib=R} + ( 1 EXT_CIC_DATA1 ) + ( 2 CIC_DATA1 ) + ) + ( /4B6EC9C3/4CA6556E SM0805_FIXEDMASK R332 680 {Lib=R} + ( 1 CIC_DATA0 ) + ( 2 EXT_CIC_DATA0 ) + ) + ( /4B6EC9C3/4C42D578 SM0805_FIXEDMASK R331 680 {Lib=R} + ( 1 N-000284 ) + ( 2 CIC_CLK ) + ) + ( /4B6EC9C3/4C17DE31 SM0805_FIXEDMASK C342 1u {Lib=C} + ( 1 +3.3VDAC ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4C05ACA2 SM0805_FIXEDMASK C301 4.7u {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4C05AC9D SM0805_FIXEDMASK C302 4.7u {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BF98EC6 SM0805_FIXEDMASK R341 470 {Lib=R} + ( 1 AUDIO_R ) + ( 2 N-000277 ) + ) + ( /4B6EC9C3/4BF98EC4 SM0805_FIXEDMASK R342 10k {Lib=R} + ( 1 N-000277 ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98EBF SM0805_FIXEDMASK C349 10n {Lib=C} + ( 1 AUDIO_L ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98EBE SM0805_FIXEDMASK C346 3.3u {Lib=C} + ( 1 N-000277 ) + ( 2 N-000286 ) + ) + ( /4B6EC9C3/4BF98EBB SM0805_FIXEDMASK C348 3.3u {Lib=C} + ( 1 N-000285 ) + ( 2 N-000278 ) + ) + ( /4B6EC9C3/4BF98EB9 SM0805_FIXEDMASK R344 10k {Lib=R} + ( 1 N-000285 ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98EB4 SM0805_FIXEDMASK R343 470 {Lib=R} + ( 1 AUDIO_L ) + ( 2 N-000285 ) + ) + ( /4B6EC9C3/4BF98E9E SM0805_FIXEDMASK C347 10n {Lib=C} + ( 1 AUDIO_R ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98AAB SM0805_FIXEDMASK C345 10u {Lib=C} + ( 1 N-000281 ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98AA5 SM0805_FIXEDMASK C344 10u {Lib=C} + ( 1 N-000279 ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BF98AA2 SM0805_FIXEDMASK C343 100n {Lib=C} + ( 1 N-000279 ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BAF2EAF BT_KEYSTONE_1059_20MM BT351 Keystone_1059_/_KZH20PCB {Lib=BATTERY} + ( 1 +BATT ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BADC720 SM0805_FIXEDMASK C341 100n {Lib=C} + ( 1 +3.3VDAC ) + ( 2 AGND ) + ) + ( /4B6EC9C3/4BAA9331 TSSOP10 U341 CS4344 {Lib=CS4344} + ( 1 DAC_SDIN ) + ( 2 DAC_/DEM ) + ( 3 DAC_LRCK ) + ( 4 DAC_MCLK ) + ( 5 N-000279 ) + ( 6 N-000281 ) + ( 7 N-000278 ) + ( 8 AGND ) + ( 9 +3.3VDAC ) + ( 10 N-000286 ) + ) + ( /4B6EC9C3/4BADC719 SM0805_FIXEDMASK C331 100n {Lib=C} + ( 1 +5V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BABCB68 SM0805_FIXEDMASK C312 4.7u {Lib=C} + ( 1 +1.8V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BABCB5C SM0805_FIXEDMASK C311 4.7u {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BABCAD2 SM0805_FIXEDMASK C322 4.7u {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BABCA9C SM0805_FIXEDMASK C321 4.7u {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6EC9C3/4BAA92DB SO8N U331 PIC12F629-I/P {Lib=PIC12F629} + ( 1 +5V ) + ( 2 N-000284 ) + ( 3 CIC_STATUS ) + ( 4 CIC_MCLR ) + ( 5 CIC_RESET ) + ( 6 CIC_DATA1 ) + ( 7 CIC_DATA0 ) + ( 8 GND ) + ) + ( /4B6EC9C3/4B6ED144 SOT23-5 U311 MCP1824-1802E/OT {Lib=MCP1824-SOT23-Fixed} + ( 1 +3.3V ) + ( 2 GND ) + ( 3 +3.3V ) + ( 4 ? ) + ( 5 +1.8V ) + ) + ( /4B6EC9C3/4B6ED134 SOT23-5 U321 MCP1824-2502E/OT {Lib=MCP1824-SOT23-Fixed} + ( 1 +3.3V ) + ( 2 GND ) + ( 3 +3.3V ) + ( 4 ? ) + ( 5 +2.5V ) + ) + ( /4B6E18FC/4D2F566A SM0805_FIXEDMASK C234 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D2F497B SM0805_FIXEDMASK C233 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D2F4979 SM0805_FIXEDMASK C232 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D2F4480 SM0805_FIXEDMASK C215 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D2F4344 SM0805_FIXEDMASK C231 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D2F4312 SM0805_FIXEDMASK C209 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4D252B5C SM0805_FIXEDMASK C214 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4C7FF87E $noname P113 CONN_1 {Lib=CONN_1} + ( 1 N-000193 ) + ) + ( /4B6E18FC/4BF5A441 SM0805_FIXEDMASK C224 100n {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BF5A43F SM0805_FIXEDMASK C223 100n {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE85 SM0805_FIXEDMASK C222 100n {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE7D SM0805_FIXEDMASK C221 100n {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE7B SM0805_FIXEDMASK C213 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE7A SM0805_FIXEDMASK C212 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE78 SM0805_FIXEDMASK C211 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE74 SM0805_FIXEDMASK C210 100n {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE6D SM0805_FIXEDMASK C208 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE6B SM0805_FIXEDMASK C207 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE6A SM0805_FIXEDMASK C206 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE67 SM0805_FIXEDMASK C205 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE65 SM0805_FIXEDMASK C204 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE64 SM0805_FIXEDMASK C203 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE62 SM0805_FIXEDMASK C202 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4BADCE47 SM0805_FIXEDMASK C201 100n {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4B6E18FC/4B6E1931 PQFP208 U201 XC3S400-PQ208 {Lib=XC3S400-PQ208} + ( 1 GND ) + ( 2 ROM_A12 ) + ( 3 ROM_A18 ) + ( 4 ROM_A19 ) + ( 5 ROM_DQ15 ) + ( 6 +3.3V ) + ( 7 ROM_DQ13 ) + ( 8 GND ) + ( 9 ROM_DQ14 ) + ( 10 ROM_DQ12 ) + ( 11 ROM_A17 ) + ( 12 ROM_DQ11 ) + ( 13 ROM_DQ9 ) + ( 14 GND ) + ( 15 ROM_DQ10 ) + ( 16 ROM_DQ8 ) + ( 17 +2.5V ) + ( 18 ROM_A5 ) + ( 19 RAM_DQ3 ) + ( 20 RAM_DQ2 ) + ( 21 RAM_DQ4 ) + ( 22 RAM_DQ1 ) + ( 23 +3.3V ) + ( 24 RAM_DQ5 ) + ( 25 GND ) + ( 26 RAM_DQ0 ) + ( 27 RAM_DQ6 ) + ( 28 RAM_A0 ) + ( 29 RAM_DQ7 ) + ( 30 GND ) + ( 31 RAM_A1 ) + ( 32 +3.3V ) + ( 33 RAM_A2 ) + ( 34 RAM_A10 ) + ( 35 RAM_A3 ) + ( 36 RAM_/OE ) + ( 37 RAM_A4 ) + ( 38 +2.5V ) + ( 39 RAM_A11 ) + ( 40 RAM_A5 ) + ( 41 GND ) + ( 42 RAM_A9 ) + ( 43 RAM_A6 ) + ( 44 RAM_A8 ) + ( 45 RAM_A7 ) + ( 46 RAM_A13 ) + ( 47 GND ) + ( 48 RAM_A12 ) + ( 49 +3.3V ) + ( 50 RAM_/WE ) + ( 51 RAM_A14 ) + ( 52 RAM_A18 ) + ( 53 GND ) + ( 54 ? ) + ( 55 ? ) + ( 56 ? ) + ( 57 RAM_A16 ) + ( 58 RAM_A15 ) + ( 59 GND ) + ( 60 +3.3V ) + ( 61 RAM_A17 ) + ( 62 SD_DAT2 ) + ( 63 SD_DAT3 ) + ( 64 SD_CLK ) + ( 65 SD_DAT0 ) + ( 66 GND ) + ( 67 SD_CMD ) + ( 68 MCU_SPI_SS ) + ( 69 +2.5V ) + ( 70 +1.2V ) + ( 71 MCU_SPI_SCK ) + ( 72 MCU_SPI_MISO ) + ( 73 +3.3V ) + ( 74 MCU_SPI_MOSI ) + ( 75 GND ) + ( 76 DAC_MCLK ) + ( 77 DAC_LRCK ) + ( 78 DAC_SDIN ) + ( 79 SD_DAT1 ) + ( 80 FPGA_CLK ) + ( 81 SNES_PA4 ) + ( 82 GND ) + ( 83 INIT_B+MCU_IRQ ) + ( 84 +3.3V ) + ( 85 SNES_PA5 ) + ( 86 SNES_PA2 ) + ( 87 SNES_PA3 ) + ( 88 +1.2V ) + ( 89 +2.5V ) + ( 90 SNES_PA0 ) + ( 91 GND ) + ( 92 DIN+MCU_/OVR ) + ( 93 SNES_PA1 ) + ( 94 SNES_/WR ) + ( 95 SNES_CPU_CLK ) + ( 96 SNES_D3 ) + ( 97 SNES_D7 ) + ( 98 +3.3V ) + ( 99 GND ) + ( 100 SNES_D2 ) + ( 101 SNES_D6 ) + ( 102 SNES_D1 ) + ( 103 DONE ) + ( 104 CCLK ) + ( 105 GND ) + ( 106 SNES_D5 ) + ( 107 SNES_D0 ) + ( 108 SNES_D4 ) + ( 109 DATABUS_/OE ) + ( 110 +3.3V ) + ( 111 DATABUS_DIR ) + ( 112 GND ) + ( 113 N-000193 ) + ( 114 SNES_IRQ_EN ) + ( 115 SNES_/RD ) + ( 116 SNES_/ROMSEL ) + ( 117 SNES_A23 ) + ( 118 GND ) + ( 119 SNES_A0 ) + ( 120 SNES_A22 ) + ( 121 +2.5V ) + ( 122 SNES_A1 ) + ( 123 SNES_A21 ) + ( 124 SNES_A2 ) + ( 125 SNES_A20 ) + ( 126 SNES_A3 ) + ( 127 +3.3V ) + ( 128 SNES_A19 ) + ( 129 GND ) + ( 130 SNES_A4 ) + ( 131 SNES_A18 ) + ( 132 SNES_A5 ) + ( 133 SNES_A17 ) + ( 134 GND ) + ( 135 SNES_A6 ) + ( 136 +3.3V ) + ( 137 SNES_A16 ) + ( 138 SNES_A7 ) + ( 139 SNES_A15 ) + ( 140 SNES_A8 ) + ( 141 SNES_A14 ) + ( 142 +2.5V ) + ( 143 SNES_A9 ) + ( 144 SNES_A13 ) + ( 145 GND ) + ( 146 SNES_A10 ) + ( 147 SNES_A12 ) + ( 148 SNES_A11 ) + ( 149 SNES_/PARD ) + ( 150 SNES_/PAWR ) + ( 151 GND ) + ( 152 SNES_PA6 ) + ( 153 +3.3V ) + ( 154 SNES_PA7 ) + ( 155 SNES_REFRESH ) + ( 156 ROM_/LB ) + ( 157 GND ) + ( 158 ? ) + ( 159 ? ) + ( 160 ? ) + ( 161 ROM_/UB ) + ( 162 ROM_/OE ) + ( 163 GND ) + ( 164 +3.3V ) + ( 165 ROM_A3 ) + ( 166 ROM_A0 ) + ( 167 ROM_A7 ) + ( 168 ROM_A1 ) + ( 169 ROM_A4 ) + ( 170 GND ) + ( 171 ROM_A2 ) + ( 172 ROM_/CE ) + ( 173 +2.5V ) + ( 174 +1.2V ) + ( 175 ROM_A6 ) + ( 176 ROM_DQ0 ) + ( 177 +3.3V ) + ( 178 ROM_DQ1 ) + ( 179 GND ) + ( 180 SNES_SYS_CLK ) + ( 181 ROM_DQ2 ) + ( 182 ROM_DQ3 ) + ( 183 ROM_DQ4 ) + ( 184 ROM_A15 ) + ( 185 ROM_DQ6 ) + ( 186 GND ) + ( 187 ROM_DQ5 ) + ( 188 +3.3V ) + ( 189 ROM_DQ7 ) + ( 190 ROM_/WE ) + ( 191 ROM_A20 ) + ( 192 +1.2V ) + ( 193 +2.5V ) + ( 194 ROM_A13 ) + ( 195 GND ) + ( 196 ROM_A11 ) + ( 197 ROM_A10 ) + ( 198 ROM_A22 ) + ( 199 ROM_A16 ) + ( 200 ROM_A14 ) + ( 201 +3.3V ) + ( 202 GND ) + ( 203 ROM_A21 ) + ( 204 ROM_A9 ) + ( 205 ROM_A8 ) + ( 206 GND ) + ( 207 PROG_B ) + ( 208 ? ) + ) +) +* +{ Allowed footprints by component: +$component C128 + SM* + C? + C1-1 +$endlist +$component C127 + SM* + C? + C1-1 +$endlist +$component C126 + SM* + C? + C1-1 +$endlist +$component C125 + SM* + C? + C1-1 +$endlist +$component C124 + SM* + C? + C1-1 +$endlist +$component C123 + SM* + C? + C1-1 +$endlist +$component C122 + SM* + C? + C1-1 +$endlist +$component C121 + SM* + C? + C1-1 +$endlist +$component R103 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R102 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C111 + SM* + C? + C1-1 +$endlist +$component C112 + SM* + C? + C1-1 +$endlist +$component C113 + SM* + C? + C1-1 +$endlist +$component C106 + SM* + C? + C1-1 +$endlist +$component C105 + SM* + C? + C1-1 +$endlist +$component C104 + SM* + C? + C1-1 +$endlist +$component R101 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C116 + SM* + C? + C1-1 +$endlist +$component C115 + SM* + C? + C1-1 +$endlist +$component C114 + SM* + C? + C1-1 +$endlist +$component C103 + SM* + C? + C1-1 +$endlist +$component C102 + SM* + C? + C1-1 +$endlist +$component C101 + SM* + C? + C1-1 +$endlist +$component R511 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R513 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R512 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C502 + SM* + C? + C1-1 +$endlist +$component C511 + SM* + C? + C1-1 +$endlist +$component C501 + SM* + C? + C1-1 +$endlist +$component R407 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R422 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R421 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C412 + SM* + C? + C1-1 +$endlist +$component D403 + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$endlist +$component R403 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C405 + SM* + C? + C1-1 +$endlist +$component R404 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R423 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R405 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R406 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R402 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R401 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component D401 + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$endlist +$component D402 + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$endlist +$component C404 + SM* + C? + C1-1 +$endlist +$component C403 + SM* + C? + C1-1 +$endlist +$component C402 + SM* + C? + C1-1 +$endlist +$component C401 + SM* + C? + C1-1 +$endlist +$component C411 + SM* + C? + C1-1 +$endlist +$component C409 + SM* + C? + C1-1 +$endlist +$component C408 + SM* + C? + C1-1 +$endlist +$component C407 + SM* + C? + C1-1 +$endlist +$component C406 + SM* + C? + C1-1 +$endlist +$component C304 + SM* + C? + C1-1 +$endlist +$component C303 + SM* + C? + C1-1 +$endlist +$component R301 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C332 + SM* + C? + C1-1 +$endlist +$component C333 + SM* + C? + C1-1 +$endlist +$component R333 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R332 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R331 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C342 + SM* + C? + C1-1 +$endlist +$component C301 + SM* + C? + C1-1 +$endlist +$component C302 + SM* + C? + C1-1 +$endlist +$component R341 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R342 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C349 + SM* + C? + C1-1 +$endlist +$component C346 + SM* + C? + C1-1 +$endlist +$component C348 + SM* + C? + C1-1 +$endlist +$component R344 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component R343 + R? + SM0603 + SM0805 + R?-* + SM1206 +$endlist +$component C347 + SM* + C? + C1-1 +$endlist +$component C345 + SM* + C? + C1-1 +$endlist +$component C344 + SM* + C? + C1-1 +$endlist +$component C343 + SM* + C? + C1-1 +$endlist +$component C341 + SM* + C? + C1-1 +$endlist +$component C331 + SM* + C? + C1-1 +$endlist +$component C312 + SM* + C? + C1-1 +$endlist +$component C311 + SM* + C? + C1-1 +$endlist +$component C322 + SM* + C? + C1-1 +$endlist +$component C321 + SM* + C? + C1-1 +$endlist +$component C234 + SM* + C? + C1-1 +$endlist +$component C233 + SM* + C? + C1-1 +$endlist +$component C232 + SM* + C? + C1-1 +$endlist +$component C215 + SM* + C? + C1-1 +$endlist +$component C231 + SM* + C? + C1-1 +$endlist +$component C209 + SM* + C? + C1-1 +$endlist +$component C214 + SM* + C? + C1-1 +$endlist +$component C224 + SM* + C? + C1-1 +$endlist +$component C223 + SM* + C? + C1-1 +$endlist +$component C222 + SM* + C? + C1-1 +$endlist +$component C221 + SM* + C? + C1-1 +$endlist +$component C213 + SM* + C? + C1-1 +$endlist +$component C212 + SM* + C? + C1-1 +$endlist +$component C211 + SM* + C? + C1-1 +$endlist +$component C210 + SM* + C? + C1-1 +$endlist +$component C208 + SM* + C? + C1-1 +$endlist +$component C207 + SM* + C? + C1-1 +$endlist +$component C206 + SM* + C? + C1-1 +$endlist +$component C205 + SM* + C? + C1-1 +$endlist +$component C204 + SM* + C? + C1-1 +$endlist +$component C203 + SM* + C? + C1-1 +$endlist +$component C202 + SM* + C? + C1-1 +$endlist +$component C201 + SM* + C? + C1-1 +$endlist +$endfootprintlist +} +{ Pin List by Nets +Net 1 "GND" "GND" + U201 186 + U201 145 + U201 195 + U201 202 + U201 112 + U201 163 + J101 36 + U201 129 + U201 179 + U201 206 + U201 118 + U201 157 + U201 14 + U201 25 + U201 75 + U201 41 + U201 91 + C207 2 + U103 1 + C222 2 + C221 2 + U103 4 + C213 2 + C212 2 + C211 2 + C210 2 + C208 2 + U103 10 + U201 105 + C206 2 + C205 2 + C204 2 + U103 21 + C203 2 + U201 99 + U201 134 + U201 47 + U201 53 + U201 59 + U201 8 + U201 66 + U201 170 + U201 82 + U201 151 + U101 21 + C322 2 + C321 2 + BT351 2 + U102 39 + C301 2 + U102 28 + U102 48 + C331 2 + J101 5 + U101 1 + U101 4 + C312 2 + C311 2 + U101 10 + C102 2 + C101 2 + C202 2 + C201 2 + U201 1 + C304 2 + C103 2 + R301 1 + U201 30 + C303 2 + U301 2 + C116 2 + C115 2 + U302 2 + C114 2 + C209 2 + C214 2 + C224 2 + C223 2 + C231 2 + C234 2 + C233 2 + C232 2 + C215 2 + J411 3 + C123 2 + C122 2 + C121 2 + R102 2 + C124 2 + J411 6 + C409 2 + Q101 1 + P402 1 + P401 3 + C412 2 + C126 2 + P403 1 + C333 2 + C405 2 + C408 2 + C407 2 + C128 2 + C406 2 + C127 2 + U401 57 + C125 2 + C105 2 + J411 GND2 + J411 GND1 + U401 33 + U401 43 + U401 24 + U401 66 + U401 9 + U401 12 + C501 2 + C511 2 + C502 2 + R101 1 + U501 J3 + U501 J2 + U501 E6 + U501 A6 + U501 D1 + C404 2 + U511 16 + C401 2 + C402 2 + C403 2 + U401 78 + C411 2 + J421 5 + J421 6 + J421 7 + Q511 1 + R513 2 + U103 24 + U103 34 + U103 15 + U103 25 + U103 45 + JP402 1 + U102 24 + U102 34 + U102 15 + U102 25 + U102 45 + U101 45 + FB342 1 + C302 2 + U101 28 + U101 48 + U101 39 + C332 2 + U103 28 + U103 48 + U103 39 + U102 1 + U331 8 + U311 2 + U101 34 + U321 2 + U101 15 + U102 10 + U102 4 + U102 21 + C104 2 + C106 2 + C113 2 + C112 2 + C111 2 +Net 2 "/SNES Slot/SNES_EXT_SYS_CLK" "SNES_EXT_SYS_CLK" + U103 23 + J101 1 + R101 2 +Net 3 "/SNES Slot/SNES_EXT_A2" "SNES_EXT_A2" + RA107 1 + J101 15 +Net 4 "/SNES Slot/SNES_EXT_/PAWR" "SNES_EXT_/PAWR" + RA112 8 + J101 35 +Net 5 "/SNES Slot/SNES_EXT_PA6" "SNES_EXT_PA6" + RA112 7 + J101 3 +Net 6 "/SNES Slot/SNES_EXT_PA7" "SNES_EXT_PA7" + J101 34 + RA112 6 +Net 7 "/SNES Slot/SNES_EXT_REFRESH" "SNES_EXT_REFRESH" + J101 33 + RA112 5 + C126 1 +Net 8 "/SNES Slot/SNES_EXT_D3" "SNES_EXT_D3" + J101 22 + RA103 1 +Net 9 "/SNES Slot/SNES_EXT_D7" "SNES_EXT_D7" + J101 53 + RA103 2 +Net 10 "/SNES Slot/SNES_EXT_D2" "SNES_EXT_D2" + J101 21 + RA103 3 +Net 11 "/SNES Slot/SNES_EXT_D6" "SNES_EXT_D6" + J101 52 + RA103 4 +Net 12 "" "" + U102 2 + C125 1 + RA105 7 +Net 13 "" "" + RA102 6 + U101 11 + C124 1 +Net 14 "SNES_IRQ_EN" "SNES_IRQ_EN" + U201 114 + R103 1 +Net 15 "/SNES Slot/SNES_EXT_A6" "SNES_EXT_A6" + J101 11 + RA109 1 +Net 16 "/SNES Slot/SNES_EXT_PA0" "SNES_EXT_PA0" + J101 28 + RA102 1 +Net 17 "/SNES Slot/SNES_EXT_PA1" "SNES_EXT_PA1" + RA102 2 + J101 59 +Net 18 "/SNES Slot/SNES_EXT_/WR" "SNES_EXT_/WR" + RA102 3 + J101 54 +Net 19 "/SNES Slot/SNES_EXT_CPU_CLK" "SNES_EXT_CPU_CLK" + J101 57 + RA102 4 +Net 20 "/SNES Slot/SNES_EXT_PA4" "SNES_EXT_PA4" + J101 30 + RA101 1 +Net 21 "/SNES Slot/SNES_EXT_PA5" "SNES_EXT_PA5" + RA101 2 + J101 61 +Net 22 "/SNES Slot/SNES_EXT_PA2" "SNES_EXT_PA2" + J101 29 + RA101 3 +Net 23 "/SNES Slot/SNES_EXT_PA3" "SNES_EXT_PA3" + J101 60 + RA101 4 +Net 24 "/SNES Slot/SNES_EXT_D1" "SNES_EXT_D1" + J101 20 + RA104 1 +Net 25 "/SNES Slot/SNES_EXT_D5" "SNES_EXT_D5" + RA104 2 + J101 51 +Net 26 "/SNES Slot/SNES_EXT_D0" "SNES_EXT_D0" + J101 19 + RA104 3 +Net 27 "/SNES Slot/SNES_EXT_D4" "SNES_EXT_D4" + RA104 4 + J101 50 +Net 28 "SNES_D4" "SNES_D4" + U201 108 + RA114 5 +Net 29 "SNES_D0" "SNES_D0" + U201 107 + RA114 6 +Net 30 "SNES_D5" "SNES_D5" + U201 106 + RA114 7 +Net 31 "SNES_D1" "SNES_D1" + U201 102 + RA114 8 +Net 32 "SNES_D6" "SNES_D6" + U201 101 + RA113 5 +Net 33 "SNES_D2" "SNES_D2" + U201 100 + RA113 6 +Net 34 "SNES_D7" "SNES_D7" + U201 97 + RA113 7 +Net 35 "SNES_D3" "SNES_D3" + U201 96 + RA113 8 +Net 36 "" "" + Q101 2 + R103 2 + R102 1 +Net 37 "" "" + U102 22 + RA108 5 +Net 38 "" "" + RA105 5 + U102 5 +Net 39 "" "" + RA106 8 + U102 6 +Net 40 "" "" + U102 8 + RA106 7 +Net 41 "" "" + RA106 6 + U102 9 +Net 42 "" "" + RA108 6 + U102 20 +Net 43 "SNES_A18" "SNES_A18" + U201 131 + U102 30 +Net 44 "SNES_A1" "SNES_A1" + U201 122 + U102 40 +Net 45 "" "" + U102 11 + RA106 5 +Net 46 "SNES_A22" "SNES_A22" + U201 120 + U102 41 +Net 47 "" "" + RA107 8 + U102 12 +Net 48 "SNES_A4" "SNES_A4" + U201 130 + U102 32 +Net 49 "" "" + RA107 7 + U102 13 +Net 50 "" "" + U102 23 + RA109 8 +Net 51 "SNES_A19" "SNES_A19" + U102 33 + U201 128 +Net 52 "SNES_A0" "SNES_A0" + U201 119 + U102 43 +Net 53 "" "" + U102 14 + RA107 6 +Net 54 "SNES_A23" "SNES_A23" + U102 44 + U201 117 +Net 55 "SNES_A3" "SNES_A3" + U201 126 + U102 35 +Net 56 "" "" + RA107 5 + U102 16 +Net 57 "SNES_SYS_CLK" "SNES_SYS_CLK" + U201 180 + U103 26 +Net 58 "SNES_/PAWR" "SNES_/PAWR" + U201 150 + U103 32 +Net 59 "SNES_/PARD" "SNES_/PARD" + U103 33 + U201 149 +Net 60 "SNES_A8" "SNES_A8" + U103 43 + U201 140 +Net 61 "SNES_A15" "SNES_A15" + U103 44 + U201 139 +Net 62 "SNES_A11" "SNES_A11" + U103 35 + U201 148 +Net 63 "SNES_A6" "SNES_A6" + U102 26 + U201 135 +Net 64 "SNES_A12" "SNES_A12" + U201 147 + U103 36 +Net 65 "SNES_A7" "SNES_A7" + U103 46 + U201 138 +Net 66 "SNES_REFRESH" "SNES_REFRESH" + U201 155 + U103 27 +Net 67 "SNES_A10" "SNES_A10" + U103 37 + U201 146 +Net 68 "SNES_A16" "SNES_A16" + U201 137 + U103 47 +Net 69 "SNES_A13" "SNES_A13" + U103 38 + U201 144 +Net 70 "SNES_PA7" "SNES_PA7" + U103 29 + U201 154 +Net 71 "" "" + U101 16 + RA103 6 +Net 72 "" "" + RA104 6 + U101 22 +Net 73 "" "" + RA113 4 + U101 32 +Net 74 "" "" + RA103 8 + U101 13 +Net 75 "" "" + U101 23 + RA104 5 +Net 76 "" "" + U101 33 + RA113 3 +Net 77 "SNES_PA3" "SNES_PA3" + U201 87 + U101 43 +Net 78 "" "" + RA103 7 + U101 14 +Net 79 "DATABUS_DIR" "DATABUS_DIR" + U201 111 + U101 24 +Net 80 "SNES_PA2" "SNES_PA2" + U201 86 + U101 44 +Net 81 "DATABUS_/OE" "DATABUS_/OE" + U101 25 + U201 109 +Net 82 "" "" + U101 35 + RA113 2 +Net 83 "" "" + RA114 4 + U101 26 +Net 84 "" "" + RA113 1 + U101 36 +Net 85 "SNES_PA5" "SNES_PA5" + U201 85 + U101 46 +Net 86 "" "" + U101 17 + RA103 5 +Net 87 "" "" + U101 27 + RA114 3 +Net 88 "SNES_CPU_CLK" "SNES_CPU_CLK" + U101 37 + U201 95 +Net 89 "SNES_PA4" "SNES_PA4" + U101 47 + U201 81 +Net 90 "SNES_/WR" "SNES_/WR" + U201 94 + U101 38 +Net 91 "" "" + RA104 8 + U101 19 +Net 92 "" "" + U101 3 + RA101 7 +Net 93 "SNES_A20" "SNES_A20" + U102 36 + U201 125 +Net 94 "SNES_/ROMSEL" "SNES_/ROMSEL" + U102 46 + U201 116 +Net 95 "" "" + RA108 8 + U102 17 +Net 96 "SNES_A17" "SNES_A17" + U102 27 + U201 133 +Net 97 "SNES_A2" "SNES_A2" + U102 37 + U201 124 +Net 98 "SNES_/RD" "SNES_/RD" + U201 115 + U102 47 +Net 99 "SNES_A21" "SNES_A21" + U102 38 + U201 123 +Net 100 "" "" + RA108 7 + U102 19 +Net 101 "SNES_A5" "SNES_A5" + U201 132 + U102 29 +Net 102 "" "" + U101 2 + RA101 8 +Net 103 "" "" + RA101 6 + U101 5 +Net 104 "" "" + U101 6 + RA101 5 +Net 105 "" "" + RA102 8 + U101 8 +Net 106 "" "" + RA102 7 + U101 9 +Net 107 "" "" + RA104 7 + U101 20 +Net 108 "" "" + RA114 1 + U101 30 +Net 109 "SNES_PA1" "SNES_PA1" + U201 93 + U101 40 +Net 110 "SNES_PA0" "SNES_PA0" + U101 41 + U201 90 +Net 112 "+5V" "+5V" + C331 1 + U101 18 + U103 7 + U103 18 + U102 18 + C301 1 + C114 1 + U301 3 + C116 1 + U301 1 + C111 1 + C115 1 + U101 7 + C112 1 + C113 1 + Q301 S + U331 1 + C303 1 + U302 1 + U302 3 + U102 7 + P401 2 +Net 113 "/SNES Slot/SNES_EXT_A11" "SNES_EXT_A11" + RA111 3 + J101 6 +Net 114 "/SNES Slot/SNES_EXT_A10" "SNES_EXT_A10" + J101 7 + RA111 1 +Net 115 "/SNES Slot/SNES_EXT_A9" "SNES_EXT_A9" + RA110 3 + J101 8 +Net 116 "/SNES Slot/SNES_EXT_A8" "SNES_EXT_A8" + J101 9 + RA110 1 +Net 117 "/SNES Slot/SNES_EXT_A7" "SNES_EXT_A7" + J101 10 + RA109 3 +Net 118 "/SNES Slot/SNES_EXT_A15" "SNES_EXT_A15" + RA109 4 + J101 40 +Net 119 "AUDIO_L" "AUDIO_L" + C349 1 + R343 1 + J101 31 +Net 120 "" "" + U103 3 + RA109 6 +Net 121 "/SNES Slot/SNES_EXT_A12" "SNES_EXT_A12" + RA111 2 + J101 37 +Net 122 "/SNES Slot/SNES_EXT_/IRQ" "SNES_EXT_/IRQ" + J101 18 + RA105 1 +Net 123 "/SNES Slot/SNES_EXT_A13" "SNES_EXT_A13" + J101 38 + RA110 4 +Net 124 "/SNES Slot/SNES_EXT_A14" "SNES_EXT_A14" + J101 39 + RA110 2 +Net 125 "" "" + U103 2 + RA109 7 +Net 126 "+5VL" "+5VL" + J101 27 + J101 58 + Q301 D +Net 127 "" "" + RA109 5 + U103 5 +Net 128 "SNES_PA6" "SNES_PA6" + U201 152 + U103 30 +Net 129 "SNES_A9" "SNES_A9" + U201 143 + U103 40 +Net 130 "SNES_A14" "SNES_A14" + U201 141 + U103 41 +Net 131 "EXT_CIC_DATA1" "EXT_CIC_DATA1" + R333 1 + J101 24 +Net 132 "/SNES Slot/SNES_EXT_A16" "SNES_EXT_A16" + RA109 2 + J101 41 +Net 134 "/SNES Slot/SNES_EXT_A17" "SNES_EXT_A17" + J101 42 + RA108 4 +Net 135 "AUDIO_R" "AUDIO_R" + J101 62 + R341 1 + C347 1 +Net 136 "/SNES Slot/SNES_EXT_A18" "SNES_EXT_A18" + RA108 2 + J101 43 +Net 137 "" "" + U103 6 + RA110 8 +Net 138 "CIC_RESET" "CIC_RESET" + J101 25 + U331 5 +Net 139 "EXT_CIC_DATA0" "EXT_CIC_DATA0" + J101 55 + R332 2 +Net 140 "SNES_/RESET" "SNES_/RESET" + J101 26 + U401 32 +Net 141 "CIC_CLK" "CIC_CLK" + J101 56 + R331 2 +Net 142 "+3.3V" "+3.3V" + R407 2 + C208 1 + U103 31 + C203 1 + C204 1 + C205 1 + C206 1 + C207 1 + C202 1 + C501 1 + C209 1 + U102 42 + U103 42 + U102 31 + L302 2 + U302 4 + U311 1 + FB341 1 + U101 42 + C304 1 + C311 1 + U101 31 + C321 1 + C103 1 + U321 3 + U321 1 + U311 3 + C201 1 + U201 6 + C231 1 + U201 60 + C232 1 + C233 1 + C234 1 + C102 1 + C101 1 + U501 E1 + U401 77 + U401 10 + U401 56 + U401 34 + D402 1 + D401 1 + U201 32 + U401 67 + C404 1 + U201 23 + P401 1 + U201 73 + J411 4 + U201 110 + U201 136 + C411 1 + C401 1 + U201 127 + U201 177 + U401 21 + C402 1 + U401 42 + C403 1 + U401 8 + U201 84 + R404 2 + U201 201 + D403 1 + C412 1 + U201 49 + U201 98 + D511 1 + C106 1 + R512 2 + U201 153 + C104 1 + C105 1 + U201 188 + U201 164 +Net 143 "" "" + U102 3 + RA105 6 + C122 1 +Net 144 "" "" + C121 1 + U101 12 + RA102 5 +Net 145 "" "" + U101 29 + RA114 2 +Net 146 "" "" + RA111 8 + U103 12 +Net 147 "" "" + Q101 3 + RA105 8 + C123 1 +Net 148 "/SNES Slot/SNES_EXT_/RD" "SNES_EXT_/RD" + J101 23 + RA105 2 +Net 149 "/SNES Slot/SNES_EXT_/ROMSEL" "SNES_EXT_/ROMSEL" + RA105 3 + J101 49 +Net 150 "/SNES Slot/SNES_EXT_A23" "SNES_EXT_A23" + RA105 4 + J101 48 +Net 151 "" "" + C127 1 + U103 17 + RA112 1 +Net 152 "" "" + U103 19 + RA112 2 +Net 153 "" "" + RA112 3 + U103 20 +Net 154 "" "" + U103 22 + RA112 4 +Net 155 "/SNES Slot/SNES_EXT_/PARD" "SNES_EXT_/PARD" + J101 4 + RA111 4 +Net 156 "" "" + RA111 5 + U103 16 + C128 1 +Net 157 "" "" + RA111 6 + U103 14 +Net 158 "" "" + U103 13 + RA111 7 +Net 159 "" "" + RA110 5 + U103 11 +Net 160 "" "" + U103 9 + RA110 6 +Net 161 "" "" + U103 8 + RA110 7 +Net 162 "/SNES Slot/SNES_EXT_A4" "SNES_EXT_A4" + RA108 1 + J101 13 +Net 163 "/SNES Slot/SNES_EXT_A5" "SNES_EXT_A5" + RA108 3 + J101 12 +Net 164 "/SNES Slot/SNES_EXT_A20" "SNES_EXT_A20" + J101 45 + RA107 2 +Net 165 "/SNES Slot/SNES_EXT_A3" "SNES_EXT_A3" + RA107 3 + J101 14 +Net 166 "/SNES Slot/SNES_EXT_A19" "SNES_EXT_A19" + J101 44 + RA107 4 +Net 167 "/SNES Slot/SNES_EXT_A0" "SNES_EXT_A0" + J101 17 + RA106 1 +Net 168 "/SNES Slot/SNES_EXT_A22" "SNES_EXT_A22" + J101 47 + RA106 2 +Net 169 "/SNES Slot/SNES_EXT_A1" "SNES_EXT_A1" + RA106 3 + J101 16 +Net 170 "/SNES Slot/SNES_EXT_A21" "SNES_EXT_A21" + RA106 4 + J101 46 +Net 171 "ROM_A12" "ROM_A12" + U201 2 + U501 G3 +Net 172 "DONE" "DONE" + U201 103 + U401 44 +Net 173 "SD_DAT3" "SD_DAT3" + U401 55 + U201 63 + J411 1 +Net 174 "SD_DAT0" "SD_DAT0" + U201 65 + J411 7 + U401 60 +Net 175 "MCU_SPI_SS" "MCU_SPI_SS" + U201 68 + U401 48 +Net 176 "MCU_SPI_MISO" "MCU_SPI_MISO" + U201 72 + U401 46 +Net 177 "DAC_MCLK" "DAC_MCLK" + U201 76 + U341 4 +Net 178 "DAC_SDIN" "DAC_SDIN" + U341 1 + U201 78 +Net 179 "ROM_/LB" "ROM_/LB" + U201 156 + U501 A1 +Net 180 "DIN+MCU_/OVR" "DIN+MCU_/OVR" + U201 92 + U401 50 +Net 181 "RAM_A1" "RAM_A1" + U511 11 + U201 31 +Net 182 "RAM_/WE" "RAM_/WE" + U511 29 + U201 50 +Net 183 "RAM_A4" "RAM_A4" + U201 37 + U511 8 +Net 184 "RAM_A3" "RAM_A3" + U511 9 + U201 35 +Net 185 "RAM_A7" "RAM_A7" + U201 45 + U511 5 +Net 186 "RAM_A6" "RAM_A6" + U511 6 + U201 43 +Net 187 "RAM_DQ0" "RAM_DQ0" + U511 13 + U201 26 +Net 188 "RAM_A8" "RAM_A8" + U201 44 + U511 27 +Net 189 "PROG_B" "PROG_B" + U201 207 + R406 2 +Net 190 "CCLK" "CCLK" + U201 104 + R405 1 +Net 191 "SD_DAT2" "SD_DAT2" + U201 62 + U401 58 + J411 9 +Net 192 "SD_DAT1" "SD_DAT1" + J411 8 + U201 79 + U401 59 +Net 193 "" "" + U201 113 + P113 1 +Net 194 "RAM_DQ2" "RAM_DQ2" + U201 20 + U511 15 +Net 195 "RAM_A10" "RAM_A10" + U511 23 + U201 34 +Net 196 "RAM_A2" "RAM_A2" + U511 10 + U201 33 +Net 197 "RAM_DQ7" "RAM_DQ7" + U511 21 + U201 29 +Net 198 "RAM_A0" "RAM_A0" + U511 12 + U201 28 +Net 199 "RAM_DQ6" "RAM_DQ6" + U201 27 + U511 20 +Net 200 "RAM_DQ5" "RAM_DQ5" + U511 19 + U201 24 +Net 201 "RAM_DQ1" "RAM_DQ1" + U201 22 + U511 14 +Net 202 "RAM_DQ4" "RAM_DQ4" + U201 21 + U511 18 +Net 203 "RAM_/OE" "RAM_/OE" + U511 24 + U201 36 +Net 204 "RAM_DQ3" "RAM_DQ3" + U511 17 + U201 19 +Net 205 "ROM_A5" "ROM_A5" + U201 18 + U501 C3 +Net 206 "ROM_DQ10" "ROM_DQ10" + U201 15 + U501 C2 +Net 207 "ROM_DQ9" "ROM_DQ9" + U201 13 + U501 C1 +Net 208 "ROM_DQ11" "ROM_DQ11" + U501 D2 + U201 12 +Net 209 "ROM_A17" "ROM_A17" + U201 11 + U501 D3 +Net 210 "ROM_DQ12" "ROM_DQ12" + U501 E2 + U201 10 +Net 211 "ROM_DQ14" "ROM_DQ14" + U201 9 + U501 F1 +Net 212 "ROM_DQ13" "ROM_DQ13" + U201 7 + U501 F2 +Net 213 "ROM_DQ15" "ROM_DQ15" + U201 5 + U501 G1 +Net 214 "ROM_A19" "ROM_A19" + U501 G2 + U201 4 +Net 215 "RAM_A18" "RAM_A18" + U511 30 + U201 52 +Net 216 "INIT_B+MCU_IRQ" "INIT_B+MCU_IRQ" + U401 49 + U201 83 +Net 217 "ROM_/UB" "ROM_/UB" + U501 B2 + U201 161 +Net 218 "RAM_A17" "RAM_A17" + U201 61 + U511 1 +Net 219 "RAM_A15" "RAM_A15" + U201 58 + U511 31 +Net 220 "RAM_A16" "RAM_A16" + U201 57 + U511 2 +Net 221 "ROM_A18" "ROM_A18" + U201 3 + U501 H1 +Net 222 "RAM_A14" "RAM_A14" + U511 3 + U201 51 +Net 223 "RAM_A12" "RAM_A12" + U201 48 + U511 4 +Net 224 "RAM_A13" "RAM_A13" + U201 46 + U511 28 +Net 225 "RAM_A9" "RAM_A9" + U201 42 + U511 26 +Net 226 "RAM_A5" "RAM_A5" + U201 40 + U511 7 +Net 227 "RAM_A11" "RAM_A11" + U511 25 + U201 39 +Net 228 "FPGA_CLK" "FPGA_CLK" + U201 80 + U401 39 +Net 229 "DAC_LRCK" "DAC_LRCK" + U201 77 + U341 3 +Net 230 "MCU_SPI_MOSI" "MCU_SPI_MOSI" + U201 74 + U401 45 +Net 231 "MCU_SPI_SCK" "MCU_SPI_SCK" + U201 71 + U401 47 +Net 232 "SD_CMD" "SD_CMD" + U401 61 + U201 67 + J411 2 +Net 233 "SD_CLK" "SD_CLK" + J411 5 + U201 64 + U401 63 +Net 234 "ROM_A8" "ROM_A8" + U201 205 + U501 H2 +Net 235 "ROM_A9" "ROM_A9" + U201 204 + U501 H3 +Net 236 "ROM_A21" "ROM_A21" + U201 203 + U501 E3 +Net 237 "ROM_A14" "ROM_A14" + U501 F3 + U201 200 +Net 238 "ROM_A16" "ROM_A16" + U201 199 + U501 E4 +Net 239 "ROM_A22" "ROM_A22" + U201 198 + U501 J4 +Net 240 "ROM_A10" "ROM_A10" + U201 197 + U501 H4 +Net 241 "ROM_DQ8" "ROM_DQ8" + U501 B1 + U201 16 +Net 242 "ROM_A11" "ROM_A11" + U501 H5 + U201 196 +Net 243 "ROM_A13" "ROM_A13" + U201 194 + U501 G4 +Net 244 "ROM_A20" "ROM_A20" + U201 191 + U501 H6 +Net 245 "ROM_/WE" "ROM_/WE" + U501 G5 + U201 190 +Net 246 "ROM_DQ7" "ROM_DQ7" + U201 189 + U501 G6 +Net 247 "ROM_DQ5" "ROM_DQ5" + U201 187 + U501 F5 +Net 248 "ROM_DQ6" "ROM_DQ6" + U201 185 + U501 F6 +Net 249 "ROM_A15" "ROM_A15" + U501 F4 + U201 184 +Net 250 "ROM_DQ4" "ROM_DQ4" + U501 E5 + U201 183 +Net 251 "ROM_DQ3" "ROM_DQ3" + U201 182 + U501 D5 +Net 252 "ROM_DQ2" "ROM_DQ2" + U501 C6 + U201 181 +Net 253 "ROM_DQ1" "ROM_DQ1" + U201 178 + U501 C5 +Net 254 "ROM_DQ0" "ROM_DQ0" + U501 B6 + U201 176 +Net 255 "ROM_A6" "ROM_A6" + U501 C4 + U201 175 +Net 256 "ROM_/CE" "ROM_/CE" + U201 172 + U501 B5 +Net 257 "ROM_A2" "ROM_A2" + U501 A5 + U201 171 +Net 258 "ROM_A4" "ROM_A4" + U201 169 + U501 B4 +Net 259 "ROM_A1" "ROM_A1" + U201 168 + U501 A4 +Net 260 "ROM_A7" "ROM_A7" + U201 167 + U501 D4 +Net 261 "ROM_A0" "ROM_A0" + U201 166 + U501 A3 +Net 262 "ROM_A3" "ROM_A3" + U501 B3 + U201 165 +Net 263 "ROM_/OE" "ROM_/OE" + U201 162 + U501 A2 +Net 264 "+2.5V" "+2.5V" + U201 69 + U321 5 + C210 1 + C215 1 + C211 1 + C322 1 + C212 1 + U201 17 + U201 121 + C213 1 + U201 89 + U201 38 + U201 142 + U201 173 + U201 193 + C214 1 +Net 265 "+1.2V" "+1.2V" + U201 192 + C302 1 + C223 1 + C224 1 + U201 174 + U201 88 + U301 4 + L301 2 + C221 1 + U201 70 + C222 1 +Net 273 "+3.3VDAC" "+3.3VDAC" + C341 1 + C342 1 + U341 9 + FB341 2 +Net 274 "/Power Supply / Misc./LX12" "LX12" + L301 1 + U301 5 +Net 275 "" "" + Q301 G + R301 2 +Net 276 "/Power Supply / Misc./LX33" "LX33" + U302 5 + L302 1 +Net 277 "" "" + C346 1 + R341 2 + R342 1 +Net 278 "" "" + U341 7 + C348 2 +Net 279 "" "" + C343 1 + U341 5 + C344 1 +Net 280 "AGND" "AGND" + C344 2 + U341 8 + C345 2 + C347 2 + R344 2 + C349 2 + R342 2 + FB342 2 + C343 2 + C341 2 + C342 2 +Net 281 "" "" + C345 1 + U341 6 +Net 282 "+BATT" "+BATT" + D511 2 + BT351 1 + U401 16 +Net 283 "DAC_/DEM" "DAC_/DEM" + U341 2 + U401 30 +Net 284 "" "" + U331 2 + R331 1 +Net 285 "" "" + C348 1 + R344 1 + R343 2 +Net 286 "" "" + U341 10 + C346 2 +Net 289 "CIC_DATA0" "CIC_DATA0" + U331 7 + C332 1 + R332 1 + U401 38 +Net 290 "CIC_DATA1" "CIC_DATA1" + U331 6 + C333 1 + U401 37 + R333 2 +Net 291 "CIC_MCLR" "CIC_MCLR" + JP401 2 + U331 4 +Net 292 "CIC_STATUS" "CIC_STATUS" + U401 36 + U331 3 +Net 293 "+1.8V" "+1.8V" + U501 D6 + C502 1 + C312 1 + U311 5 +Net 294 "" "" + R401 1 + U401 54 +Net 295 "" "" + J411 WP + U401 64 +Net 296 "/USEBATT" "/USEBATT" + JP402 2 + U401 70 +Net 297 "P1_D0" "P1_D0" + U401 76 + P404 1 +Net 298 "P_LATCH" "P_LATCH" + U401 74 + P404 3 +Net 299 "P2_CLK" "P2_CLK" + P404 5 + U401 72 +Net 300 "" "" + JP401 1 + U401 31 +Net 301 "P2_D0" "P2_D0" + P404 6 + U401 71 +Net 302 "P2.10" "P2.10" + P401 4 + R407 1 + U401 41 +Net 303 "P1_CLK" "P1_CLK" + U401 75 + P404 2 +Net 304 "MCU_SPARE" "MCU_SPARE" + P404 4 + U401 73 +Net 305 "" "" + R402 2 + D402 2 +Net 306 "TX0" "TX0" + P401 14 + U401 79 +Net 307 "TCK" "TCK" + U401 5 + P401 8 +Net 308 "EXT_TDI" "EXT_TDI" + P401 11 + U401 2 +Net 309 "" "" + U401 22 + R421 2 +Net 310 "" "" + J421 2 + R422 1 +Net 311 "" "" + D403 2 + R403 2 +Net 312 "TX3" "TX3" + U401 7 + P401 6 +Net 313 "" "" + P403 2 + U401 25 +Net 314 "" "" + U401 23 + R422 2 +Net 315 "" "" + R423 1 + R421 1 + J421 3 +Net 316 "" "" + R401 2 + D401 2 +Net 317 "USB_SWCONN" "USB_SWCONN" + U401 65 + R423 2 +Net 318 "" "" + U401 62 + J411 DT +Net 319 "/RESET" "/RESET" + P402 2 + U401 14 + R404 1 + C405 1 + P401 5 +Net 320 "RX3" "RX3" + U401 6 + P401 7 +Net 321 "/TRST" "/TRST" + U401 4 + P401 9 +Net 322 "" "" + R402 1 + U401 53 +Net 323 "" "" + R403 1 + U401 29 +Net 324 "" "" + R406 1 + U401 69 +Net 325 "RX0" "RX0" + P401 13 + U401 80 +Net 326 "EXT_TDO" "EXT_TDO" + P401 12 + U401 1 +Net 327 "" "" + U401 40 + R405 2 +Net 328 "" "" + J421 1 + U401 18 +Net 329 "TMS" "TMS" + P401 10 + U401 3 +Net 337 "" "" + C408 1 + X402 1 + U401 13 +Net 338 "" "" + U401 15 + X402 2 + C409 1 +Net 339 "" "" + C406 1 + U401 19 + X401 1 +Net 340 "" "" + X401 2 + C407 1 + U401 20 +Net 343 "/Memory/RAM_/CE" "RAM_/CE" + U511 22 + Q511 3 + R511 2 +Net 344 "" "" + Q511 2 + R512 1 + R513 1 +Net 345 "/Memory/SRAM_Vcc" "SRAM_Vcc" + D511 3 + U511 32 + C511 1 + R511 1 +} +#End diff --git a/pcb/kicad/RevE2/sd2snes.pro b/pcb/kicad/RevE2/sd2snes.pro new file mode 100644 index 0000000..8bb5643 --- /dev/null +++ b/pcb/kicad/RevE2/sd2snes.pro @@ -0,0 +1,116 @@ +update=Tue 27 Dec 2011 01:22:01 AM CET +version=1 +last_client=pcbnew +[general] +version=1 +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[eeschema] +version=1 +LibDir=../../kicad +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=50 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=libs/snescart +LibName32=libs/misc-74 +LibName33=libs/vreg +LibName34=libs/lpc1754 +LibName35=libs/sd_card +LibName36=libs/cy62148ev30 +LibName37=libs/mt45w8mw16 +LibName38=libs/cs4344 +LibName39=libs/double_sch_kcom +LibName40=libs/usb_minib +LibName41=libs/mic23250 +[pcbnew] +version=1 +PadDrlX=400 +PadDimH=660 +PadDimV=660 +BoardThickness=630 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +VEgarde=40 +DrawLar=70 +EdgeLar=40 +TxtLar=120 +MSegLar=79 +LastNetListRead=sd2snes.net +[pcbnew/libraries] +LibDir=../../kicad +LibName1=sockets +LibName2=connect +LibName3=discret +LibName4=pin_array +LibName5=divers +LibName6=libcms +LibName7=display +LibName8=valves +LibName9=led +LibName10=dip_sockets +LibName11=libs/mypackages +LibName12=libs/hai +LibName13=libs/snescart +LibName14=libs/sdcard diff --git a/pcb/kicad/RevE2/sd2snes.sch b/pcb/kicad/RevE2/sd2snes.sch new file mode 100644 index 0000000..f9fc6ea --- /dev/null +++ b/pcb/kicad/RevE2/sd2snes.sch @@ -0,0 +1,93 @@ +EESchema Schematic File Version 2 date Mon 26 Dec 2011 09:56:13 PM CET +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:snescart +LIBS:misc-74 +LIBS:vreg +LIBS:lpc1754 +LIBS:sd_card +LIBS:cy62148ev30 +LIBS:mt45w8mw16 +LIBS:cs4344 +LIBS:double_sch_kcom +LIBS:usb_minib +LIBS:mic23250 +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 6 +Title "sd2snes Mark II" +Date "26 dec 2011" +Rev "E2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Notes Line + 3650 4200 6150 4200 +Text Notes 3300 3250 0 100 ~ 0 +Changes from Rev.A / TODO:\n [x] remove FPGA from JTAG chain\n [x] remove SNES IRQ_DIR+IRQ, replace with IRQ_OE. IRQ is unidirectional cart -> console\n (replace 1gate w/ transistor)\n [x] disconnect P2.10 from FPGA, using a different GPIO for IRQ / INIT_B\n [x] add pullup to P2.10\n [ ] add JTAG pullups\n [x] add series resistor for CPU_CLK\n [x] add a jumper in PIC MCLR line to MCU\n [x] change PIC to DIP8 type for easier preprogramming\n [x] change "P1" to "P401" in pin description in silk screen\n [x] filter CIC data lines\n [x] rearrange SD card interface/LEDs on MCU\n [x] RAs for SNES signals?\n [x] reroute/add decoupling capacitors\n [x] filter SNES control signals (RD, WR, PARD, PAWR, CPU_CLK, IRQ)\n [x] replace 4Mbit SRAM with much cheaper TSOP-II type\n [x] add inverse polarity protection\n [x] separate GND plane for DAC\n [ ] separate JTAG pads for FPGA\n [x] add USE_BATT jumper\n [x] move PROG_B to P1.15 +$Sheet +S 1250 1250 1700 1250 +U 4B6E16F2 +F0 "SNES Slot" 60 +F1 "snesslot.sch" 60 +$EndSheet +Text Notes 750 7700 0 500 ~ 100 +sd2snes Mark II +$Sheet +S 1250 3300 1600 1150 +U 4BAA6ABD +F0 "Memory" 60 +F1 "memory.sch" 60 +$EndSheet +$Sheet +S 8050 1250 1600 1250 +U 4B6ED75B +F0 "MCU" 60 +F1 "mcu.sch" 60 +$EndSheet +$Sheet +S 5900 1250 1600 1250 +U 4B6EC9C3 +F0 "Power Supply / Misc." 60 +F1 "pwr_misc.sch" 60 +$EndSheet +$Sheet +S 3650 1250 1650 1250 +U 4B6E18FC +F0 "FPGA" 60 +F1 "fpga.sch" 60 +$EndSheet +$EndSCHEMATC diff --git a/pcb/kicad/RevE2/snesslot.sch b/pcb/kicad/RevE2/snesslot.sch new file mode 100644 index 0000000..6a959f8 --- /dev/null +++ b/pcb/kicad/RevE2/snesslot.sch @@ -0,0 +1,2058 @@ +EESchema Schematic File Version 2 date Mon 26 Dec 2011 09:56:13 PM CET +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:snescart +LIBS:misc-74 +LIBS:vreg +LIBS:lpc1754 +LIBS:sd_card +LIBS:cy62148ev30 +LIBS:mt45w8mw16 +LIBS:cs4344 +LIBS:double_sch_kcom +LIBS:usb_minib +LIBS:mic23250 +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11700 +encoding utf-8 +Sheet 2 6 +Title "sd2snes Mark II" +Date "26 dec 2011" +Rev "E2" +Comp "Maximilian Rehkopf" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 8300 7600 +Wire Wire Line + 8300 7600 8300 7700 +Wire Wire Line + 15450 4700 15600 4700 +Wire Wire Line + 15450 4600 15600 4600 +Wire Wire Line + 15450 4500 15600 4500 +Wire Wire Line + 15450 4400 15600 4400 +Wire Wire Line + 15450 4300 15600 4300 +Wire Wire Line + 15450 4200 15600 4200 +Wire Wire Line + 15450 4100 15600 4100 +Wire Wire Line + 15450 4000 15600 4000 +Connection ~ 3600 5500 +Wire Wire Line + 3600 5600 3600 5500 +Connection ~ 3450 4300 +Wire Wire Line + 3450 5000 3450 4300 +Connection ~ 9650 5900 +Wire Wire Line + 9650 5900 9650 7050 +Wire Wire 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Part="1" +AR Path="/4B6E16F2/4D95CDD4" Ref="RA104" Part="1" +F 0 "RA104" H 12400 4650 40 0000 C CNN +F 1 "FB" H 12400 4950 40 0000 C CNN + 1 12400 4750 + 1 0 0 -1 +$EndComp +$Comp +L R_PACK4 RA103 +U 1 1 4D95CDCD +P 12400 4350 +F 0 "RA103" H 12400 4800 40 0000 C CNN +F 1 "FB" H 12400 4550 40 0000 C CNN + 1 12400 4350 + 1 0 0 -1 +$EndComp +$Comp +L +5VL #PWR17 +U 1 1 4D4BC910 +P 8300 2900 +F 0 "#PWR17" H 8300 3030 20 0001 C CNN +F 1 "+5VL" H 8300 3000 30 0000 C CNN + 1 8300 2900 + 1 0 0 -1 +$EndComp +$Comp +L C C128 +U 1 1 4D115250 +P 3750 5200 +F 0 "C128" V 3800 5350 50 0000 L CNN +F 1 "10p" V 3650 5300 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3750 5200 60 0001 C CNN + 1 3750 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C127 +U 1 1 4D11524F +P 3450 5200 +F 0 "C127" V 3500 5350 50 0000 L CNN +F 1 "10p" V 3350 5300 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 3450 5200 60 0001 C CNN + 1 3450 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C126 +U 1 1 4D11524E +P 9650 7250 +F 0 "C126" V 9700 7400 50 0000 L CNN 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0 "C121" V 13050 5350 50 0000 L CNN +F 1 "10p" V 12900 5300 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 13000 5200 60 0001 C CNN + 1 13000 5200 + 1 0 0 -1 +$EndComp +Entry Wire Line + 5750 6600 5850 6700 +Text GLabel 7750 8250 2 50 Input ~ 0 +SNES_IRQ_EN +$Comp +L R R103 +U 1 1 4C7EAF13 +P 7300 8250 +F 0 "R103" V 7380 8250 50 0000 C CNN +F 1 "4k7" V 7300 8250 50 0000 C CNN + 1 7300 8250 + 0 1 1 0 +$EndComp +$Comp +L R R102 +U 1 1 4C7EAEBF +P 6850 8600 +F 0 "R102" V 6930 8600 50 0000 C CNN +F 1 "100k" V 6850 8600 50 0000 C CNN + 1 6850 8600 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q101 +U 1 1 4C7EAD01 +P 6500 8850 +F 0 "Q101" H 6500 8700 50 0000 R CNN +F 1 "2N2222A" H 6500 9000 50 0000 R CNN + 1 6500 8850 + 0 -1 1 0 +$EndComp +NoConn ~ 9300 5800 +NoConn ~ 9300 6000 +Text Notes 13800 9950 0 250 ~ 50 +SNES bus,\nlevel shift +$Comp +L GND #PWR05 +U 1 1 4BAD42F7 +P 11800 10300 +F 0 "#PWR05" H 11800 10300 30 0001 C CNN +F 1 "GND" H 11800 10230 30 0001 C CNN + 1 11800 10300 + 1 0 0 -1 +$EndComp +$Comp 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9850 60 0001 C CNN + 1 11200 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C104 +U 1 1 4BFB1190 +P 10950 9850 +F 0 "C104" H 11000 9950 50 0000 L CNN +F 1 "100n" H 11000 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10950 9850 60 0001 C CNN + 1 10950 9850 + 1 0 0 -1 +$EndComp +Text GLabel 6500 6600 0 50 3State ~ 0 +SNES_/RESET +Text GLabel 1300 8400 0 50 Output ~ 0 +SNES_A6 +Text GLabel 1300 8300 0 50 Output ~ 0 +SNES_A17 +Text GLabel 1300 8200 0 50 Output ~ 0 +SNES_A5 +Text GLabel 1300 8100 0 50 Output ~ 0 +SNES_A18 +Text GLabel 1300 8000 0 50 Output ~ 0 +SNES_A4 +Text GLabel 1300 7900 0 50 Output ~ 0 +SNES_A19 +Text GLabel 1300 7800 0 50 Output ~ 0 +SNES_A3 +Text GLabel 1300 7700 0 50 Output ~ 0 +SNES_A20 +Text GLabel 1300 7400 0 50 Output ~ 0 +SNES_A2 +Text GLabel 1300 7300 0 50 Output ~ 0 +SNES_A21 +Text GLabel 1300 7200 0 50 Output ~ 0 +SNES_A1 +Text GLabel 1300 7100 0 50 Output ~ 0 +SNES_A22 +Text GLabel 1300 7000 0 50 Output ~ 0 +SNES_A0 +Text GLabel 1300 6900 0 50 Output ~ 0 +SNES_A23 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10300 6800 2 50 Input ~ 0 +AUDIO_R +Text GLabel 10300 6700 2 50 Input ~ 0 +AUDIO_L +Text GLabel 10300 6500 2 50 Output ~ 0 +CIC_RESET +Text GLabel 10300 6400 2 50 Output ~ 0 +CIC_CLK +Text GLabel 10300 6300 2 50 BiDi ~ 0 +EXT_CIC_DATA0 +Text GLabel 10300 6200 2 50 BiDi ~ 0 +EXT_CIC_DATA1 +$Comp +L GND #PWR06 +U 1 1 4BAEAB97 +P 3200 7550 +F 0 "#PWR06" H 3200 7550 30 0001 C CNN +F 1 "GND" H 3200 7480 30 0001 C CNN + 1 3200 7550 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 4BAEAB8D +P 3200 8550 +F 0 "#PWR07" H 3200 8550 30 0001 C CNN +F 1 "GND" H 3200 8480 30 0001 C CNN + 1 3200 8550 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR08 +U 1 1 4BAEAB85 +P 3200 3850 +F 0 "#PWR08" H 3200 3850 30 0001 C CNN +F 1 "GND" H 3200 3780 30 0001 C CNN + 1 3200 3850 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR09 +U 1 1 4BAEAB7E +P 3100 4950 +F 0 "#PWR09" H 3100 4950 30 0001 C CNN +F 1 "GND" H 3100 4880 30 0001 C CNN + 1 3100 4950 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR010 +U 1 1 4BAEAB58 +P 13200 3850 +F 0 "#PWR010" H 13200 3850 30 0001 C CNN +F 1 "GND" H 13200 3780 30 0001 C CNN + 1 13200 3850 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR011 +U 1 1 4BAEAAFB +P 15100 3850 +F 0 "#PWR011" H 15100 3850 30 0001 C CNN +F 1 "GND" H 15100 3780 30 0001 C CNN + 1 15100 3850 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR012 +U 1 1 4BAEAAF9 +P 1300 8550 +F 0 "#PWR012" H 1300 8550 30 0001 C CNN +F 1 "GND" H 1300 8480 30 0001 C CNN + 1 1300 8550 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR013 +U 1 1 4BAEAAF5 +P 1300 4850 +F 0 "#PWR013" H 1300 4850 30 0001 C CNN +F 1 "GND" H 1300 4780 30 0001 C CNN + 1 1300 4850 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR014 +U 1 1 4BAEAAEF +P 1300 7550 +F 0 "#PWR014" H 1300 7550 30 0001 C CNN +F 1 "GND" H 1300 7480 30 0001 C CNN + 1 1300 7550 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR015 +U 1 1 4BAEAAE9 +P 1300 3850 +F 0 "#PWR015" H 1300 3850 30 0001 C CNN +F 1 "GND" H 1300 3780 30 0001 C CNN + 1 1300 3850 + -1 0 0 -1 +$EndComp +Text GLabel 1300 3000 0 50 Output ~ 0 +SNES_A16 +Text GLabel 1300 3100 0 50 Output ~ 0 +SNES_A7 +Text GLabel 1300 4700 0 50 Output ~ 0 +SNES_SYS_CLK +Text GLabel 1300 4600 0 50 Output ~ 0 +SNES_REFRESH +Text GLabel 1300 4500 0 50 Output ~ 0 +SNES_PA7 +Text GLabel 1300 4400 0 50 Output ~ 0 +SNES_PA6 +Text GLabel 1300 4300 0 50 Output ~ 0 +SNES_/PAWR +Text GLabel 1300 4200 0 50 Output ~ 0 +SNES_/PARD +Text GLabel 1300 4100 0 50 Output ~ 0 +SNES_A11 +Text GLabel 1300 4000 0 50 Output ~ 0 +SNES_A12 +Text GLabel 1300 3700 0 50 Output ~ 0 +SNES_A10 +Text GLabel 1300 3600 0 50 Output ~ 0 +SNES_A13 +Text GLabel 1300 3500 0 50 Output ~ 0 +SNES_A9 +Text GLabel 1300 3400 0 50 Output ~ 0 +SNES_A14 +Text GLabel 1300 3300 0 50 Output ~ 0 +SNES_A8 +Text GLabel 1300 3200 0 50 Output ~ 0 +SNES_A15 +$Comp +L GND #PWR016 +U 1 1 4BAE51D9 +P 6150 7700 +F 0 "#PWR016" H 6150 7700 30 0001 C CNN +F 1 "GND" H 6150 7630 30 0001 C CNN + 1 6150 7700 + 1 0 0 -1 +$EndComp +$Comp +L R R101 +U 1 1 4BAE51CA +P 6150 7250 +F 0 "R101" V 6230 7250 50 0000 C CNN +F 1 "270" V 6150 7250 50 0000 C CNN +F 2 "SM0805_FIXEDMASK" H 6150 7250 60 0001 C CNN + 1 6150 7250 + 1 0 0 1 +$EndComp +Text Label 11550 3000 0 50 ~ 0 +SNES_EXT_PA4 +Text Label 11550 3100 0 50 ~ 0 +SNES_EXT_PA5 +Text Label 11550 3200 0 50 ~ 0 +SNES_EXT_PA2 +Text Label 11550 3300 0 50 ~ 0 +SNES_EXT_PA3 +Text Label 11550 3400 0 50 ~ 0 +SNES_EXT_PA0 +Text Label 11550 3500 0 50 ~ 0 +SNES_EXT_PA1 +Text Label 11550 3700 0 50 ~ 0 +SNES_EXT_CPU_CLK +Text Label 11550 3600 0 50 ~ 0 +SNES_EXT_/WR +Text Label 11550 4000 0 50 ~ 0 +SNES_EXT_D3 +Text Label 11550 4100 0 50 ~ 0 +SNES_EXT_D7 +Text Label 11550 4200 0 50 ~ 0 +SNES_EXT_D2 +Text Label 11550 4300 0 50 ~ 0 +SNES_EXT_D6 +Text Label 11550 4400 0 50 ~ 0 +SNES_EXT_D1 +Text Label 11550 4500 0 50 ~ 0 +SNES_EXT_D5 +Text Label 11550 4600 0 50 ~ 0 +SNES_EXT_D0 +Text Label 11550 4700 0 50 ~ 0 +SNES_EXT_D4 +Text Label 4400 6700 0 50 ~ 0 +SNES_EXT_/RD +Text Label 4400 6800 0 50 ~ 0 +SNES_EXT_/ROMSEL +Text Label 4400 6900 0 50 ~ 0 +SNES_EXT_A23 +Text Label 4400 7000 0 50 ~ 0 +SNES_EXT_A0 +Text Label 4400 7100 0 50 ~ 0 +SNES_EXT_A22 +Text Label 4400 7200 0 50 ~ 0 +SNES_EXT_A1 +Text Label 4400 7300 0 50 ~ 0 +SNES_EXT_A21 +Text Label 4400 7600 0 50 ~ 0 +SNES_EXT_A2 +Text Label 4400 7700 0 50 ~ 0 +SNES_EXT_A20 +Text Label 4400 7800 0 50 ~ 0 +SNES_EXT_A3 +Text Label 4400 7900 0 50 ~ 0 +SNES_EXT_A19 +Text Label 4400 8000 0 50 ~ 0 +SNES_EXT_A4 +Text Label 4400 8100 0 50 ~ 0 +SNES_EXT_A18 +Text Label 4400 8200 0 50 ~ 0 +SNES_EXT_A5 +Text Label 4400 8300 0 50 ~ 0 +SNES_EXT_A17 +Text Label 4400 2900 0 50 ~ 0 +SNES_EXT_A6 +Text Label 4400 3000 0 50 ~ 0 +SNES_EXT_A16 +Text Label 4400 3100 0 50 ~ 0 +SNES_EXT_A7 +Text Label 4400 3200 0 50 ~ 0 +SNES_EXT_A15 +Text Label 4400 3300 0 50 ~ 0 +SNES_EXT_A8 +Text Label 4400 3400 0 50 ~ 0 +SNES_EXT_A14 +Text Label 4400 3500 0 50 ~ 0 +SNES_EXT_A9 +Text Label 4400 3600 0 50 ~ 0 +SNES_EXT_A13 +Text Label 4400 3900 0 50 ~ 0 +SNES_EXT_A10 +Text Label 4400 4000 0 50 ~ 0 +SNES_EXT_A12 +Text Label 4400 4100 0 50 ~ 0 +SNES_EXT_A11 +Text Label 4400 4200 0 50 ~ 0 +SNES_EXT_/PARD +Text Label 4400 4300 0 50 ~ 0 +SNES_EXT_/PAWR +Text Label 4400 4400 0 50 ~ 0 +SNES_EXT_PA6 +Text Label 4400 4500 0 50 ~ 0 +SNES_EXT_PA7 +Text Label 4400 4600 0 50 ~ 0 +SNES_EXT_REFRESH +Text Label 4400 4850 0 50 ~ 0 +SNES_EXT_SYS_CLK +Entry Wire Line + 11450 4600 11550 4700 +Entry Wire Line + 11450 4500 11550 4600 +Entry Wire Line + 11450 4400 11550 4500 +Entry Wire Line + 11450 4300 11550 4400 +Entry Wire Line + 11450 4200 11550 4300 +Entry Wire Line + 11450 4100 11550 4200 +Entry Wire Line + 11450 4000 11550 4100 +Entry Wire Line + 11450 3900 11550 4000 +Entry Wire Line + 11450 3600 11550 3700 +Entry Wire Line + 11450 3500 11550 3600 +Entry Wire Line + 11450 3400 11550 3500 +Entry Wire Line + 11450 3300 11550 3400 +Entry Wire Line + 11450 3200 11550 3300 +Entry Wire Line + 11450 3100 11550 3200 +Entry Wire Line + 11450 3000 11550 3100 +Entry Wire Line + 11450 2900 11550 3000 +Text Label 5850 6400 0 50 ~ 0 +SNES_EXT_/IRQ +Entry Wire Line + 5750 6300 5850 6400 +Text Label 10100 5900 0 50 ~ 0 +SNES_EXT_REFRESH +Text Label 10100 5600 0 50 ~ 0 +SNES_EXT_/PAWR +Text Label 10100 5500 0 50 ~ 0 +SNES_EXT_/PARD +Entry Wire Line + 10750 5900 10850 6000 +Entry Wire Line + 10750 5600 10850 5700 +Entry Wire Line + 10750 5500 10850 5600 +Entry Bus Bus + 11350 2650 11450 2750 +Entry Bus Bus + 10750 2650 10850 2750 +Entry Bus Bus + 5150 2750 5250 2650 +Entry Bus Bus + 5750 2750 5850 2650 +Text Label 10100 5300 0 50 ~ 0 +SNES_EXT_PA7 +Text Label 10100 5200 0 50 ~ 0 +SNES_EXT_PA6 +Text Label 10100 5100 0 50 ~ 0 +SNES_EXT_PA5 +Text Label 10100 5000 0 50 ~ 0 +SNES_EXT_PA4 +Text Label 10100 4900 0 50 ~ 0 +SNES_EXT_PA3 +Text Label 10100 4800 0 50 ~ 0 +SNES_EXT_PA2 +Text Label 10100 4700 0 50 ~ 0 +SNES_EXT_PA1 +Text Label 10100 4600 0 50 ~ 0 +SNES_EXT_PA0 +Text Label 10100 4400 0 50 ~ 0 +SNES_EXT_D7 +Text Label 10100 4300 0 50 ~ 0 +SNES_EXT_D6 +Text Label 10100 4200 0 50 ~ 0 +SNES_EXT_D5 +Text Label 10100 4100 0 50 ~ 0 +SNES_EXT_D4 +Text Label 10100 4000 0 50 ~ 0 +SNES_EXT_D3 +Text Label 10100 3900 0 50 ~ 0 +SNES_EXT_D2 +Text Label 10100 3800 0 50 ~ 0 +SNES_EXT_D1 +Text Label 10100 3700 0 50 ~ 0 +SNES_EXT_D0 +Entry Wire Line + 10750 5300 10850 5400 +Entry Wire Line + 10750 5200 10850 5300 +Entry Wire Line + 10750 5100 10850 5200 +Entry Wire Line + 10750 5000 10850 5100 +Entry Wire Line + 10750 4900 10850 5000 +Entry Wire Line + 10750 4800 10850 4900 +Entry Wire Line + 10750 4700 10850 4800 +Entry Wire Line + 10750 4600 10850 4700 +Entry Wire Line + 10750 4400 10850 4500 +Entry Wire Line + 10750 4300 10850 4400 +Entry Wire Line + 10750 4200 10850 4300 +Entry Wire Line + 10750 4100 10850 4200 +Entry Wire Line + 10750 4000 10850 4100 +Entry Wire Line + 10750 3900 10850 4000 +Entry Wire Line + 10750 3800 10850 3900 +Entry Wire Line + 10750 3700 10850 3800 +Entry Wire Line + 5050 2900 5150 3000 +Entry Wire Line + 5050 8300 5150 8400 +Entry Wire Line + 5050 8200 5150 8300 +Entry Wire Line + 5050 8100 5150 8200 +Entry Wire Line + 5050 8000 5150 8100 +Entry Wire Line + 5050 7900 5150 8000 +Entry Wire Line + 5050 7800 5150 7900 +Entry Wire Line + 5050 7700 5150 7800 +Entry Wire Line + 5050 7600 5150 7700 +Entry Wire Line + 5050 7300 5150 7400 +Entry Wire Line + 5050 7200 5150 7300 +Entry Wire Line + 5050 7100 5150 7200 +Entry Wire Line + 5050 7000 5150 7100 +Entry Wire Line + 5050 6900 5150 7000 +Entry Wire Line + 5050 6800 5150 6900 +Entry Wire Line + 5050 6700 5150 6800 +Entry Wire Line + 5050 4850 5150 4950 +Entry Wire Line + 5050 4600 5150 4700 +Entry Wire Line + 5050 4500 5150 4600 +Entry Wire Line + 5050 4400 5150 4500 +Entry Wire Line + 5050 4300 5150 4400 +Entry Wire Line + 5050 4200 5150 4300 +Entry Wire Line + 5050 4100 5150 4200 +Entry Wire Line + 5050 4000 5150 4100 +Entry Wire Line + 5050 3900 5150 4000 +Entry Wire Line + 5050 3600 5150 3700 +Entry Wire Line + 5050 3500 5150 3600 +Entry Wire Line + 5050 3400 5150 3500 +Entry Wire Line + 5050 3300 5150 3400 +Entry Wire Line + 5050 3200 5150 3300 +Entry Wire Line + 5050 3100 5150 3200 +Entry Wire Line + 5050 3000 5150 3100 +Entry Wire Line + 5750 5300 5850 5400 +Entry Wire Line + 5750 5200 5850 5300 +Entry Wire Line + 5750 5100 5850 5200 +Entry Wire Line + 5750 5000 5850 5100 +Entry Wire Line + 5750 4900 5850 5000 +Entry Wire Line + 5750 4800 5850 4900 +Entry Wire Line + 5750 4700 5850 4800 +Entry Wire Line + 5750 4600 5850 4700 +Entry Wire Line + 5750 4500 5850 4600 +Entry Wire Line + 5750 4400 5850 4500 +Entry Wire Line + 5750 4300 5850 4400 +Entry Wire Line + 5750 4200 5850 4300 +Entry Wire Line + 5750 4100 5850 4200 +Entry Wire Line + 5750 4000 5850 4100 +Entry Wire Line + 5750 3900 5850 4000 +Entry Wire Line + 5750 3800 5850 3900 +Entry Wire Line + 5750 3700 5850 3800 +Entry Wire Line + 5750 3600 5850 3700 +Entry Wire Line + 5750 5400 5850 5500 +Entry Wire Line + 5750 5500 5850 5600 +Entry Wire Line + 5750 5600 5850 5700 +Entry Wire Line + 5750 5700 5850 5800 +Entry Wire Line + 5750 5800 5850 5900 +Entry Wire Line + 5750 5900 5850 6000 +Entry Wire Line + 5750 6100 5850 6200 +Entry Wire Line + 5750 6200 5850 6300 +Entry Wire Line + 5750 6400 5850 6500 +Entry Wire Line + 5750 6700 5850 6800 +Text Label 5850 6800 0 50 ~ 0 +SNES_EXT_SYS_CLK +Text Label 6500 6700 0 50 ~ 0 +SNES_EXT_CPU_CLK +Text Label 6500 6600 0 50 ~ 0 +SNES_/RESET +Text Label 5850 6500 0 50 ~ 0 +SNES_EXT_/ROMSEL +Text Label 5850 6300 0 50 ~ 0 +SNES_EXT_/WR +Text Label 5850 6200 0 50 ~ 0 +SNES_EXT_/RD +Text Label 5850 6000 0 50 ~ 0 +SNES_EXT_A23 +Text Label 5850 5900 0 50 ~ 0 +SNES_EXT_A22 +Text Label 5850 5800 0 50 ~ 0 +SNES_EXT_A21 +Text Label 5850 5700 0 50 ~ 0 +SNES_EXT_A20 +Text Label 5850 5600 0 50 ~ 0 +SNES_EXT_A19 +Text Label 5850 5500 0 50 ~ 0 +SNES_EXT_A18 +Text Label 5850 5400 0 50 ~ 0 +SNES_EXT_A17 +Text Label 5850 5300 0 50 ~ 0 +SNES_EXT_A16 +Text Label 5850 5200 0 50 ~ 0 +SNES_EXT_A15 +Text Label 5850 5100 0 50 ~ 0 +SNES_EXT_A14 +Text Label 5850 5000 0 50 ~ 0 +SNES_EXT_A13 +Text Label 5850 4900 0 50 ~ 0 +SNES_EXT_A12 +Text Label 5850 4800 0 50 ~ 0 +SNES_EXT_A11 +Text Label 5850 4700 0 50 ~ 0 +SNES_EXT_A10 +Text Label 5850 4600 0 50 ~ 0 +SNES_EXT_A9 +Text Label 5850 4500 0 50 ~ 0 +SNES_EXT_A8 +Text Label 5850 4400 0 50 ~ 0 +SNES_EXT_A7 +Text Label 5850 4300 0 50 ~ 0 +SNES_EXT_A6 +Text Label 5850 4200 0 50 ~ 0 +SNES_EXT_A5 +Text Label 5850 4100 0 50 ~ 0 +SNES_EXT_A4 +Text Label 5850 4000 0 50 ~ 0 +SNES_EXT_A3 +Text Label 5850 3900 0 50 ~ 0 +SNES_EXT_A2 +Text Label 5850 3800 0 50 ~ 0 +SNES_EXT_A1 +Text Label 5850 3700 0 50 ~ 0 +SNES_EXT_A0 +$Comp +L GND #PWR017 +U 1 1 4BAD4383 +P 7550 9850 +F 0 "#PWR017" H 7550 9850 30 0001 C CNN +F 1 "GND" H 7550 9780 30 0001 C CNN + 1 7550 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C116 +U 1 1 4BAD42E2 +P 13050 9850 +F 0 "C116" H 13100 9950 50 0000 L CNN +F 1 "100n" H 13100 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 13050 9850 60 0001 C CNN + 1 13050 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C115 +U 1 1 4BAD42E0 +P 12800 9850 +F 0 "C115" H 12850 9950 50 0000 L CNN +F 1 "100n" H 12850 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 12800 9850 60 0001 C CNN + 1 12800 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C114 +U 1 1 4BAD42DF +P 12550 9850 +F 0 "C114" H 12600 9950 50 0000 L CNN +F 1 "100n" H 12600 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 12550 9850 60 0001 C CNN + 1 12550 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C103 +U 1 1 4BAD42DA +P 10700 9850 +F 0 "C103" H 10750 9950 50 0000 L CNN +F 1 "100n" H 10750 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10700 9850 60 0001 C CNN + 1 10700 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C102 +U 1 1 4BAD42D8 +P 10450 9850 +F 0 "C102" H 10500 9950 50 0000 L CNN +F 1 "100n" H 10500 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10450 9850 60 0001 C CNN + 1 10450 9850 + 1 0 0 -1 +$EndComp +$Comp +L C C101 +U 1 1 4BAD42D5 +P 10200 9850 +F 0 "C101" H 10250 9950 50 0000 L CNN +F 1 "100n" H 10250 9750 50 0000 L CNN +F 2 "SM0805_FIXEDMASK" H 10200 9850 60 0001 C CNN + 1 10200 9850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR018 +U 1 1 4BAD42C1 +P 10200 10300 +F 0 "#PWR018" H 10200 10300 30 0001 C CNN +F 1 "GND" H 10200 10230 30 0001 C CNN + 1 10200 10300 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR019 +U 1 1 4BAD42B7 +P 11800 9400 +F 0 "#PWR019" H 11800 9490 20 0001 C CNN +F 1 "+5V" H 11800 9490 30 0000 C CNN + 1 11800 9400 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR020 +U 1 1 4BAD42B3 +P 10200 9400 +F 0 "#PWR020" H 10200 9360 30 0001 C CNN +F 1 "+3.3V" H 10200 9510 30 0000 C CNN + 1 10200 9400 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR021 +U 1 1 4B6ED29E +P 2150 2200 +F 0 "#PWR021" H 2150 2160 30 0001 C CNN +F 1 "+3.3V" H 2150 2310 30 0000 C CNN + 1 2150 2200 + -1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR022 +U 1 1 4B6ED291 +P 2150 5900 +F 0 "#PWR022" H 2150 5860 30 0001 C CNN +F 1 "+3.3V" H 2150 6010 30 0000 C CNN + 1 2150 5900 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR023 +U 1 1 4B6E9E3A +P 14250 2200 +F 0 "#PWR023" H 14250 2160 50 0001 C CNN +F 1 "+3.3V" H 14100 2250 50 0000 C CNN + 1 14250 2200 + -1 0 0 -1 +$EndComp +$Comp +L +5V #PWR024 +U 1 1 4B6E9DCF +P 2450 5900 +F 0 "#PWR024" H 2450 5990 20 0001 C CNN +F 1 "+5V" H 2450 5990 30 0000 C CNN + 1 2450 5900 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR025 +U 1 1 4B6E9DCB +P 2450 2200 +F 0 "#PWR025" H 2450 2290 20 0001 C CNN +F 1 "+5V" H 2450 2290 30 0000 C CNN + 1 2450 2200 + -1 0 0 -1 +$EndComp +$Comp +L +5V #PWR026 +U 1 1 4B6E9DC6 +P 13950 2200 +F 0 "#PWR026" H 13950 2290 50 0001 C CNN +F 1 "+5V" H 13850 2250 50 0000 C CNN + 1 13950 2200 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR027 +U 1 1 4B6E9C12 +P 14100 5600 +F 0 "#PWR027" H 14100 5600 30 0001 C CNN +F 1 "GND" H 14100 5530 30 0001 C CNN + 1 14100 5600 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR028 +U 1 1 4B6E9C04 +P 2300 5600 +F 0 "#PWR028" H 2300 5600 30 0001 C CNN +F 1 "GND" H 2300 5530 30 0001 C CNN + 1 2300 5600 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR029 +U 1 1 4B6E9BA6 +P 8300 7700 +F 0 "#PWR029" H 8300 7700 30 0001 C CNN +F 1 "GND" H 8300 7630 30 0001 C CNN + 1 8300 7700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR030 +U 1 1 4B6E9B44 +P 2300 9300 +F 0 "#PWR030" H 2300 9300 30 0001 C CNN +F 1 "GND" H 2300 9230 30 0001 C CNN + 1 2300 9300 + 1 0 0 -1 +$EndComp +$Comp +L SNESCART_EXT J101 +U 1 1 4B6E1766 +P 8300 5200 +F 0 "J101" H 7850 7100 60 0000 C CNN +F 1 "SNESCART_EXT" H 8800 3200 60 0000 C CNN +F 2 "SNESCART_EXT" H 8300 5200 60 0001 C CNN + 1 8300 5200 + 1 0 0 -1 +$EndComp +$Comp +L 74ALVC164245 U103 +U 1 1 4B6E1748 +P 2300 3900 +F 0 "U103" H 2300 4000 60 0000 C CNN +F 1 "74ALVC164245DGG" H 2300 3900 60 0000 C CNN +F 2 "TSSOP48" H 2300 3900 60 0001 C CNN + 1 2300 3900 + 1 0 0 -1 +$EndComp +$Comp +L 74ALVC164245 U102 +U 1 1 4B6E1744 +P 2300 7600 +F 0 "U102" H 2300 7700 60 0000 C CNN +F 1 "74ALVC164245DGG" H 2300 7600 60 0000 C CNN +F 2 "TSSOP48" H 2300 7600 60 0001 C CNN + 1 2300 7600 + 1 0 0 -1 +$EndComp +$Comp +L 74ALVC164245 U101 +U 1 1 4B6E1740 +P 14100 3900 +F 0 "U101" H 14100 4000 60 0000 C CNN +F 1 "74ALVC164245DGG" H 14100 3900 60 0000 C CNN +F 2 "TSSOP48" H 14100 3900 60 0001 C CNN + 1 14100 3900 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/pcb/kicad/libs/mypackages.mod b/pcb/kicad/libs/mypackages.mod index 28caf95..bab330d 100644 --- a/pcb/kicad/libs/mypackages.mod +++ b/pcb/kicad/libs/mypackages.mod @@ -1,4 +1,4 @@ -PCBNEW-LibModule-V1 Wed 14 Sep 2011 12:39:55 AM CEST +PCBNEW-LibModule-V1 Tue 27 Dec 2011 12:29:40 AM CET # encoding utf-8 $INDEX BT_KEYSTONE_1059_20MM @@ -7,11 +7,14 @@ DIP-36 HC49US LED-3MM-FIXED LQFP80-.5 +L_4.2X4.2 PAD_1x1mm PQFP208_ALTPADS QFN10-2x2 QFN10-2x2_LONGPADS R_PACK_0804 +R_PACK_0804_LONGPADS +R_PACK_1206 SM0805_FIXEDMASK SM1210L SM1210L_NEW @@ -23,7 +26,9 @@ TSOP40 TSOPII-32 TSOPII-44 TSSOP10 +TSSOP10_LONGPADS TSSOP48 +TSSOP48_LONGPADS USB-MINIB-THT VFBGA36 VFBGA48 @@ -4107,41 +4112,6 @@ Of 0.000000 0.000000 0.000000 Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SM1210L_NEW -$MODULE LED-3MM-FIXED -Po 0 0 0 15 4D251EA9 00000000 ~~ -Li LED-3MM-FIXED -Cd LED 3mm - Lead pitch 100mil (2,54mm) -Kw LED led 3mm 3MM 100mil 2,54mm -Sc 00000000 -AR /4B6ED75B/4C0DA78D -Op 0 0 0 -At VIRTUAL -T0 -300 -2125 320 320 0 70 N V 21 N"D403" -T1 25 3575 320 320 2700 70 N V 21 N"LED_2mA_1.7V,_red" -DS 669 669 669 394 80 21 -DS 669 -669 669 -394 80 21 -DA 0 0 669 669 2700 80 21 -$PAD -Sh "1" C 660 660 0 0 0 -Dr 400 0 0 -At STD N 00E8FFFF -Ne 1 "+3.3V" -Po -500 0 -$EndPAD -$PAD -Sh "2" C 660 660 0 0 0 -Dr 400 0 0 -At STD N 00E8FFFF -Ne 2 "N-000262" -Po 500 0 -$EndPAD -$SHAPE3D -Na "libs/led3_vertical_red.wrl" -Sc 1.000000 1.000000 1.000000 -Of 0.000000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$EndMODULE LED-3MM-FIXED $MODULE HC49US Po 0 0 0 15 4D2590A9 00000000 ~~ Li HC49US @@ -5668,4 +5638,638 @@ Ne 33 "N-000035" Po -3828 1870 $EndPAD $EndMODULE TSOP40 +$MODULE R_PACK_1206 +Po 0 0 0 15 4EF2E0E8 00000000 ~~ +Li R_PACK_1206 +Sc 00000000 +AR R_PACK_1206 +Op 0 0 0 +T0 0 0 600 600 0 120 N V 21 N "R_PACK_1206" +T1 0 0 600 600 0 120 N V 21 N "VAL**" +DS -866 -827 866 -827 79 21 +DS 866 -827 866 827 79 21 +DS 866 827 -866 827 79 21 +DS -866 827 -866 -827 79 21 +$PAD +Sh "1" R 248 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -510 384 +$EndPAD +$PAD +Sh "2" R 173 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -157 384 +$EndPAD +$PAD +Sh "3" R 173 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 157 384 +$EndPAD +$PAD +Sh "4" R 248 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 510 384 +$EndPAD +$PAD +Sh "5" R 248 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 510 -384 +$EndPAD +$PAD +Sh "6" R 173 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 157 -384 +$EndPAD +$PAD +Sh "7" R 173 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -157 -384 +$EndPAD +$PAD +Sh "8" R 248 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -510 -384 +$EndPAD +$EndMODULE R_PACK_1206 +$MODULE R_PACK_0804_LONGPADS +Po 0 0 0 15 4EF2E2A7 00000000 ~~ +Li R_PACK_0804_LONGPADS +Sc 00000000 +AR +Op 0 0 0 +T0 0 0 320 320 0 70 N V 21 N "R_PACK_0804" +T1 0 0 320 320 0 70 N V 21 N "VAL**" +DS 551 591 551 -591 79 21 +DS -551 -591 -551 591 79 21 +DS -551 -591 551 -591 79 21 +DS 551 591 -551 591 79 21 +$PAD +Sh "7" R 118 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 -276 +$EndPAD +$PAD +Sh "6" R 118 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 -276 +$EndPAD +$PAD +Sh "2" R 118 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 276 +$EndPAD +$PAD +Sh "3" R 118 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 276 +$EndPAD +$PAD +Sh "8" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -335 -276 +$EndPAD +$PAD +Sh "5" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 335 -276 +$EndPAD +$PAD +Sh "4" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 335 276 +$EndPAD +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -335 276 +$EndPAD +$EndMODULE R_PACK_0804_LONGPADS +$MODULE TSSOP10_LONGPADS +Po 0 0 0 15 4EF2E58B 00000000 ~~ +Li TSSOP10_LONGPADS +Sc 00000000 +AR +Op 0 0 0 +T0 0 0 600 600 0 120 N V 21 N "Test" +T1 0 0 600 600 0 120 N V 21 N "VAL**" +DC -394 394 -315 394 60 21 +DS -590 -590 590 -590 60 21 +DS 590 -590 590 590 60 21 +DS -590 590 590 590 60 21 +DS -590 -590 -590 590 60 21 +$PAD +Sh "1" R 118 551 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -393 965 +$EndPAD +$PAD +Sh "2" R 118 551 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 965 +$EndPAD +$PAD +Sh "3" R 118 551 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 965 +$EndPAD +$PAD +Sh "4" R 118 551 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 965 +$EndPAD +$PAD +Sh "5" R 118 551 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 965 +$EndPAD +$PAD +Sh "6" R 118 551 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 -965 +$EndPAD +$PAD +Sh "7" R 118 551 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -965 +$EndPAD +$PAD +Sh "8" R 118 551 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -965 +$EndPAD +$PAD +Sh "9" R 118 551 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 -965 +$EndPAD +$PAD +Sh "10" R 118 551 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -393 -965 +$EndPAD +$EndMODULE TSSOP10_LONGPADS +$MODULE TSSOP48_LONGPADS +Po 0 0 0 15 4B6E17E6 00000000 ~~ +Li TSSOP48_LONGPADS +Sc 00000000 +AR +Op 0 0 0 +T0 0 -551 600 600 0 120 N V 21 N "Test" +T1 0 630 600 600 0 120 N V 21 N "VAL**" +DC -2205 945 -2087 945 40 21 +DS -2460 -1200 2460 -1200 47 21 +DS 2460 -1200 2460 1200 47 21 +DS -2460 1200 2460 1200 47 21 +DS -2460 -1200 -2460 1200 47 21 +$PAD +Sh "1" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2263 1614 +$EndPAD +$PAD +Sh "2" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2066 1614 +$EndPAD +$PAD +Sh "3" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1870 1614 +$EndPAD +$PAD +Sh "4" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1673 1614 +$EndPAD +$PAD +Sh "5" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1476 1614 +$EndPAD +$PAD +Sh "6" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1279 1614 +$EndPAD +$PAD +Sh "7" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1082 1614 +$EndPAD +$PAD +Sh "8" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -885 1614 +$EndPAD +$PAD +Sh "9" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 1614 +$EndPAD +$PAD +Sh "10" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -492 1614 +$EndPAD +$PAD +Sh "11" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -295 1614 +$EndPAD +$PAD +Sh "12" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 1614 +$EndPAD +$PAD +Sh "13" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 1614 +$EndPAD +$PAD +Sh "14" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 295 1614 +$EndPAD +$PAD +Sh "15" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 492 1614 +$EndPAD +$PAD +Sh "16" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 1614 +$EndPAD +$PAD +Sh "17" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 885 1614 +$EndPAD +$PAD +Sh "18" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1082 1614 +$EndPAD +$PAD +Sh "19" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1279 1614 +$EndPAD +$PAD +Sh "20" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1476 1614 +$EndPAD +$PAD +Sh "21" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1673 1614 +$EndPAD +$PAD +Sh "22" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1870 1614 +$EndPAD +$PAD +Sh "23" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2066 1614 +$EndPAD +$PAD +Sh "24" R 118 630 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2263 1614 +$EndPAD +$PAD +Sh "25" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2263 -1614 +$EndPAD +$PAD +Sh "26" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2066 -1614 +$EndPAD +$PAD +Sh "27" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1870 -1614 +$EndPAD +$PAD +Sh "28" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1673 -1614 +$EndPAD +$PAD +Sh "29" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1476 -1614 +$EndPAD +$PAD +Sh "30" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1279 -1614 +$EndPAD +$PAD +Sh "31" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1082 -1614 +$EndPAD +$PAD +Sh "32" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 885 -1614 +$EndPAD +$PAD +Sh "33" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 -1614 +$EndPAD +$PAD +Sh "34" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 492 -1614 +$EndPAD +$PAD +Sh "35" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 295 -1614 +$EndPAD +$PAD +Sh "36" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 -1614 +$EndPAD +$PAD +Sh "37" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 -1614 +$EndPAD +$PAD +Sh "38" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -295 -1614 +$EndPAD +$PAD +Sh "39" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -492 -1614 +$EndPAD +$PAD +Sh "40" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 -1614 +$EndPAD +$PAD +Sh "41" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -885 -1614 +$EndPAD +$PAD +Sh "42" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1082 -1614 +$EndPAD +$PAD +Sh "43" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1279 -1614 +$EndPAD +$PAD +Sh "44" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1476 -1614 +$EndPAD +$PAD +Sh "45" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1673 -1614 +$EndPAD +$PAD +Sh "46" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1870 -1614 +$EndPAD +$PAD +Sh "47" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2066 -1614 +$EndPAD +$PAD +Sh "48" R 118 630 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2263 -1614 +$EndPAD +$EndMODULE TSSOP48_LONGPADS +$MODULE L_4.2X4.2 +Po 0 0 0 15 4EF777D2 00000000 ~~ +Li L_4.2X4.2 +Sc 00000000 +AR +Op 0 0 0 +T0 0 0 600 600 0 120 N V 21 N "L_4.2X4.2" +T1 0 0 600 600 0 120 N V 21 N "VAL**" +DS -1024 -984 1024 -984 79 21 +DS 1024 -984 1024 984 79 21 +DS 1024 984 -1024 984 79 21 +DS -1024 984 -1024 -984 79 21 +$PAD +Sh "1" R 591 1654 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -571 0 +$EndPAD +$PAD +Sh "2" R 591 1654 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 571 0 +$EndPAD +$EndMODULE L_4.2X4.2 +$MODULE LED-3MM-FIXED +Po 0 0 0 15 4EF9035D 00000000 ~~ +Li LED-3MM-FIXED +Cd LED 3mm - Lead pitch 100mil (2,54mm) +Kw LED led 3mm 3MM 100mil 2,54mm +Sc 00000000 +AR /4B6ED75B/4C0DA78D +Op 0 0 0 +At VIRTUAL +T0 -300 -2125 320 320 0 70 N V 21 N "D403" +T1 25 3575 320 320 2700 70 N V 21 N "LED_2mA_1.7V,_red" +DS 669 669 669 394 80 21 +DS 669 -669 669 -394 80 21 +DA 0 0 669 669 2700 80 21 +$PAD +Sh "1" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 1 "+3.3V" +Po -500 0 +$EndPAD +$PAD +Sh "2" C 660 660 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 2 "N-000262" +Po 500 0 +$EndPAD +$SHAPE3D +Na "libs/led3_vertical_red.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE LED-3MM-FIXED $EndLIBRARY diff --git a/pcb/kicad/libs/sdcard.bak b/pcb/kicad/libs/sdcard.bak index 33d67cd..e88c81a 100644 --- a/pcb/kicad/libs/sdcard.bak +++ b/pcb/kicad/libs/sdcard.bak @@ -1,4 +1,4 @@ -PCBNEW-LibModule-V1 Mon 26 Jul 2010 02:13:00 PM CEST +PCBNEW-LibModule-V1 Mon 26 Jul 2010 09:33:33 PM CEST $INDEX SD-RSMT-2-MQ-WF HRS-DM1AA @@ -124,29 +124,28 @@ Po 3740 709 $EndPAD $EndMODULE SD-RSMT-2-MQ-WF $MODULE HRS-DM1AA -Po 0 0 0 15 4C4D706D 00000000 ~~ +Po 0 0 0 15 4C4DE307 00000000 ~~ Li HRS-DM1AA Sc 00000000 AR Op 0 0 0 T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA" T1 0 0 300 300 0 60 N V 21 N"VAL**" -DS -5906 4725 -5906 4686 120 21 -DS 5905 6025 5905 4686 120 21 -DS 5905 -2637 5905 3584 120 21 -DS 5905 -5983 5905 -3779 120 21 +DS 4134 -5984 5512 -5984 120 21 +DS 5512 6024 -5512 6024 120 21 +DS -5512 -5984 -4685 -5984 120 21 +DS -5512 4685 -5512 6024 120 21 +DS 5511 6025 5511 4686 120 21 +DS 5511 -2637 5511 3584 120 21 +DS 5511 -5983 5511 -3779 120 21 DS 4133 -5511 3779 -5511 120 21 DS -4686 -5511 -4529 -5511 120 21 -DS -5906 6025 -5906 4725 120 21 -DS -5906 2521 -5906 2796 120 21 -DS -5906 -983 -5906 1773 120 21 -DS -5906 -2637 -5906 -1731 120 21 -DS -5906 -5983 -5906 -3779 120 21 -DS -5906 -5983 -4686 -5983 120 21 +DS -5512 2521 -5512 2796 120 21 +DS -5512 -983 -5512 1773 120 21 +DS -5512 -2637 -5512 -1731 120 21 +DS -5512 -5983 -5512 -3779 120 21 DS -4686 -5983 -4686 -5511 120 21 DS 4133 -5511 4133 -5983 120 21 -DS 4133 -5983 5905 -5983 120 21 -DS 5905 6025 -5906 6025 120 21 $PAD Sh "~" C 512 512 0 0 0 Dr 512 0 0 diff --git a/pcb/kicad/libs/sdcard.mod b/pcb/kicad/libs/sdcard.mod index e88c81a..152df86 100644 --- a/pcb/kicad/libs/sdcard.mod +++ b/pcb/kicad/libs/sdcard.mod @@ -1,7 +1,8 @@ -PCBNEW-LibModule-V1 Mon 26 Jul 2010 09:33:33 PM CEST +PCBNEW-LibModule-V1 Tue 27 Dec 2011 01:25:51 AM CET +# encoding utf-8 $INDEX -SD-RSMT-2-MQ-WF HRS-DM1AA +SD-RSMT-2-MQ-WF $EndINDEX $MODULE SD-RSMT-2-MQ-WF Po 0 0 0 15 4C4D74E3 00000000 ~~ @@ -124,13 +125,13 @@ Po 3740 709 $EndPAD $EndMODULE SD-RSMT-2-MQ-WF $MODULE HRS-DM1AA -Po 0 0 0 15 4C4DE307 00000000 ~~ +Po 0 0 0 15 4EF9108C 00000000 ~~ Li HRS-DM1AA Sc 00000000 -AR +AR HRS-DM1AA Op 0 0 0 -T0 0 0 300 300 0 60 N V 21 N"HRS-DM1AA" -T1 0 0 300 300 0 60 N V 21 N"VAL**" +T0 0 0 300 300 0 60 N V 21 N "HRS-DM1AA" +T1 0 0 300 300 0 60 N V 21 N "VAL**" DS 4134 -5984 5512 -5984 120 21 DS 5512 6024 -5512 6024 120 21 DS -5512 -5984 -4685 -5984 120 21 @@ -147,16 +148,16 @@ DS -5512 -5983 -5512 -3779 120 21 DS -4686 -5983 -4686 -5511 120 21 DS 4133 -5511 4133 -5983 120 21 $PAD -Sh "~" C 512 512 0 0 0 +Sh "~" C 510 510 0 0 0 Dr 512 0 0 -At STD N 00E0FFFF +At STD N 0000FFFF Ne 0 "" Po -4686 -4999 $EndPAD $PAD -Sh "~" C 512 512 0 0 0 +Sh "~" C 510 510 0 0 0 Dr 512 0 0 -At STD N 00E0FFFF +At STD N 0000FFFF Ne 0 "" Po 4133 -4999 $EndPAD From 6d28f3fb51cb823ce03cdfe79e52a44c30fe4d36 Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 27 Dec 2011 10:31:39 +0100 Subject: [PATCH 42/66] PCB: very basic solder paste pad reduction script --- pcb/kicad/RevE2/padreduce.sh | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100755 pcb/kicad/RevE2/padreduce.sh diff --git a/pcb/kicad/RevE2/padreduce.sh b/pcb/kicad/RevE2/padreduce.sh new file mode 100755 index 0000000..f4a14e9 --- /dev/null +++ b/pcb/kicad/RevE2/padreduce.sh @@ -0,0 +1,17 @@ +cp "$1" "$1".bak + +sed -e 's/^%ADD\(..\)R/%ADD\1O/g' < "$1" > "$1".tmp1 + +grep ^%ADD..O "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; Y=${ln:17:8}; X2=`echo $X-.002 | bc -l`; Y2=`echo $Y-.002 | bc -l`; echo $LS`printf '%01.6f' $X2`X`printf '%01.6f' $Y2`*%; done > "$1".tmp2 + +grep ^%ADD..C "$1".tmp1 | while read ln; do LS=${ln:0:8}; X=${ln:8:8}; X2=`echo $X-.002 | bc -l`; echo $LS`printf '%01.6f' $X2`*%; done >> "$1".tmp2 + +while read ln; do echo "$ln" | grep '^%ADD' >/dev/null && break; echo "$ln"; done < "$1".tmp1 > "$1" + +cat "$1".tmp2 >> "$1" + +grep -A100000 'G04 APERTURE END LIST\*' "$1".tmp1 >> "$1" + +rm "$1".tmp1 "$1".tmp2 + + From 97aef4a2d3dadf4500be3e511c30def9923258b8 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 2 Jan 2012 23:31:40 +0100 Subject: [PATCH 43/66] Firmware: gather+display system information --- src/Makefile | 2 +- src/cic.c | 5 +++++ src/cic.h | 1 + src/cli.c | 2 +- src/filetypes.c | 6 ++++++ src/main.c | 10 ++++++++-- src/memory.h | 25 +++++++++++++------------ src/sdnative.c | 23 ++++++++++++++++------- src/sdnative.h | 1 + src/snes.h | 1 + 10 files changed, 53 insertions(+), 23 deletions(-) diff --git a/src/Makefile b/src/Makefile index 46f029d..e7e6157 100644 --- a/src/Makefile +++ b/src/Makefile @@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes # List C source files here. (C dependencies are automatically generated.) -SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c +SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c sysinfo.c # usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c diff --git a/src/cic.c b/src/cic.c index 9d6a75f..efb0d11 100644 --- a/src/cic.c +++ b/src/cic.c @@ -5,11 +5,16 @@ #include "cic.h" char *cicstatenames[4] = { "CIC_OK", "CIC_FAIL", "CIC_PAIR", "CIC_SCIC" }; +char *cicstatefriendly[4] = {"Original or no CIC", "Original CIC(failed)", "SuperCIC enhanced", "SuperCIC detected, not used"}; void print_cic_state() { printf("CIC state: %s\n", get_cic_statename(get_cic_state())); } +inline char *get_cic_statefriendlyname(enum cicstates state) { + return cicstatefriendly[state]; +} + inline char *get_cic_statename(enum cicstates state) { return cicstatenames[state]; } diff --git a/src/cic.h b/src/cic.h index 03e0648..23fd767 100644 --- a/src/cic.h +++ b/src/cic.h @@ -13,6 +13,7 @@ enum cic_region { CIC_NTSC = 0, CIC_PAL }; void print_cic_state(void); char *get_cic_statename(enum cicstates state); +char *get_cic_statefriendlyname(enum cicstates state); enum cicstates get_cic_state(void); void cic_init(int allow_pairmode); diff --git a/src/cli.c b/src/cli.c index 9c0c8e3..7362350 100644 --- a/src/cli.c +++ b/src/cli.c @@ -134,7 +134,7 @@ static int8_t parse_wordlist(char *wordlist) { do { // If current word list character is \0: No match found if (c == 0) { - printf("Unknown word: %s\n",curchar); + printf("Unknown word: %s\n(use ? for help)",curchar); return -1; } diff --git a/src/filetypes.c b/src/filetypes.c index ad91bde..6e03b3d 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -66,6 +66,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t static uint32_t parent_tgt; static uint32_t dir_end = 0; static uint8_t was_empty = 0; + static uint16_t num_files_total = 0; + static uint16_t num_dirs_total = 0; uint32_t dir_tgt; uint16_t numentries; uint32_t dirsize; @@ -91,6 +93,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t numentries=0; for(pass = 0; pass < 2; pass++) { if(pass) { + num_dirs_total++; dirsize = 4*(numentries); next_subdir_tgt += dirsize + 4; if(parent_tgt) next_subdir_tgt += 4; @@ -180,6 +183,7 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t } else { SNES_FTYPE type = determine_filetype((char*)fn); if(type != TYPE_UNKNOWN) { + num_files_total++; numentries++; if(pass) { if(mkdb) { @@ -250,6 +254,8 @@ uint32_t scan_dir(char* path, FILINFO* fno_param, char mkdb, uint32_t this_dir_t // printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end); sram_writelong(db_tgt, SRAM_DB_ADDR+4); sram_writelong(dir_end, SRAM_DB_ADDR+8); + sram_writeshort(num_files_total, SRAM_DB_ADDR+12); + sram_writeshort(num_dirs_total, SRAM_DB_ADDR+14); return crc; } diff --git a/src/main.c b/src/main.c index 8f961ce..28a3564 100644 --- a/src/main.c +++ b/src/main.c @@ -26,6 +26,7 @@ #include "smc.h" #include "msu1.h" #include "rtc.h" +#include "sysinfo.h" #define EMC0TOGGLE (3<<4) #define MR0R (1<<1) @@ -208,7 +209,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS); set_fpga_time(get_bcdtime()); } - + sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20); printf("SNES GO!\n"); snes_reset(1); delay_ms(1); @@ -243,8 +244,13 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); /* set RTC */ set_bcdtime(btime); set_fpga_time(btime); - cmd=0; /* stay in loop */ + cmd=0; /* stay in menu loop */ break; + case SNES_CMD_SYSINFO: + /* go to sysinfo loop */ + sysinfo_loop(); + cmd=0; /* stay in menu loop */ + break; default: printf("unknown cmd: %d\n", cmd); cmd=0; /* unknown cmd: stay in loop */ diff --git a/src/memory.h b/src/memory.h index 321563d..7ee78e1 100644 --- a/src/memory.h +++ b/src/memory.h @@ -30,19 +30,20 @@ #include #include "smc.h" -#define SRAM_ROM_ADDR (0x000000L) -#define SRAM_SAVE_ADDR (0xE00000L) +#define SRAM_ROM_ADDR (0x000000L) +#define SRAM_SAVE_ADDR (0xE00000L) -#define SRAM_MENU_ADDR (0xE00000L) -#define SRAM_DB_ADDR (0xE40000L) -#define SRAM_DIR_ADDR (0xE10000L) -#define SRAM_CMD_ADDR (0xFF1000L) -#define SRAM_PARAM_ADDR (0xFF1004L) -#define SRAM_STATUS_ADDR (0xFF1100L) -#define SRAM_MENU_SAVE_ADDR (0xFF0000L) -#define SRAM_SCRATCHPAD (0xFFFF00L) -#define SRAM_DIRID (0xFFFFF0L) -#define SRAM_RELIABILITY_SCORE (0x100) +#define SRAM_MENU_ADDR (0xE00000L) +#define SRAM_DB_ADDR (0xE40000L) +#define SRAM_DIR_ADDR (0xE10000L) +#define SRAM_CMD_ADDR (0xFF1000L) +#define SRAM_PARAM_ADDR (0xFF1004L) +#define SRAM_STATUS_ADDR (0xFF1100L) +#define SRAM_SYSINFO_ADDR (0xFF1110L) +#define SRAM_MENU_SAVE_ADDR (0xFF0000L) +#define SRAM_SCRATCHPAD (0xFFFF00L) +#define SRAM_DIRID (0xFFFFF0L) +#define SRAM_RELIABILITY_SCORE (0x100) #define LOADROM_WITH_SRAM (1) #define LOADROM_WITH_RESET (2) diff --git a/src/sdnative.c b/src/sdnative.c index 474ebdb..6d88107 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -111,6 +111,7 @@ uint8_t cmd[6]={0,0,0,0,0,0}; uint8_t rsp[17]; uint8_t csd[17]; +uint8_t cid[17]; uint8_t ccs=0; uint32_t rca; @@ -158,6 +159,17 @@ static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) { return result; } +void sdn_checkinit(BYTE drv) { + if(disk_state == DISK_CHANGED) { + disk_initialize(drv); + } +} + +uint8_t* sdn_getcid() { + sdn_checkinit(0); + return cid; +} + static inline void wiggle_slow_pos(uint16_t times) { while(times--) { delay_us(2); @@ -578,12 +590,6 @@ int acmd_fast(uint8_t cmd, uint32_t param, uint8_t crc, uint8_t* dat, uint8_t* r return cmd_fast(cmd, param, crc, dat, rsp); } -void sdn_checkinit(BYTE drv) { - if(disk_state == DISK_CHANGED) { - disk_initialize(drv); - } -} - int stream_datablock(uint8_t *buf) { // uint8_t datshift=8; int j=512; @@ -887,7 +893,10 @@ DRESULT sdn_initialize(BYTE drv) { } /* record CSD for getinfo */ - cmd_slow(SEND_CSD, rca, 0, NULL, rsp); + cmd_slow(SEND_CSD, rca, 0, NULL, csd); + + /* record CID */ + cmd_slow(SEND_CID, rca, 0, NULL, cid); /* select the card */ if(cmd_slow(SELECT_CARD, rca, 0, NULL, rsp)) { diff --git a/src/sdnative.h b/src/sdnative.h index 636bc37..3deff21 100644 --- a/src/sdnative.h +++ b/src/sdnative.h @@ -24,6 +24,7 @@ DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count); DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer); void sdn_changed(void); +uint8_t* sdn_getcid(void); #endif diff --git a/src/snes.h b/src/snes.h index fa7b762..b8548e3 100644 --- a/src/snes.h +++ b/src/snes.h @@ -29,6 +29,7 @@ #define SNES_CMD_LOADROM (1) #define SNES_CMD_SETRTC (2) +#define SNES_CMD_SYSINFO (3) #define MENU_ERR_OK (0) #define MENU_ERR_NODSP (1) From fec9004dc176201b6f6adf4d86bd16cc51dd8416 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 2 Jan 2012 23:33:24 +0100 Subject: [PATCH 44/66] SNES: display system information (new menu entry) --- snes/Makefile | 2 +- snes/const.a65 | 12 +++++++++--- snes/mainmenu.a65 | 7 ++++++- snes/memmap.i65 | 3 +++ snes/text.a65 | 44 ++++++++++++++++++++++++++++++++++++++------ 5 files changed, 57 insertions(+), 11 deletions(-) diff --git a/snes/Makefile b/snes/Makefile index e687c31..079b43e 100644 --- a/snes/Makefile +++ b/snes/Makefile @@ -1,4 +1,4 @@ -OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 # gfx.o65 # vars.o65 +OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 # gfx.o65 # vars.o65 all: menu.bin diff --git a/snes/const.a65 b/snes/const.a65 index 268a661..02d27a6 100644 --- a/snes/const.a65 +++ b/snes/const.a65 @@ -136,7 +136,9 @@ window_nh .byt 24 window_sh .byt 25 window_wv .byt 26 window_ev .byt 27 -text_clkset .byt 28,"Please set the clock.", 29,0 +window_tl .byt 28 +window_tr .byt 29 +text_clkset .byt "Please set the clock.", 0 text_buttonB .byt "Dpad: sel/chg, B: OK", 0 time_win_x .byt 18 time_win_y .byt 15 @@ -146,7 +148,11 @@ main_win_x .byt 18 main_win_y .byt 11 main_win_w .byt 27 main_win_h .byt 13 -text_mainmenu .byt 28,"Main Menu", 29, 0 +text_mainmenu .byt "Main Menu", 0 +sysinfo_win_x .byt 10 +sysinfo_win_y .byt 9 +sysinfo_win_w .byt 43 +sysinfo_win_h .byt 17 text_mm_file .byt "File Browser", 0 text_mm_last .byt "Run last game", 0 @@ -154,5 +160,5 @@ text_mm_time .byt "Set Clock", 0 text_mm_scic .byt "Enable SuperCIC", 0 text_mm_vmode_menu .byt "Menu video mode", 0 text_mm_vmode_game .byt "Game video mode", 0 - +text_mm_sysinfo .byt "System Information", 0 text_statusbar_keys .byt "B:Select A:Back X:Menu", 0 diff --git a/snes/mainmenu.a65 b/snes/mainmenu.a65 index cb35d01..06f7d4e 100644 --- a/snes/mainmenu.a65 +++ b/snes/mainmenu.a65 @@ -1,6 +1,6 @@ #include "memmap.i65" ;number of menu entries -main_entries .byt 1 +main_entries .byt 2 ;menu entry data main_enttab ;Set Clock .word !text_mm_time @@ -8,6 +8,11 @@ main_enttab ;Set Clock .word !time_init-1 .byt ^time_init .byt 1, 0 + ;System Information + .word !text_mm_sysinfo + .byt ^text_mm_sysinfo + .word !show_sysinfo-1 + .byt ^show_sysinfo ;SuperCIC .word !text_mm_scic .byt ^text_mm_scic diff --git a/snes/memmap.i65 b/snes/memmap.i65 index 7784cdb..97f1497 100644 --- a/snes/memmap.i65 +++ b/snes/memmap.i65 @@ -20,5 +20,8 @@ #define AVR_CMD $307000 #define AVR_PARAM $307004 #define RTC_STATUS $307100 +#define SYSINFO_BLK $307110 #define ROOT_DIR $C10000 + +#define CMD_SYSINFO $03 diff --git a/snes/text.a65 b/snes/text.a65 index a574c53..9a95ecf 100644 --- a/snes/text.a65 +++ b/snes/text.a65 @@ -53,7 +53,9 @@ print_loop phx ; source addr print_loop_inner lda !0,x - asl + bne + + jmp print_end2 ++ asl sta @$2180 lda @print_pal asl @@ -81,6 +83,7 @@ print_loop2 lda @print_count dec sta @print_count_tmp + beq print_end2 lda #$00 pha plb @@ -100,7 +103,9 @@ print_loop2 plb print_loop2_inner lda !0,x - asl + bne + + jmp print_end ++ asl sta @$2180 lda @print_pal asl @@ -124,6 +129,10 @@ print_loop2_inner beq print_end bmi print_end bra print_loop2_inner +print_end2 ; clean up the stack (6 bytes) + ply + ply + ply print_end lda #$00 pha @@ -157,7 +166,7 @@ loprint: sta $2183 ldx !print_src lda !print_bank - pha + pha plb loprint_loop_inner lda !0,x @@ -257,16 +266,39 @@ draw_window: jsr hiprint ; print window title + lda print_x + pha inc print_x inc print_x + lda #^window_tl + sta print_bank + ldx #!window_tl + stx print_src + lda #$01 + sta print_count + jsr hiprint + inc print_x lda window_tbank sta print_bank ldx window_taddr stx print_src + lda window_w + sta print_count jsr hiprint - dec print_x - dec print_x - + lda print_done + adc print_x + sta print_x + lda #^window_tr + sta print_bank + ldx #!window_tr + stx print_src + lda #$01 + sta print_count + jsr hiprint + lda window_w + sta print_count + pla + sta print_x ; draw left+right borders + space inside window lda #^stringbuf sta print_bank From 2c14c3f9256de25cb1876cffda210aeb90f76f76 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 2 Jan 2012 23:34:31 +0100 Subject: [PATCH 45/66] SNES: fix crash on empty database --- snes/menu.a65 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/snes/menu.a65 b/snes/menu.a65 index d648f45..ccf2f41 100644 --- a/snes/menu.a65 +++ b/snes/menu.a65 @@ -210,11 +210,12 @@ redraw_filelist_loop redraw_filelist_dirend dey ; recover last valid direntry number dey ; (we had 2x iny of the direntry pointer above, + beq + dey ; so account for those too) dey dey dey - sty dirend_idx ; dirend_idx <- last valid directory entry. ++ sty dirend_idx ; dirend_idx <- last valid directory entry. lda #$01 ; encountered during redraw, so must be on screen sta dirend_onscreen bra redraw_filelist_out From 22fe28c624a7fb9fa72051cd90903e4695991cb9 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 2 Jan 2012 23:34:45 +0100 Subject: [PATCH 46/66] SNES: insert debug marker --- snes/text.a65 | 1 + 1 file changed, 1 insertion(+) diff --git a/snes/text.a65 b/snes/text.a65 index 9a95ecf..aca3394 100644 --- a/snes/text.a65 +++ b/snes/text.a65 @@ -1,5 +1,6 @@ .text #include "memmap.i65" +.byt "===HIPRINT===" hiprint: sep #$20 : .as lda print_count From a52638b4be638dd27308847f4bc5878af8521341 Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 2 Jan 2012 23:36:42 +0100 Subject: [PATCH 47/66] Firmware: update version number to 0.1.2 --- src/config | 6 +++--- src/config.h | 3 ++- src/main.c | 3 ++- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/config b/src/config index aa88b57..a0e56b1 100644 --- a/src/config +++ b/src/config @@ -1,4 +1,4 @@ -CONFIG_VERSION=0.1.1 -#FWVER=000101 -CONFIG_FWVER=257 +CONFIG_VERSION="0.1.2" +#FWVER=00010200 +CONFIG_FWVER=66048 CONFIG_MCU_FOSC=12000000 diff --git a/src/config.h b/src/config.h index 03d5d0c..14f5d60 100644 --- a/src/config.h +++ b/src/config.h @@ -1,12 +1,13 @@ #ifndef _CONFIG_H #define _CONFIG_H +#include "autoconf.h" + // #define DEBUG_FS // #define DEBUG_SD // #define DEBUG_IRQ // #define DEBUG_MSU1 -#define VER "0.0.1(NSFW)" #define IN_AHBRAM __attribute__ ((section(".ahbram"))) #define SD_DT_INT_SETUP() do {\ diff --git a/src/main.c b/src/main.c index 28a3564..730974b 100644 --- a/src/main.c +++ b/src/main.c @@ -76,7 +76,7 @@ int main(void) { LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ led_pwm(); sdn_init(); - printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); + printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); printf("PCONP=%lx\n", LPC_SC->PCONP); file_init(); @@ -127,6 +127,7 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); } file_close(); } + uart_trace(sdn_getcid(), 0, 17); snes_bootprint(" Loading ... \0"); if(get_cic_state() == CIC_PAIR) { printf("PAIR MODE ENGAGED!\n"); From cbe30cb38828583798db809e837330242db099a6 Mon Sep 17 00:00:00 2001 From: ikari Date: Tue, 10 Jan 2012 23:59:33 +0100 Subject: [PATCH 48/66] PCB Rev.E: update BOM (-> RA103, RA104 pending) --- pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods | Bin 21435 -> 23053 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods b/pcb/kicad/RevE/sd2snes-BOM-with-supplier.ods index 219763411a49c2ededb7834e828f88bd2e12b9b2..b474404cfb1454d110e0828367c03c3c91060274 100644 GIT binary patch delta 20867 zcmZs?1yo$Y)-{N`ySux)26y-19^8TiXx!c1CBY@QyE_C37F>h7&dvM2`RC27>9tth z&~>ZMJ#}R7U6+n>@YtW=D5?sOP*`AKaA07%Eev9bD5{`;?_mG+LIggWJ2|>rI=ZuX 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ikari Date: Sat, 14 Jan 2012 01:05:15 +0100 Subject: [PATCH 50/66] Firmware/bootldr: size reduction and stability measures --- src/bootldr/clock.c | 4 +-- src/bootldr/config.h | 2 +- src/bootldr/ffconf.h | 4 +-- src/bootldr/iap.c | 19 +++++++++++--- src/bootldr/timer.c | 46 --------------------------------- src/bootldr/uart.c | 61 +++----------------------------------------- 6 files changed, 23 insertions(+), 113 deletions(-) diff --git a/src/bootldr/clock.c b/src/bootldr/clock.c index d766ae6..8bd7914 100644 --- a/src/bootldr/clock.c +++ b/src/bootldr/clock.c @@ -14,8 +14,8 @@ void clock_disconnect() { void clock_init() { -/* set flash access time to 5 clks (80RICTRL = BV(RITINT); - NVIC_ClearPendingIRQ(RIT_IRQn); - wokefromrit = 1; - RIT_Hook(); -} - void timer_init(void) { /* turn on power to RIT */ BITBAND(LPC_SC->PCONP, PCRIT) = 1; @@ -54,8 +28,6 @@ void timer_init(void) { /* PCLK = CCLK */ BITBAND(LPC_SC->PCLKSEL1, 26) = 1; BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1; - /* enable SysTick */ - SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk)); } void delay_us(unsigned int time) { @@ -84,21 +56,3 @@ void delay_ms(unsigned int time) { LPC_RIT->RICTRL = 0; } -void sleep_ms(unsigned int time) { - - wokefromrit = 0; - /* Prepare RIT */ - LPC_RIT->RICOUNTER = 0; - LPC_RIT->RICOMPVAL = (CONFIG_CPU_FREQUENCY / 1000) * time; - LPC_RIT->RICTRL = BV(RITEN) | BV(RITINT); - NVIC_EnableIRQ(RIT_IRQn); - - /* Wait until RIT signals an interrupt */ -//uart_putc(';'); - while(!wokefromrit) { - __WFI(); - } - NVIC_DisableIRQ(RIT_IRQn); - /* Disable RIT */ - LPC_RIT->RICTRL = BV(RITINT); -} diff --git a/src/bootldr/uart.c b/src/bootldr/uart.c index 15fee39..d5f224f 100644 --- a/src/bootldr/uart.c +++ b/src/bootldr/uart.c @@ -74,65 +74,14 @@ } } */ -static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; +//static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; static volatile unsigned int read_idx,write_idx; -void UART_HANDLER(void) { - int iir = UART_REGS->IIR; - if (!(iir & 1)) { - /* Interrupt is pending */ - switch (iir & 14) { -#if CONFIG_UART_NUM == 1 - case 0: /* modem status */ - (void) UART_REGS->MSR; // dummy read to clear - break; -#endif - - case 2: /* THR empty - send */ - if (read_idx != write_idx) { - int maxchars = 16; - while (read_idx != write_idx && --maxchars > 0) { - UART_REGS->THR = (unsigned char)txbuf[read_idx]; - read_idx = (read_idx+1) & (sizeof(txbuf)-1); - } - if (read_idx == write_idx) { - /* buffer empty - turn off THRE interrupt */ - BITBAND(UART_REGS->IER, 1) = 0; - } - } - break; - - case 12: /* RX timeout */ - case 4: /* data received - not implemented yet */ - (void) UART_REGS->RBR; // dummy read to clear - break; - - case 6: /* RX error */ - (void) UART_REGS->LSR; // dummy read to clear - - default: break; - } - } -} - void uart_putc(char c) { if (c == '\n') uart_putc('\r'); - - unsigned int tmp = (write_idx+1) & (sizeof(txbuf)-1) ; - - if (read_idx == write_idx && (BITBAND(UART_REGS->LSR, 5))) { - /* buffer empty, THR empty -> send immediately */ - UART_REGS->THR = (unsigned char)c; - } else { -#ifdef CONFIG_UART_DEADLOCKABLE - while (tmp == read_idx) ; -#endif - BITBAND(UART_REGS->IER, 1) = 0; // turn off UART interrupt - txbuf[write_idx] = c; - write_idx = tmp; - BITBAND(UART_REGS->IER, 1) = 1; - } + while(!(UART_REGS->LSR & (0x20))); + UART_REGS->THR = c; } /* Polling version only */ @@ -183,10 +132,6 @@ void uart_init(void) { /* reset and enable FIFO */ UART_REGS->FCR = BV(0); - /* enable transmit interrupt */ - BITBAND(UART_REGS->IER, 1) = 1; - NVIC_EnableIRQ(UART_IRQ); - UART_REGS->THR = '?'; } From afc26397b1a651c5d8261ec7139e9b2ce0cae63b Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:10:13 +0100 Subject: [PATCH 51/66] Firmware: region override (patch register $213f) --- src/fpga_spi.c | 11 ++++++++++- src/fpga_spi.h | 5 ++++- src/memory.c | 2 ++ src/smc.h | 3 ++- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/fpga_spi.c b/src/fpga_spi.c index ebdf7c5..2ff1ede 100644 --- a/src/fpga_spi.c +++ b/src/fpga_spi.c @@ -80,6 +80,7 @@ EB - put DSP into reset EC - release DSP from reset ED - set feature enable bits (see below) + EE - set $213f override value (0=NTSC, 1=PAL) F0 - receive test token (to see if FPGA is alive) F1 - receive status (16bit, MSB first), see below @@ -117,7 +118,7 @@ 7 - 6 - 5 - - 4 - + 4 enable $213F override 3 enable MSU1 registers 2 enable SRTC registers 1 enable ST0010 mapping @@ -411,3 +412,11 @@ void fpga_set_features(uint8_t feat) { FPGA_DESELECT(); } +void fpga_set_213f(uint8_t data) { + printf("set 213f: %d\n", data); + FPGA_SELECT(); + FPGA_TX_BYTE(0xee); + FPGA_TX_BYTE(data); + FPGA_DESELECT(); +} + diff --git a/src/fpga_spi.h b/src/fpga_spi.h index d04a954..b13c382 100644 --- a/src/fpga_spi.h +++ b/src/fpga_spi.h @@ -50,12 +50,14 @@ #define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST) #define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW) -#define FEAT_CX4 (1 << 4) +#define FEAT_213F (1 << 4) #define FEAT_MSU1 (1 << 3) #define FEAT_SRTC (1 << 2) #define FEAT_ST0010 (1 << 1) #define FEAT_DSPX (1 << 0) +#define FEAT_CX4 (1 << 4) + #define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0) void fpga_spi_init(void); @@ -90,4 +92,5 @@ void fpga_write_dspx_pgm(uint32_t data); void fpga_write_dspx_dat(uint16_t data); void fpga_dspx_reset(uint8_t reset); void fpga_set_features(uint8_t feat); +void fpga_set_213f(uint8_t data); #endif diff --git a/src/memory.c b/src/memory.c index d276178..8ecd6bd 100644 --- a/src/memory.c +++ b/src/memory.c @@ -281,7 +281,9 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) { printf("done\n"); romprops.fpga_features |= FEAT_SRTC; + romprops.fpga_features |= FEAT_213F; + fpga_set_213f(romprops.region); fpga_set_features(romprops.fpga_features); if(flags & LOADROM_WITH_RESET) { diff --git a/src/smc.h b/src/smc.h index 8e77b7c..5c3d018 100644 --- a/src/smc.h +++ b/src/smc.h @@ -66,10 +66,11 @@ typedef struct _snes_romprops { const uint8_t* dsp_fw; /* DSP (NEC / Hitachi) ROM filename */ const uint8_t* fpga_conf; /* FPGA config file to load (default: base) */ uint8_t has_dspx; /* DSP[1-4] presence flag */ - uint8_t has_st0010; /* st0010 presence flag (additional to dspx)*/ + uint8_t has_st0010; /* st0010 presence flag (additional to dspx) */ uint8_t has_msu1; /* MSU1 presence flag */ uint8_t has_cx4; /* CX4 presence flag */ uint8_t fpga_features; /* feature/peripheral enable bits*/ + uint8_t region; /* game region (derived from destination code) */ snes_header_t header; /* original header from ROM image */ } snes_romprops_t; From b272a6fc1c5ad5a3d8f1dcf3949e1b1958dbab53 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:13:36 +0100 Subject: [PATCH 52/66] Firmware: optimize non-sector-aligned SD DMA reads --- src/fpga_spi.c | 16 ++++++++++----- src/main.c | 2 ++ src/sdnative.c | 56 ++++++++++++++++++++++++++++++++++++++++---------- 3 files changed, 58 insertions(+), 16 deletions(-) diff --git a/src/fpga_spi.c b/src/fpga_spi.c index 2ff1ede..8f44916 100644 --- a/src/fpga_spi.c +++ b/src/fpga_spi.c @@ -47,9 +47,15 @@ s: Bit 2 = partial, Bit 1:0 = target target: see above - 60 sssseeee set SD DMA partial transfer start+end - ssss = start offset (msb first) - eeee = end offset (msb first) + 60 xsssyeee set SD DMA partial transfer parameters + x: 0 = read from sector start (skip until + start offset reached) + 8 = assume mid-sector position and read + immediately + sss = start offset (msb first) + y: 0 = skip rest of SD sector + 8 = stop mid-sector if end offset reached + eee = end offset (msb first) 8p - read (RAM only) p: 0 = no increment after read @@ -98,7 +104,7 @@ 15 SD DMA busy (0=idle, 1=busy) 14 DAC read pointer MSB 13 MSU read pointer MSB - 12 [TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0] + 12 reserved (0) 11 reserved (0) 10 reserved (0) 9 reserved (0) @@ -239,7 +245,7 @@ void fpga_sddma(uint8_t tgt, uint8_t partial) { } DBG_SD printf("...complete\n"); FPGA_DESELECT(); - if(test<5)printf("loopy: %ld %02x\n", test, status); +// if(test<5)printf("loopy: %ld %02x\n", test, status); BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1; } diff --git a/src/main.c b/src/main.c index 730974b..931dea2 100644 --- a/src/main.c +++ b/src/main.c @@ -35,6 +35,8 @@ int i; int sd_offload = 0, ff_sd_offload = 0, sd_offload_tgt = 0; int sd_offload_partial = 0; +int sd_offload_start_mid = 0; +int sd_offload_end_mid = 0; uint16_t sd_offload_partial_start = 0; uint16_t sd_offload_partial_end = 0; diff --git a/src/sdnative.c b/src/sdnative.c index 6d88107..b7725a9 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -115,11 +115,12 @@ uint8_t cid[17]; uint8_t ccs=0; uint32_t rca; -enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE }; +enum trans_state { TRANS_NONE = 0, TRANS_READ, TRANS_WRITE, TRANS_MID }; enum cmd_state { CMD_RSP = 0, CMD_RSPDAT, CMD_DAT }; int during_blocktrans = TRANS_NONE; uint32_t last_block = 0; +uint16_t last_offset = 0; volatile int sd_changed; @@ -395,7 +396,6 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){ printf("CMD%d timed out\n", cmdno); return 0; /* no response within timeout */ } - i=rsplen; uint8_t cmddata=0, datdata=0; while(i--) { /* process response */ @@ -460,20 +460,31 @@ int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){ state=CMD_DAT; j=datcnt; datshift=8; + timeout=2000000; DBG_SD printf("response over, waiting for data...\n"); /* wait for data start bit on DAT0 */ while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { wiggle_fast_neg1(); } +//printf("%ld\n", timeout); DBG_SD if(!timeout) printf("timed out!\n"); wiggle_fast_neg1(); /* eat the start bit */ if(sd_offload) { if(sd_offload_partial) { + if(sd_offload_partial_start != 0) { + if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000; + } + if(sd_offload_partial_end != 512) { + sd_offload_partial_end |= 0x8000; + } + DBG_SD printf("new partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end); fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end); fpga_sddma(sd_offload_tgt, 1); - sd_offload_partial=0; +// sd_offload_partial=0; + last_offset=sd_offload_partial_end; } else { fpga_sddma(sd_offload_tgt, 0); + last_offset=0; } state=CMD_RSP; return rsplen; @@ -597,17 +608,24 @@ int stream_datablock(uint8_t *buf) { uint32_t timeout=1000000; DBG_SD printf("stream_datablock: wait for ready...\n"); - while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { - wiggle_fast_neg1(); + if(during_blocktrans != TRANS_MID) { + while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { + wiggle_fast_neg1(); + } + DBG_SD if(!timeout) printf("timeout!\n"); + wiggle_fast_neg1(); /* eat the start bit */ } - DBG_SD if(!timeout) printf("timeout!\n"); - - wiggle_fast_neg1(); /* eat the start bit */ if(sd_offload) { if(sd_offload_partial) { + if(sd_offload_partial_start != 0) { + if(during_blocktrans == TRANS_MID) sd_offload_partial_start |= 0x8000; + } + if(sd_offload_partial_end != 512) { + sd_offload_partial_end |= 0x8000; + } + DBG_SD printf("str partial %d - %d\n", sd_offload_partial_start, sd_offload_partial_end); fpga_set_sddma_range(sd_offload_partial_start, sd_offload_partial_end); fpga_sddma(sd_offload_tgt, 1); - sd_offload_partial=0; } else { fpga_sddma(sd_offload_tgt, 0); } @@ -772,7 +790,21 @@ void read_block(uint32_t address, uint8_t *buf) { #else stream_datablock(buf); #endif - last_block=address; + last_block = address; + last_offset = sd_offload_partial_end & 0x1ff; + if(sd_offload_partial && sd_offload_partial_end != 512) { + during_blocktrans = TRANS_MID; + } + sd_offload_partial = 0; + } else if (during_blocktrans == TRANS_MID + && last_block == address + && last_offset == sd_offload_partial_start + && sd_offload_partial) { + stream_datablock(buf); + last_offset = sd_offload_partial_end & 0x1ff; + sd_offload_partial_start |= 0x8000; + during_blocktrans = TRANS_READ; + sd_offload_partial = 0; } else { if(during_blocktrans) { // uart_putc('_'); @@ -780,7 +812,7 @@ void read_block(uint32_t address, uint8_t *buf) { /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */ cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); } - last_block=address; + last_block = address; if(!ccs) { address <<= 9; } @@ -792,8 +824,10 @@ void read_block(uint32_t address, uint8_t *buf) { #else cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp); #endif + sd_offload_partial = 0; during_blocktrans = TRANS_READ; } +// printf("trans state = %d\n", during_blocktrans); } void write_block(uint32_t address, uint8_t* buf) { From 03ee71a6264e38300184396b83aecea2817e589e Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:14:37 +0100 Subject: [PATCH 53/66] Firmware/MSU1: add debug macros before logging statements --- src/msu1.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/msu1.c b/src/msu1.c index 3e1e884..b7d7fc6 100644 --- a/src/msu1.c +++ b/src/msu1.c @@ -127,21 +127,21 @@ int msu1_loop() { /* get trackno */ msu_track = get_msu_track(); - printf("Audio requested! Track=%d\n", msu_track); + DBG_MSU1 printf("Audio requested! Track=%d\n", msu_track); /* open file, fill buffer */ f_close(&file_handle); snprintf(suffix, sizeof(suffix), "-%d.pcm", msu_track); strcpy((char*)file_buf, (char*)file_lfn); strcpy(strrchr((char*)file_buf, (int)'.'), suffix); - printf("filename: %s\n", file_buf); + DBG_MSU1 printf("filename: %s\n", file_buf); f_open(&file_handle, (const TCHAR*)file_buf, FA_READ); file_handle.cltbl = pcm_cltbl; pcm_cltbl[0] = CLTBL_SIZE; f_lseek(&file_handle, CREATE_LINKMAP); f_lseek(&file_handle, 4L); f_read(&file_handle, &msu_loop_point, 4, &bytes_read); - printf("loop point: %ld samples\n", msu_loop_point); + DBG_MSU1 printf("loop point: %ld samples\n", msu_loop_point); ff_sd_offload=1; sd_offload_tgt=1; f_lseek(&file_handle, 8L); @@ -159,12 +159,12 @@ int msu1_loop() { if(fpga_status_now & 0x0010) { /* get address */ msu_offset=get_msu_offset(); - printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start); + DBG_MSU1 printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start); if( ((msu_offset < msu_page1_start) || (msu_offset >= msu_page1_start + msu_page_size)) && ((msu_offset < msu_page2_start) || (msu_offset >= msu_page2_start + msu_page_size))) { - printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start, + DBG_MSU1 printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start, msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1); /* "cache miss" */ /* fill buffer */ @@ -220,19 +220,19 @@ int msu1_loop() { if(fpga_status_now & 0x0004) { msu_repeat = 1; set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */ - printf("Repeat set!\n"); + DBG_MSU1 printf("Repeat set!\n"); } else { msu_repeat = 0; set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */ - printf("Repeat clear!\n"); + DBG_MSU1 printf("Repeat clear!\n"); } if(fpga_status_now & 0x0002) { - printf("PLAY!\n"); + DBG_MSU1 printf("PLAY!\n"); set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */ dac_play(); } else { - printf("PAUSE!\n"); + DBG_MSU1 printf("PAUSE!\n"); set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */ dac_pause(); } @@ -245,7 +245,7 @@ int msu1_loop() { ff_sd_offload=0; sd_offload=0; if(msu_repeat) { - printf("loop\n"); + DBG_MSU1 printf("loop\n"); ff_sd_offload=1; sd_offload_tgt=1; f_lseek(&file_handle, 8L+msu_loop_point*4); From 3436ccf46ac4e70053cfef68e8771b19e4db0cfa Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:17:20 +0100 Subject: [PATCH 54/66] Firmware: improve map detection --- src/main.c | 1 - src/smc.c | 134 ++++++++++++++++++++++++++++++++--------------------- src/smc.h | 15 +++++- 3 files changed, 95 insertions(+), 55 deletions(-) diff --git a/src/main.c b/src/main.c index 931dea2..15ba57d 100644 --- a/src/main.c +++ b/src/main.c @@ -129,7 +129,6 @@ printf("PCONP=%lx\n", LPC_SC->PCONP); } file_close(); } - uart_trace(sdn_getcid(), 0, 17); snes_bootprint(" Loading ... \0"); if(get_cic_state() == CIC_PAIR) { printf("PAIR MODE ENGAGED!\n"); diff --git a/src/smc.c b/src/smc.c index 3a07223..83302a0 100644 --- a/src/smc.c +++ b/src/smc.c @@ -34,28 +34,6 @@ snes_romprops_t romprops; uint32_t hdr_addr[6] = {0xffb0, 0x101b0, 0x7fb0, 0x81b0, 0x40ffb0, 0x4101b0}; -uint8_t countAllASCII(uint8_t* data, int size) { - uint8_t res = 0; - do { - size--; - if(data[size] >= 0x20 && data[size] <= 0x7e) { - res++; - } - } while (size); - return res; -} - -uint8_t countAllJISX0201(uint8_t* data, int size) { - uint8_t res = 0; - do { - size--; - if((data[size] >= 0x20 && data[size] <= 0x7e) - ||(data[size] >= 0xa1 && data[size] <= 0xdf)) { - res++; - } - } while (size); - return res; -} uint8_t isFixed(uint8_t* data, int size, uint8_t value) { uint8_t res = 1; @@ -72,7 +50,7 @@ uint8_t checkChksum(uint16_t cchk, uint16_t chk) { uint32_t sum = cchk + chk; uint8_t res = 0; if(sum==0x0000ffff) { - res = 0x10; + res = 1; } return res; } @@ -87,32 +65,13 @@ void smc_id(snes_romprops_t* props) { props->fpga_features = 0; props->fpga_conf = NULL; for(uint8_t num = 0; num < 6; num++) { - if(!file_readblock(header, hdr_addr[num], sizeof(snes_header_t)) - || file_res) { - score = 0; - } else { - score = smc_headerscore(header)/(1+(num&1)); - if((file_handle.fsize & 0x2ff) == 0x200) { - if(num&1) { - score+=20; - } else { - score=0; - } - } else { - if(!(num&1)) { - score+=20; - } else { - score=0; - } - } - } -//printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ + score = smc_headerscore(hdr_addr[num], header); + printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ if(score>=maxscore) { score_idx=num; maxscore=score; } } - if(score_idx & 1) { props->offset = 0x200; } else { @@ -163,7 +122,7 @@ void smc_id(snes_romprops_t* props) { (header->map == 0x30 && header->carttype == 0x05 && header->licensee != 0xb2)) { props->has_dspx = 1; props->fpga_features |= FEAT_DSPX; - // Pilotwings uses DSP1 instead of DSP1B + /* Pilotwings uses DSP1 instead of DSP1B */ if(!memcmp(header->name, "PILOTWINGS", 10)) { props->dsp_fw = DSPFW_1; } else { @@ -236,17 +195,86 @@ void smc_id(snes_romprops_t* props) { if(props->ramsize_bytes > 32768 || props->ramsize_bytes < 2048) { props->ramsize_bytes = 0; } + props->region = (header->destcode <= 1 || header->destcode >= 13) ? 0 : 1; + /*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */ } -uint8_t smc_headerscore(snes_header_t* header) { - uint8_t score=0; - score += countAllASCII(header->maker, sizeof(header->maker)); - score += countAllASCII(header->gamecode, sizeof(header->gamecode)); - score += isFixed(header->fixed_00, sizeof(header->fixed_00), 0x00); - score += countAllJISX0201(header->name, sizeof(header->name)); - score += 3*isFixed(&header->licensee, sizeof(header->licensee), 0x33); - score += checkChksum(header->cchk, header->chk); +uint8_t smc_headerscore(uint32_t addr, snes_header_t* header) { + int score=0; + uint8_t reset_inst; + uint16_t header_offset; + if((addr & 0xfff) == 0x1b0) { + header_offset = 0x200; + } else { + header_offset = 0; + } + if((file_readblock(header, addr, sizeof(snes_header_t)) < sizeof(snes_header_t)) + || file_res) { + return 0; + } + uint8_t mapper = header->map & ~0x10; + uint16_t resetvector = header->vect_reset; /* not endian safe! */ + uint32_t file_addr = (((addr - header_offset) & ~0x7fff) | (resetvector & 0x7fff)) + header_offset; + if(resetvector < 0x8000) return 0; + + score += 2*isFixed(&header->licensee, sizeof(header->licensee), 0x33); + score += 4*checkChksum(header->cchk, header->chk); + if(header->carttype < 0x08) score++; + if(header->romsize < 0x10) score++; + if(header->ramsize < 0x08) score++; + if(header->destcode < 0x0e) score++; + + if((addr-header_offset) == 0x007fc0 && mapper == 0x20) score += 2; + if((addr-header_offset) == 0x00ffc0 && mapper == 0x21) score += 2; + if((addr-header_offset) == 0x007fc0 && mapper == 0x22) score += 2; + if((addr-header_offset) == 0x40ffc0 && mapper == 0x25) score += 2; + + file_readblock(&reset_inst, file_addr, 1); + switch(reset_inst) { + case 0x78: /* sei */ + case 0x18: /* clc */ + case 0x38: /* sec */ + case 0x9c: /* stz abs */ + case 0x4c: /* jmp abs */ + case 0x5c: /* jml abs */ + score += 8; + break; + + case 0xc2: /* rep */ + case 0xe2: /* sep */ + case 0xad: /* lda abs */ + case 0xae: /* ldx abs */ + case 0xac: /* ldy abs */ + case 0xaf: /* lda abs long */ + case 0xa9: /* lda imm */ + case 0xa2: /* ldx imm */ + case 0xa0: /* ldy imm */ + case 0x20: /* jsr abs */ + case 0x22: /* jsl abs */ + score += 4; + break; + + case 0x40: /* rti */ + case 0x60: /* rts */ + case 0x6b: /* rtl */ + case 0xcd: /* cmp abs */ + case 0xec: /* cpx abs */ + case 0xcc: /* cpy abs */ + score -= 4; + break; + + case 0x00: /* brk */ + case 0x02: /* cop */ + case 0xdb: /* stp */ + case 0x42: /* wdm */ + case 0xff: /* sbc abs long indexed */ + score -= 8; + break; + } + + if(score && addr > 0x400000) score += 4; + if(score < 0) score = 0; return score; } diff --git a/src/smc.h b/src/smc.h index 5c3d018..a73843a 100644 --- a/src/smc.h +++ b/src/smc.h @@ -54,6 +54,19 @@ typedef struct _snes_header { uint8_t ver; /* 0xDB */ uint16_t cchk; /* 0xDC */ uint16_t chk; /* 0xDE */ + uint32_t pad1; /* 0xE0 */ + uint16_t vect_cop16; /* 0xE4 */ + uint16_t vect_brk16; /* 0xE6 */ + uint16_t vect_abt16; /* 0xE8 */ + uint16_t vect_nmi16; /* 0xEA */ + uint16_t vect_irq16; /* 0xEE */ + uint16_t pad2; /* 0xF0 */ + uint16_t vect_cop8; /* 0xF4 */ + uint32_t pad3; /* 0xF6 */ + uint16_t vect_abt8; /* 0xF8 */ + uint16_t vect_nmi8; /* 0xFA */ + uint16_t vect_reset; /* 0xFC */ + uint16_t vect_brk8; /* 0xFE */ } snes_header_t; typedef struct _snes_romprops { @@ -75,6 +88,6 @@ typedef struct _snes_romprops { } snes_romprops_t; void smc_id(snes_romprops_t*); -uint8_t smc_headerscore(snes_header_t*); +uint8_t smc_headerscore(uint32_t addr, snes_header_t* header); #endif From 5f87768a148cd4703b2d621b7c7f4071a816c781 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:17:59 +0100 Subject: [PATCH 55/66] Firmware: remove unnecessary crc16.c from Makefile --- src/tests/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/tests/Makefile b/src/tests/Makefile index ec89962..6bbc9cf 100644 --- a/src/tests/Makefile +++ b/src/tests/Makefile @@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes # List C source files here. (C dependencies are automatically generated.) -SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c crc16.c tests.c +SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c tests.c # usbcontrol.c usb_hid.c usbhw_lpc.c usbinit.c usbstdreq.c From 5a3e935a3e314015f2c78ef9f26f58685150b7ce Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:21:21 +0100 Subject: [PATCH 56/66] FPGA: region override (patch register $213f) --- verilog/sd2snes/address.v | 18 +++++---- verilog/sd2snes/main.ucf | 22 +++++++++++ verilog/sd2snes/main.v | 77 ++++++++++++++++++++++++++++++++------- verilog/sd2snes/mcu_cmd.v | 8 +++- 4 files changed, 102 insertions(+), 23 deletions(-) diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v index 8b50fa1..c833d97 100644 --- a/verilog/sd2snes/address.v +++ b/verilog/sd2snes/address.v @@ -19,9 +19,10 @@ ////////////////////////////////////////////////////////////////////////////////// module address( input CLK, - input [3:0] featurebits, // peripheral enable/disable + input [7:0] featurebits, // peripheral enable/disable input [2:0] MAPPER, // MCU detected mapper input [23:0] SNES_ADDR, // requested address from SNES + input [7:0] SNES_PA, // peripheral address from SNES output [23:0] ROM_ADDR, // Address to request from SRAM0 output ROM_SEL, // enable SRAM0 (active low) output IS_SAVERAM, // address/CS mapped as SRAM? @@ -35,14 +36,16 @@ module address( input [14:0] bsx_regs, output dspx_enable, output dspx_dp_enable, - output dspx_a0 + output dspx_a0, + output r213f_enable ); parameter [2:0] FEAT_DSPX = 0, FEAT_ST0010 = 1, FEAT_SRTC = 2, - FEAT_MSU1 = 3 + FEAT_MSU1 = 3, + FEAT_213F = 4 ; wire [23:0] SRAM_SNES_ADDR; @@ -223,10 +226,6 @@ assign dspx_a0 = featurebits[FEAT_DSPX] ?SNES_ADDR[0] :1'b1; -//reg [7:0] dspx_dp_enable_r; -//initial dspx_dp_enable_r = 8'b00000000; -//always @(posedge CLK) dspx_dp_enable_r <= {dspx_dp_enable_r[6:0], dspx_dp_enable_w}; -//assign dspx_dp_enable = &dspx_dp_enable_r[5:2]; assign dspx_dp_enable = dspx_dp_enable_w; reg [5:0] dspx_enable_r; @@ -234,5 +233,10 @@ initial dspx_enable_r = 6'b000000; always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w}; assign dspx_enable = &dspx_enable_r[5:2]; +wire r213f_enable_w = (SNES_PA == 8'h3f); +reg [5:0] r213f_enable_r; +initial r213f_enable_r = 6'b000000; +always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w}; +assign r213f_enable = &r213f_enable_r[5:2] & featurebits[FEAT_213F]; endmodule diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index 7ed7b66..64577df 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -460,6 +460,28 @@ NET "SNES_READ" LOC = P115; NET "SNES_REFRESH" LOC = P155; NET "SNES_WRITE" LOC = P94; +NET "SNES_PA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[0]" LOC = P90; +NET "SNES_PA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[1]" LOC = P93; +NET "SNES_PA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[2]" LOC = P86; +NET "SNES_PA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[3]" LOC = P87; +NET "SNES_PA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[4]" LOC = P81; +NET "SNES_PA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[5]" LOC = P85; +NET "SNES_PA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[6]" LOC = P152; +NET "SNES_PA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[7]" LOC = P154; + +NET "SNES_PARD" IOSTANDARD = LVCMOS33; +NET "SNES_PARD" LOC = P149; +NET "SNES_PAWR" IOSTANDARD = LVCMOS33; +NET "SNES_PAWR" LOC = P150; + NET "SPI_MISO" LOC = P72; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 7d3fc6b..e63a5db 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -35,6 +35,10 @@ module main( output SNES_DATABUS_DIR, input SNES_SYSCLK, + input [7:0] SNES_PA, + input SNES_PARD, + input SNES_PAWR, + /* SRAM signals */ /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */ inout [15:0] ROM_DATA, @@ -124,7 +128,7 @@ wire [15:0] dspx_dat_data; wire [10:0] dspx_dat_addr; wire dspx_dat_we; -wire [3:0] featurebits; +wire [7:0] featurebits; wire [23:0] MAPPED_SNES_ADDR; wire ROM_ADDR0; @@ -321,7 +325,8 @@ mcu_cmd snes_mcu_cmd( .featurebits_out(featurebits), .mcu_rrq(MCU_RRQ), .mcu_wrq(MCU_WRQ), - .mcu_rq_rdy(MCU_RDY) + .mcu_rq_rdy(MCU_RDY), + .region_out(mcu_region) ); wire [7:0] DCM_STATUS; @@ -334,17 +339,29 @@ my_dcm snes_dcm( .STATUS(DCM_STATUS) ); +my_dcm snes_dcm2( + .CLKIN(SNES_SYSCLK), + .CLKFX(SYSCLK2), + .RST(DCM_RST) +); + assign DCM_RST=0; +reg [5:0] SNES_PARDr; reg [5:0] SNES_READr; reg [5:0] SNES_WRITEr; reg [5:0] SNES_CPU_CLKr; +wire SNES_PARD_start = (SNES_PARDr == 6'b111110); wire SNES_RD_start = (SNES_READr == 6'b111110); wire SNES_WR_start = (SNES_WRITEr == 6'b111110); wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); +always @(posedge SYSCLK2) begin + SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD}; +end + always @(posedge CLK2) begin SNES_READr <= {SNES_READr[4:0], SNES_READ}; SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; @@ -356,6 +373,7 @@ address snes_addr( .MAPPER(MAPPER), .featurebits(featurebits), .SNES_ADDR(SNES_ADDR), // requested address from SNES + .SNES_PA(SNES_PA), .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) .ROM_SEL(ROM_SEL), // which SRAM unit to access .IS_SAVERAM(IS_SAVERAM), @@ -373,7 +391,8 @@ address snes_addr( //uPD77C25 .dspx_enable(dspx_enable), .dspx_dp_enable(dspx_dp_enable), - .dspx_a0(DSPX_A0) + .dspx_a0(DSPX_A0), + .r213f_enable(r213f_enable) ); parameter MODE_SNES = 1'b0; @@ -414,11 +433,23 @@ assign BSX_SNES_DATA_IN = SNES_DATA; reg [7:0] SNES_DINr; reg [7:0] ROM_DOUTr; -assign SNES_DATA = (!SNES_READ) ? (srtc_enable ? SRTC_SNES_DATA_OUT +reg [7:0] r213fr; +reg r213f_forceread; +reg [2:0] r213f_delay; +reg [1:0] r213f_state; +initial r213fr = 8'h55; +initial r213f_forceread = 0; +initial r213f_state = 2'b01; +initial r213f_delay = 3'b011; + + +assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr + :(!SNES_READ ^ r213f_forceread) + ? (srtc_enable ? SRTC_SNES_DATA_OUT :dspx_enable ? DSPX_SNES_DATA_OUT - :dspx_dp_enable ? DSPX_SNES_DATA_OUT - :msu_enable ? MSU_SNES_DATA_OUT - :bsx_data_ovr ? BSX_SNES_DATA_OUT + :dspx_dp_enable ? DSPX_SNES_DATA_OUT + :msu_enable ? MSU_SNES_DATA_OUT + :bsx_data_ovr ? BSX_SNES_DATA_OUT :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ; reg [3:0] ST_MEM_DELAYr; @@ -446,14 +477,14 @@ assign MCU_RDY = RQ_MCU_RDYr; always @(posedge CLK2) begin if(MCU_RRQ) begin MCU_RD_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(MCU_WRQ) begin MCU_WR_PENDr <= 1'b1; - RQ_MCU_RDYr <= 1'b0; + RQ_MCU_RDYr <= 1'b0; end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin MCU_RD_PENDr <= 1'b0; - MCU_WR_PENDr <= 1'b0; - RQ_MCU_RDYr <= 1'b1; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; end end @@ -470,7 +501,7 @@ always @(posedge CLK2) begin ROM_ADDRr <= MAPPED_SNES_ADDR; if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; - else STATE <= ST_IDLE; + else STATE <= ST_IDLE; end ST_SNES_RD_ADDR: begin STATE <= ST_SNES_RD_WAIT; @@ -564,7 +595,22 @@ always @(posedge CLK2) begin STATE <= ST_IDLE; end - endcase + endcase + end +end + +always @(posedge SYSCLK2) begin + if(SNES_PARD_start & r213f_enable) begin + r213f_forceread <= 1'b1; + r213f_delay <= 3'b001; + r213f_state <= 2'b10; + end else if(r213f_state == 2'b10) begin + r213f_delay <= r213f_delay - 1; + if(r213f_delay == 3'b000) begin + r213f_forceread <= 1'b0; + r213f_state <= 2'b01; + r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]}; + end end end @@ -595,12 +641,15 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 : msu_enable ? 1'b0 : bsx_data_ovr ? (SNES_READ & SNES_WRITE) : srtc_enable ? (SNES_READ & SNES_WRITE) : + r213f_enable & !SNES_PARD ? 1'b0 : ((IS_ROM & SNES_CS) |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) |(SNES_READ & SNES_WRITE) ); -assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; +assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable)) + ? 1'b1 ^ r213f_forceread + : 1'b0; assign IRQ_DIR = 1'b0; assign SNES_IRQ = 1'bZ; diff --git a/verilog/sd2snes/mcu_cmd.v b/verilog/sd2snes/mcu_cmd.v index 0c843eb..4ccd9e8 100644 --- a/verilog/sd2snes/mcu_cmd.v +++ b/verilog/sd2snes/mcu_cmd.v @@ -91,8 +91,9 @@ module mcu_cmd( output reg dspx_reset_out, // feature enable - output reg [3:0] featurebits_out, + output reg [7:0] featurebits_out, + output reg region_out, // SNES sync/clk input snes_sysclk ); @@ -101,6 +102,7 @@ initial begin dspx_pgm_addr_out = 11'b00000000000; dspx_dat_addr_out = 10'b0000000000; dspx_reset_out = 1'b1; + region_out = 0; end wire [31:0] snes_sysclk_freq; @@ -342,7 +344,9 @@ always @(posedge clk) begin 8'hec: // release DSPx reset dspx_reset_out <= 1'b0; 8'hed: - featurebits_out <= param_data[3:0]; + featurebits_out <= param_data; + 8'hee: + region_out <= param_data[0]; endcase end end From eefcc712cadba203d291cd9ed6505b32fe36fea0 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:21:40 +0100 Subject: [PATCH 57/66] FPGA: add RAM1 pinout to user constraints --- verilog/sd2snes/main.ucf | 92 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index 64577df..4588d4f 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -543,3 +543,95 @@ NET "SD_DAT[3]" IOSTANDARD = LVCMOS33; NET "SNES_SYSCLK" LOC = P180; NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33; +NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK"; +TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %; + +#NET "RAM_DATA[0]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[0]" DRIVE = 8; +#NET "RAM_DATA[0]" LOC = P26; +#NET "RAM_DATA[1]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[1]" DRIVE = 8; +#NET "RAM_DATA[1]" LOC = P22; +#NET "RAM_DATA[2]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[2]" DRIVE = 8; +#NET "RAM_DATA[2]" LOC = P20; +#NET "RAM_DATA[3]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[3]" DRIVE = 8; +#NET "RAM_DATA[3]" LOC = P19; +#NET "RAM_DATA[4]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[4]" DRIVE = 8; +#NET "RAM_DATA[4]" LOC = P21; +#NET "RAM_DATA[5]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[5]" DRIVE = 8; +#NET "RAM_DATA[5]" LOC = P24; +#NET "RAM_DATA[6]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[6]" DRIVE = 8; +#NET "RAM_DATA[6]" LOC = P27; +#NET "RAM_DATA[7]" IOSTANDARD = LVCMOS33; +#NET "RAM_DATA[7]" DRIVE = 8; +#NET "RAM_DATA[7]" LOC = P29; +# +#NET "RAM_OE" IOSTANDARD = LVCMOS33; +#NET "RAM_OE" DRIVE = 8; +#NET "RAM_OE" LOC = P36; +#NET "RAM_WE" IOSTANDARD = LVCMOS33; +#NET "RAM_WE" DRIVE = 8; +#NET "RAM_WE" LOC = P50; +# +#NET "RAM_ADDR[0]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[0]" DRIVE = 8; +#NET "RAM_ADDR[0]" LOC = P28; +#NET "RAM_ADDR[1]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[1]" DRIVE = 8; +#NET "RAM_ADDR[1]" LOC = P31; +#NET "RAM_ADDR[2]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[2]" DRIVE = 8; +#NET "RAM_ADDR[2]" LOC = P33; +#NET "RAM_ADDR[3]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[3]" DRIVE = 8; +#NET "RAM_ADDR[3]" LOC = P35; +#NET "RAM_ADDR[4]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[4]" DRIVE = 8; +#NET "RAM_ADDR[4]" LOC = P37; +#NET "RAM_ADDR[5]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[5]" DRIVE = 8; +#NET "RAM_ADDR[5]" LOC = P40; +#NET "RAM_ADDR[6]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[6]" DRIVE = 8; +#NET "RAM_ADDR[6]" LOC = P43; +#NET "RAM_ADDR[7]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[7]" DRIVE = 8; +#NET "RAM_ADDR[7]" LOC = P45; +#NET "RAM_ADDR[8]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[8]" DRIVE = 8; +#NET "RAM_ADDR[8]" LOC = P44; +#NET "RAM_ADDR[9]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[9]" DRIVE = 8; +#NET "RAM_ADDR[9]" LOC = P42; +#NET "RAM_ADDR[10]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[10]" DRIVE = 8; +#NET "RAM_ADDR[10]" LOC = P34; +#NET "RAM_ADDR[11]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[11]" DRIVE = 8; +#NET "RAM_ADDR[11]" LOC = P39; +#NET "RAM_ADDR[12]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[12]" DRIVE = 8; +#NET "RAM_ADDR[12]" LOC = P48; +#NET "RAM_ADDR[13]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[13]" DRIVE = 8; +#NET "RAM_ADDR[13]" LOC = P46; +#NET "RAM_ADDR[14]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[14]" DRIVE = 8; +#NET "RAM_ADDR[14]" LOC = P51; +#NET "RAM_ADDR[15]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[15]" DRIVE = 8; +#NET "RAM_ADDR[15]" LOC = P58; +#NET "RAM_ADDR[16]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[16]" DRIVE = 8; +#NET "RAM_ADDR[16]" LOC = P57; +#NET "RAM_ADDR[17]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[17]" DRIVE = 8; +#NET "RAM_ADDR[17]" LOC = P61; +#NET "RAM_ADDR[18]" IOSTANDARD = LVCMOS33; +#NET "RAM_ADDR[18]" DRIVE = 8; +#NET "RAM_ADDR[18]" LOC = P52; From a50522b4e90b5c008ac5ce0f8c88f5aea5a3c71f Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 01:22:38 +0100 Subject: [PATCH 58/66] FPGA: optimize non-sector-aligned SD DMA reads --- verilog/sd2snes/main.v | 6 +++++- verilog/sd2snes/mcu_cmd.v | 15 ++++++++++++--- verilog/sd2snes/sd_dma.v | 14 ++++++++++---- 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index e63a5db..027c7df 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -144,7 +144,9 @@ sd_dma snes_sd_dma( .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), .SD_DMA_PARTIAL(SD_DMA_PARTIAL), .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), - .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK), + .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK) ); wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)); @@ -293,6 +295,8 @@ mcu_cmd snes_mcu_cmd( .SD_DMA_PARTIAL(SD_DMA_PARTIAL), .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK), + .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK), .dac_addr_out(dac_addr), .DAC_STATUS(DAC_STATUS), // .dac_volume_out(dac_volume), diff --git a/verilog/sd2snes/mcu_cmd.v b/verilog/sd2snes/mcu_cmd.v index 4ccd9e8..6706087 100644 --- a/verilog/sd2snes/mcu_cmd.v +++ b/verilog/sd2snes/mcu_cmd.v @@ -48,7 +48,9 @@ module mcu_cmd( output SD_DMA_PARTIAL, output [10:0] SD_DMA_PARTIAL_START, output [10:0] SD_DMA_PARTIAL_END, - + output reg SD_DMA_START_MID_BLOCK, + output reg SD_DMA_END_MID_BLOCK, + // DAC output [10:0] dac_addr_out, input DAC_STATUS, @@ -103,6 +105,8 @@ initial begin dspx_dat_addr_out = 10'b0000000000; dspx_reset_out = 1'b1; region_out = 0; + SD_DMA_START_MID_BLOCK = 0; + SD_DMA_END_MID_BLOCK = 0; end wire [31:0] snes_sysclk_freq; @@ -179,6 +183,7 @@ initial begin MSU_ADDR_OUT_BUF = 0; SD_DMA_ENr = 0; MAPPER_BUF = 1; + SD_DMA_PARTIALr = 0; end // command interpretation @@ -221,12 +226,16 @@ always @(posedge clk) begin SD_DMA_ENr <= 1'b0; 8'h6x: case (spi_byte_cnt) - 32'h2: + 32'h2: begin + SD_DMA_START_MID_BLOCK <= param_data[7]; SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0]; + end 32'h3: SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0}; - 32'h4: + 32'h4: begin + SD_DMA_END_MID_BLOCK <= param_data[7]; SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0]; + end 32'h5: SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0}; endcase diff --git a/verilog/sd2snes/sd_dma.v b/verilog/sd2snes/sd_dma.v index 2137370..ad3ace6 100644 --- a/verilog/sd2snes/sd_dma.v +++ b/verilog/sd2snes/sd_dma.v @@ -29,7 +29,9 @@ module sd_dma( output [7:0] SD_DMA_SRAM_DATA, input SD_DMA_PARTIAL, input [10:0] SD_DMA_PARTIAL_START, - input [10:0] SD_DMA_PARTIAL_END + input [10:0] SD_DMA_PARTIAL_END, + input SD_DMA_START_MID_BLOCK, + input SD_DMA_END_MID_BLOCK ); reg [10:0] SD_DMA_STARTr; @@ -85,7 +87,9 @@ always @(posedge CLK) begin end always @(posedge CLK) begin - if(cyclecnt == 1042) SD_DMA_DONEr <= 1; + if(cyclecnt == 1042 + || ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END)) + SD_DMA_DONEr <= 1; else SD_DMA_DONEr <= 0; end @@ -100,8 +104,10 @@ always @(posedge CLK) begin end always @(posedge CLK) begin - if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0; - else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1; + if(SD_DMA_EN_rising) + cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0; + else if(!SD_DMA_STATUSr) cyclecnt <= 0; + else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1; end // we have 8 clk cycles to complete one RAM write From 3243143c3965dcae2669f67ac9beea3511011eb9 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 02:19:39 +0100 Subject: [PATCH 59/66] FPGA/Cx4: region override (patch register $213f) --- verilog/sd2snes_cx4/address.v | 11 ++++++- verilog/sd2snes_cx4/main.v | 59 +++++++++++++++++++++++++++++++---- 2 files changed, 63 insertions(+), 7 deletions(-) diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v index 1ec0902..bbd74ac 100644 --- a/verilog/sd2snes_cx4/address.v +++ b/verilog/sd2snes_cx4/address.v @@ -21,6 +21,7 @@ module address( input CLK, input [2:0] MAPPER, // MCU detected mapper input [23:0] SNES_ADDR, // requested address from SNES + input [7:0] SNES_PA, // peripheral address from SNES input SNES_CS, // SNES ROMSEL signal output [23:0] ROM_ADDR, // Address to request from SRAM0 output ROM_SEL, // enable SRAM0 (active low) @@ -32,7 +33,8 @@ module address( input use_msu1, output msu_enable, output cx4_enable, - output cx4_vect_enable + output cx4_vect_enable, + output r213f_enable ); wire [23:0] SRAM_SNES_ADDR; @@ -64,4 +66,11 @@ always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w}; assign cx4_enable = &cx4_enable_r[5:2]; assign cx4_vect_enable = &SNES_ADDR[15:5]; + +wire r213f_enable_w = (SNES_PA == 8'h3f); +reg [5:0] r213f_enable_r; +initial r213f_enable_r = 6'b000000; +always @(posedge CLK) r213f_enable_r <= {r213f_enable_r[4:0], r213f_enable_w}; +assign r213f_enable = &r213f_enable_r[5:2]; + endmodule diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index 9e564dc..7142dc1 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -35,6 +35,10 @@ module main( output SNES_DATABUS_DIR, input SNES_SYSCLK, + input [7:0] SNES_PA, + input SNES_PARD, + input SNES_PAWR, + /* SRAM signals */ /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */ inout [15:0] ROM_DATA, @@ -234,7 +238,8 @@ mcu_cmd snes_mcu_cmd( .cx4_datrom_addr_out(cx4_datrom_addr), .cx4_datrom_data_out(cx4_datrom_data), .cx4_datrom_we_out(cx4_datrom_we), - .cx4_reset_out(cx4_reset) + .cx4_reset_out(cx4_reset), + .region_out(mcu_region) ); wire [7:0] DCM_STATUS; @@ -247,17 +252,29 @@ my_dcm snes_dcm( .STATUS(DCM_STATUS) ); +my_dcm snes_dcm2( + .CLKIN(SNES_SYSCLK), + .CLKFX(SYSCLK2), + .RST(DCM_RST) +); + assign DCM_RST=0; +reg [5:0] SNES_PARDr; reg [5:0] SNES_READr; reg [5:0] SNES_WRITEr; reg [5:0] SNES_CPU_CLKr; +wire SNES_PARD_start = (SNES_PARDr == 6'b111110); wire SNES_RD_start = (SNES_READr == 6'b111110); wire SNES_WR_start = (SNES_WRITEr == 6'b111110); wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); +always @(posedge SYSCLK2) begin + SNES_PARDr <= {SNES_PARDr[4:0], SNES_PARD}; +end + always @(posedge CLK2) begin SNES_READr <= {SNES_READr[4:0], SNES_READ}; SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; @@ -268,6 +285,7 @@ address snes_addr( .CLK(CLK2), .MAPPER(MAPPER), .SNES_ADDR(SNES_ADDR), // requested address from SNES + .SNES_PA(SNES_PA), .SNES_CS(SNES_CS), .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) .ROM_SEL(ROM_SEL), // which SRAM unit to access @@ -281,7 +299,8 @@ address snes_addr( .msu_enable(msu_enable), //CX4 .cx4_enable(cx4_enable), - .cx4_vect_enable(cx4_vect_enable) + .cx4_vect_enable(cx4_vect_enable), + .r213f_enable(r213f_enable) ); reg [7:0] CX4_DINr; @@ -347,11 +366,21 @@ assign CX4_SNES_DATA_IN = SNES_DATA; reg [7:0] SNES_DINr; reg [7:0] ROM_DOUTr; -assign SNES_DATA = (!SNES_READ) - ? (msu_enable ? MSU_SNES_DATA_OUT +reg [7:0] r213fr; +reg r213f_forceread; +reg [2:0] r213f_delay; +reg [1:0] r213f_state; +initial r213fr = 8'h55; +initial r213f_forceread = 0; +initial r213f_state = 2'b01; +initial r213f_delay = 3'b011; + +assign SNES_DATA = (r213f_enable & (!SNES_PARD ^ r213f_forceread)) ? r213fr + :(!SNES_READ ^ r213f_forceread) + ? (msu_enable ? MSU_SNES_DATA_OUT :cx4_enable ? CX4_SNES_DATA_OUT :(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT - : SNES_DINr) + :SNES_DINr) : 8'bZ; reg [3:0] ST_MEM_DELAYr; @@ -539,6 +568,21 @@ always @(posedge CLK2) begin end end +always @(posedge SYSCLK2) begin + if(SNES_PARD_start & r213f_enable) begin + r213f_forceread <= 1'b1; + r213f_delay <= 3'b001; + r213f_state <= 2'b10; + end else if(r213f_state == 2'b10) begin + r213f_delay <= r213f_delay - 1; + if(r213f_delay == 3'b000) begin + r213f_forceread <= 1'b0; + r213f_state <= 2'b01; + r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]}; + end + end +end + assign ROM_DATA[7:0] = ROM_ADDR0 ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) : (!ROM_WE ? ROM_DOUTr : 8'bZ) @@ -565,11 +609,14 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; assign SNES_DATABUS_OE = msu_enable ? 1'b0 : cx4_enable ? 1'b0 : (cx4_active & cx4_vect_enable) ? 1'b0 : + r213f_enable & !SNES_PARD ? 1'b0 : ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE) |(SNES_READ & SNES_WRITE) ); -assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; +assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable)) + ? 1'b1 ^ r213f_forceread + : 1'b0; assign IRQ_DIR = 1'b0; assign SNES_IRQ = 1'bZ; From 059966f06a60b42ad8c83dfbd8c7b3ce02c12c0c Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 02:21:01 +0100 Subject: [PATCH 60/66] FPGA/Cx4: optimize non-sector-aligned SD DMA reads --- verilog/sd2snes_cx4/main.v | 6 +++++- verilog/sd2snes_cx4/sd_dma.v | 14 ++++++++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v index 7142dc1..25382ca 100644 --- a/verilog/sd2snes_cx4/main.v +++ b/verilog/sd2snes_cx4/main.v @@ -125,7 +125,9 @@ sd_dma snes_sd_dma( .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), .SD_DMA_PARTIAL(SD_DMA_PARTIAL), .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), - .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK), + .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK) ); wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)); @@ -215,6 +217,8 @@ mcu_cmd snes_mcu_cmd( .SD_DMA_PARTIAL(SD_DMA_PARTIAL), .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK), + .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK), .dac_addr_out(dac_addr), .DAC_STATUS(DAC_STATUS), // .dac_volume_out(dac_volume), diff --git a/verilog/sd2snes_cx4/sd_dma.v b/verilog/sd2snes_cx4/sd_dma.v index 2137370..ad3ace6 100644 --- a/verilog/sd2snes_cx4/sd_dma.v +++ b/verilog/sd2snes_cx4/sd_dma.v @@ -29,7 +29,9 @@ module sd_dma( output [7:0] SD_DMA_SRAM_DATA, input SD_DMA_PARTIAL, input [10:0] SD_DMA_PARTIAL_START, - input [10:0] SD_DMA_PARTIAL_END + input [10:0] SD_DMA_PARTIAL_END, + input SD_DMA_START_MID_BLOCK, + input SD_DMA_END_MID_BLOCK ); reg [10:0] SD_DMA_STARTr; @@ -85,7 +87,9 @@ always @(posedge CLK) begin end always @(posedge CLK) begin - if(cyclecnt == 1042) SD_DMA_DONEr <= 1; + if(cyclecnt == 1042 + || ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END)) + SD_DMA_DONEr <= 1; else SD_DMA_DONEr <= 0; end @@ -100,8 +104,10 @@ always @(posedge CLK) begin end always @(posedge CLK) begin - if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0; - else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1; + if(SD_DMA_EN_rising) + cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0; + else if(!SD_DMA_STATUSr) cyclecnt <= 0; + else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1; end // we have 8 clk cycles to complete one RAM write From d139fdb40cc400577712156a5fe3defc22f14d25 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 02:22:42 +0100 Subject: [PATCH 61/66] SNES menu: helper script for map creation --- snes/Makefile | 12 ++++++++---- snes/data.a65 | 1 + snes/header.a65 | 12 +++++++++++- snes/utils/mkmap.sh | 24 ++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 5 deletions(-) create mode 100755 snes/utils/mkmap.sh diff --git a/snes/Makefile b/snes/Makefile index 079b43e..253cac4 100644 --- a/snes/Makefile +++ b/snes/Makefile @@ -1,19 +1,23 @@ OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 # gfx.o65 # vars.o65 -all: menu.bin +all: clean menu.bin map smc: menu.bin cat menu.bin sd2snes.rom > menu.smc + +map: menu.bin + utils/mkmap.sh $(OBJS) + menu.bin: $(OBJS) - sneslink -fsmc -o $@ $^ + sneslink -fsmc -o $@ $^ 2>&1 | tee link.log # Generic rule to create .o65 out from .a65 %.o65: %.a65 - snescom -J -Wall -o $@ $< + snescom -J -Wall -o $@ $< 2>&1 | tee $@.log # Generic rule to create .ips out from .a65 %.ips: %.a65 - snescom -I -J -Wall -o $@ $< + snescom -I -J -Wall -o $@ $< 2>&1 | tee $@.log clean: rm -f *.ips *.o65 *~ menu.bin diff --git a/snes/data.a65 b/snes/data.a65 index df04d5d..6f7abd5 100644 --- a/snes/data.a65 +++ b/snes/data.a65 @@ -1,3 +1,4 @@ +*=$7E0000 .data ;don't anger the stack! dirptr_addr .word 0 diff --git a/snes/header.a65 b/snes/header.a65 index d33cd62..02d6c73 100644 --- a/snes/header.a65 +++ b/snes/header.a65 @@ -1,6 +1,16 @@ -; This file is part of the snescom-asm demo - a demo of how to build a SNES program. +; This file is a modified version of the header.a65 file from: +; snescom-asm demo - a demo of how to build a SNES program. ; See http://bisqwit.iki.fi/source/snescom.html for details. +; fill whole area beforehand so the linker does not create multiple +; objects from it. (necessary for map creation) + +*= $C0FF00 + .word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + ; Begin assembling to this address. *= $C0FF00 diff --git a/snes/utils/mkmap.sh b/snes/utils/mkmap.sh new file mode 100755 index 0000000..b133c3b --- /dev/null +++ b/snes/utils/mkmap.sh @@ -0,0 +1,24 @@ +#!/bin/bash + +args=("$@") +objcount=0 + +grep object_ link.log | \ +sed -e 's/object_//g; s/_code//g; s/_data//g' | \ +while read obj; do + objcount=$((objcount+1)) + read base idx <<< "$obj" + base="0x${base}" + fn=${args[$idx-1]} + echo ======$fn, base=$base====== > ${fn%%.*}.map + sed -e '/^Externs/,$d;/^Labels/d' < $fn.log | \ + while read line; do + read addr label <<< "$line" + addr="0x$addr" + decaddr=`printf "%d" $addr` + [ "$decaddr" -gt "65535" ] && base=0 + ea=`printf "%X" $((base+addr))` + echo $ea $label >> ${fn%%.*}.map + done +done + From 2d89eb8000416c65b86fb949ade04a12abdca484 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 02:23:43 +0100 Subject: [PATCH 62/66] SNES menu: swap A and B buttons --- snes/const.a65 | 4 ++-- snes/data.a65 | 1 + snes/mainmenu.a65 | 12 ++++++------ snes/menu.a65 | 8 ++++---- snes/time.a65 | 17 +++++++++++++++-- 5 files changed, 28 insertions(+), 14 deletions(-) diff --git a/snes/const.a65 b/snes/const.a65 index 02d27a6..add69a7 100644 --- a/snes/const.a65 +++ b/snes/const.a65 @@ -139,7 +139,7 @@ window_ev .byt 27 window_tl .byt 28 window_tr .byt 29 text_clkset .byt "Please set the clock.", 0 -text_buttonB .byt "Dpad: sel/chg, B: OK", 0 +text_buttonB .byt "Dpad: sel/chg, A: OK", 0 time_win_x .byt 18 time_win_y .byt 15 time_win_w .byt 27 @@ -161,4 +161,4 @@ text_mm_scic .byt "Enable SuperCIC", 0 text_mm_vmode_menu .byt "Menu video mode", 0 text_mm_vmode_game .byt "Game video mode", 0 text_mm_sysinfo .byt "System Information", 0 -text_statusbar_keys .byt "B:Select A:Back X:Menu", 0 +text_statusbar_keys .byt "A:Select B:Back X:Menu", 0 diff --git a/snes/data.a65 b/snes/data.a65 index 6f7abd5..e14798e 100644 --- a/snes/data.a65 +++ b/snes/data.a65 @@ -78,6 +78,7 @@ time_y10 .byt 0 time_y100 .byt 0 time_sel .byt 0 time_exit .byt 0 +time_cancel .byt 0 time_ptr .byt 0 time_tmp .byt 0 ;-- diff --git a/snes/mainmenu.a65 b/snes/mainmenu.a65 index 06f7d4e..760efd2 100644 --- a/snes/mainmenu.a65 +++ b/snes/mainmenu.a65 @@ -120,13 +120,13 @@ mm_menuloop and pad1trig+1 bne mmkey_b bra mm_menuloop -mmkey_a +mmkey_b jsr restore_screen plp rts -mmkey_b - jsr mmkey_b_2 +mmkey_a + jsr mmkey_a_2 jmp mm_redraw mmkey_down @@ -156,10 +156,10 @@ mmkey_up_2 + rts -mmkey_b_2 +mmkey_a_2 jsr restore_screen phk ; push return bank for subroutine - per mmkey_b_2_return-1 ; push return addr for subroutine + per mmkey_a_2_return-1 ; push return addr for subroutine xba lda #$00 xba @@ -175,7 +175,7 @@ mmkey_b_2 pha ; push subroutine addr sep #$20 : .as rtl ; jump to subroutine -mmkey_b_2_return +mmkey_a_2_return rts mm_do_refresh diff --git a/snes/menu.a65 b/snes/menu.a65 index ccf2f41..0837533 100644 --- a/snes/menu.a65 +++ b/snes/menu.a65 @@ -442,7 +442,7 @@ menu_key_right: sep #$20 : .as rts -menu_key_b: +menu_key_a: jsr select_item rts @@ -456,15 +456,15 @@ do_setup448 jsr setup_448 rts -menu_key_a: +menu_key_b: rep #$20 : .al lda dirstart_addr - beq skip_key_a + beq skip_key_b sta dirptr_addr lda #$0000 sta menu_sel bra select_item -skip_key_a +skip_key_b sep #$20 : .as rts diff --git a/snes/time.a65 b/snes/time.a65 index 669253b..35ace85 100644 --- a/snes/time.a65 +++ b/snes/time.a65 @@ -2,7 +2,7 @@ #include "dma.i65" timebox_data - ; string offset, selection width, bcdtime offset, 1s limit, 10s limit + ; string offset, selection width, bcdtime offset .byt 0, 4, 9 .byt 5, 2, 8 .byt 8, 2, 6 @@ -46,6 +46,7 @@ time_init: jsr gettime stz time_sel stz time_exit + stz time_cancel lda #^text_buttonB sta print_bank ldx #!text_buttonB @@ -120,17 +121,29 @@ timeloop1 lda #$80 and pad1trig+1 bne tkey_b + lda #$80 + and pad1trig + bne tkey_a ; do stuff lda time_exit - beq timeloop1 + bne timesave ; set clock + lda time_cancel + bne timenosave + beq timeloop1 +timesave jsr settime +timenosave ; restore text area jsr restore_screen plp rtl tkey_b + inc time_cancel + jmp time_update + +tkey_a inc time_exit jmp time_update From d7ad74084393e5d7a61dbb550302ddc8e22aafa1 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 02:25:34 +0100 Subject: [PATCH 63/66] FPGA/Cx4: add missing file main.ucf --- verilog/sd2snes_cx4/main.ucf | 606 +++++++++++++++++++++++++++++++++++ 1 file changed, 606 insertions(+) create mode 100644 verilog/sd2snes_cx4/main.ucf diff --git a/verilog/sd2snes_cx4/main.ucf b/verilog/sd2snes_cx4/main.ucf new file mode 100644 index 0000000..cac7a2a --- /dev/null +++ b/verilog/sd2snes_cx4/main.ucf @@ -0,0 +1,606 @@ +NET "CLKIN" TNM_NET = "CLKIN"; +TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %; +//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %; +NET "p113_out" IOSTANDARD = LVCMOS33; +NET "p113_out" LOC = P113; + +NET "SNES_SYSCLK" LOC = P180; +NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33; +NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK"; +TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %; + +NET "SPI_SCK" LOC = P71; +NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE; +NET "SPI_SCK" TNM_NET = "SPI_SCK"; +TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48MHz HIGH 50 %; + +NET "SPI_SCK" IOSTANDARD = LVCMOS33; +NET "SPI_SCK" DRIVE = 8; +NET "SPI_SCK" PULLUP; + +NET "SNES_CS" IOSTANDARD = LVCMOS33; +NET "SNES_READ" IOSTANDARD = LVCMOS33; +NET "SNES_WRITE" IOSTANDARD = LVCMOS33; +NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33; +NET "SNES_REFRESH" IOSTANDARD = LVCMOS33; + +NET "CLKIN" IOSTANDARD = LVCMOS33; +//NET "CLKIN" PULLUP; +NET "SPI_SS" PULLUP; +//NET "DCM_RST" LOC = P46; +//NET "DCM_RST" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33; +NET "SNES_IRQ" IOSTANDARD = LVCMOS33; + +NET "ROM_CE" LOC = P172; +NET "ROM_CE" IOSTANDARD = LVCMOS33; +NET "ROM_CE" DRIVE = 8; + +NET "SNES_ADDR[0]" LOC = P119; +NET "SNES_ADDR[10]" LOC = P146; +NET "SNES_ADDR[11]" LOC = P148; +NET "SNES_ADDR[12]" LOC = P147; +NET "SNES_ADDR[13]" LOC = P144; +NET "SNES_ADDR[14]" LOC = P141; +NET "SNES_ADDR[15]" LOC = P139; +NET "SNES_ADDR[16]" LOC = P137; +NET "SNES_ADDR[17]" LOC = P133; +NET "SNES_ADDR[18]" LOC = P131; +NET "SNES_ADDR[19]" LOC = P128; +NET "SNES_ADDR[1]" LOC = P122; +NET "SNES_ADDR[20]" LOC = P125; +NET "SNES_ADDR[21]" LOC = P123; +NET "SNES_ADDR[22]" LOC = P120; +NET "SNES_ADDR[23]" LOC = P117; +NET "SNES_ADDR[2]" LOC = P124; +NET "SNES_ADDR[3]" LOC = P126; +NET "SNES_ADDR[4]" LOC = P130; +NET "SNES_ADDR[5]" LOC = P132; +NET "SNES_ADDR[6]" LOC = P135; +NET "SNES_ADDR[7]" LOC = P138; +NET "SNES_ADDR[8]" LOC = P140; +NET "SNES_ADDR[9]" LOC = P143; +NET "SNES_DATA[0]" LOC = P107; +NET "SNES_DATA[1]" LOC = P102; +NET "SNES_DATA[2]" LOC = P100; +NET "SNES_DATA[3]" LOC = P96; +NET "SNES_DATA[4]" LOC = P108; +NET "SNES_DATA[5]" LOC = P106; +NET "SNES_DATA[6]" LOC = P101; +NET "SNES_DATA[7]" LOC = P97; + + +NET "CLKIN" LOC = P80; +// NET "RST" LOC = P113; +NET "MCU_OVR" LOC = P92; + + +NET "MCU_OVR" IOSTANDARD = LVCMOS33; +NET "MCU_OVR" DRIVE = 8; + +NET "MCU_RDY" LOC = P83; +NET "MCU_RDY" IOSTANDARD = LVCMOS33; +NET "MCU_RDY" DRIVE = 8; + + +NET "ROM_ADDR[0]" LOC = P166; + + +NET "ROM_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[0]" DRIVE = 8; + + +NET "ROM_ADDR[10]" LOC = P197; + + +NET "ROM_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[10]" DRIVE = 8; + + +NET "ROM_ADDR[11]" LOC = P196; + + +NET "ROM_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[11]" DRIVE = 8; + + +NET "ROM_ADDR[12]" LOC = P2; + + +NET "ROM_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[12]" DRIVE = 8; + + +NET "ROM_ADDR[13]" LOC = P194; + + +NET "ROM_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[13]" DRIVE = 8; + + +NET "ROM_ADDR[14]" LOC = P200; + + +NET "ROM_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[14]" DRIVE = 8; + + +NET "ROM_ADDR[15]" LOC = P184; + + +NET "ROM_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[15]" DRIVE = 8; + + +NET "ROM_ADDR[16]" LOC = P199; + + +NET "ROM_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[16]" DRIVE = 8; + + +NET "ROM_ADDR[17]" LOC = P11; + + +NET "ROM_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[17]" DRIVE = 8; + + +NET "ROM_ADDR[18]" LOC = P3; + + +NET "ROM_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[18]" DRIVE = 8; + + +NET "ROM_ADDR[19]" LOC = P4; + + +NET "ROM_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[19]" DRIVE = 8; + + +NET "ROM_ADDR[1]" LOC = P168; + + +NET "ROM_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[1]" DRIVE = 8; + + +NET "ROM_ADDR[20]" LOC = P191; + + +NET "ROM_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[20]" DRIVE = 8; + + +NET "ROM_ADDR[21]" LOC = P203; + + +NET "ROM_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[21]" DRIVE = 8; + + +NET "ROM_ADDR[22]" LOC = P198; + + +NET "ROM_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[22]" DRIVE = 8; + + +NET "ROM_ADDR[2]" LOC = P171; + + +NET "ROM_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[2]" DRIVE = 8; + + +NET "ROM_ADDR[3]" LOC = P165; + + +NET "ROM_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[3]" DRIVE = 8; + + +NET "ROM_ADDR[4]" LOC = P169; + + +NET "ROM_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[4]" DRIVE = 8; + + +NET "ROM_ADDR[5]" LOC = P18; + + +NET "ROM_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[5]" DRIVE = 8; + + +NET "ROM_ADDR[6]" LOC = P175; + + +NET "ROM_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[6]" DRIVE = 8; + + +NET "ROM_ADDR[7]" LOC = P167; + + +NET "ROM_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[7]" DRIVE = 8; + + +NET "ROM_ADDR[8]" LOC = P205; + + +NET "ROM_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[8]" DRIVE = 8; + + +NET "ROM_ADDR[9]" LOC = P204; + + +NET "ROM_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[9]" DRIVE = 8; + + +NET "ROM_BHE" LOC = P161; + + +NET "ROM_BHE" IOSTANDARD = LVCMOS33; +NET "ROM_BHE" DRIVE = 8; + + +NET "ROM_BLE" LOC = P156; + + +NET "ROM_BLE" IOSTANDARD = LVCMOS33; +NET "ROM_BLE" DRIVE = 8; + + +NET "ROM_DATA[0]" LOC = P176; + + +NET "ROM_DATA[0]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[0]" DRIVE = 8; + + +NET "ROM_DATA[10]" LOC = P15; + + +NET "ROM_DATA[10]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[10]" DRIVE = 8; + + +NET "ROM_DATA[11]" LOC = P12; + + +NET "ROM_DATA[11]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[11]" DRIVE = 8; + + +NET "ROM_DATA[12]" LOC = P10; + + +NET "ROM_DATA[12]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[12]" DRIVE = 8; + + +NET "ROM_DATA[13]" LOC = P7; + + +NET "ROM_DATA[13]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[13]" DRIVE = 8; + + +NET "ROM_DATA[14]" LOC = P9; + + +NET "ROM_DATA[14]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[14]" DRIVE = 8; + + +NET "ROM_DATA[15]" LOC = P5; + + +NET "ROM_DATA[15]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[15]" DRIVE = 8; + + +NET "ROM_DATA[1]" LOC = P178; + + +NET "ROM_DATA[1]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[1]" DRIVE = 8; + + +NET "ROM_DATA[2]" LOC = P181; + + +NET "ROM_DATA[2]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[2]" DRIVE = 8; + + +NET "ROM_DATA[3]" LOC = P182; + + +NET "ROM_DATA[3]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[3]" DRIVE = 8; + + +NET "ROM_DATA[4]" LOC = P183; + + +NET "ROM_DATA[4]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[4]" DRIVE = 8; + + +NET "ROM_DATA[5]" LOC = P187; + + +NET "ROM_DATA[5]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[5]" DRIVE = 8; + + +NET "ROM_DATA[6]" LOC = P185; + + +NET "ROM_DATA[6]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[6]" DRIVE = 8; + + +NET "ROM_DATA[7]" LOC = P189; + + +NET "ROM_DATA[7]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[7]" DRIVE = 8; + + +NET "ROM_DATA[8]" LOC = P16; + + +NET "ROM_DATA[8]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[8]" DRIVE = 8; + + +NET "ROM_DATA[9]" LOC = P13; + + +NET "ROM_DATA[9]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[9]" DRIVE = 8; + + +NET "ROM_OE" LOC = P162; + + +NET "ROM_OE" IOSTANDARD = LVCMOS33; +NET "ROM_OE" DRIVE = 8; + + +NET "ROM_WE" LOC = P190; + + +NET "ROM_WE" IOSTANDARD = LVCMOS33; +NET "ROM_WE" DRIVE = 8; +NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[0]" DRIVE = 8; +NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[10]" DRIVE = 8; +NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[11]" DRIVE = 8; +NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[12]" DRIVE = 8; +NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[13]" DRIVE = 8; +NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[14]" DRIVE = 8; +NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[15]" DRIVE = 8; +NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[16]" DRIVE = 8; +NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[17]" DRIVE = 8; +NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[18]" DRIVE = 8; +NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[19]" DRIVE = 8; +NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[1]" DRIVE = 8; +NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[20]" DRIVE = 8; +NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[21]" DRIVE = 8; +NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[22]" DRIVE = 8; +NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[23]" DRIVE = 8; +NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[2]" DRIVE = 8; +NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[3]" DRIVE = 8; +NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[4]" DRIVE = 8; +NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[5]" DRIVE = 8; +NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[6]" DRIVE = 8; +NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[7]" DRIVE = 8; +NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[8]" DRIVE = 8; +NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[9]" DRIVE = 8; + + +NET "SNES_CPU_CLK" LOC = P95; +NET "SNES_CS" LOC = P116; +NET "SNES_DATABUS_DIR" LOC = P111; +NET "SNES_DATABUS_OE" LOC = P109; +NET "SNES_DATABUS_DIR" DRIVE = 8; +NET "SNES_DATABUS_OE" DRIVE = 8; + + +NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[0]" DRIVE = 8; +NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[1]" DRIVE = 8; +NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[2]" DRIVE = 8; +NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[3]" DRIVE = 8; +NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[4]" DRIVE = 8; +NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[5]" DRIVE = 8; +NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[6]" DRIVE = 8; +NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[7]" DRIVE = 8; + + +NET "SNES_IRQ" LOC = P114; +NET "SNES_READ" LOC = P115; +NET "SNES_REFRESH" LOC = P155; +NET "SNES_WRITE" LOC = P94; + +NET "SNES_PA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[0]" LOC = P90; +NET "SNES_PA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[1]" LOC = P93; +NET "SNES_PA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[2]" LOC = P86; +NET "SNES_PA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[3]" LOC = P87; +NET "SNES_PA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[4]" LOC = P81; +NET "SNES_PA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[5]" LOC = P85; +NET "SNES_PA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[6]" LOC = P152; +NET "SNES_PA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_PA[7]" LOC = P154; + +NET "SNES_PARD" IOSTANDARD = LVCMOS33; +NET "SNES_PARD" LOC = P149; +NET "SNES_PAWR" IOSTANDARD = LVCMOS33; +NET "SNES_PAWR" LOC = P150; + +NET "SPI_MISO" LOC = P72; + + +NET "SPI_MISO" IOSTANDARD = LVCMOS33; +NET "SPI_MISO" DRIVE = 8; + + +NET "SPI_MOSI" LOC = P74; + + +NET "SPI_MOSI" IOSTANDARD = LVCMOS33; +NET "SPI_MOSI" DRIVE = 8; + + +NET "SPI_SS" LOC = P68; + + +NET "SPI_SS" IOSTANDARD = LVCMOS33; +NET "SPI_SS" DRIVE = 8; + + +NET "DAC_LRCK" LOC = P77; + + +NET "DAC_LRCK" IOSTANDARD = LVCMOS33; +NET "DAC_LRCK" DRIVE = 8; + + +NET "DAC_MCLK" LOC = P76; + + +NET "DAC_MCLK" IOSTANDARD = LVCMOS33; +NET "DAC_MCLK" DRIVE = 8; + + +NET "DAC_SDOUT" LOC = P78; + + +NET "DAC_SDOUT" IOSTANDARD = LVCMOS33; +NET "DAC_SDOUT" DRIVE = 8; + +# PlanAhead Generated physical constraints +NET "SD_CLK" LOC = P64; +NET "SD_CMD" LOC = P67; +NET "SD_DAT[0]" LOC = P65; +NET "SD_DAT[1]" LOC = P79; +NET "SD_DAT[2]" LOC = P62; +NET "SD_DAT[3]" LOC = P63; + +# PlanAhead Generated IO constraints +NET "SD_CLK" IOSTANDARD = LVCMOS33; +NET "SD_CMD" IOSTANDARD = LVCMOS33; +NET "SD_DAT[0]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[1]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[2]" IOSTANDARD = LVCMOS33; +NET "SD_DAT[3]" IOSTANDARD = LVCMOS33; + +NET "SNES_SYSCLK" LOC = P180; +NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +TIMEGRP "msu_track_out_r" = FFS("snes_msu/track_out_r<0>") FFS("snes_msu/track_out_r<1>") FFS("snes_msu/track_out_r<2>") FFS("snes_msu/track_out_r<3>") FFS("snes_msu/track_out_r<4>") FFS("snes_msu/track_out_r<5>") FFS("snes_msu/track_out_r<6>") FFS("snes_msu/track_out_r<7>") FFS("snes_msu/track_out_r<8>") FFS("snes_msu/track_out_r<9>") FFS("snes_msu/track_out_r<10>") FFS("snes_msu/track_out_r<11>") FFS("snes_msu/track_out_r<12>") FFS("snes_msu/track_out_r<13>") FFS("snes_msu/track_out_r<14>") FFS("snes_msu/track_out_r<15>"); +TIMEGRP "msu_addr_r" = FFS("snes_msu/addr_out_r<0>") FFS("snes_msu/addr_out_r<1>") FFS("snes_msu/addr_out_r<2>") FFS("snes_msu/addr_out_r<3>") FFS("snes_msu/addr_out_r<4>") FFS("snes_msu/addr_out_r<5>") FFS("snes_msu/addr_out_r<6>") FFS("snes_msu/addr_out_r<7>") FFS("snes_msu/addr_out_r<8>") FFS("snes_msu/addr_out_r<9>") FFS("snes_msu/addr_out_r<10>") FFS("snes_msu/addr_out_r<11>") FFS("snes_msu/addr_out_r<12>") FFS("snes_msu/addr_out_r<13>") FFS("snes_msu/addr_out_r<14>") FFS("snes_msu/addr_out_r<15>") FFS("snes_msu/addr_out_r<16>") FFS("snes_msu/addr_out_r<17>") FFS("snes_msu/addr_out_r<18>") FFS("snes_msu/addr_out_r<19>") FFS("snes_msu/addr_out_r<20>") FFS("snes_msu/addr_out_r<21>") FFS("snes_msu/addr_out_r<22>") FFS("snes_msu/addr_out_r<23>") FFS("snes_msu/addr_out_r<24>") FFS("snes_msu/addr_out_r<25>") FFS("snes_msu/addr_out_r<26>") FFS("snes_msu/addr_out_r<27>") FFS("snes_msu/addr_out_r<28>") FFS("snes_msu/addr_out_r<29>") FFS("snes_msu/addr_out_r<30>") FFS("snes_msu/addr_out_r<31>"); +TIMEGRP "mcu_cmd_msu_addr_out" = FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<0>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<1>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<2>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<3>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<4>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<5>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<6>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<7>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<8>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<9>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<10>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<11>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<12>") FFS("snes_mcu_cmd/MSU_ADDR_OUT_BUF<13>"); +TIMEGRP "cx4_cache_src_addr" = FFS("snes_cx4/CACHE_SRC_ADDRr<0>") FFS("snes_cx4/CACHE_SRC_ADDRr<1>") FFS("snes_cx4/CACHE_SRC_ADDRr<2>") FFS("snes_cx4/CACHE_SRC_ADDRr<3>") FFS("snes_cx4/CACHE_SRC_ADDRr<4>") FFS("snes_cx4/CACHE_SRC_ADDRr<5>") FFS("snes_cx4/CACHE_SRC_ADDRr<6>") FFS("snes_cx4/CACHE_SRC_ADDRr<7>") FFS("snes_cx4/CACHE_SRC_ADDRr<8>") FFS("snes_cx4/CACHE_SRC_ADDRr<9>") FFS("snes_cx4/CACHE_SRC_ADDRr<10>") FFS("snes_cx4/CACHE_SRC_ADDRr<11>") FFS("snes_cx4/CACHE_SRC_ADDRr<12>") FFS("snes_cx4/CACHE_SRC_ADDRr<13>") FFS("snes_cx4/CACHE_SRC_ADDRr<14>") FFS("snes_cx4/CACHE_SRC_ADDRr<15>") FFS("snes_cx4/CACHE_SRC_ADDRr<16>") FFS("snes_cx4/CACHE_SRC_ADDRr<17>") FFS("snes_cx4/CACHE_SRC_ADDRr<18>") FFS("snes_cx4/CACHE_SRC_ADDRr<19>") FFS("snes_cx4/CACHE_SRC_ADDRr<20>") FFS("snes_cx4/CACHE_SRC_ADDRr<21>") FFS("snes_cx4/CACHE_SRC_ADDRr<22>") FFS("snes_cx4/CACHE_SRC_ADDRr<23>"); +TIMEGRP "cx4_cpu_busaddr" = FFS("snes_cx4/cpu_busaddr<0>") FFS("snes_cx4/cpu_busaddr<1>") FFS("snes_cx4/cpu_busaddr<2>") FFS("snes_cx4/cpu_busaddr<3>") FFS("snes_cx4/cpu_busaddr<4>") FFS("snes_cx4/cpu_busaddr<5>") FFS("snes_cx4/cpu_busaddr<6>") FFS("snes_cx4/cpu_busaddr<7>") FFS("snes_cx4/cpu_busaddr<8>") FFS("snes_cx4/cpu_busaddr<9>") FFS("snes_cx4/cpu_busaddr<10>") FFS("snes_cx4/cpu_busaddr<11>") FFS("snes_cx4/cpu_busaddr<12>") FFS("snes_cx4/cpu_busaddr<13>") FFS("snes_cx4/cpu_busaddr<14>") FFS("snes_cx4/cpu_busaddr<15>") FFS("snes_cx4/cpu_busaddr<16>") FFS("snes_cx4/cpu_busaddr<17>") FFS("snes_cx4/cpu_busaddr<18>") FFS("snes_cx4/cpu_busaddr<19>") FFS("snes_cx4/cpu_busaddr<20>") FFS("snes_cx4/cpu_busaddr<21>") FFS("snes_cx4/cpu_busaddr<22>") FFS("snes_cx4/cpu_busaddr<23>"); +TIMEGRP "cx4_cpu_ramaddr" = FFS("snes_cx4/cpu_ramaddr<0>") FFS("snes_cx4/cpu_ramaddr<1>") FFS("snes_cx4/cpu_ramaddr<2>") FFS("snes_cx4/cpu_ramaddr<3>") FFS("snes_cx4/cpu_ramaddr<4>") FFS("snes_cx4/cpu_ramaddr<5>") FFS("snes_cx4/cpu_ramaddr<6>") FFS("snes_cx4/cpu_ramaddr<7>") FFS("snes_cx4/cpu_ramaddr<8>") FFS("snes_cx4/cpu_ramaddr<9>") FFS("snes_cx4/cpu_ramaddr<10>") FFS("snes_cx4/cpu_ramaddr<11>") FFS("snes_cx4/cpu_ramaddr<12>") FFS("snes_cx4/cpu_ramaddr<13>") FFS("snes_cx4/cpu_ramaddr<14>") FFS("snes_cx4/cpu_ramaddr<15>") FFS("snes_cx4/cpu_ramaddr<16>") FFS("snes_cx4/cpu_ramaddr<17>") FFS("snes_cx4/cpu_ramaddr<18>") FFS("snes_cx4/cpu_ramaddr<19>") FFS("snes_cx4/cpu_ramaddr<20>") FFS("snes_cx4/cpu_ramaddr<21>") FFS("snes_cx4/cpu_ramaddr<22>") FFS("snes_cx4/cpu_ramaddr<23>"); +TIMEGRP "mcu_cmd_dac_addr_out" = FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<10>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<0>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<1>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<2>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<3>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<4>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<5>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<6>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<7>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<8>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<9>"); +TIMEGRP "cx4_cpu_a" = FFS("snes_cx4/cpu_a<0>") FFS("snes_cx4/cpu_a<1>") FFS("snes_cx4/cpu_a<2>") FFS("snes_cx4/cpu_a<3>") FFS("snes_cx4/cpu_a<4>") FFS("snes_cx4/cpu_a<5>") FFS("snes_cx4/cpu_a<6>") FFS("snes_cx4/cpu_a<7>") FFS("snes_cx4/cpu_a<8>") FFS("snes_cx4/cpu_a<9>") FFS("snes_cx4/cpu_a<10>") FFS("snes_cx4/cpu_a<11>") FFS("snes_cx4/cpu_a<12>") FFS("snes_cx4/cpu_a<13>") FFS("snes_cx4/cpu_a<14>") FFS("snes_cx4/cpu_a<15>") FFS("snes_cx4/cpu_a<16>") FFS("snes_cx4/cpu_a<17>") FFS("snes_cx4/cpu_a<18>") FFS("snes_cx4/cpu_a<19>") FFS("snes_cx4/cpu_a<20>") FFS("snes_cx4/cpu_a<21>") FFS("snes_cx4/cpu_a<22>") FFS("snes_cx4/cpu_a<23>"); +TIMEGRP "cx4_pgmrom_addr" = FFS("snes_cx4/cx4_pgmrom_addr<0>") FFS("snes_cx4/cx4_pgmrom_addr<1>") FFS("snes_cx4/cx4_pgmrom_addr<2>") FFS("snes_cx4/cx4_pgmrom_addr<3>") FFS("snes_cx4/cx4_pgmrom_addr<4>") FFS("snes_cx4/cx4_pgmrom_addr<5>") FFS("snes_cx4/cx4_pgmrom_addr<6>") FFS("snes_cx4/cx4_pgmrom_addr<7>") FFS("snes_cx4/cx4_pgmrom_addr<8>") FFS("snes_cx4/cx4_pgmrom_addr<9>"); +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +TIMEGRP "cx4_cpu_idb" = FFS("snes_cx4/cpu_idb<0>") FFS("snes_cx4/cpu_idb_1_BRB1") FFS("snes_cx4/cpu_idb_1_BRB3") FFS("snes_cx4/cpu_idb_2_BRB1") FFS("snes_cx4/cpu_idb_2_BRB3") FFS("snes_cx4/cpu_idb_3_BRB1") FFS("snes_cx4/cpu_idb_3_BRB3") FFS("snes_cx4/cpu_idb_4_BRB1") FFS("snes_cx4/cpu_idb_4_BRB3") FFS("snes_cx4/cpu_idb_5_BRB1") FFS("snes_cx4/cpu_idb_5_BRB3") FFS("snes_cx4/cpu_idb_6_BRB0") FFS("snes_cx4/cpu_idb_6_BRB1") FFS("snes_cx4/cpu_idb_6_BRB3") FFS("snes_cx4/cpu_idb_7_BRB0") FFS("snes_cx4/cpu_idb_7_BRB1") FFS("snes_cx4/cpu_idb_7_BRB2") FFS("snes_cx4/cpu_idb_8_BRB0") FFS("snes_cx4/cpu_idb_8_BRB1") FFS("snes_cx4/cpu_idb_8_BRB2") FFS("snes_cx4/cpu_idb_8_BRB3") FFS("snes_cx4/cpu_idb_9_BRB0") FFS("snes_cx4/cpu_idb_9_BRB1") FFS("snes_cx4/cpu_idb_9_BRB2") FFS("snes_cx4/cpu_idb_9_BRB3") FFS("snes_cx4/cpu_idb_10_BRB0") FFS("snes_cx4/cpu_idb_10_BRB1") FFS("snes_cx4/cpu_idb_10_BRB2") FFS("snes_cx4/cpu_idb_10_BRB3") FFS("snes_cx4/cpu_idb_11_BRB0") FFS("snes_cx4/cpu_idb_11_BRB1") FFS("snes_cx4/cpu_idb_11_BRB2") FFS("snes_cx4/cpu_idb_11_BRB3") FFS("snes_cx4/cpu_idb_12_BRB0") FFS("snes_cx4/cpu_idb_12_BRB1") FFS("snes_cx4/cpu_idb_12_BRB2") FFS("snes_cx4/cpu_idb_12_BRB3") FFS("snes_cx4/cpu_idb_13_BRB0") FFS("snes_cx4/cpu_idb_13_BRB1") FFS("snes_cx4/cpu_idb_13_BRB2") FFS("snes_cx4/cpu_idb_13_BRB3") FFS("snes_cx4/cpu_idb_14_BRB0") FFS("snes_cx4/cpu_idb_14_BRB1") FFS("snes_cx4/cpu_idb_14_BRB2") FFS("snes_cx4/cpu_idb_14_BRB3") FFS("snes_cx4/cpu_idb_15_BRB0") FFS("snes_cx4/cpu_idb_15_BRB1") FFS("snes_cx4/cpu_idb_15_BRB2") FFS("snes_cx4/cpu_idb_15_BRB3") FFS("snes_cx4/cpu_idb_16_BRB0") FFS("snes_cx4/cpu_idb_16_BRB1") FFS("snes_cx4/cpu_idb_16_BRB2") FFS("snes_cx4/cpu_idb_16_BRB3") FFS("snes_cx4/cpu_idb_17_BRB0") FFS("snes_cx4/cpu_idb_17_BRB1") FFS("snes_cx4/cpu_idb_17_BRB2") FFS("snes_cx4/cpu_idb_17_BRB3") FFS("snes_cx4/cpu_idb_18_BRB0") FFS("snes_cx4/cpu_idb_18_BRB1") FFS("snes_cx4/cpu_idb_18_BRB2") FFS("snes_cx4/cpu_idb_18_BRB3") FFS("snes_cx4/cpu_idb_19_BRB0") FFS("snes_cx4/cpu_idb_19_BRB1") FFS("snes_cx4/cpu_idb_19_BRB2") FFS("snes_cx4/cpu_idb_19_BRB3") FFS("snes_cx4/cpu_idb_20_BRB0") FFS("snes_cx4/cpu_idb_20_BRB1") FFS("snes_cx4/cpu_idb_20_BRB2") FFS("snes_cx4/cpu_idb_20_BRB3") FFS("snes_cx4/cpu_idb_21_BRB0") FFS("snes_cx4/cpu_idb_21_BRB1") FFS("snes_cx4/cpu_idb_21_BRB2") FFS("snes_cx4/cpu_idb_21_BRB3") FFS("snes_cx4/cpu_idb_22_BRB0") FFS("snes_cx4/cpu_idb_22_BRB1") FFS("snes_cx4/cpu_idb_22_BRB2") FFS("snes_cx4/cpu_idb_22_BRB3") FFS("snes_cx4/cpu_idb_23_BRB0") FFS("snes_cx4/cpu_idb_23_BRB1") FFS("snes_cx4/cpu_idb_23_BRB2") FFS("snes_cx4/cpu_idb_23_BRB3"); +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +TIMEGRP "mcu_cmd_param_data" = FFS("snes_spi/param_data_r<0>") FFS("snes_spi/param_data_r<1>") FFS("snes_spi/param_data_r<2>") FFS("snes_spi/param_data_r<3>") FFS("snes_spi/param_data_r<4>") FFS("snes_spi/param_data_r<5>") FFS("snes_spi/param_data_r<6>") FFS("snes_spi/param_data_r<7>") FFS("snes_spi/param_ready_r") FFS("snes_spi/param_ready_r2"); +TIMEGRP "mcu_cmd_ADDR_OUT_BUF" = FFS("snes_mcu_cmd/ADDR_OUT_BUF<0>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<1>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<2>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<3>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<4>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<5>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<6>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<7>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<8>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<9>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<10>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<11>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<12>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<13>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<14>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<15>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<16>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<17>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<18>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<19>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<20>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<21>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<22>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<23>"); +TIMEGRP "mcu_cmd_MCU_DATA_OUT_BUF" = FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<0>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<1>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<2>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<3>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<4>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<5>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<6>") FFS("snes_mcu_cmd/MCU_DATA_OUT_BUF<7>"); +TIMEGRP "mcu_cmd_MCU_ADDR_OUT_BUF" = FFS("snes_mcu_cmd/ADDR_OUT_BUF<0>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<1>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<2>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<3>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<4>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<5>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<6>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<7>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<8>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<9>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<10>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<11>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<12>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<13>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<14>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<15>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<16>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<17>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<18>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<19>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<20>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<21>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<22>") FFS("snes_mcu_cmd/ADDR_OUT_BUF<23>"); +TIMEGRP "mcu_cmd_MSU_PTR_OUT_BUF" = FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<0>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<1>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<2>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<3>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<4>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<5>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<6>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<7>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<8>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<9>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<10>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<11>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<12>") FFS("snes_mcu_cmd/MSU_PTR_OUT_BUF<13>"); +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/28 +TIMEGRP "cx4_gpr" = FFS("snes_cx4/gpr_0_0") FFS("snes_cx4/gpr_0_1") FFS("snes_cx4/gpr_0_2") FFS("snes_cx4/gpr_0_3") FFS("snes_cx4/gpr_0_4") FFS("snes_cx4/gpr_0_5") FFS("snes_cx4/gpr_0_6") FFS("snes_cx4/gpr_0_7") FFS("snes_cx4/gpr_1_0") FFS("snes_cx4/gpr_1_1") FFS("snes_cx4/gpr_1_2") FFS("snes_cx4/gpr_1_3") FFS("snes_cx4/gpr_1_4") FFS("snes_cx4/gpr_1_5") FFS("snes_cx4/gpr_1_6") FFS("snes_cx4/gpr_1_7") FFS("snes_cx4/gpr_2_0") FFS("snes_cx4/gpr_2_1") FFS("snes_cx4/gpr_2_2") FFS("snes_cx4/gpr_2_3") FFS("snes_cx4/gpr_2_4") FFS("snes_cx4/gpr_2_5") FFS("snes_cx4/gpr_2_6") FFS("snes_cx4/gpr_2_7") FFS("snes_cx4/gpr_3_0") FFS("snes_cx4/gpr_3_1") FFS("snes_cx4/gpr_3_2") FFS("snes_cx4/gpr_3_3") FFS("snes_cx4/gpr_3_4") FFS("snes_cx4/gpr_3_5") FFS("snes_cx4/gpr_3_6") FFS("snes_cx4/gpr_3_7") FFS("snes_cx4/gpr_4_0") FFS("snes_cx4/gpr_4_1") FFS("snes_cx4/gpr_4_2") FFS("snes_cx4/gpr_4_3") FFS("snes_cx4/gpr_4_4") FFS("snes_cx4/gpr_4_5") FFS("snes_cx4/gpr_4_6") FFS("snes_cx4/gpr_4_7") FFS("snes_cx4/gpr_5_0") FFS("snes_cx4/gpr_5_1") FFS("snes_cx4/gpr_5_2") FFS("snes_cx4/gpr_5_3") FFS("snes_cx4/gpr_5_4") FFS("snes_cx4/gpr_5_5") FFS("snes_cx4/gpr_5_6") FFS("snes_cx4/gpr_5_7") FFS("snes_cx4/gpr_6_0") FFS("snes_cx4/gpr_6_1") FFS("snes_cx4/gpr_6_2") FFS("snes_cx4/gpr_6_3") FFS("snes_cx4/gpr_6_4") FFS("snes_cx4/gpr_6_5") FFS("snes_cx4/gpr_6_6") FFS("snes_cx4/gpr_6_7") FFS("snes_cx4/gpr_7_0") FFS("snes_cx4/gpr_7_1") FFS("snes_cx4/gpr_7_2") FFS("snes_cx4/gpr_7_3") FFS("snes_cx4/gpr_7_4") FFS("snes_cx4/gpr_7_5") FFS("snes_cx4/gpr_7_6") FFS("snes_cx4/gpr_7_7") FFS("snes_cx4/gpr_8_0") FFS("snes_cx4/gpr_8_1") FFS("snes_cx4/gpr_8_2") FFS("snes_cx4/gpr_8_3") FFS("snes_cx4/gpr_8_4") FFS("snes_cx4/gpr_8_5") FFS("snes_cx4/gpr_8_6") FFS("snes_cx4/gpr_8_7") FFS("snes_cx4/gpr_9_0") FFS("snes_cx4/gpr_9_1") FFS("snes_cx4/gpr_9_2") FFS("snes_cx4/gpr_9_3") FFS("snes_cx4/gpr_9_4") FFS("snes_cx4/gpr_9_5") FFS("snes_cx4/gpr_9_6") FFS("snes_cx4/gpr_9_7") FFS("snes_cx4/gpr_10_0") FFS("snes_cx4/gpr_10_1") FFS("snes_cx4/gpr_10_2") FFS("snes_cx4/gpr_10_3") FFS("snes_cx4/gpr_10_4") FFS("snes_cx4/gpr_10_5") FFS("snes_cx4/gpr_10_6") FFS("snes_cx4/gpr_10_7") FFS("snes_cx4/gpr_11_0") FFS("snes_cx4/gpr_11_1") FFS("snes_cx4/gpr_11_2") FFS("snes_cx4/gpr_11_3") FFS("snes_cx4/gpr_11_4") FFS("snes_cx4/gpr_11_5") FFS("snes_cx4/gpr_11_6") FFS("snes_cx4/gpr_11_7") FFS("snes_cx4/gpr_12_0") FFS("snes_cx4/gpr_12_1") FFS("snes_cx4/gpr_12_2") FFS("snes_cx4/gpr_12_3") FFS("snes_cx4/gpr_12_4") FFS("snes_cx4/gpr_12_5") FFS("snes_cx4/gpr_12_6") FFS("snes_cx4/gpr_12_7") FFS("snes_cx4/gpr_13_0") FFS("snes_cx4/gpr_13_1") FFS("snes_cx4/gpr_13_2") FFS("snes_cx4/gpr_13_3") FFS("snes_cx4/gpr_13_4") FFS("snes_cx4/gpr_13_5") FFS("snes_cx4/gpr_13_6") FFS("snes_cx4/gpr_13_7") FFS("snes_cx4/gpr_14_0") FFS("snes_cx4/gpr_14_1") FFS("snes_cx4/gpr_14_2") FFS("snes_cx4/gpr_14_3") FFS("snes_cx4/gpr_14_4") FFS("snes_cx4/gpr_14_5") FFS("snes_cx4/gpr_14_6") FFS("snes_cx4/gpr_14_7") FFS("snes_cx4/gpr_15_0") FFS("snes_cx4/gpr_15_1") FFS("snes_cx4/gpr_15_2") FFS("snes_cx4/gpr_15_3") FFS("snes_cx4/gpr_15_4") FFS("snes_cx4/gpr_15_5") FFS("snes_cx4/gpr_15_6") FFS("snes_cx4/gpr_15_7") FFS("snes_cx4/gpr_16_0") FFS("snes_cx4/gpr_16_1") FFS("snes_cx4/gpr_16_2") FFS("snes_cx4/gpr_16_3") FFS("snes_cx4/gpr_16_4") FFS("snes_cx4/gpr_16_5") FFS("snes_cx4/gpr_16_6") FFS("snes_cx4/gpr_16_7") FFS("snes_cx4/gpr_17_0") FFS("snes_cx4/gpr_17_1") FFS("snes_cx4/gpr_17_2") FFS("snes_cx4/gpr_17_3") FFS("snes_cx4/gpr_17_4") FFS("snes_cx4/gpr_17_5") FFS("snes_cx4/gpr_17_6") FFS("snes_cx4/gpr_17_7") FFS("snes_cx4/gpr_18_0") FFS("snes_cx4/gpr_18_1") FFS("snes_cx4/gpr_18_2") FFS("snes_cx4/gpr_18_3") FFS("snes_cx4/gpr_18_4") FFS("snes_cx4/gpr_18_5") FFS("snes_cx4/gpr_18_6") FFS("snes_cx4/gpr_18_7") FFS("snes_cx4/gpr_19_0") FFS("snes_cx4/gpr_19_1") FFS("snes_cx4/gpr_19_2") FFS("snes_cx4/gpr_19_3") FFS("snes_cx4/gpr_19_4") FFS("snes_cx4/gpr_19_5") FFS("snes_cx4/gpr_19_6") FFS("snes_cx4/gpr_19_7") FFS("snes_cx4/gpr_20_0") FFS("snes_cx4/gpr_20_1") FFS("snes_cx4/gpr_20_2") FFS("snes_cx4/gpr_20_3") FFS("snes_cx4/gpr_20_4") FFS("snes_cx4/gpr_20_5") FFS("snes_cx4/gpr_20_6") FFS("snes_cx4/gpr_20_7") FFS("snes_cx4/gpr_21_0") FFS("snes_cx4/gpr_21_1") FFS("snes_cx4/gpr_21_2") FFS("snes_cx4/gpr_21_3") FFS("snes_cx4/gpr_21_4") FFS("snes_cx4/gpr_21_5") FFS("snes_cx4/gpr_21_6") FFS("snes_cx4/gpr_21_7") FFS("snes_cx4/gpr_22_0") FFS("snes_cx4/gpr_22_1") FFS("snes_cx4/gpr_22_2") FFS("snes_cx4/gpr_22_3") FFS("snes_cx4/gpr_22_4") FFS("snes_cx4/gpr_22_5") FFS("snes_cx4/gpr_22_6") FFS("snes_cx4/gpr_22_7") FFS("snes_cx4/gpr_23_0") FFS("snes_cx4/gpr_23_1") FFS("snes_cx4/gpr_23_2") FFS("snes_cx4/gpr_23_3") FFS("snes_cx4/gpr_23_4") FFS("snes_cx4/gpr_23_5") FFS("snes_cx4/gpr_23_6") FFS("snes_cx4/gpr_23_7") FFS("snes_cx4/gpr_24_0") FFS("snes_cx4/gpr_24_1") FFS("snes_cx4/gpr_24_2") FFS("snes_cx4/gpr_24_3") FFS("snes_cx4/gpr_24_4") FFS("snes_cx4/gpr_24_5") FFS("snes_cx4/gpr_24_6") FFS("snes_cx4/gpr_24_7") FFS("snes_cx4/gpr_25_0") FFS("snes_cx4/gpr_25_1") FFS("snes_cx4/gpr_25_2") FFS("snes_cx4/gpr_25_3") FFS("snes_cx4/gpr_25_4") FFS("snes_cx4/gpr_25_5") FFS("snes_cx4/gpr_25_6") FFS("snes_cx4/gpr_25_7") FFS("snes_cx4/gpr_26_0") FFS("snes_cx4/gpr_26_1") FFS("snes_cx4/gpr_26_2") FFS("snes_cx4/gpr_26_3") FFS("snes_cx4/gpr_26_4") FFS("snes_cx4/gpr_26_5") FFS("snes_cx4/gpr_26_6") FFS("snes_cx4/gpr_26_7") FFS("snes_cx4/gpr_27_0") FFS("snes_cx4/gpr_27_1") FFS("snes_cx4/gpr_27_2") FFS("snes_cx4/gpr_27_3") FFS("snes_cx4/gpr_27_4") FFS("snes_cx4/gpr_27_5") FFS("snes_cx4/gpr_27_6") FFS("snes_cx4/gpr_27_7") FFS("snes_cx4/gpr_28_0") FFS("snes_cx4/gpr_28_1") FFS("snes_cx4/gpr_28_2") FFS("snes_cx4/gpr_28_3") FFS("snes_cx4/gpr_28_4") FFS("snes_cx4/gpr_28_5") FFS("snes_cx4/gpr_28_6") FFS("snes_cx4/gpr_28_7") FFS("snes_cx4/gpr_29_0") FFS("snes_cx4/gpr_29_1") FFS("snes_cx4/gpr_29_2") FFS("snes_cx4/gpr_29_3") FFS("snes_cx4/gpr_29_4") FFS("snes_cx4/gpr_29_5") FFS("snes_cx4/gpr_29_6") FFS("snes_cx4/gpr_29_7") FFS("snes_cx4/gpr_30_0") FFS("snes_cx4/gpr_30_1") FFS("snes_cx4/gpr_30_2") FFS("snes_cx4/gpr_30_3") FFS("snes_cx4/gpr_30_4") FFS("snes_cx4/gpr_30_5") FFS("snes_cx4/gpr_30_6") FFS("snes_cx4/gpr_30_7") FFS("snes_cx4/gpr_31_0") FFS("snes_cx4/gpr_31_1") FFS("snes_cx4/gpr_31_2") FFS("snes_cx4/gpr_31_3") FFS("snes_cx4/gpr_31_4") FFS("snes_cx4/gpr_31_5") FFS("snes_cx4/gpr_31_6") FFS("snes_cx4/gpr_31_7") FFS("snes_cx4/gpr_32_0") FFS("snes_cx4/gpr_32_1") FFS("snes_cx4/gpr_32_2") FFS("snes_cx4/gpr_32_3") FFS("snes_cx4/gpr_32_4") FFS("snes_cx4/gpr_32_5") FFS("snes_cx4/gpr_32_6") FFS("snes_cx4/gpr_32_7") FFS("snes_cx4/gpr_33_0") FFS("snes_cx4/gpr_33_1") FFS("snes_cx4/gpr_33_2") FFS("snes_cx4/gpr_33_3") FFS("snes_cx4/gpr_33_4") FFS("snes_cx4/gpr_33_5") FFS("snes_cx4/gpr_33_6") FFS("snes_cx4/gpr_33_7") FFS("snes_cx4/gpr_34_0") FFS("snes_cx4/gpr_34_1") FFS("snes_cx4/gpr_34_2") FFS("snes_cx4/gpr_34_3") FFS("snes_cx4/gpr_34_4") FFS("snes_cx4/gpr_34_5") FFS("snes_cx4/gpr_34_6") FFS("snes_cx4/gpr_34_7") FFS("snes_cx4/gpr_35_0") FFS("snes_cx4/gpr_35_1") FFS("snes_cx4/gpr_35_2") FFS("snes_cx4/gpr_35_3") FFS("snes_cx4/gpr_35_4") FFS("snes_cx4/gpr_35_5") FFS("snes_cx4/gpr_35_6") FFS("snes_cx4/gpr_35_7") FFS("snes_cx4/gpr_36_0") FFS("snes_cx4/gpr_36_1") FFS("snes_cx4/gpr_36_2") FFS("snes_cx4/gpr_36_3") FFS("snes_cx4/gpr_36_4") FFS("snes_cx4/gpr_36_5") FFS("snes_cx4/gpr_36_6") FFS("snes_cx4/gpr_36_7") FFS("snes_cx4/gpr_37_0") FFS("snes_cx4/gpr_37_1") FFS("snes_cx4/gpr_37_2") FFS("snes_cx4/gpr_37_3") FFS("snes_cx4/gpr_37_4") FFS("snes_cx4/gpr_37_5") FFS("snes_cx4/gpr_37_6") FFS("snes_cx4/gpr_37_7") FFS("snes_cx4/gpr_38_0") FFS("snes_cx4/gpr_38_1") FFS("snes_cx4/gpr_38_2") FFS("snes_cx4/gpr_38_3") FFS("snes_cx4/gpr_38_4") FFS("snes_cx4/gpr_38_5") FFS("snes_cx4/gpr_38_6") FFS("snes_cx4/gpr_38_7") FFS("snes_cx4/gpr_39_0") FFS("snes_cx4/gpr_39_1") FFS("snes_cx4/gpr_39_2") FFS("snes_cx4/gpr_39_3") FFS("snes_cx4/gpr_39_4") FFS("snes_cx4/gpr_39_5") FFS("snes_cx4/gpr_39_6") FFS("snes_cx4/gpr_39_7") FFS("snes_cx4/gpr_40_0") FFS("snes_cx4/gpr_40_1") FFS("snes_cx4/gpr_40_2") FFS("snes_cx4/gpr_40_3") FFS("snes_cx4/gpr_40_4") FFS("snes_cx4/gpr_40_5") FFS("snes_cx4/gpr_40_6") FFS("snes_cx4/gpr_40_7") FFS("snes_cx4/gpr_41_0") FFS("snes_cx4/gpr_41_1") FFS("snes_cx4/gpr_41_2") FFS("snes_cx4/gpr_41_3") FFS("snes_cx4/gpr_41_4") FFS("snes_cx4/gpr_41_5") FFS("snes_cx4/gpr_41_6") FFS("snes_cx4/gpr_41_7") FFS("snes_cx4/gpr_42_0") FFS("snes_cx4/gpr_42_1") FFS("snes_cx4/gpr_42_2") FFS("snes_cx4/gpr_42_3") FFS("snes_cx4/gpr_42_4") FFS("snes_cx4/gpr_42_5") FFS("snes_cx4/gpr_42_6") FFS("snes_cx4/gpr_42_7") FFS("snes_cx4/gpr_43_0") FFS("snes_cx4/gpr_43_1") FFS("snes_cx4/gpr_43_2") FFS("snes_cx4/gpr_43_3") FFS("snes_cx4/gpr_43_4") FFS("snes_cx4/gpr_43_5") FFS("snes_cx4/gpr_43_6") FFS("snes_cx4/gpr_43_7") FFS("snes_cx4/gpr_44_0") FFS("snes_cx4/gpr_44_1") FFS("snes_cx4/gpr_44_2") FFS("snes_cx4/gpr_44_3") FFS("snes_cx4/gpr_44_4") FFS("snes_cx4/gpr_44_5") FFS("snes_cx4/gpr_44_6") FFS("snes_cx4/gpr_44_7") FFS("snes_cx4/gpr_45_0") FFS("snes_cx4/gpr_45_1") FFS("snes_cx4/gpr_45_2") FFS("snes_cx4/gpr_45_3") FFS("snes_cx4/gpr_45_4") FFS("snes_cx4/gpr_45_5") FFS("snes_cx4/gpr_45_6") FFS("snes_cx4/gpr_45_7") FFS("snes_cx4/gpr_46_0") FFS("snes_cx4/gpr_46_1") FFS("snes_cx4/gpr_46_2") FFS("snes_cx4/gpr_46_3") FFS("snes_cx4/gpr_46_4") FFS("snes_cx4/gpr_46_5") FFS("snes_cx4/gpr_46_6") FFS("snes_cx4/gpr_46_7") FFS("snes_cx4/gpr_47_0") FFS("snes_cx4/gpr_47_1") FFS("snes_cx4/gpr_47_2") FFS("snes_cx4/gpr_47_3") FFS("snes_cx4/gpr_47_4") FFS("snes_cx4/gpr_47_5") FFS("snes_cx4/gpr_47_6") FFS("snes_cx4/gpr_47_7"); +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMEGRP "DAC" = FFS("snes_dac/dac_address_r<0>") FFS("snes_dac/dac_address_r<1>") FFS("snes_dac/dac_address_r<2>") FFS("snes_dac/dac_address_r<3>") FFS("snes_dac/dac_address_r<4>") FFS("snes_dac/dac_address_r<5>") FFS("snes_dac/dac_address_r<6>") FFS("snes_dac/dac_address_r<7>") FFS("snes_dac/dac_address_r<8>") FFS("snes_dac/lrck_sreg<1>") FFS("snes_dac/lrck_sreg<2>") FFS("snes_dac/Mshreg_lrck_sreg_1") FFS("snes_dac/Mshreg_sclk_sreg_1") FFS("snes_dac/play_r") FFS("snes_dac/reset_sreg<0>") FFS("snes_dac/reset_sreg<1>") FFS("snes_dac/samples<0>") FFS("snes_dac/samples<1>") FFS("snes_dac/sclk_sreg<1>") FFS("snes_dac/sclk_sreg<2>") FFS("snes_dac/sdout_reg") FFS("snes_dac/smpshift<0>") FFS("snes_dac/smpshift<1>") FFS("snes_dac/smpshift<2>") FFS("snes_dac/smpshift<3>") FFS("snes_dac/smpshift<4>") FFS("snes_dac/smpshift<5>") FFS("snes_dac/smpshift<6>") FFS("snes_dac/smpshift<7>") FFS("snes_dac/smpshift<8>") FFS("snes_dac/smpshift<9>") FFS("snes_dac/smpshift<10>") FFS("snes_dac/smpshift<11>") FFS("snes_dac/smpshift<12>") FFS("snes_dac/smpshift<13>") FFS("snes_dac/smpshift<14>") FFS("snes_dac/smpshift_15_BRB0") FFS("snes_dac/smpshift_15_BRB1") FFS("snes_dac/smpshift_15_BRB2") FFS("snes_dac/sysclk_sreg<0>") FFS("snes_dac/sysclk_sreg<1>") FFS("snes_dac/sysclk_sreg<2>") FFS("snes_dac/vol_latch_reg<0>") FFS("snes_dac/vol_latch_reg<1>") FFS("snes_dac/vol_reg<0>") FFS("snes_dac/vol_reg<1>") FFS("snes_dac/vol_reg<2>") FFS("snes_dac/vol_reg<3>") FFS("snes_dac/vol_reg<4>") FFS("snes_dac/vol_reg<5>") FFS("snes_dac/vol_reg<6>") FFS("snes_dac/vol_reg<7>") FFS("snes_dac/vol_target_reg<0>") FFS("snes_dac/vol_target_reg<1>") FFS("snes_dac/vol_target_reg<2>") FFS("snes_dac/vol_target_reg<3>") FFS("snes_dac/vol_target_reg<4>") FFS("snes_dac/vol_target_reg<5>") FFS("snes_dac/vol_target_reg<6>") FFS("snes_dac/vol_target_reg<7>") FFS("snes_dac/vol_valid") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<0>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<1>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<2>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<3>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<4>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<5>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<6>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<7>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<8>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<9>") FFS("snes_mcu_cmd/DAC_ADDR_OUT_BUF<10>") FFS("snes_mcu_cmd/DAC_PLAY_OUT_BUF") FFS("snes_mcu_cmd/DAC_RESET_OUT_BUF") FFS("snes_mcu_cmd/DAC_STATUSr"); +TIMESPEC TS_DAC = FROM "FFS" TO "DAC" TS_CLK21 / 4; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMESPEC TS_CX4_GPR = FROM "FFS" TO "cx4_gpr" TS_CLK21 / 4; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMESPEC TS_CX4_CACHE = FROM "FFS" TO "cx4_cache_src_addr" TS_CLK21 / 2; +TIMESPEC TS_CX4_BUSADDR = FROM "FFS" TO "cx4_cpu_busaddr" TS_CLK21 / 4; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMESPEC TS_DAC2 = FROM "RAMS" TO "DAC" TS_CLK21 / 4; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMESPEC TS_CX4_IDB = FROM "cx4_idb_downstrean" TO "FFS" TS_CLK21 / 2; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +NET "snes_cx4/cpu_idb*" TNM_NET = cx4_idb_downstrean; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +NET "*cx4*mul*" TNM_NET = CX4_MUL_downstream; +TIMESPEC TS_CX4_MUL = FROM "CX4_MUL_downstream" TO "cx4_cpu_idb" TS_CLK21 / 2; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMEGRP "CX4_FL_Z" = FFS("*cx4*fl_z*"); +TIMEGRP "CX4_FL_C" = FFS("*cx4*fl_c*"); +TIMEGRP "CX4_FL_N" = FFS("*cx4*fl_n*"); +TIMEGRP "CX4_MULT" = MULTS("snes_cx4/cx4_mul/sig000000e5") MULTS("snes_cx4/cx4_mul/sig000000e4") MULTS("snes_cx4/cx4_mul/sig000000e3") MULTS("snes_cx4/cx4_mul/sig000000e2") MULTS("snes_cx4/cx4_mul/sig000000ee") MULTS("snes_cx4/cx4_mul/sig000000ed") MULTS("snes_cx4/cx4_mul/sig000000ec") MULTS("snes_cx4/cx4_mul/sig000000eb") MULTS("snes_cx4/cx4_mul/sig000000ea") MULTS("snes_cx4/cx4_mul/sig000000e9") MULTS("snes_cx4/cx4_mul/sig000000e8") MULTS("snes_cx4/cx4_mul/sig000000e7") MULTS("snes_cx4/cx4_mul/sig000000e6") MULTS("snes_cx4/cx4_mul/sig000000e1") MULTS("snes_cx4/cx4_mul/sig000000d8") MULTS("snes_cx4/cx4_mul/sig000000d7") MULTS("snes_cx4/cx4_mul/sig000000d6") MULTS("snes_cx4/cx4_mul/sig000000d5") MULTS("snes_cx4/cx4_mul/sig000000d3") MULTS("snes_cx4/cx4_mul/sig000000d2") MULTS("snes_cx4/cx4_mul/sig000000d1") MULTS("snes_cx4/cx4_mul/sig000000d0") MULTS("snes_cx4/cx4_mul/sig000000cf") MULTS("snes_cx4/cx4_mul/sig000000ce") MULTS("snes_cx4/cx4_mul/sig000000cd") MULTS("snes_cx4/cx4_mul/sig000000cc") MULTS("snes_cx4/cx4_mul/sig000000cb") MULTS("snes_cx4/cx4_mul/sig000000ca") MULTS("snes_cx4/cx4_mul/sig000000e0") MULTS("snes_cx4/cx4_mul/sig000000df") MULTS("snes_cx4/cx4_mul/sig000000de") MULTS("snes_cx4/cx4_mul/sig000000dd") MULTS("snes_cx4/cx4_mul/sig000000dc") MULTS("snes_cx4/cx4_mul/sig000000db") MULTS("snes_cx4/cx4_mul/sig000000da") MULTS("snes_cx4/cx4_mul/sig000000d9") MULTS("snes_cx4/cx4_mul/sig000000d4") MULTS("snes_cx4/cx4_mul/sig000000c9") MULTS("snes_cx4/cx4_mul/sig000000c0") MULTS("snes_cx4/cx4_mul/sig000000bf") MULTS("snes_cx4/cx4_mul/sig000000be") MULTS("snes_cx4/cx4_mul/sig000000bd") MULTS("snes_cx4/cx4_mul/sig000000bb") MULTS("snes_cx4/cx4_mul/sig000000ba") MULTS("snes_cx4/cx4_mul/sig000000b9") MULTS("snes_cx4/cx4_mul/sig000000b8") MULTS("snes_cx4/cx4_mul/sig000000b7") MULTS("snes_cx4/cx4_mul/sig000000b6") MULTS("snes_cx4/cx4_mul/sig000000b5") MULTS("snes_cx4/cx4_mul/sig000000b4") MULTS("snes_cx4/cx4_mul/sig000000b3") MULTS("snes_cx4/cx4_mul/sig000000b2") MULTS("snes_cx4/cx4_mul/sig000000c8") MULTS("snes_cx4/cx4_mul/sig000000c7") MULTS("snes_cx4/cx4_mul/sig000000c6") MULTS("snes_cx4/cx4_mul/sig000000c5") MULTS("snes_cx4/cx4_mul/sig000000c4") MULTS("snes_cx4/cx4_mul/sig000000c3") MULTS("snes_cx4/cx4_mul/sig000000c2") MULTS("snes_cx4/cx4_mul/sig000000c1") MULTS("snes_cx4/cx4_mul/sig000000bc") MULTS("snes_cx4/cx4_mul/sig000000b1") MULTS("snes_cx4/cx4_mul/sig000000a9") MULTS("snes_cx4/cx4_mul/sig000000a8") MULTS("snes_cx4/cx4_mul/sig000000a7") MULTS("snes_cx4/cx4_mul/sig000000a6") MULTS("snes_cx4/cx4_mul/sig000000a5") MULTS("snes_cx4/cx4_mul/sig000000a3") MULTS("snes_cx4/cx4_mul/sig000000a2") MULTS("snes_cx4/cx4_mul/sig000000a1") MULTS("snes_cx4/cx4_mul/sig000000a0") MULTS("snes_cx4/cx4_mul/sig0000009f") MULTS("snes_cx4/cx4_mul/sig0000009e") MULTS("snes_cx4/cx4_mul/sig0000009d") MULTS("snes_cx4/cx4_mul/sig0000009c") MULTS("snes_cx4/cx4_mul/sig0000009b") MULTS("snes_cx4/cx4_mul/sig0000009a") MULTS("snes_cx4/cx4_mul/sig00000098") MULTS("snes_cx4/cx4_mul/sig00000097") MULTS("snes_cx4/cx4_mul/sig00000096") MULTS("snes_cx4/cx4_mul/sig00000095") MULTS("snes_cx4/cx4_mul/sig00000094") MULTS("snes_cx4/cx4_mul/sig00000093") MULTS("snes_cx4/cx4_mul/sig00000092") MULTS("snes_cx4/cx4_mul/sig00000091") MULTS("snes_cx4/cx4_mul/sig00000090") MULTS("snes_cx4/cx4_mul/sig0000008f") MULTS("snes_cx4/cx4_mul/sig000000b0") MULTS("snes_cx4/cx4_mul/sig000000af") MULTS("snes_cx4/cx4_mul/sig000000ae") MULTS("snes_cx4/cx4_mul/sig000000ad") MULTS("snes_cx4/cx4_mul/sig000000ac") MULTS("snes_cx4/cx4_mul/sig000000ab") MULTS("snes_cx4/cx4_mul/sig000000aa") MULTS("snes_cx4/cx4_mul/sig000000a4") MULTS("snes_cx4/cx4_mul/sig00000099") MULTS("snes_cx4/cx4_mul/sig0000008e"); +TIMEGRP "CX4_MUL_FF" = FFS("snes_cx4/cx4_mul/sig00000129") FFS("snes_cx4/cx4_mul/sig00000128") FFS("snes_cx4/cx4_mul/sig00000127") FFS("snes_cx4/cx4_mul/sig00000126") FFS("snes_cx4/cx4_mul/sig00000124") FFS("snes_cx4/cx4_mul/sig00000123") FFS("snes_cx4/cx4_mul/sig00000122") FFS("snes_cx4/cx4_mul/sig00000121") FFS("snes_cx4/cx4_mul/sig00000120") FFS("snes_cx4/cx4_mul/sig0000011f") FFS("snes_cx4/cx4_mul/sig0000011e") FFS("snes_cx4/cx4_mul/sig0000011d") FFS("snes_cx4/cx4_mul/sig0000011c") FFS("snes_cx4/cx4_mul/sig0000011b") FFS("snes_cx4/cx4_mul/sig00000130") FFS("snes_cx4/cx4_mul/sig0000012f") FFS("snes_cx4/cx4_mul/sig0000012e") FFS("snes_cx4/cx4_mul/sig0000012d") FFS("snes_cx4/cx4_mul/sig0000012c") FFS("snes_cx4/cx4_mul/sig0000012b") FFS("snes_cx4/cx4_mul/sig0000012a") FFS("snes_cx4/cx4_mul/sig00000125") FFS("snes_cx4/cx4_mul/sig0000011a") FFS("snes_cx4/cx4_mul/sig00000119") FFS("snes_cx4/cx4_mul/sig00000111") FFS("snes_cx4/cx4_mul/sig00000110") FFS("snes_cx4/cx4_mul/sig0000010f") FFS("snes_cx4/cx4_mul/sig0000010e") FFS("snes_cx4/cx4_mul/sig0000010c") FFS("snes_cx4/cx4_mul/sig0000010b") FFS("snes_cx4/cx4_mul/sig0000010a") FFS("snes_cx4/cx4_mul/sig00000109") FFS("snes_cx4/cx4_mul/sig00000108") FFS("snes_cx4/cx4_mul/sig00000107") FFS("snes_cx4/cx4_mul/sig00000106") FFS("snes_cx4/cx4_mul/sig00000105") FFS("snes_cx4/cx4_mul/sig00000104") FFS("snes_cx4/cx4_mul/sig00000103") FFS("snes_cx4/cx4_mul/sig00000118") FFS("snes_cx4/cx4_mul/sig00000117") FFS("snes_cx4/cx4_mul/sig00000116") FFS("snes_cx4/cx4_mul/sig00000133") FFS("snes_cx4/cx4_mul/sig0000013e") FFS("snes_cx4/cx4_mul/sig0000013d") FFS("snes_cx4/cx4_mul/sig0000013c") FFS("snes_cx4/cx4_mul/sig0000013b") FFS("snes_cx4/cx4_mul/sig0000013a") FFS("snes_cx4/cx4_mul/sig000000fb") FFS("snes_cx4/cx4_mul/sig000000fa") FFS("snes_cx4/cx4_mul/sig000000f9") FFS("snes_cx4/cx4_mul/sig000000f8") FFS("snes_cx4/cx4_mul/sig000000f7") FFS("snes_cx4/cx4_mul/sig000000f6") FFS("snes_cx4/cpu_mul_result<13>") FFS("snes_cx4/cpu_mul_result<12>") FFS("snes_cx4/cpu_mul_result<11>") FFS("snes_cx4/cpu_mul_result<10>") FFS("snes_cx4/cpu_mul_result<9>") FFS("snes_cx4/cpu_mul_result<8>") FFS("snes_cx4/cx4_mul/sig00000115") FFS("snes_cx4/cx4_mul/sig00000114") FFS("snes_cx4/cx4_mul/sig00000113") FFS("snes_cx4/cx4_mul/sig00000112") FFS("snes_cx4/cx4_mul/sig0000010d") FFS("snes_cx4/cx4_mul/sig00000102") FFS("snes_cx4/cx4_mul/sig00000101") FFS("snes_cx4/cx4_mul/sig00000136") FFS("snes_cx4/cx4_mul/sig00000135") FFS("snes_cx4/cx4_mul/sig00000134") FFS("snes_cx4/cx4_mul/sig00000139") FFS("snes_cx4/cx4_mul/sig00000138") FFS("snes_cx4/cx4_mul/sig00000137") FFS("snes_cx4/cx4_mul/sig00000132") FFS("snes_cx4/cx4_mul/sig00000131") FFS("snes_cx4/cx4_mul/sig00000100") FFS("snes_cx4/cx4_mul/sig000000ff") FFS("snes_cx4/cx4_mul/sig000000fe") FFS("snes_cx4/cx4_mul/sig000000fd") FFS("snes_cx4/cx4_mul/sig000000fc") FFS("snes_cx4/cx4_mul/sig000000f5") FFS("snes_cx4/cx4_mul/sig000000f4") FFS("snes_cx4/cx4_mul/sig000000f3") FFS("snes_cx4/cx4_mul/sig000000f2") FFS("snes_cx4/cx4_mul/sig000000f1") FFS("snes_cx4/cx4_mul/sig000000f0") FFS("snes_cx4/cx4_mul/sig000000ef") FFS("snes_cx4/cpu_mul_result<16>") FFS("snes_cx4/cpu_mul_result<15>") FFS("snes_cx4/cpu_mul_result<14>") FFS("snes_cx4/cpu_mul_result<7>") FFS("snes_cx4/cpu_mul_result<6>") FFS("snes_cx4/cpu_mul_result<5>") FFS("snes_cx4/cpu_mul_result<4>") FFS("snes_cx4/cpu_mul_result<3>") FFS("snes_cx4/cpu_mul_result<2>") FFS("snes_cx4/cpu_mul_result<1>") FFS("snes_cx4/cpu_mul_result<0>") FFS("snes_cx4/Mmult__COND_15_Madd_cy<2>11_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_cy<2>11_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_cy<3>11_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_cy<3>11_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB_1") FFS("snes_cx4/Mmult__COND_15_Madd_lut<1>1_FRB_2") FFS("snes_cx4/Mmult__COND_15_Madd_lut<2>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<3>1_FRB") FFS("snes_cx4/Mmult__COND_15_Madd_lut<3>1_FRB_1"); +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMESPEC TS_CX4_MUL2 = FROM "MULTS" TO "cx4_cpu_idb" TS_CLK21 / 2; +TIMESPEC TS_CX4_FL_Z = FROM "CX4_MUL_downstream" TO "CX4_FL_Z" TS_CLK21 / 2; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/30 +TIMEGRP "CX4_TMP" = FFS("snes_cx4/cpu_tmp<0>") FFS("snes_cx4/cpu_tmp<1>") FFS("snes_cx4/cpu_tmp<2>") FFS("snes_cx4/cpu_tmp<3>") FFS("snes_cx4/cpu_tmp<4>") FFS("snes_cx4/cpu_tmp<5>") FFS("snes_cx4/cpu_tmp<6>") FFS("snes_cx4/cpu_tmp<7>") FFS("snes_cx4/cpu_tmp<8>") FFS("snes_cx4/cpu_tmp<9>") FFS("snes_cx4/cpu_tmp<10>") FFS("snes_cx4/cpu_tmp<11>") FFS("snes_cx4/cpu_tmp<12>") FFS("snes_cx4/cpu_tmp<13>") FFS("snes_cx4/cpu_tmp<14>") FFS("snes_cx4/cpu_tmp<15>") FFS("snes_cx4/cpu_tmp<16>") FFS("snes_cx4/cpu_tmp<17>") FFS("snes_cx4/cpu_tmp<18>") FFS("snes_cx4/cpu_tmp<19>") FFS("snes_cx4/cpu_tmp<20>") FFS("snes_cx4/cpu_tmp<21>") FFS("snes_cx4/cpu_tmp<22>") FFS("snes_cx4/cpu_tmp<23>") FFS("snes_cx4/cpu_tmp_cmp_eq0005111_FRB"); +TIMESPEC TS_CX4_TMP = FROM "CX4_MUL_downstream" TO "CX4_TMP" TS_CLK21 / 2; +#Created by Constraints Editor (xc3s400-pq208-4) - 2011/10/31 From b8f4c9b5846ebe25deeeca777102d98618efe9b9 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 11:58:20 +0100 Subject: [PATCH 64/66] Firmware: optimize non-sector-aligned SD DMA reads (bugfix) --- src/ff.c | 12 ++++++++++-- src/sdnative.c | 6 +++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/ff.c b/src/ff.c index bcd68c1..819b33c 100644 --- a/src/ff.c +++ b/src/ff.c @@ -2639,8 +2639,16 @@ FRESULT f_lseek ( fp->flag &= ~FA__DIRTY; } #endif - if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) - ABORT(fp->fs, FR_DISK_ERR); + if(!ff_sd_offload) { + sd_offload_partial=0; + if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) + ABORT(fp->fs, FR_DISK_ERR); + } else { + sd_offload_partial=1; + sd_offload_partial_start = fp->fptr % SS(fp->fs); + } +// if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) +// ABORT(fp->fs, FR_DISK_ERR); #endif fp->dsect = dsc; } diff --git a/src/sdnative.c b/src/sdnative.c index b7725a9..21adbab 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -800,10 +800,10 @@ void read_block(uint32_t address, uint8_t *buf) { && last_block == address && last_offset == sd_offload_partial_start && sd_offload_partial) { - stream_datablock(buf); - last_offset = sd_offload_partial_end & 0x1ff; sd_offload_partial_start |= 0x8000; + stream_datablock(buf); during_blocktrans = TRANS_READ; + last_offset = sd_offload_partial_end & 0x1ff; sd_offload_partial = 0; } else { if(during_blocktrans) { @@ -812,6 +812,7 @@ void read_block(uint32_t address, uint8_t *buf) { /* send STOP_TRANSMISSION to end an open READ/WRITE_MULTIPLE_BLOCK */ cmd_fast(STOP_TRANSMISSION, 0, 0x61, NULL, rsp); } + during_blocktrans = TRANS_READ; last_block = address; if(!ccs) { address <<= 9; @@ -825,7 +826,6 @@ void read_block(uint32_t address, uint8_t *buf) { cmd_fast(READ_MULTIPLE_BLOCK, address, 0, buf, rsp); #endif sd_offload_partial = 0; - during_blocktrans = TRANS_READ; } // printf("trans state = %d\n", during_blocktrans); } From da2386e45355b77f289309d009012551815e3c46 Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 12:18:13 +0100 Subject: [PATCH 65/66] Firmware/MSU1: stop DAC at end of audio file --- src/msu1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/msu1.c b/src/msu1.c index b7d7fc6..824e0e3 100644 --- a/src/msu1.c +++ b/src/msu1.c @@ -254,6 +254,7 @@ int msu1_loop() { f_read(&file_handle, file_buf, (MSU_DAC_BUFSIZE / 2) - bytes_read, &bytes_read); } else { set_msu_status(0x00, 0x02); /* clear play bit */ + dac_pause(); } bytes_read = MSU_DAC_BUFSIZE; } From a79a53856056d7c9bfcebe2db35e1b977c1ddd5d Mon Sep 17 00:00:00 2001 From: ikari Date: Sat, 14 Jan 2012 23:08:12 +0100 Subject: [PATCH 66/66] update changelog --- CHANGELOG | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 1cbc8fc..51dc47c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -11,3 +11,14 @@ v0.1.1a (bugfix release) - SuperCIC pair mode was erroneously enabled in firmware binary - SNES menu crashed on empty database + +v0.1.2 +====== + + * Auto region override (eliminate "This game pak is not designed..." messages) + * Improved mapper detection (fixes Batman vs. Joker and many PD ROMs) + * Improved data streaming performance + (should reduce MSU1 errors with some cards) + * A and B buttons swapped in menu to match common key mappings + * Fixes: + - MSU1: Stop audio playback on end of audio file

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