diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v
index ea359a2..9695d1e 100644
--- a/verilog/sd2snes/address.v
+++ b/verilog/sd2snes/address.v
@@ -41,6 +41,7 @@ module address(
   output use_bsx,
   input [14:0] bsx_regs,
   output dspx_enable,
+  output dspx_dp_enable,
   output dspx_a0
 );
 
@@ -73,8 +74,9 @@ assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
 
 assign IS_SAVERAM = SAVERAM_MASK[0]
                     &(featurebits[FEAT_ST0010]
-                      ?(SNES_ADDR[22:19] == 4'b1101
-                        && SNES_ADDR[15:12] == 4'b0000)
+                      ?((SNES_ADDR[22:19] == 4'b1101)
+                        & &(~SNES_ADDR[15:12])
+                        & SNES_ADDR[11])
                       :((MAPPER == 3'b000
                         || MAPPER == 3'b010
                         || MAPPER == 3'b110
@@ -220,6 +222,10 @@ wire dspx_enable_w =
   ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & &(~SNES_ADDR[19:16]) & ~SNES_ADDR[15])
   :1'b0;
 
+wire dspx_dp_enable_w = featurebits[FEAT_ST0010]
+                         &(SNES_ADDR[22:19] == 4'b1101
+                          && SNES_ADDR[15:11] == 5'b00000);
+
 assign dspx_a0 = featurebits[FEAT_DSPX]
                  ?((MAPPER == 3'b001) ? SNES_ADDR[14]
                    :(MAPPER == 3'b000) ? SNES_ADDR[12]
@@ -228,6 +234,11 @@ assign dspx_a0 = featurebits[FEAT_DSPX]
                  ?SNES_ADDR[0]
                  :1'b1;
 
+reg [7:0] dspx_dp_enable_r;
+initial dspx_dp_enable_r = 8'b00000000;
+always @(posedge CLK) dspx_dp_enable_r <= {dspx_dp_enable_r[6:0], dspx_dp_enable_w};
+assign dspx_dp_enable = &dspx_dp_enable_r[5:2];
+
 reg [7:0] dspx_enable_r;
 initial dspx_enable_r = 8'b00000000;
 always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[6:0], dspx_enable_w};
diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v
index 85d7a03..a1c72c0 100644
--- a/verilog/sd2snes/data.v
+++ b/verilog/sd2snes/data.v
@@ -46,7 +46,8 @@ module data(
   input msu_enable,
   input bsx_data_ovr,
   input srtc_enable,
-  input dspx_enable
+  input dspx_enable,
+  input dspx_dp_enable
 );
 
 reg [7:0] SNES_IN_MEM;
@@ -67,6 +68,7 @@ assign SNES_DATA = SNES_READ ? 8'bZ
                        : bsx_data_ovr ? BSX_DATA_OUT
                        : srtc_enable ? SRTC_DATA_OUT
                        : dspx_enable ? DSPX_DATA_OUT
+                       : dspx_dp_enable ? DSPX_DATA_OUT
                        : SNES_OUT_MEM)
                     );
 
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.v b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
index 42af65f..ac34494 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.v
@@ -42,26 +42,36 @@ module upd77c25_datram(
   wea,
   addra,
   dina,
-  douta
+  douta,
+  clkb,
+  web,
+  addrb,
+  dinb,
+  doutb
 );
 
 input clka;
 input [0 : 0] wea;
-input [7 : 0] addra;
+input [9 : 0] addra;
 input [15 : 0] dina;
 output [15 : 0] douta;
+input clkb;
+input [0 : 0] web;
+input [10 : 0] addrb;
+input [7 : 0] dinb;
+output [7 : 0] doutb;
 
 // synthesis translate_off
 
   BLK_MEM_GEN_V6_1 #(
-    .C_ADDRA_WIDTH(8),
-    .C_ADDRB_WIDTH(8),
+    .C_ADDRA_WIDTH(10),
+    .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
     .C_AXI_ID_WIDTH(4),
     .C_AXI_SLAVE_TYPE(0),
     .C_AXI_TYPE(1),
     .C_BYTE_SIZE(9),
-    .C_COMMON_CLK(0),
+    .C_COMMON_CLK(1),
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
@@ -85,13 +95,13 @@ output [15 : 0] douta;
     .C_INITB_VAL("0"),
     .C_INTERFACE_TYPE(0),
     .C_LOAD_INIT_FILE(0),
-    .C_MEM_TYPE(0),
+    .C_MEM_TYPE(2),
     .C_MUX_PIPELINE_STAGES(0),
     .C_PRIM_TYPE(1),
-    .C_READ_DEPTH_A(256),
-    .C_READ_DEPTH_B(256),
+    .C_READ_DEPTH_A(1024),
+    .C_READ_DEPTH_B(2048),
     .C_READ_WIDTH_A(16),
-    .C_READ_WIDTH_B(16),
+    .C_READ_WIDTH_B(8),
     .C_RST_PRIORITY_A("CE"),
     .C_RST_PRIORITY_B("CE"),
     .C_RST_TYPE("SYNC"),
@@ -105,12 +115,12 @@ output [15 : 0] douta;
     .C_USE_SOFTECC(0),
     .C_WEA_WIDTH(1),
     .C_WEB_WIDTH(1),
-    .C_WRITE_DEPTH_A(256),
-    .C_WRITE_DEPTH_B(256),
+    .C_WRITE_DEPTH_A(1024),
+    .C_WRITE_DEPTH_B(2048),
     .C_WRITE_MODE_A("WRITE_FIRST"),
     .C_WRITE_MODE_B("WRITE_FIRST"),
     .C_WRITE_WIDTH_A(16),
-    .C_WRITE_WIDTH_B(16),
+    .C_WRITE_WIDTH_B(8),
     .C_XDEVICEFAMILY("spartan3")
   )
   inst (
@@ -119,17 +129,17 @@ output [15 : 0] douta;
     .ADDRA(addra),
     .DINA(dina),
     .DOUTA(douta),
+    .CLKB(clkb),
+    .WEB(web),
+    .ADDRB(addrb),
+    .DINB(dinb),
+    .DOUTB(doutb),
     .RSTA(),
     .ENA(),
     .REGCEA(),
-    .CLKB(),
     .RSTB(),
     .ENB(),
     .REGCEB(),
-    .WEB(),
-    .ADDRB(),
-    .DINB(),
-    .DOUTB(),
     .INJECTSBITERR(),
     .INJECTDBITERR(),
     .SBITERR(),
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
index 14b0488..6ca0c10 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 13.1
-# Date: Mon Jun 13 22:15:19 2011
+# Date: Sun Jun 19 20:18:04 2011
 #
 ##############################################################
 #
@@ -37,7 +37,7 @@ SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
 CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
+CSET assume_synchronous_clk=true
 CSET axi_id_width=4
 CSET axi_slave_type=Memory_Slave
 CSET axi_type=AXI4_Full
@@ -55,7 +55,7 @@ CSET error_injection_type=Single_Bit_Error_Injection
 CSET fill_remaining_memory_locations=false
 CSET interface_type=Native
 CSET load_init_file=false
-CSET memory_type=Single_Port_RAM
+CSET memory_type=True_Dual_Port_RAM
 CSET operating_mode_a=WRITE_FIRST
 CSET operating_mode_b=WRITE_FIRST
 CSET output_reset_value_a=0
@@ -64,12 +64,12 @@ CSET pipeline_stages=0
 CSET port_a_clock=100
 CSET port_a_enable_rate=100
 CSET port_a_write_rate=50
-CSET port_b_clock=0
-CSET port_b_enable_rate=0
-CSET port_b_write_rate=0
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=50
 CSET primitive=8kx2
 CSET read_width_a=16
-CSET read_width_b=16
+CSET read_width_b=8
 CSET register_porta_input_of_softecc=false
 CSET register_porta_output_of_memory_core=false
 CSET register_porta_output_of_memory_primitives=false
@@ -90,12 +90,12 @@ CSET use_regcea_pin=false
 CSET use_regceb_pin=false
 CSET use_rsta_pin=false
 CSET use_rstb_pin=false
-CSET write_depth_a=256
+CSET write_depth_a=1024
 CSET write_width_a=16
-CSET write_width_b=16
+CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
 MISC pkg_timestamp=2011-02-03T22:20:43.000Z
 # END Extra information
 GENERATE
-# CRC: 47f41c0a
+# CRC: 78e2bfe1
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xise b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xise
index a3a9453..bf1c887 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datram.xise
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datram.xise
@@ -16,18 +16,18 @@
 
   <files>
     <file xil_pn:name="upd77c25_datram.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="upd77c25_datram.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
@@ -57,8 +57,8 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_DesignName" xil_pn:value="upd77c25_datram" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-12T12:22:04" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E74E33E1C0D35CC1635D07CFA337E6AE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-19T22:19:34" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7F45C8B1F52A8325441F5123ACDF0DA6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
diff --git a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise
index 42d3a55..4841bfe 100644
--- a/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise
+++ b/verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise
@@ -36,333 +36,27 @@
   </files>
 
   <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="upd77c25_datrom" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-06-18T15:59:22" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DF454E6807C1C626F0BE34B0774C60B8" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 230eab6..045e87e 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -73,8 +73,8 @@ module main(
   ,
   output p113_out
 );
-
-assign p113_out = SNES_READ;
+wire dspx_dp_enable;
+assign p113_out = dspx_dp_enable;
 
 wire [7:0] spi_cmd_data;
 wire [7:0] spi_param_data;
@@ -260,7 +260,9 @@ upd77c25 snes_dspx (
   .PGM_WR_ADDR(dspx_pgm_addr),
   .DAT_WR(dspx_dat_we),
   .DAT_DI(dspx_dat_data),
-  .DAT_WR_ADDR(dspx_dat_addr)
+  .DAT_WR_ADDR(dspx_dat_addr),
+  .DP_nCS(~dspx_dp_enable),
+  .DP_ADDR(SNES_ADDR[10:0])
 );
 
 mcu_cmd snes_mcu_cmd(
@@ -396,6 +398,7 @@ address snes_addr(
   .srtc_enable(srtc_enable),
   //uPD77C25
   .dspx_enable(dspx_enable),
+  .dspx_dp_enable(dspx_dp_enable),
   .dspx_a0(DSPX_A0)
 );
 
@@ -432,7 +435,8 @@ data snes_data(
   .msu_enable(msu_enable),
   .bsx_data_ovr(bsx_data_ovr),
   .srtc_enable(srtc_enable),
-  .dspx_enable(dspx_enable)
+  .dspx_enable(dspx_enable),
+  .dspx_dp_enable(dspx_dp_enable)
 );
 
 parameter MODE_SNES = 1'b0;
@@ -624,7 +628,7 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
 //assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
 
 //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
-assign SNES_DATABUS_OE = dspx_enable ? 1'b0 :
+assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          msu_enable ? 1'b0 :
                          bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
                          srtc_enable ? (SNES_READ & SNES_WRITE) :
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index 5a39501..e9b2558 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -204,7 +204,7 @@
     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -381,8 +381,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
diff --git a/verilog/sd2snes/upd77c25.v b/verilog/sd2snes/upd77c25.v
index d0361c5..b91894a 100644
--- a/verilog/sd2snes/upd77c25.v
+++ b/verilog/sd2snes/upd77c25.v
@@ -34,6 +34,9 @@ module upd77c25(
   input [15:0] DAT_DI,
   input [10:0] DAT_WR_ADDR,
 
+  input DP_nCS,
+  input [10:0] DP_ADDR,
+
   // debug
   output [15:0] DR,
   output [15:0] SR,
@@ -73,6 +76,7 @@ reg [10:0] pc;        // program counter
 
 reg [7:0] insn_state; // execute state
 
+reg [1:0] regs_dpb;
 reg [3:0] regs_dph;
 reg [3:0] regs_dpl;
 
@@ -122,17 +126,48 @@ upd77c25_datrom datrom (
   .doutb(dat_doutb) // output [15 : 0] doutb
 );
 
-wire [15:0] ram_douta;
-wire [7:0] ram_addra;
-upd77c25_datram datram (
-  .clka(CLK),
-  .wea(ram_wea), // Bus [0 : 0]
-  .addra(ram_addra), // Bus [7 : 0]
-  .dina(ram_dina), // Bus [15 : 0]
-  .douta(ram_douta)); // Bus [15 : 0]
+reg [7:0] reg_nCS_sreg;
+initial reg_nCS_sreg = 8'b11111111;
+always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS};
 
+reg [5:0] reg_oe_sreg;
+initial reg_oe_sreg = 6'b111111;
+always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
+wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
+wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000);
+
+reg [7:0] reg_DP_nCS_sreg;
+initial reg_DP_nCS_sreg = 8'b11111111;
+always @(posedge CLK) reg_DP_nCS_sreg <= {reg_DP_nCS_sreg[6:0], DP_nCS};
+
+reg [5:0] reg_we_sreg;
+initial reg_we_sreg = 6'b111111;
+always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
+wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
+wire reg_dp_we_rising = !reg_DP_nCS_sreg[2] && (reg_we_sreg[5:0] == 6'b000011);
+
+wire [15:0] ram_douta;
+wire [9:0] ram_addra;
+reg [7:0] DP_DOr;
+wire [7:0] DP_DO;
+wire [7:0] UPD_DO;
+
+
+upd77c25_datram datram (
+  .clka(CLK), // input clka
+  .wea(ram_wea), // input [0 : 0] wea
+  .addra(ram_addra), // input [9 : 0] addra
+  .dina(ram_dina), // input [15 : 0] dina
+  .douta(ram_douta), // output [15 : 0] douta
+  .clkb(CLK), // input clkb
+  .web(reg_dp_we_rising), // input [0 : 0] web
+  .addrb(DP_ADDR), // input [10 : 0] addrb
+  .dinb(DI), // input [7 : 0] dinb
+  .doutb(DP_DO) // output [7 : 0] doutb
+);
 assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_NEXT);
-assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100)
+assign ram_addra = {regs_dpb,
+                    regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100)
                                 ? 4'b0100
                                 : 4'b0000),
                     regs_dpl};
@@ -186,6 +221,7 @@ initial begin
   pc = 11'b0;
   regs_sr = 16'b0;
   regs_rp = 16'h0000;
+  regs_dpb = 2'b0;
   regs_dph = 4'b0;
   regs_dpl = 4'b0;
   regs_k = 16'b0;
@@ -203,24 +239,6 @@ initial begin
   regs_dr = 16'b0;
 end
 
-always @(posedge CLK) begin
-
-end
-
-reg [7:0] reg_nCS_sreg;
-initial reg_nCS_sreg = 8'b11111111;
-always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS};
-
-reg [5:0] reg_oe_sreg;
-initial reg_oe_sreg = 6'b111111;
-always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
-wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
-
-reg [5:0] reg_we_sreg;
-initial reg_we_sreg = 6'b111111;
-always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
-wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
-
 reg [7:0] A0r;
 initial A0r = 8'b11111111;
 always @(posedge CLK) A0r <= {A0r[6:0], A0};
@@ -303,7 +321,12 @@ always @(posedge CLK) begin
   end
 end
 
-assign DO = (A0 ? regs_sr[15:8] : (regs_sr[SR_DRC] ? regs_dr[7:0] : (regs_sr[SR_DRS] ? regs_dr[15:8] : regs_dr[7:0])));
+always @(posedge CLK) begin
+  if(reg_oe_falling) DP_DOr <= DP_DO;
+end
+
+assign UPD_DO = (A0 ? regs_sr[15:8] : (regs_sr[SR_DRC] ? regs_dr[7:0] : (regs_sr[SR_DRS] ? regs_dr[15:8] : regs_dr[7:0])));
+assign DO = !DP_nCS ? DP_DOr : UPD_DO;
 
 always @(posedge CLK) begin
   if(RST) begin
@@ -338,7 +361,7 @@ always @(posedge CLK) begin
               4'b0001: idb <= regs_ab[0];
               4'b0010: idb <= regs_ab[1];
               4'b0011: idb <= regs_tr;
-              4'b0100: idb <= {regs_dph,regs_dpl};
+              4'b0100: idb <= {regs_dpb,regs_dph,regs_dpl};
               4'b0101: idb <= regs_rp;
               4'b0110: idb <= dat_doutb; // Address: [regs_rp]
               4'b0111: idb <= flags_s1[0] ? 16'h7fff : 16'h8000;
@@ -410,7 +433,7 @@ always @(posedge CLK) begin
                 alu_store <= 2'b01;
               end
               4'b0011: regs_tr <= idb;
-              4'b0100: {regs_dph,regs_dpl} <= idb[7:0];
+              4'b0100: {regs_dpb,regs_dph,regs_dpl} <= idb[9:0];
               4'b0101: regs_rp <= idb;
 //              4'b0110: regs_dr <= idb;
               4'b0111: begin
@@ -481,7 +504,7 @@ always @(posedge CLK) begin
               4'b0001: regs_ab[0] <= ld_id;
               4'b0010: regs_ab[1] <= ld_id;
               4'b0011: regs_tr <= ld_id;
-              4'b0100: {regs_dph,regs_dpl} <= ld_id[7:0];
+              4'b0100: {regs_dpb,regs_dph,regs_dpl} <= ld_id[9:0];
               4'b0101: regs_rp <= ld_id;
 //              4'b0110: regs_dr <= ld_id;
               4'b0111: begin
@@ -599,6 +622,7 @@ always @(posedge CLK) begin
     regs_sr[8] <= 0;
     regs_sr[7] <= 0;
     regs_rp <= 16'h0000;
+    regs_dpb <= 2'b0;
     regs_dph <= 4'b0;
     regs_dpl <= 4'b0;
     regs_k <= 16'b0;