From 60d7a0811738e38182c2f6f76c40308bf7f835a4 Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Mon, 9 Jul 2012 02:13:44 +0200 Subject: [PATCH] FPGA: Adjust Cx4 timing to new master clock rate --- verilog/sd2snes_cx4/cx4.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v index a7197e1..c2a94d9 100644 --- a/verilog/sd2snes_cx4/cx4.v +++ b/verilog/sd2snes_cx4/cx4.v @@ -752,21 +752,21 @@ always @(posedge CLK) begin cpu_op <= cpu_op_w; casex(cpu_op_w[15:11]) 5'b00x01, 5'b00x10, 5'b00100, 5'b00111: begin - cpu_wait <= 8'h08; + cpu_wait <= 8'h07; CPU_STATE <= ST_CPU_4; end 5'b01110, 5'b01101, 5'b11101: begin cpu_wait <= 8'h03; CPU_STATE <= ST_CPU_4; end - 5'b10011: begin - cpu_wait <= 8'h03; + /*5'b10011: begin + cpu_wait <= 8'h02; CPU_STATE <= ST_CPU_4; end 5'b01000: begin - cpu_wait <= 8'h13; + cpu_wait <= 8'h0e; CPU_STATE <= ST_CPU_4; - end + end*/ default: begin cpu_wait <= 8'h00; CPU_STATE <= ST_CPU_0;