diff --git a/pcb/cart/sd2snes18.brd b/pcb/cart/sd2snes18.brd
index fc39185..c0c8839 100644
Binary files a/pcb/cart/sd2snes18.brd and b/pcb/cart/sd2snes18.brd differ
diff --git a/pcb/cart/sd2snes18.sch b/pcb/cart/sd2snes18.sch
index 8fbcfc7..1648ed0 100644
Binary files a/pcb/cart/sd2snes18.sch and b/pcb/cart/sd2snes18.sch differ
diff --git a/src/config b/src/config
index e402dff..a306bd8 100644
--- a/src/config
+++ b/src/config
@@ -27,7 +27,7 @@
 
 CONFIG_MCU=atmega644
 CONFIG_LINKER_RELAX=n
-CONFIG_MCU_FREQ=13500000
+CONFIG_MCU_FREQ=12288000
 CONFIG_BOOTLOADER=y
 CONFIG_BOOT_DEVID=0x4e534453
 CONFIG_UART_DEBUG=y
@@ -35,7 +35,7 @@ CONFIG_UART_BAUDRATE=38400
 CONFIG_UART_BUF_SHIFT=7
 CONFIG_HARDWARE_NAME=sd2snes
 CONFIG_SD_AUTO_RETRIES=10
-#CONFIG_SD_DATACRC=y
+CONFIG_SD_DATACRC=y
 CONFIG_EEPROM_SIZE=512
 CONFIG_EEPROM_OFFSET=512
 CONFIG_MAX_PARTITIONS=1
diff --git a/src/config.h b/src/config.h
index 6c33409..a5e6255 100644
--- a/src/config.h
+++ b/src/config.h
@@ -62,8 +62,8 @@
 #    error Unknown chip!
 #  endif
 #  define SD_CHANGE_VECT        INT0_vect
-#  define SDCARD_WP  			(PINB & _BV(PB3))
-#  define SDCARD_WP_SETUP()     do { DDRB &= ~ _BV(PB3); PORTB |= _BV(PB3); } while(0)
+#  define SDCARD_WP  			(PINB & _BV(PB1))
+#  define SDCARD_WP_SETUP()     do { DDRB &= ~ _BV(PB1); PORTB |= _BV(PB1); } while(0)
 #  define SD_CHANGE_ICR         MCUCR
 #  define SD_SUPPLY_VOLTAGE     (1L<<21)
 #  define DEVICE_SELECT         (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3)))
diff --git a/src/fpga.c b/src/fpga.c
index 846f84d..516fc59 100644
--- a/src/fpga.c
+++ b/src/fpga.c
@@ -31,9 +31,11 @@
    CCLK			PD4		OUT
    INIT_B		PD7		IN
    DIN			PC7		OUT
+   DONE			PA3		IN
  */
 
 #include <avr/pgmspace.h>
+#include <util/delay.h>
 #include "fpga.h"
 #include "config.h"
 #include "uart.h"
@@ -89,11 +91,13 @@ void fpga_init() {
 	DDRC = _BV(PC7);	// for FPGA config, PC7 is output
 
 	DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
+	
+	DDRA = ~_BV(PA3); // PA3 is input <- DONE
 	set_cclk(0);    // initial clk=0
 }
 
 int fpga_get_done(void) {
-	return 0;
+	return PINA & _BV(PA3);
 }
 
 void fpga_postinit() {
@@ -103,43 +107,45 @@ void fpga_postinit() {
 }
 
 void fpga_pgm(char* filename) {
-	set_prog_b(0);
-	uart_putc('P');
-	set_prog_b(1);
-	loop_until_bit_is_set(PIND, PD7);
-	uart_putc('p');
-	
-//	FIL in;
-//	FRESULT res;
-	UINT bytes_read;
+	int MAXRETRIES = 10;
+//	int retries = MAXRETRIES;
+	do {
+		set_prog_b(0);
+		uart_putc('P');
+		set_prog_b(1);
+		loop_until_bit_is_set(PIND, PD7);
+		uart_putc('p');
+		
+		UINT bytes_read;
 
-	// open configware file
-//	res=f_open(&in, filename, FA_READ);
-	file_open(filename, FA_READ);
-	if(file_res) {
-		uart_putc('?');
-		uart_putc(0x30+file_res);
-		return;
-	}
-	// file open successful
-	set_cs_b(0);
-	set_rdwr_b(0);
-
-    for (;;) {
-//        res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read);
-		bytes_read = file_read();
-		if (file_res || bytes_read == 0) break;   // error or eof
-		for(int i=0; i<bytes_read; i++) {
-			//FPGA_SEND_BYTE(file_buf[i]);
-			FPGA_SEND_BYTE_SERIAL(file_buf[i]);
+		// open configware file
+		file_open(filename, FA_READ);
+		if(file_res) {
+			uart_putc('?');
+			uart_putc(0x30+file_res);
+			return;
 		}
-    }
-
-	file_close();
+		// file open successful
+		set_cs_b(0);
+		set_rdwr_b(0);
+	
+		for (;;) {
+			bytes_read = file_read();
+			if (file_res || bytes_read == 0) break;   // error or eof
+			for(int i=0; i<bytes_read; i++) {
+				FPGA_SEND_BYTE_SERIAL(file_buf[i]);
+			}
+		}
+		file_close();
+		_delay_ms(10);
+	} while (0); //(!fpga_get_done() && retries--);
+	if(!fpga_get_done()) {
+		dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
+		_delay_ms(50);
+	}
 	fpga_postinit();
 }
 
-
 void set_avr_read(uint8_t val) {
 	if(val) {
 		PORTB |= _BV(PB3);
@@ -210,3 +216,4 @@ void set_avr_bank(uint8_t val) {
 	FPGA_SS_HIGH();
 	SPI_SS_LOW();
 }
+
diff --git a/src/led.c b/src/led.c
index 02091ba..a787b71 100644
--- a/src/led.c
+++ b/src/led.c
@@ -43,15 +43,24 @@ void update_leds(void) {
 }
 
 void toggle_busy_led(void) {
-	PORTB &= ~_BV(PB1);
-	DDRB ^= _BV(PB1);
+	PORTB &= ~_BV(PB3);
+	DDRB ^= _BV(PB3);
 }
 
 void set_busy_led(uint8_t state) {
-	PORTB &= ~_BV(PB1);
+	PORTB &= ~_BV(PB3);
 	if(state) {
-		DDRB |= _BV(PB1);
+		DDRB |= _BV(PB3);
 	} else {
-		DDRB &= ~_BV(PB1);
+		DDRB &= ~_BV(PB3);
+	}
+}
+
+void set_pwr_led(uint8_t state) {
+	PORTB &= ~_BV(PB0);
+	if(state) {
+		DDRB |= _BV(PB0);
+	} else {
+		DDRB &= ~_BV(PB0);
 	}
 }
diff --git a/src/led.h b/src/led.h
index d21d51d..4afe06e 100644
--- a/src/led.h
+++ b/src/led.h
@@ -41,6 +41,7 @@ extern volatile uint8_t led_state;
 void update_leds(void);
 void toggle_busy_led(void);
 void set_busy_led(uint8_t);
+void set_pwr_led(uint8_t);
 
 
 #endif
diff --git a/src/main.c b/src/main.c
index ae51d50..59f79d9 100644
--- a/src/main.c
+++ b/src/main.c
@@ -131,6 +131,7 @@ int main(void) {
 	snes_reset(1);
 	uart_init();
 	sei();   // suspected to reset the AVR when inserting an SD card
+	set_busy_led(0);
 	_delay_ms(100);
 	disk_init();
 	snes_init();
@@ -141,11 +142,11 @@ int main(void) {
 	file_init();
 	FATFS fatfs;
 	f_mount(0,&fatfs);
-	set_busy_led(1);
 	uart_putc('W');
 	fpga_init();
 	fpga_pgm("/sd2snes/main.bit");
 	_delay_ms(100);
+	set_pwr_led(1);
 	fpga_spi_init();
 	uart_putc('!');
 	_delay_ms(100);
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 7fae137..90e082a 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -120,8 +120,8 @@ NET "SRAM_ADDR[10]" LOC = P60;
 NET "SRAM_ADDR[11]" LOC = P59;
 NET "SRAM_ADDR[12]" LOC = P57;
 NET "SRAM_ADDR[13]" LOC = P56;
-NET "SRAM_ADDR[14]" LOC = P53;
-NET "SRAM_ADDR[15]" LOC = P52;
+NET "SRAM_ADDR[14]" LOC = P51;
+NET "SRAM_ADDR[15]" LOC = P50;
 NET "SRAM_ADDR[19]" LOC = P69;
 NET "SRAM_ADDR[8]" LOC = P68;
 NET "SRAM_ADDR[9]" LOC = P63;
@@ -233,9 +233,5 @@ NET "CLKIN" IOSTANDARD = LVCMOS33;
 NET "CLKIN" PULLUP;
 NET "SPI_SS" IOSTANDARD = LVCMOS33;
 NET "SPI_SS" PULLUP;
-NET "DCM_FX_STOPPED" LOC = P44;
-NET "DCM_FX_STOPPED" IOSTANDARD = LVCMOS33;
-NET "DCM_IN_STOPPED" LOC = P41;
-NET "DCM_IN_STOPPED" IOSTANDARD = LVCMOS33;
 //NET "DCM_RST" LOC = P46;
 //NET "DCM_RST" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 9ee6679..ea23033 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -110,8 +110,6 @@ avr_cmd snes_avr_cmd(
 );
 
 wire [7:0] DCM_STATUS;
-assign DCM_FX_STOPPED = DCM_STATUS[2];
-assign DCM_IN_STOPPED = DCM_STATUS[1];
 my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLKFX(CLK2),
                   .LOCKED(DCM_LOCKED),
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index 62923c1..4049288 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -73,6 +73,7 @@
     <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s200"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="true"/>
     <property xil_pn:name="Extra Effort" xil_pn:value="Normal"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
     <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>