diff --git a/verilog/sd2snes/bsx.v b/verilog/sd2snes/bsx.v
index d77d097..9fa6783 100644
--- a/verilog/sd2snes/bsx.v
+++ b/verilog/sd2snes/bsx.v
@@ -182,24 +182,25 @@ end
 
 
 always @(posedge clkin) begin
-  if(reg_oe_rising) begin
-    if(base_enable) begin
-	   case(base_addr)
-		  5'h0b: bs_stb0_offset <= bs_stb0_offset + 1;
-		  5'h0c: bs_page0_offset <= bs_page0_offset + 1; 
-		  5'h11: bs_stb1_offset <= bs_stb1_offset + 1;
-		  5'h12: bs_page1_offset <= bs_page1_offset + 1;
-		endcase
-	 end
-  end
+  if(reg_oe_rising && base_enable) begin
+    case(base_addr)
+	   5'h0b: begin
+		  bs_stb0_offset <= bs_stb0_offset + 1;
+		  base_regs[5'h0d] <= base_regs[5'h0d] | reg_data_in;
+		end
+		5'h0c: bs_page0_offset <= bs_page0_offset + 1; 
+		5'h11: begin
+		  bs_stb1_offset <= bs_stb1_offset + 1;
+  		  base_regs[5'h13] <= base_regs[5'h13] | reg_data_in;
+		end
+		5'h12: bs_page1_offset <= bs_page1_offset + 1;
+	 endcase
+  end else 
   if(reg_oe_falling) begin
     if(cart_enable)
       reg_data_outr <= {regs_outr[reg_addr], 7'b0};
     else if(base_enable) begin
       case(base_addr)
-		  5'h0b, 5'h11: begin
-		    base_regs[base_addr+5'h02] <= base_regs[base_addr+5'h02] | reg_data_in;
-		  end
         5'h0c, 5'h12: begin
           case (bs_page1_offset)
             4: reg_data_outr <= 8'h3;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index e3075b7..83ba278 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -463,7 +463,7 @@ reg [7:0] ROM_DOUTr;
 assign DSPX_SNES_DATA_IN = SNES_DATA;
 assign SRTC_SNES_DATA_IN = SNES_DATA[3:0];
 assign MSU_SNES_DATA_IN = SNES_DATA;
-assign BSX_SNES_DATA_IN = bs_page_enable ? SNES_DINr : SNES_DATA;
+assign BSX_SNES_DATA_IN = SNES_DATA;
 
 reg [7:0] r213fr;
 reg r213f_forceread;