From 68f255d75b804e30184f61c6b0cabb3f30508ee6 Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 10 Nov 2011 17:54:52 +0100 Subject: [PATCH] firmware, FPGA: fix for some SD cards --- src/sdnative.c | 3 +++ verilog/sd2snes/sd_dma.v | 6 +++--- verilog/sd2snes_cx4/sd_dma.v | 6 +++--- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/sdnative.c b/src/sdnative.c index 95abd93..76218b9 100644 --- a/src/sdnative.c +++ b/src/sdnative.c @@ -867,6 +867,9 @@ DRESULT sdn_initialize(BYTE drv) { if(rsp[1]&0x80) break; } + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + BITBAND(SD_DAT3REG->FIOCLR, SD_DAT3PIN) = 1; + ccs = (rsp[1]>>6) & 1; /* SDHC/XC */ cmd_slow(ALL_SEND_CID, 0, 0x4d, NULL, rsp); diff --git a/verilog/sd2snes/sd_dma.v b/verilog/sd2snes/sd_dma.v index 0d7d2c8..2137370 100644 --- a/verilog/sd2snes/sd_dma.v +++ b/verilog/sd2snes/sd_dma.v @@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; // we have 4 internal cycles per SD clock, 8 per RAM byte write reg [2:0] clkcnt; initial clkcnt = 3'b000; -reg SD_CLKr; -always @(posedge CLK) SD_CLKr <= clkcnt[1]; -assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; +reg [1:0] SD_CLKr; +always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]}; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ; always @(posedge CLK) begin if(SD_DMA_EN_rising) begin diff --git a/verilog/sd2snes_cx4/sd_dma.v b/verilog/sd2snes_cx4/sd_dma.v index 0d7d2c8..2137370 100644 --- a/verilog/sd2snes_cx4/sd_dma.v +++ b/verilog/sd2snes_cx4/sd_dma.v @@ -71,9 +71,9 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; // we have 4 internal cycles per SD clock, 8 per RAM byte write reg [2:0] clkcnt; initial clkcnt = 3'b000; -reg SD_CLKr; -always @(posedge CLK) SD_CLKr <= clkcnt[1]; -assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; +reg [1:0] SD_CLKr; +always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]}; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ; always @(posedge CLK) begin if(SD_DMA_EN_rising) begin