From 7109f9e03079cfe0b302aac1fe7998cd81c5dd80 Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Wed, 2 May 2012 10:46:27 +0200 Subject: [PATCH] FPGA: add SD clock pullup to test configuration --- verilog/sd2snes_test/main.ucf | 1 + 1 file changed, 1 insertion(+) diff --git a/verilog/sd2snes_test/main.ucf b/verilog/sd2snes_test/main.ucf index 453ebf9..67fa757 100644 --- a/verilog/sd2snes_test/main.ucf +++ b/verilog/sd2snes_test/main.ucf @@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63; # PlanAhead Generated IO constraints NET "SD_CLK" IOSTANDARD = LVCMOS33; +NET "SD_CLK" PULLUP; NET "SD_CMD" IOSTANDARD = LVCMOS33; NET "SD_DAT[0]" IOSTANDARD = LVCMOS33; NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;