SuperCIC/key: fix unreliable pair mode entry (sync with lock)
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37a9f09a78
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@ -64,6 +64,7 @@ processor p12f629
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; 0x4d buffer for eeprom access
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; 0x4e loop variable for longwait
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; 0x4f loop variable for wait
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; 0x5c GPIO buffer variable for pair mode allow
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; 0x5d 0: SuperCIC pair mode available flag
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; 0x5e SuperCIC pair mode detect (phase 1)
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; 0x5f SuperCIC pair mode detect (phase 2)
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@ -90,8 +91,8 @@ isr
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clrf 0x5f ; clear pair mode detect
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bsf 0x5f, 1 ;
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clrf 0x5d ; clear pair mode available
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nop
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nop
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clrf 0x5c ; clear pair mode allow buffer
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bsf 0x5c, 3 ; assume disallow
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bsf INTCON, 7 ; re-enable interrupts (ISR will continue as main)
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goto main
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init
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@ -296,8 +297,8 @@ swapskip
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; indirect access, no post increment, etc.
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mangle
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call mangle_lock
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nop
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nop
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movf GPIO, w ; buffer GPIO state
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movwf 0x5c ; for pair mode "transaction"
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mangle_key
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movf 0x2f, w
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movwf 0x20
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@ -459,7 +460,7 @@ mangle_key_withskip
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;-------pair mode code-------
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bcf GPIO, 0
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movf GPIO, w
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btfss GPIO, 3
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btfss 0x5c, 3
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bsf GPIO, 0
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movwf 0x5e
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movf GPIO, w
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@ -642,7 +643,7 @@ mangle_lock_withskip
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goto scic_pair_skip1
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btfsc 0x5f, 1
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goto scic_pair_skip2
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btfsc GPIO, 3
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btfsc 0x5c, 3
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goto scic_pair_skip3
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goto supercic_pairmode
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scic_pair_skip1
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