diff --git a/pcb/cart/sd2snes1.brd b/pcb/cart/sd2snes1.brd
index f61956f..9097d72 100644
Binary files a/pcb/cart/sd2snes1.brd and b/pcb/cart/sd2snes1.brd differ
diff --git a/pcb/cart/sd2snes1.sch b/pcb/cart/sd2snes1.sch
index 46b1062..84bd277 100644
Binary files a/pcb/cart/sd2snes1.sch and b/pcb/cart/sd2snes1.sch differ
diff --git a/src/Makefile b/src/Makefile
index 3371ab8..aa7604d 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -100,7 +100,7 @@ FORMAT = ihex
 TARGET = $(OBJDIR)/sd2snes
 
 # List C source files here. (C dependencies are automatically generated.)
-SRC = main.c ff.c utils.c timer.c led.c diskio.c sdcard.c spi.c crc7.c snes.c fpga.c memory.c crc16.c fileops.c
+SRC = main.c ff.c utils.c timer.c led.c diskio.c sdcard.c spi.c crc7.c snes.c fpga.c memory.c crc16.c fileops.c fpga_spi.c
 
 ifeq ($(CONFIG_UART_DEBUG),y)
   SRC += uart.c
diff --git a/src/config b/src/config
index 1227775..a098d1f 100644
--- a/src/config
+++ b/src/config
@@ -25,9 +25,9 @@
 # This file is included in the main sd2iec Makefile and also parsed
 # into autoconf.h.
 
-CONFIG_MCU=atmega644p
+CONFIG_MCU=atmega644
 CONFIG_LINKER_RELAX=n
-CONFIG_MCU_FREQ=14318180
+CONFIG_MCU_FREQ=13500000
 CONFIG_BOOTLOADER=y
 CONFIG_BOOT_DEVID=0x4e534453
 CONFIG_UART_DEBUG=y
diff --git a/src/fpga.c b/src/fpga.c
index 32c3cd1..5be7c27 100644
--- a/src/fpga.c
+++ b/src/fpga.c
@@ -6,7 +6,8 @@
 
    FPGA pin mapping
    ================
-
+ PSM:
+ ====
    FPGA			AVR		dir
    ------------------------
    PROG_B		PD3		OUT
@@ -14,6 +15,7 @@
    CS_B			PD7		OUT
    INIT_B		PB2		IN
    RDWR_B		PB3		OUT
+
    D7			PC0		OUT
    D6			PC1		OUT
    D5			PC2		OUT
@@ -23,6 +25,12 @@
    D1			PC6		OUT
    D0			PC7		OUT
 
+ SSM:
+ ====
+   PROG_B		PD3		OUT
+   CCLK			PD4		OUT
+   INIT_B		PD7		IN
+   DIN			PC7		OUT
  */
 
 #include <avr/pgmspace.h>
@@ -33,6 +41,9 @@
 #include "diskio.h"
 #include "ff.h"
 #include "fileops.h"
+#include "fpga_spi.h"
+#include "spi.h"
+#include "avrcompat.h"
 
 DWORD get_fattime(void) {
 	return 0L;
@@ -71,12 +82,12 @@ void set_cclk(uint8_t val) {
 
 void fpga_init() {
 	DDRB |= _BV(PB3);	// PB3 is output
-    DDRB &= ~_BV(PB2);  // PB2 is input
 
-    DDRC = 0xff;	// for FPGA config, all PORTC pins are outputs
+    DDRD &= ~_BV(PD7);  // PD7 is input
 
-	DDRD |= _BV(PD3) | _BV(PD4) | _BV(PD7); // PD3, PD4, PD7 are outputs
+    DDRC = _BV(PC7);	// for FPGA config, PC7 is output
 
+	DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
 	set_cclk(0);    // initial clk=0
 }
 
@@ -87,23 +98,26 @@ int fpga_get_done(void) {
 void fpga_postinit() {
 	DDRA |= _BV(PA0) | _BV(PA1) | _BV(PA2) | _BV(PA4) | _BV(PA5) | _BV(PA6); // MAPPER+NEXTADDR output
 	DDRB |= _BV(PB2) | _BV(PB1) | _BV(PB0);	// turn PB2 into output, enable AVR_BANK
+    DDRD |= _BV(PD7);	// turn PD7 into output
 }
 
 void fpga_pgm(char* filename) {
 	set_prog_b(0);
 	uart_putc('P');
 	set_prog_b(1);
-	loop_until_bit_is_set(PINB, PB2);
+	loop_until_bit_is_set(PIND, PD7);
 	uart_putc('p');
 	
-	FIL in;
-	FRESULT res;
+//	FIL in;
+//	FRESULT res;
 	UINT bytes_read;
 
 	// open configware file
-	res=f_open(&in, filename, FA_READ);
-	if(res) {
+//	res=f_open(&in, filename, FA_READ);
+	file_open(filename, FA_READ);
+	if(file_res) {
 		uart_putc('?');
+		uart_putc(0x30+file_res);
 		return;
 	}
 	// file open successful
@@ -111,14 +125,16 @@ void fpga_pgm(char* filename) {
 	set_rdwr_b(0);
 
     for (;;) {
-        res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read);
-        if (res || bytes_read == 0) break;   // error or eof
+//        res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read);
+		bytes_read = file_read();
+        if (file_res || bytes_read == 0) break;   // error or eof
 		for(int i=0; i<bytes_read; i++) {
-			FPGA_SEND_BYTE(file_buf[i]);
+			//FPGA_SEND_BYTE(file_buf[i]);
+			FPGA_SEND_BYTE_SERIAL(file_buf[i]);
 		}
     }
 
-	f_close(&in);
+	file_close();
 	fpga_postinit();
 }
 
@@ -176,8 +192,11 @@ void set_avr_addr_en(uint8_t val) {
 }
 
 void set_avr_mapper(uint8_t val) {
-	PORTA &= 0xF0;
-	PORTA |= val&0x07;
+	SPI_SS_HIGH();
+	FPGA_SS_LOW();
+	spiTransferByte(0x30 | (val & 0x0f));
+	FPGA_SS_HIGH();
+	SPI_SS_LOW();
 }
 
 void set_avr_bank(uint8_t val) {
diff --git a/src/fpga.h b/src/fpga.h
index a265121..799f6ca 100644
--- a/src/fpga.h
+++ b/src/fpga.h
@@ -21,6 +21,11 @@ void set_avr_bank(uint8_t val);
 
 // some macros for bulk transfers (faster)
 #define FPGA_SEND_BYTE(data)	do {SET_AVR_DATA(data); CCLK();} while (0)
+#define FPGA_SEND_BYTE_SERIAL(data)	do {SET_AVR_DATA(data); CCLK();\
+SET_AVR_DATA(data<<1); CCLK(); SET_AVR_DATA(data<<2); CCLK();\
+SET_AVR_DATA(data<<3); CCLK(); SET_AVR_DATA(data<<4); CCLK();\
+SET_AVR_DATA(data<<5); CCLK(); SET_AVR_DATA(data<<6); CCLK();\
+SET_AVR_DATA(data<<7); CCLK();} while (0)
 #define SET_CCLK()				do {PORTD |= _BV(PD4);} while (0)
 #define CLR_CCLK()				do {PORTD &= ~_BV(PD4);} while (0)
 #define CCLK()					do {SET_CCLK(); CLR_CCLK();} while (0)
diff --git a/src/led.c b/src/led.c
index d49563d..67d96d9 100644
--- a/src/led.c
+++ b/src/led.c
@@ -41,3 +41,8 @@ volatile uint8_t led_state;
  */
 void update_leds(void) {
 }
+
+void toggle_busy_led(void) {
+	PORTB &= ~_BV(PB1);
+	DDRB ^= _BV(PB1);
+}
diff --git a/src/led.h b/src/led.h
index 7992aad..858f36d 100644
--- a/src/led.h
+++ b/src/led.h
@@ -39,6 +39,7 @@ extern volatile uint8_t led_state;
 
 /* Update the LEDs to match the buffer state */
 void update_leds(void);
+void toggle_busy_led(void);
 
 /* Wrapped in do..while to avoid "ambigious else" warnings */
 #ifdef SINGLE_LED
diff --git a/src/main.c b/src/main.c
index a4310e8..0c3f6e7 100644
--- a/src/main.c
+++ b/src/main.c
@@ -44,6 +44,7 @@
 #include "snes.h"
 #include "fileops.h"
 #include "memory.h"
+#include "fpga_spi.h"
 
 char stringbuf[100];
 
@@ -152,36 +153,35 @@ int main(void) {
     uart_putc('W');
     fpga_init();
     fpga_pgm("/sd2snes/main.bit");
+	fpga_spi_init();
     uart_putc('!');
 	_delay_ms(100);
-    set_avr_bank(0);
+//set_avr_bank(0);
     set_avr_ena(0);
-    set_avr_read(1);
-    set_avr_write(1);
-    AVR_ADDR_RESET();
-    set_avr_addr_en(0);
+//    set_avr_read(1);
+//    set_avr_write(1);
+//    AVR_ADDR_RESET();
+//    set_avr_addr_en(0);
 	snes_reset(1);
 
 	uart_putc('(');
 	load_rom("/test.smc");
 	uart_putc(')');
 
-	uart_putc('[');
+/*XXX	uart_putc('[');
 	load_sram("/test.srm");
-	uart_putc(']');
+	uart_putc(']');*/
 
-	AVR_ADDR_RESET();
-	set_avr_mapper(0); 
+	set_avr_mapper(1); 
 	set_avr_ena(1);
-	set_avr_read(0);
-	set_avr_bank(0);
 	_delay_ms(100);
 	uart_puts_P(PSTR("SNES GO!"));
 	snes_reset(0);
-	DDRC = 0x00;
 
+	_delay_ms(6553.6);
+	
 	while(1) {
-		snes_main_loop();
+//		snes_main_loop();
 	}
 	while(1) {
 	    uint8_t data=PINC;
diff --git a/src/memory.c b/src/memory.c
index 19caa8a..59c2e41 100644
--- a/src/memory.c
+++ b/src/memory.c
@@ -10,29 +10,49 @@
 #include "crc16.h"
 #include "ff.h"
 #include "fileops.h"
+#include "spi.h"
+#include "fpga_spi.h"
+#include "avrcompat.h"
+#include "led.h"
 
 char* hex = "0123456789ABCDEF";
 
 uint32_t load_rom(char* filename) {
 // TODO Mapper, Mirroring, Bankselect
 //	snes_rom_properties_t romprops;
-	set_avr_bank(0);
-	AVR_ADDR_RESET();
-	SET_AVR_READ();
+//	set_avr_bank(0);
 	UINT bytes_read;
 	DWORD filesize;
+	UINT count=0;
 	file_open(filename, FA_READ);
 	filesize = file_handle.fsize;
-	if(file_res) return 0;
+	if(file_res) {
+		uart_putc('?');
+		uart_putc(0x30+file_res);
+		return 0;
+	}
 //	snes_rom_id(&romprops, &file_handle);
 	for(;;) {
+		FPGA_SS_HIGH();
+		SPI_SS_LOW();
 		bytes_read = file_read();
+		SPI_SS_HIGH();
 		if (file_res || !bytes_read) break;
-		for(int j=0; j<bytes_read; j++) {
-			SET_AVR_DATA(file_buf[j]);
-			AVR_WRITE();
-			AVR_NEXTADDR();
+		FPGA_SS_LOW();
+		_delay_us(1);
+		spiTransferByte(0x91); // write w/ increment
+		if(!(count++ % 16)) {
+			toggle_busy_led();
 		}
+		for(int j=0; j<bytes_read; j++) {
+			spiTransferByte(file_buf[j]);
+//			uart_putc((file_buf[j] > 0x20)
+//						&& (file_buf[j] < ('z'+1)) ? file_buf[j]:'.');
+//			_delay_ms(2);
+		}
+		spiTransferByte(0x00); // dummy tx for increment+write pulse
+		_delay_us(10);
+		FPGA_SS_HIGH();
 	}
 	file_close();
 	return (uint32_t)filesize;
diff --git a/src/sdcard.c b/src/sdcard.c
index a27aff0..d5814c1 100644
--- a/src/sdcard.c
+++ b/src/sdcard.c
@@ -536,6 +536,7 @@ DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
         res = sendCommand(drv, READ_SINGLE_BLOCK, (sector+sec) << 9, 0);
 
       if (res != 0) {
+		uart_putc('?');
         SPI_SS_HIGH(drv);
         disk_state = DISK_ERROR;
         return RES_ERROR;
@@ -543,6 +544,7 @@ DRESULT sd_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) {
 
       // Wait for data token
       if (!sdResponse(0xFE)) {
+		uart_putc('-');
         SPI_SS_HIGH(drv);
         disk_state = DISK_ERROR;
         return RES_ERROR;
diff --git a/src/snes.c b/src/snes.c
index 46f5907..f817c92 100644
--- a/src/snes.c
+++ b/src/snes.c
@@ -17,7 +17,8 @@ uint32_t sram_crc, sram_crc_old;
 uint32_t sram_size = 8192; // sane default
 
 void snes_init() {
-	DDRD |= _BV(PD5); 	// PD5 = OUTPUT
+	DDRD |= _BV(PD5);	// PD5 = RESET_DIR
+	DDRD |= _BV(PD6); 	// PD6 = RESET
 	snes_reset(1); 
 }
 
@@ -28,9 +29,13 @@ void snes_init() {
  */
 void snes_reset(int state) {
 	if(state) {
-		PORTD &= ~ _BV(PD5);
+		DDRD |= _BV(PD6);	// /RESET pin -> out
+		PORTD &= ~_BV(PD6); // /RESET = 0
+		PORTD |= _BV(PD5);  // RESET_DIR = 1;
 	} else {
-		PORTD |= _BV(PD5);
+		PORTD &= ~_BV(PD5); // RESET_DIR = 0;
+		DDRD &= ~_BV(PD6);  // /RESET pin -> in
+		PORTD |= _BV(PD6);  // /RESET = 1
 	}
 }
 
diff --git a/src/spi.c b/src/spi.c
index c01dc14..8cc6119 100644
--- a/src/spi.c
+++ b/src/spi.c
@@ -67,7 +67,7 @@ void spiInit(void)
   //   leading edge rising, sample on leading edge, clock = f/4
   SPCR = 0b01010000;
 
-  // Enable SPI double speed mode -> clock = f/8
+  // Enable SPI double speed mode -> clock = f/2
   SPSR = _BV(SPI2X);
 
   // clear status
diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v
index 3f6fb9d..1094979 100644
--- a/verilog/sd2snes/address.v
+++ b/verilog/sd2snes/address.v
@@ -23,35 +23,34 @@ module address(
     input [2:0] MAPPER,       // AVR detected mapper
     input [23:0] SNES_ADDR,   // requested address from SNES
     input SNES_CS,            // "CART" pin from SNES (active low)
-    output [20:0] SRAM_ADDR,  // Address to request from SRAM
+    output [19:0] SRAM_ADDR,  // Address to request from SRAM
     output [3:0] ROM_SEL,     // which SRAM unit to access (active low)
-    input AVR_ADDR_RESET,     // reset AVR sequence (active low)
-    input AVR_NEXTADDR,       // next byte request from AVR
     input AVR_ENA,            // enable AVR master mode (active low)
-    input AVR_ADDR_EN,        // enable address counter (active low)
-    input [1:0] AVR_BANK,     // which bank does the AVR want
 	 input MODE,               // AVR(1) or SNES(0) ("bus phase")
     output IS_SAVERAM,        // address/CS mapped as SRAM?
     output IS_ROM,            // address mapped as ROM?
-    input AVR_NEXTADDR_CURR,
-    input AVR_NEXTADDR_PREV
+    input [23:0] AVR_ADDR,    // allow address to be set externally
+    input ADDR_WRITE,
+    output SRAM_BHE,
+    output SRAM_BLE,
+    output SRAM_ADDR0
     );
 
 reg [22:0] SRAM_ADDR_BUF;
 reg [3:0] ROM_SEL_BUF;
 reg [3:0] AVR_ROM_SEL_BUF;
-reg [20:0] AVR_ADDR;
 reg [3:0] CS_ARRAY[3:0];
+reg [1:0] AVR_BANK;
 
 wire [3:0] CURRENT_ROM_SEL;
 wire [22:0] SRAM_ADDR_FULL;
 
 initial begin
-   AVR_ADDR = 21'b0;
-   CS_ARRAY[0] = 4'b1110;
-   CS_ARRAY[1] = 4'b1101;
-   CS_ARRAY[2] = 4'b1011;
-   CS_ARRAY[3] = 4'b0111;
+   CS_ARRAY[0] = 4'b0001;
+   CS_ARRAY[1] = 4'b0010;
+   CS_ARRAY[2] = 4'b0100;
+   CS_ARRAY[3] = 4'b1000;
+   AVR_BANK = 2'b0;
 end 
 
 /* currently supported mappers:
@@ -70,14 +69,16 @@ assign IS_SAVERAM = ((MAPPER == 3'b000) ? (!SNES_ADDR[22]
 /*                               LoROM:   SRAM @ Bank 0x70-0x7f, 0xf0-0xff
                                           Offset 0000-7fff */
                     :(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
+                                           & (SNES_ADDR[19:16] < 4'b1110)
                                            & !SNES_ADDR[15]
                                            & !SNES_CS)
                     : 1'b0);
 
-assign IS_ROM = ((MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
+assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
                                          & SNES_ADDR[15])
                                        |(SNES_ADDR[22]))
-                :(MAPPER == 3'b001) ? ( (SNES_ADDR[15]) )
+                : (MAPPER == 3'b001) ? ( (SNES_ADDR[15] & !SNES_ADDR[22])
+                                        |(SNES_ADDR[22]) )
                 : 1'b0);
                                          
 assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
@@ -90,29 +91,13 @@ assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
                             : 21'b0);
 
 assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
-assign SRAM_ADDR = SRAM_ADDR_FULL[20:0];
+assign SRAM_ADDR = SRAM_ADDR_FULL[20:1];
 
-assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b0111 : 4'b1110; // CS_ARRAY[SRAM_BANK];
-//assign ROM_SEL = 4'b1110;
+// XXX assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
+assign ROM_SEL = 4'b0001;
 
-always @(posedge CLK) begin
-   if(AVR_NEXTADDR_CURR) begin
-      if(!AVR_NEXTADDR_PREV) begin
-         if(!AVR_ADDR_RESET)
-            AVR_ADDR <= 21'b0;
-         else if (!AVR_ADDR_EN)
-            AVR_ADDR <= AVR_ADDR + 1;
-      end
-   end
-end
+assign SRAM_BHE = !AVR_ENA ? SRAM_ADDR_FULL[0] : 1'b0;
+assign SRAM_BLE = !AVR_ENA ? !SRAM_ADDR_FULL[0] : 1'b0;
+assign SRAM_ADDR0 = SRAM_ADDR_FULL[0];
 
-
-/*
-always @(posedge AVR_NEXTADDR) begin
-   if (!AVR_ADDR_RESET)
-      AVR_ADDR <= 21'b0;
-   else if (!AVR_ADDR_EN)
-      AVR_ADDR <= AVR_ADDR + 1;
-end
-*/
 endmodule
diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v
index 01d7ee8..f01b6bf 100644
--- a/verilog/sd2snes/data.v
+++ b/verilog/sd2snes/data.v
@@ -25,16 +25,16 @@ module data(
       input AVR_READ,
       input AVR_WRITE,
       inout [7:0] SNES_DATA,
-      inout [7:0] SRAM_DATA,
-      inout [7:0] AVR_DATA,
+      inout [15:0] SRAM_DATA,
+      input [7:0] AVR_IN_DATA,
+      output [7:0] AVR_OUT_DATA,
       input MODE,
       input SNES_DATA_TO_MEM,
       input AVR_DATA_TO_MEM,
       input SRAM_DATA_TO_SNES_MEM,
       input SRAM_DATA_TO_AVR_MEM,
       input AVR_ENA,
-      input AVR_NEXTADDR_PREV,
-      input AVR_NEXTADDR_CURR
+      input SRAM_ADDR0
     );
 
 reg [7:0] SNES_IN_MEM;
@@ -42,24 +42,31 @@ reg [7:0] SNES_OUT_MEM;
 reg [7:0] AVR_IN_MEM;
 reg [7:0] AVR_OUT_MEM;
 
+wire [7:0] FROM_SRAM_BYTE;
+wire [7:0] TO_SRAM_BYTE;
+
 assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM;                   
 
-assign AVR_DATA = !AVR_ENA ? (!AVR_READ ? SRAM_DATA : 8'bZ)
-                  : (AVR_READ ? 8'bZ : AVR_OUT_MEM);
+assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]);
+assign TO_SRAM_BYTE = !AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) // /**/ : 8'bZ;
+                      : MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)                   
+                             : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ);
+                             
+assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE)
+                  : (AVR_OUT_MEM);
 
-assign SRAM_DATA = !AVR_ENA ? (!AVR_WRITE ? AVR_DATA : 8'bZ)//  /**/ : 8'bZ;
-                   : MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)                   
-                          : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ);
+// XXX assign SRAM_DATA = (SRAM_BHE ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ});
+assign SRAM_DATA = !AVR_ENA ? ((SRAM_ADDR0 ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ})) : 16'bZ;
 
 always @(posedge CLK) begin
    if(SNES_DATA_TO_MEM)
       SNES_IN_MEM <= SNES_DATA;
    if(AVR_DATA_TO_MEM)
-      AVR_IN_MEM <= AVR_DATA;
+      AVR_IN_MEM <= AVR_IN_DATA;
    if(SRAM_DATA_TO_SNES_MEM)
-      SNES_OUT_MEM <= SRAM_DATA;
+      SNES_OUT_MEM <= FROM_SRAM_BYTE;
    if(SRAM_DATA_TO_AVR_MEM)
-      AVR_OUT_MEM <= SRAM_DATA;
+      AVR_OUT_MEM <= FROM_SRAM_BYTE;
 end
 
 
diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v
index 9b8552a..df75da1 100644
--- a/verilog/sd2snes/dcm.v
+++ b/verilog/sd2snes/dcm.v
@@ -21,7 +21,9 @@
 module my_dcm (
          input CLKIN,
          input CLKFB,
-         output CLK2X
+         output CLK2X,
+         output CLKFX,
+         output CLK0
     );
 
    // DCM: Digital Clock Manager Circuit
@@ -33,11 +35,11 @@ module my_dcm (
       .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
       .CLKFX_DIVIDE(1),   // Can be any integer from 1 to 32
-      .CLKFX_MULTIPLY(16), // Can be any integer from 2 to 32
+      .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
       .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
-      .CLKIN_PERIOD(0.0),  // Specify period of input clock
+      .CLKIN_PERIOD(46000.0),  // Specify period of input clock
       .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
-      .CLK_FEEDBACK("2X"),  // Specify clock feedback of NONE, 1X or 2X
+      .CLK_FEEDBACK("1X"),  // Specify clock feedback of NONE, 1X or 2X
       .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             //   an integer from 0 to 15
       .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 778c00b..3524e84 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -1,126 +1,8 @@
-# INST "AVR_NEXTADDR_BUFGP" LOC = BUFGMUX7;
-# INST "CLK_BUFGP" LOC = BUFGMUX0;
-NET "AVR_BANK[0]" LOC = P56;
-NET "AVR_BANK[1]" LOC = P57;
-NET "AVR_ENA" LOC = P40;
-NET "AVR_READ" LOC = P41;
-NET "MAPPER[0]" LOC = P68;
-NET "MAPPER[1]" LOC = P69;
-NET "MAPPER[2]" LOC = P70;
-NET "ROM_SEL[0]" LOC = P124;
-NET "ROM_SEL[1]" LOC = P125;
-NET "ROM_SEL[2]" LOC = P122;
-NET "ROM_SEL[3]" LOC = P123;
-NET "SNES_ADDR[0]" LOC = P1;
-NET "SNES_ADDR[10]" LOC = P13;
-NET "SNES_ADDR[11]" LOC = P14;
-NET "SNES_ADDR[12]" LOC = P15;
-NET "SNES_ADDR[13]" LOC = P17;
-NET "SNES_ADDR[14]" LOC = P18;
-NET "SNES_ADDR[15]" LOC = P20;
-NET "SNES_ADDR[16]" LOC = P21;
-NET "SNES_ADDR[17]" LOC = P23;
-NET "SNES_ADDR[18]" LOC = P24;
-NET "SNES_ADDR[19]" LOC = P25;
-NET "SNES_ADDR[1]" LOC = P2;
-NET "SNES_ADDR[20]" LOC = P26;
-NET "SNES_ADDR[21]" LOC = P27;
-NET "SNES_ADDR[22]" LOC = P28;
-NET "SNES_ADDR[23]" LOC = P30;
-NET "SNES_ADDR[2]" LOC = P4;
-NET "SNES_ADDR[3]" LOC = P5;
-NET "SNES_ADDR[4]" LOC = P6;
-NET "SNES_ADDR[5]" LOC = P7;
-NET "SNES_ADDR[6]" LOC = P8;
-NET "SNES_ADDR[7]" LOC = P10;
-NET "SNES_ADDR[8]" LOC = P11;
-NET "SNES_ADDR[9]" LOC = P12;
-NET "SRAM_ADDR[0]" LOC = P92;
-NET "SRAM_ADDR[10]" LOC = P104;
-NET "SRAM_ADDR[11]" LOC = P105;
-NET "SRAM_ADDR[12]" LOC = P107;
-NET "SRAM_ADDR[13]" LOC = P108;
-NET "SRAM_ADDR[14]" LOC = P73;
-NET "SRAM_ADDR[15]" LOC = P74;
-NET "SRAM_ADDR[16]" LOC = P76;
-NET "SRAM_ADDR[17]" LOC = P77;
-NET "SRAM_ADDR[18]" LOC = P78;
-NET "SRAM_ADDR[19]" LOC = P79;
-NET "SRAM_ADDR[1]" LOC = P93;
-NET "SRAM_ADDR[20]" LOC = P80;
-NET "SRAM_ADDR[2]" LOC = P95;
-NET "SRAM_ADDR[3]" LOC = P96;
-NET "SRAM_ADDR[4]" LOC = P97;
-NET "SRAM_ADDR[5]" LOC = P98;
-NET "SRAM_ADDR[6]" LOC = P99;
-NET "SRAM_ADDR[7]" LOC = P100;
-NET "SRAM_ADDR[8]" LOC = P102;
-NET "SRAM_ADDR[9]" LOC = P103;
-NET "SRAM_DATA[0]" LOC = P82;
-NET "SRAM_DATA[1]" LOC = P83;
-NET "SRAM_DATA[2]" LOC = P84;
-NET "SRAM_DATA[3]" LOC = P85;
-NET "SRAM_DATA[4]" LOC = P86;
-NET "SRAM_DATA[5]" LOC = P87;
-NET "SRAM_DATA[6]" LOC = P89;
-NET "SRAM_DATA[7]" LOC = P90;
-NET "SRAM_OE" LOC = P118;
-NET "SRAM_WE" LOC = P119;
-NET "AVR_ADDR_RESET" LOC = P44;
-NET "CLKIN" LOC = P55;
-NET "AVR_NEXTADDR" LOC = P128;
-NET "SNES_READ" LOC = P31;
-NET "SNES_WRITE" LOC = P32;
-NET "AVR_WRITE" LOC = P58;
-NET "SNES_CS" LOC = P52;
-NET "AVR_ADDR_EN" LOC = P53;
 NET "CLK" TNM_NET = CLK;
-NET "AVR_DATA[0]" LOC = P46;
-NET "AVR_DATA[1]" LOC = P47;
-NET "AVR_DATA[2]" LOC = P50;
-NET "AVR_DATA[3]" LOC = P51;
-NET "AVR_DATA[4]" LOC = P59;
-NET "AVR_DATA[5]" LOC = P60;
-NET "AVR_DATA[6]" LOC = P63;
-NET "AVR_DATA[7]" LOC = P65;
-NET "SNES_DATA[0]" LOC = P129;
-NET "SNES_DATA[1]" LOC = P130;
-NET "SNES_DATA[2]" LOC = P131;
-NET "SNES_DATA[3]" LOC = P132;
-NET "SNES_DATA[4]" LOC = P135;
-NET "SNES_DATA[5]" LOC = P137;
-NET "SNES_DATA[6]" LOC = P140;
-NET "SNES_DATA[7]" LOC = P141;
-NET "SNES_DATABUS_DIR" LOC = P35;
-NET "SNES_DATABUS_OE" LOC = P33;
-NET "MODE" LOC = P112;
 NET "CLKIN" TNM_NET = CLKIN;
 TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 MHz HIGH 50 %;
-NET "AVR_ADDR_EN" IOSTANDARD = LVCMOS33;
-NET "AVR_ADDR_RESET" IOSTANDARD = LVCMOS33;
-NET "AVR_BANK[0]" IOSTANDARD = LVCMOS33;
-NET "AVR_BANK[1]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[0]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[1]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[2]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[3]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[4]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[5]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[6]" IOSTANDARD = LVCMOS33;
-NET "AVR_DATA[7]" IOSTANDARD = LVCMOS33;
 NET "AVR_ENA" IOSTANDARD = LVCMOS33;
-NET "AVR_NEXTADDR" IOSTANDARD = LVCMOS33;
-NET "AVR_READ" IOSTANDARD = LVCMOS33;
-NET "AVR_WRITE" IOSTANDARD = LVCMOS33;
-NET "CLKIN" IOSTANDARD = LVCMOS33;
-NET "MAPPER[0]" IOSTANDARD = LVCMOS33;
-NET "MAPPER[1]" IOSTANDARD = LVCMOS33;
-NET "MAPPER[2]" IOSTANDARD = LVCMOS33;
 NET "MODE" IOSTANDARD = LVCMOS33;
-NET "ROM_SEL[0]" IOSTANDARD = LVCMOS33;
-NET "ROM_SEL[1]" IOSTANDARD = LVCMOS33;
-NET "ROM_SEL[2]" IOSTANDARD = LVCMOS33;
-NET "ROM_SEL[3]" IOSTANDARD = LVCMOS33;
 NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
 NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
 NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
@@ -170,7 +52,6 @@ NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33;
-NET "SRAM_ADDR[20]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33;
 NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33;
@@ -189,3 +70,120 @@ NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33;
 NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33;
 NET "SRAM_OE" IOSTANDARD = LVCMOS33;
 NET "SRAM_WE" IOSTANDARD = LVCMOS33;
+NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33;
+NET "SNES_IRQ" IOSTANDARD = LVCMOS33;
+NET "SNES_REFRESH" IOSTANDARD = LVCMOS33;
+NET "SPI_LSB" IOSTANDARD = LVCMOS33;
+NET "SPI_MISO" IOSTANDARD = LVCMOS33;
+NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
+NET "SPI_SCK" IOSTANDARD = LVCMOS33;
+NET "SPI_SS" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[13]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[14]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[15]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[8]" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[9]" IOSTANDARD = LVCMOS33;
+NET "AVR_ENA" LOC = P58;
+NET "CLKIN" LOC = P55;
+NET "IRQ_DIR" LOC = P40;
+NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
+NET "SNES_ADDR[0]" LOC = P7;
+NET "SNES_ADDR[10]" LOC = P32;
+NET "SNES_ADDR[11]" LOC = P35;
+NET "SNES_ADDR[12]" LOC = P33;
+NET "SNES_ADDR[13]" LOC = P31;
+NET "SNES_ADDR[14]" LOC = P28;
+NET "SNES_ADDR[15]" LOC = P26;
+NET "SNES_ADDR[16]" LOC = P24;
+NET "SNES_ADDR[17]" LOC = P21;
+NET "SNES_ADDR[18]" LOC = P18;
+NET "SNES_ADDR[19]" LOC = P15;
+NET "SNES_ADDR[1]" LOC = P10;
+NET "SNES_ADDR[20]" LOC = P13;
+NET "SNES_ADDR[21]" LOC = P11;
+NET "SNES_ADDR[22]" LOC = P8;
+NET "SNES_ADDR[23]" LOC = P6;
+NET "SNES_ADDR[2]" LOC = P12;
+NET "SNES_ADDR[3]" LOC = P14;
+NET "SNES_ADDR[4]" LOC = P17;
+NET "SNES_ADDR[5]" LOC = P20;
+NET "SNES_ADDR[6]" LOC = P23;
+NET "SNES_ADDR[7]" LOC = P25;
+NET "SNES_ADDR[8]" LOC = P27;
+NET "SNES_ADDR[9]" LOC = P30;
+NET "SNES_CPU_CLK" LOC = P1;
+NET "SNES_CS" LOC = P5;
+NET "SNES_READ" LOC = P2;
+NET "SNES_REFRESH" LOC = P36;
+NET "SNES_WRITE" LOC = P4;
+NET "SPI_SS" LOC = P65;
+NET "SRAM_ADDR[10]" LOC = P60;
+NET "SRAM_ADDR[11]" LOC = P59;
+NET "SRAM_ADDR[12]" LOC = P57;
+NET "SRAM_ADDR[13]" LOC = P56;
+NET "SRAM_ADDR[14]" LOC = P53;
+NET "SRAM_ADDR[15]" LOC = P52;
+NET "SRAM_ADDR[19]" LOC = P69;
+NET "SRAM_ADDR[8]" LOC = P68;
+NET "SRAM_ADDR[9]" LOC = P63;
+NET "SRAM_CE2[0]" LOC = P77;
+NET "SRAM_CE2[0]" IOSTANDARD = LVCMOS33;
+NET "SRAM_CE2[1]" LOC = P76;
+NET "SRAM_CE2[1]" IOSTANDARD = LVCMOS33;
+NET "SRAM_CE2[2]" LOC = P74;
+NET "SRAM_CE2[2]" IOSTANDARD = LVCMOS33;
+NET "SRAM_CE2[3]" LOC = P73;
+NET "SRAM_CE2[3]" IOSTANDARD = LVCMOS33;
+NET "SRAM_WE" LOC = P70;
+NET "SNES_DATABUS_DIR" LOC = P141;
+NET "SNES_DATABUS_OE" LOC = P140;
+NET "SNES_DATA[0]" LOC = P137;
+NET "SNES_DATA[1]" LOC = P132;
+NET "SNES_DATA[2]" LOC = P130;
+NET "SNES_DATA[3]" LOC = P128;
+NET "SNES_DATA[4]" LOC = P135;
+NET "SNES_DATA[5]" LOC = P131;
+NET "SNES_DATA[6]" LOC = P129;
+NET "SNES_DATA[7]" LOC = P127;
+NET "SNES_IRQ" LOC = P125;
+NET "SPI_MISO" LOC = P123;
+NET "SPI_MOSI" LOC = P122;
+NET "SPI_SCK" LOC = P124;
+NET "SRAM_ADDR[0]" LOC = P92;
+NET "SRAM_ADDR[16]" LOC = P119;
+NET "SRAM_ADDR[17]" LOC = P82;
+NET "SRAM_ADDR[18]" LOC = P80;
+NET "SRAM_ADDR[1]" LOC = P90;
+NET "SRAM_ADDR[2]" LOC = P89;
+NET "SRAM_ADDR[3]" LOC = P87;
+NET "SRAM_ADDR[4]" LOC = P86;
+NET "SRAM_ADDR[5]" LOC = P85;
+NET "SRAM_ADDR[6]" LOC = P84;
+NET "SRAM_ADDR[7]" LOC = P83;
+NET "SRAM_BHE" LOC = P78;
+NET "SRAM_BHE" IOSTANDARD = LVCMOS33;
+NET "SRAM_BLE" LOC = P79;
+NET "SRAM_BLE" IOSTANDARD = LVCMOS33;
+NET "SRAM_DATA[0]" LOC = P95;
+NET "SRAM_DATA[10]" LOC = P100;
+NET "SRAM_DATA[11]" LOC = P103;
+NET "SRAM_DATA[12]" LOC = P105;
+NET "SRAM_DATA[13]" LOC = P108;
+NET "SRAM_DATA[14]" LOC = P113;
+NET "SRAM_DATA[15]" LOC = P118;
+NET "SRAM_DATA[1]" LOC = P97;
+NET "SRAM_DATA[2]" LOC = P99;
+NET "SRAM_DATA[3]" LOC = P102;
+NET "SRAM_DATA[4]" LOC = P104;
+NET "SRAM_DATA[5]" LOC = P107;
+NET "SRAM_DATA[6]" LOC = P112;
+NET "SRAM_DATA[7]" LOC = P116;
+NET "SRAM_DATA[8]" LOC = P96;
+NET "SRAM_DATA[9]" LOC = P98;
+NET "SRAM_OE" LOC = P93;
+NET "CLKIN" IOSTANDARD = LVCMOS33;
+NET "CLKIN" SLEW = FAST;
+NET "CLKIN" PULLUP;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 1fc770b..6615848 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -19,73 +19,150 @@
 //
 //////////////////////////////////////////////////////////////////////////////////
 module main(
+   /* input clock */
     input CLKIN,
-    input [2:0] MAPPER,
+    
+   /* SNES signals */
     input [23:0] SNES_ADDR,
     input SNES_READ,
     input SNES_WRITE,
     input SNES_CS,
     inout [7:0] SNES_DATA,
-    inout [7:0] SRAM_DATA,
-    inout [7:0] AVR_DATA,
-    output [20:0] SRAM_ADDR,
-    output [3:0] ROM_SEL,
-    output SRAM_OE,
-    output SRAM_WE,
+    input SNES_CPU_CLK,
+    input SNES_REFRESH,
+    inout SNES_IRQ,
     output SNES_DATABUS_OE,
     output SNES_DATABUS_DIR,
-    input AVR_ADDR_RESET,
-    input AVR_ADDR_EN,
-    input AVR_READ,
-    input AVR_WRITE,
-    input AVR_NEXTADDR,
+    output IRQ_DIR,
+
+   /* SRAM signals */
+    inout [15:0] SRAM_DATA,
+    output [19:0] SRAM_ADDR,
+    output [3:0] SRAM_CE2,
+    output SRAM_OE,
+    output SRAM_WE,
+    output SRAM_BHE,
+    output SRAM_BLE,
+
+   /* AVR signals */
+    input SPI_MOSI,
+    output SPI_MISO,
+    input SPI_SS,
+    input SPI_SCK,
     input AVR_ENA,
-    input [1:0] AVR_BANK,
-    output MODE
+    
+   /* debug */
+    output MODE,
+    output SPI_LSB
     );
+wire [7:0] spi_cmd_data;
+wire [7:0] spi_param_data;
+wire [7:0] spi_input_data;
+wire [31:0] spi_byte_cnt;
+wire [2:0] spi_bit_cnt;
+wire [23:0] AVR_ADDR;
+wire [7:0] avr_data_in;
+wire [7:0] avr_data_out;
+wire [7:0] AVR_IN_DATA;
+wire [7:0] AVR_OUT_DATA;
+wire [3:0] MAPPER;
+
+spi snes_spi(.clk(CLK),
+             .MOSI(SPI_MOSI),
+             .MISO(SPI_MISO),
+             .SSEL(SPI_SS),
+             .SCK(SPI_SCK),
+             .LED(SPI_LSB),
+             .cmd_ready(spi_cmd_ready),
+             .param_ready(spi_param_ready),
+             .cmd_data(spi_cmd_data),
+             .param_data(spi_param_data),
+             .endmessage(spi_endmessage),
+             .input_data(spi_input_data),
+             .byte_cnt(spi_byte_cnt),
+             .bit_cnt(spi_bit_cnt)
+);
+
+avr_cmd snes_avr_cmd(
+    .clk(CLK),
+    .cmd_ready(spi_cmd_ready),
+    .param_ready(spi_param_ready),
+    .cmd_data(spi_cmd_data),
+    .param_data(spi_param_data),
+    .avr_mapper(MAPPER),
+    .avr_sram_size(SRAM_SIZE),
+    .avr_read(AVR_READ),
+    .avr_write(AVR_WRITE),
+    .avr_data_in(AVR_OUT_DATA),
+    .avr_data_out(AVR_IN_DATA),
+    .spi_byte_cnt(spi_byte_cnt),
+    .spi_bit_cnt(spi_bit_cnt),
+    .addr_out(AVR_ADDR)
+);
 
 my_dcm snes_dcm(.CLKIN(CLKIN),
                   .CLK2X(CLK),
-                  .CLKFB(CLKFB)
+                  .CLKFB(CLKFB),
+                  .CLKFX(CLK2),
+                  .CLK0(CLK0)
                 );
-                
-assign CLKFB = CLK;
-                
+
+/*my_dcm snes_dcm2(.CLKIN(CLK),
+                  .CLK2X(CLK2),
+                  .CLKFB(CLKFB2),
+                  .CLKFX(CLKFX2)
+                );*/
+assign CLKFB = CLK0;
+//assign CLKFB2 = CLK2;
+
+wire SNES_RW;
+reg SNES_READs;
+reg SNES_WRITEs;
+reg SNES_CSs;
+
+assign SNES_RW = (SNES_READs & SNES_WRITEs);
+
+always @(posedge CLK2) begin
+   SNES_READs <= SNES_READ;
+   SNES_WRITEs <= SNES_WRITE;
+   SNES_CSs <= SNES_CS;
+end
+reg ADDR_WRITE;
+
+
 address snes_addr(
     .CLK(CLK),
     .MAPPER(MAPPER),
     .SNES_ADDR(SNES_ADDR),   // requested address from SNES
-    .SNES_CS(SNES_CS),            // "CART" pin from SNES (active low)
+    .SNES_CS(SNES_CSs),            // "CART" pin from SNES (active low)
     .SRAM_ADDR(SRAM_ADDR),  // Address to request from SRAM (active low)
-    .ROM_SEL(ROM_SEL),     // which SRAM unit to access
-    .AVR_ADDR_RESET(AVR_ADDR_RESET),     // reset AVR sequence (active low)
-    .AVR_NEXTADDR(AVR_NEXTADDR),        // next byte request from AVR
+    .ROM_SEL(SRAM_CE2),     // which SRAM unit to access
     .AVR_ENA(AVR_ENA),            // enable AVR mode (active low)
-    .AVR_ADDR_EN(AVR_ADDR_EN),  // enable AVR address counter (active low)
-    .AVR_BANK(AVR_BANK),     // which bank does the AVR want
 	 .MODE(MODE),               // AVR(1) or SNES(0) ("bus phase")
     .IS_SAVERAM(IS_SAVERAM),
     .IS_ROM(IS_ROM),
-    .AVR_NEXTADDR_PREV(AVR_NEXTADDR_PREV),
-    .AVR_NEXTADDR_CURR(AVR_NEXTADDR_CURR)
+    .AVR_ADDR(AVR_ADDR),
+    .SRAM_BHE(SRAM_BHE),
+    .SRAM_BLE(SRAM_BLE),
+    .SRAM_ADDR0(SRAM_ADDR0)
     );
     
 data snes_data(.CLK(CLK),
-      .SNES_READ(SNES_READ),
-      .SNES_WRITE(SNES_WRITE),
+      .SNES_READ(SNES_READs),
+      .SNES_WRITE(SNES_WRITEs),
       .AVR_READ(AVR_READ),
       .AVR_WRITE(AVR_WRITE),
       .SNES_DATA(SNES_DATA),
       .SRAM_DATA(SRAM_DATA),
-      .AVR_DATA(AVR_DATA),
       .MODE(MODE),
       .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
       .AVR_DATA_TO_MEM(AVR_DATA_TO_MEM),
       .SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM),
       .SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM),
       .AVR_ENA(AVR_ENA),
-      .AVR_NEXTADDR_PREV(AVR_NEXTADDR_PREV),
-      .AVR_NEXTADDR_CURR(AVR_NEXTADDR_CURR)
+      .AVR_IN_DATA(AVR_IN_DATA),
+      .AVR_OUT_DATA(AVR_OUT_DATA),
+      .SRAM_ADDR0(SRAM_ADDR0)
       );
       
 parameter MODE_SNES = 1'b0;
@@ -121,19 +198,19 @@ reg SNES_READ_CYCLE;
 reg SNES_WRITE_CYCLE;
 reg AVR_READ_CYCLE;
 reg AVR_WRITE_CYCLE;
+reg AVR_SPI_WRITEONCE;
+reg AVR_SPI_READONCE;
+reg AVR_SPI_WRITE;
+reg AVR_SPI_READ;
+reg AVR_SPI_ADDR_INCREMENT;
+reg [7:0] AVR_DATA_IN;
+reg [3:0] MAPPER_BUF;
 
 reg SNES_DATABUS_OE_BUF;
 reg SNES_DATABUS_DIR_BUF;
 
-reg AVR_NEXTADDR_PREV_BUF;
-reg AVR_NEXTADDR_CURR_BUF;
-
-wire SNES_RW;
-
 assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
 
-assign SNES_RW = (SNES_READ & SNES_WRITE);
-
 initial begin
    CYCLE_RESET = 0;
    CYCLE_RESET_ACK = 0;
@@ -147,16 +224,16 @@ initial begin
    AVR_READ_CYCLE = 1'b1;
    AVR_WRITE_CYCLE = 1'b1;
 
-   MODE_ARRAY = 8'b00011111;
+   MODE_ARRAY = 8'b00001111;
    
-   SRAM_WE_ARRAY[2'b00] = 8'b10010011;
-   SRAM_WE_ARRAY[2'b01] = 8'b10011111;
-   SRAM_WE_ARRAY[2'b10] = 8'b11110011;
+   SRAM_WE_ARRAY[2'b00] = 8'b10001000;
+   SRAM_WE_ARRAY[2'b01] = 8'b10001111;
+   SRAM_WE_ARRAY[2'b10] = 8'b11111000;
    SRAM_WE_ARRAY[2'b11] = 8'b11111111;
 
    SRAM_OE_ARRAY[2'b00] = 8'b11111111;
-   SRAM_OE_ARRAY[2'b01] = 8'b11100000;
-   SRAM_OE_ARRAY[2'b10] = 8'b00011111;
+   SRAM_OE_ARRAY[2'b01] = 8'b11110000;
+   SRAM_OE_ARRAY[2'b10] = 8'b00001111;
    SRAM_OE_ARRAY[2'b11] = 8'b00000000;
    
    SNES_DATA_TO_MEM_ARRAY[1'b0] = 8'b10000000;
@@ -169,10 +246,7 @@ initial begin
    SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 8'b00100000;
    
    SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 8'b00000000;
-   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 8'b00000010;  
-   
-   AVR_NEXTADDR_PREV_BUF = 0;
-   AVR_NEXTADDR_CURR_BUF = 0;
+   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 8'b00000001;  
 end 
 
 // falling edge of SNES /RD or /WR marks the beginning of a new cycle
@@ -180,8 +254,8 @@ end
 // CPU cycle can be 6, 8 or 12 CLK cycles so we must satisfy
 // the minimum of 6 cycles to get everything done.
 
-always @(posedge CLK) begin
-   if (!SNES_RW) begin
+always @(posedge CLK2) begin
+   if (!SNES_RW /* || !AVR_ENA */) begin
       if (!CYCLE_RESET_ACK) 
          CYCLE_RESET <= 1;
       else
@@ -210,7 +284,7 @@ always @(posedge CLK) begin
               STATE_6:
                  STATE <= STATE_7;
               STATE_7: begin
-                 if (SNES_RW) // check for end of SNES cycle to avoid looping
+                 if (SNES_RW /* || !AVR_ENA */) // check for end of SNES cycle to avoid looping
                      CYCLE_RESET_ACK <= 0;  // ready for new cycle
                  STATE <= STATE_7;
               end                 
@@ -220,12 +294,13 @@ always @(posedge CLK) begin
        end
 end
 
-always @(posedge CLK) begin
+always @(posedge CLK2) begin
+
    case (STATE)
    
       STATE_7: begin
-         SNES_READ_CYCLE <= SNES_READ;
-         SNES_WRITE_CYCLE <= SNES_WRITE;
+         SNES_READ_CYCLE <= SNES_READs;
+         SNES_WRITE_CYCLE <= SNES_WRITEs;
          AVR_READ_CYCLE <= AVR_READ;
          AVR_WRITE_CYCLE <= AVR_WRITE;
          STATEIDX <= 7;
@@ -262,8 +337,8 @@ end
 
 // When in AVR mode, enable SRAM_WE according to AVR programming
 // else enable SRAM_WE according to state&cycle
-assign SRAM_WE = !AVR_ENA ? AVR_WRITE
-                          : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
+//assign SRAM_WE = !AVR_ENA ? AVR_WRITE
+//                          : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
 
 // When in AVR mode, enable SRAM_OE whenever not writing
 // else enable SRAM_OE according to state&cycle
@@ -271,24 +346,16 @@ assign SRAM_OE = !AVR_ENA ? AVR_READ
                           : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
 
 // dumb version
-//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READ;
-//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
+//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
+assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
 
 always @(posedge CLK) begin
-   SNES_DATABUS_OE_BUF <= SNES_CS | (SNES_READ & SNES_WRITE);
+   SNES_DATABUS_OE_BUF <= SNES_CSs | (SNES_READs & SNES_WRITEs);
 end
 
-always @(posedge CLK) begin
-   AVR_NEXTADDR_PREV_BUF <= AVR_NEXTADDR_CURR_BUF;
-   AVR_NEXTADDR_CURR_BUF <= AVR_NEXTADDR;
-end
-
-assign AVR_NEXTADDR_PREV = AVR_NEXTADDR_PREV_BUF;
-assign AVR_NEXTADDR_CURR = AVR_NEXTADDR_CURR_BUF;
-
 //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
-assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE);
-assign SNES_DATABUS_DIR = !SNES_WRITE ? 1'b0 : 1'b1;
+assign SNES_DATABUS_OE = (IS_ROM & SNES_CSs) | (!IS_ROM & !IS_SAVERAM) | (SNES_READs & SNES_WRITEs);
+assign SNES_DATABUS_DIR = !SNES_WRITEs ? 1'b0 : 1'b1;
 
 assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
 assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
@@ -296,4 +363,7 @@ assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
 assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
 assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
 
+assign IRQ_DIR = 1'b0;
+assign SNES_IRQ = 1'bZ;
+
 endmodule
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index 368506e..6816022 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -30,19 +30,41 @@
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
-    <file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="tf_spi.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="PostRouteSimulation"/>
       <association xil_pn:name="PostMapSimulation"/>
       <association xil_pn:name="PostTranslateSimulation"/>
     </file>
-    <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="main_tf2.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+    <file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
+    <file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+      <library xil_pn:name="verilog"/>
+    </file>
   </files>
 
   <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
     <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s200"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
@@ -50,17 +72,17 @@
     <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|main"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main"/>
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="Package" xil_pn:value="tq144"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
     <property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|main"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|main_tf2"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
@@ -69,7 +91,9 @@
     <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
   </properties>
 
-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
+  </bindings>
 
   <libraries/>
 
diff --git a/verilog/sd2snes/tf_main.v b/verilog/sd2snes/tf_main.v
index ad7076a..14cc2fa 100644
--- a/verilog/sd2snes/tf_main.v
+++ b/verilog/sd2snes/tf_main.v
@@ -31,13 +31,7 @@ module tf_main;
 	reg SNES_READ;
 	reg SNES_WRITE;
 	reg SNES_CS;
-	reg AVR_ADDR_RESET;
-	reg AVR_WRITE;
-	reg AVR_READ;
-	reg AVR_NEXTADDR;
 	reg AVR_ENA;
-	reg [1:0] AVR_BANK;
-   reg AVR_ADDR_EN;
 
 	// Outputs
 	wire [20:0] SRAM_ADDR;
@@ -56,6 +50,79 @@ module tf_main;
    reg [7:0] SRAM_DATA_BUF;
    reg [7:0] SNES_DATA_BUF;
    
+   		SCK = 0;
+		MOSI = 0;
+		SSEL = 1;
+		input_data = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+        
+		// Add stimulus here
+      SSEL = 0;
+      MOSI=1;
+      #100 SCK=1;
+      #100 SCK=0;
+      MOSI=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      MOSI=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      MOSI=1;
+      #100 SCK=1;
+      #100 SCK=0;
+      MOSI=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #200;
+         #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #200;
+         #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SCK=1;
+      #100 SCK=0;
+      #100 SSEL=1;
+      
+      
+	end
+   always begin
+      #19 clk = ~clk;
+   end
+   
 // Instantiate the Unit Under Test (UUT)
 	main uut (
 		.CLKIN(CLK), 
@@ -66,18 +133,11 @@ module tf_main;
 		.SNES_CS(SNES_CS), 
 		.SNES_DATA(SNES_DATA), 
 		.SRAM_DATA(SRAM_DATA), 
-		.AVR_DATA(AVR_DATA), 
 		.SRAM_ADDR(SRAM_ADDR), 
 		.ROM_SEL(ROM_SEL), 
 		.SRAM_OE(SRAM_OE), 
 		.SRAM_WE(SRAM_WE), 
-		.AVR_ADDR_RESET(AVR_ADDR_RESET), 
-		.AVR_WRITE(AVR_WRITE), 
-		.AVR_NEXTADDR(AVR_NEXTADDR), 
 		.AVR_ENA(AVR_ENA), 
-		.AVR_BANK(AVR_BANK),
-      .AVR_READ(AVR_READ),
-      .AVR_ADDR_EN(AVR_ADDR_EN),
       .SNES_DATABUS_OE(SNES_DATABUS_OE),
       .SNES_DATABUS_DIR(SNES_DATABUS_DIR),
       .MODE(MODE)
@@ -92,24 +152,10 @@ module tf_main;
 		SNES_READ = 1;
 		SNES_WRITE = 1;
 		SNES_CS = 0;
-		AVR_ADDR_RESET = 1;
-		AVR_WRITE = 1;
-      AVR_READ = 0;
-		AVR_NEXTADDR = 0;
 		AVR_ENA = 1;
-		AVR_BANK = 0;
-      AVR_ADDR_EN = 0;
       SRAM_DATA_BUF = 8'hff;
 		// Wait for global reset to finish
 		#276;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
-      #276 AVR_NEXTADDR <= ~AVR_NEXTADDR;      
       SNES_ADDR <= 24'h123456;
       SNES_READ <= 0;
       #176;
@@ -119,7 +165,6 @@ module tf_main;
       #176;
       SNES_WRITE <= 1;
       #100;
-      AVR_WRITE <= 0;
       SNES_READ <= 0;
       #276;
 //      AVR_READ <= 1;
@@ -129,7 +174,6 @@ module tf_main;
    always
       #23 CLK <= ~CLK;
 //   always begin
-//      #234 AVR_NEXTADDR <= ~AVR_NEXTADDR;
 //   end
       
 endmodule