SuperCIC: documentation+cleanup

cic/supercic/supercic-lock.asm

@@ -31,30 +31,76 @@ processor p16f630
 ;      CIC clk (56) [7] |2  A5 A0 13| CIC lock reset in [8]
 ;                       |3  A4 A1 12| 50/60Hz out
 ;                       |4  A3 A2 11| host reset out [10]
-;         LED out (red) |5  C5 C0 10| CIC data i/o 0 (55) [1]
+;         LED out (grn) |5  C5 C0 10| CIC data i/o 0 (55) [1]
-;         LED out (grn) |6  C4 C1  9| CIC data i/o 1 (24) [2]
+;         LED out (red) |6  C4 C1  9| CIC data i/o 1 (24) [2]
 ;                       |7  C3 C2  8| CIC slave reset out (25) [11]
 ;                       `-----------'
 ;
-;   PORTA:  in  in  in out out  in
-;   PORTC: out out  in out out  in
-;
-;   pin 11 connected to PPU2 reset in
-;   pin 13 connected to reset button
 ;   pin 8 connected to key CIC pin 7 (or clone CIC pin 5)
 ;   pin 9 connected to key CIC pin 1 (or clone CIC pin 6)
 ;   pin 10 connected to key CIC pin 2 (or clone CIC pin 7)
+;   pin 11 connected to key CIC pin 9 (SNES /reset line)
+;   pin 12 connected to PPU1 pin 24 and PPU2 pin 30 (both isolated from mainboard)
+;   pin 13 connected to reset button
 ;
 ;   Host reset out behaves as follows:
-;   After powerup it is held low for a couple of us to properly allow the
+;   After powerup it is held low for a couple of ms to allow the components
-;   components to power-up.
+;   to power-up properly.
 ;   It is then asserted a high level even if the CIC "auth" should fail at
 ;   any point, thus enabling homebrew or other cartridges without a CIC or
 ;   CIC clone to be run properly while maintaining compatibility with CIC
 ;   demanding cartridges like S-DD1 or SA-1 powered ones.
 ;   The type of key CIC (411/413) is detected automatically.
 ;
-;   memory usage:
+;   This implementation supports automatic 50/60Hz switching based on the
+;   detected key CIC in the game cartridge. Also the 50/60Hz setting can be
+;   overridden by the user via the reset button.
+;
+;   Reset / Mode switch behaves as follows:
+;   Reset is pressed for < 586ms -> reset console upon release
+;   Reset is pressed for >= 586ms -> enter mode switch cycle, no reset
+;   Modes are cycled every 586ms as shown in Fig.1 as long as the reset button
+;   is held down.
+;   The currently selected mode is indicated by the color of the power LED
+;   (see Table 2).
+;   The mode is finally selected by releasing the reset button while the
+;   desired LED color is shown. The selected mode will then become effective
+;   and will be saved to EEPROM. Mode switching does not reset the console.
+;
+;   Note that in case a valid CIC is detected in the game cartridge, video mode
+;   will be forced to its corresponding region for the first ~9 seconds after
+;   reset or powerup. This is an attempt to trick the region detection on most
+;   games. See Table 1.
+;   In case no CIC is present in the game cartridge the user setting is applied
+;   immediately.
+;
+;   Table 1. 50/60Hz output behavior according to user setting and key CIC type.
+;   SuperCIC	key CIC		"region"
+;   ------------------------------------------------------
+;   60Hz	D/F413		50Hz for ~9 sec, then 60Hz
+;   60Hz	D/F411		60Hz permanent
+;   60Hz	none		60Hz permanent
+;
+;   50Hz	D/F413		50Hz permanent
+;   50Hz	D/F411		60Hz for ~9 sec, then 50Hz
+;   50Hz	none		50Hz permanent
+;
+;   Auto	D/F413		50Hz permanent
+;   Auto	D/F411		60Hz permanent
+;   Auto	none		60Hz permanent
+;
+;   Fig.1. SuperCIC mode cycle.
+;   ,->60Hz--->50Hz--->Auto->.
+;   `-------<--------<-------'
+;
+;   Table 2. LED color according to user setting.
+;   mode	LED color
+;   ---------------------
+;   60Hz	red
+;   50Hz	green
+;   Auto	orange
+;
+;   Table 3. memory usage.
 ;   -------------------basic CIC functions--------------------
 ;   0x20		buffer for seed calc and transfer
 ;   0x21 - 0x2f		seed area (lock seed)
@@ -67,7 +113,6 @@ processor p16f630
 ;   0x4d		buffer for eeprom access
 ;   0x4e		loop variable for longwait
 ;   0x4f		loop variable for wait
-;
 ;   -------------------SuperCIC extensions--------------------
 ;   0x50		power LED state (no bits except 4 and 5 must be set!!)
 ;   0x51		last reset button state
@@ -93,7 +138,6 @@ processor p16f630
 	nop
 	goto	init
 trap
-	org	0x0004
 	movlw	0x3
 	xorwf	PORTC, f
 	goto	trap
@@ -137,6 +181,8 @@ rst_loop
 	bsf	T1CON, 0	; start the timer	
 	goto	main		; go go go
 init
+;	PORTA:  in  in  in out out  in
+;	PORTC: out out  in out out  in
 	banksel PORTA
 	clrf	PORTA
 	movlw	0x07		; GPIO2..0 are digital I/O (not connected to comparator)
@@ -239,58 +285,49 @@ main
 	call	wait
 
 ; --------lock sends stream ID. 15 cycles per bit--------
-;	bsf	GPIO, 0		; (debug marker)
-;	bcf	GPIO, 0		; 
 	btfsc	0x31, 3		; read stream select bit
 	bsf	PORTC, 0	; send bit
 	nop
 	nop
 	bcf	PORTC, 0
-	movlw	0x1		; wait=7
+	movlw	0x1		; wait=3*0+7
-	call	wait		; burn 10 cycles
+	call	wait		; burn 10 cycles in total
 	nop
 	nop
 
-;	bsf	GPIO, 0
-;	bcf	GPIO, 0
 	btfsc	0x31, 0		; read stream select bit
 	bsf	PORTC, 0	; send bit
 	nop
 	nop
 	bcf	PORTC, 0
-	movlw	0x1		; wait=3*W+5
+	movlw	0x1		; wait=3*0+7
-	call	wait		; burn 11 cycles
+	call	wait		; burn 10 cycles in total
 	nop
 	nop
 
-;	bsf	GPIO, 0
-;	bcf	GPIO, 0
 	btfsc	0x31, 1		; read stream select bit
 	bsf	PORTC, 0	; send bit
 	nop
 	nop
 	bcf	PORTC, 0
-	movlw	0x1		; wait=3*W+5
+	movlw	0x1		; wait=3*0+7
-	call	wait		; burn 11 cycles
+	call	wait		; burn 10 cycles in total
 	nop
 	nop
 
-;	bsf	GPIO, 0
-;	bcf	GPIO, 0
 	btfsc	0x31, 2		; read stream select bit
 	bsf	PORTC, 0	; send bit
 	nop
 	nop
 	bcf	PORTC, 0
 	movlw	0x1		; wait=3*0+7
-	call	wait		; burn 10 cycles
+	call	wait		; burn 10 cycles in total
 	banksel	TRISC
 	bsf	TRISC, 0
 	bcf	TRISC, 1
 	banksel	PORTC
 	movlw	0x23		;
 	call	wait		; wait 109
-;	nop
 	movlw	0x1		; 'first time' bit
 	movwf	0x43		; for key detection
 ; --------main loop--------
@@ -329,10 +366,8 @@ loop1
 	bsf	0x43, 1		; else mark key invalid
 	btfsc	0x43, 1 	; if key invalid:
 	bcf	0x57, 1 	; set det.region=60Hz
-;	btfsc	0x43, 1 ; if key invalid:
-;	bcf	0x54, 1 ; set init.region=60Hz
 	btfsc	0x43, 1 	; if key invalid:
-	bsf	0x53, 4 ; simulate region timeout
+	bsf	0x53, 4 	; simulate region timeout->immediate region chg
 	nop
 	nop
 	nop
@@ -761,11 +796,11 @@ die
 ; --------requires 19 cycles (incl. call+return)
 checkkey
 	btfss	0x43, 0		; first time?
-	goto 	checkkey_nocheck	; if not, just burn some cycles
+	goto 	checkkey_nocheck; if not, just burn some cycles
 	movlw	0x22		; are we at the correct stream offset?
 	xorwf	FSR, w
 	btfss	STATUS, Z	; if not equal:
-	goto	checkkey_nocheck2	; burn some cycles less.
+	goto	checkkey_nocheck2; burn some cycles less.
 				; if equal do the check
 	btfss	0x42, 0		; if value from slave is set it's a 411
 	goto	checkkey_413
@@ -819,7 +854,7 @@ checkrst_1_0	; 26
 	movf	0x56, w		; get temp mode
 	movwf	0x55		; set final mode
 	movwf	0x58		; set forced mode
-	banksel	EEADR	; save to EEPROM. this somehow takes 2 extra cycles!!!
+	banksel	EEADR		; save to EEPROM. note: banksels take two cycles each!
 	movwf	EEDAT
 	bsf	EECON1,WREN
 	movlw	0x55
@@ -827,9 +862,9 @@ checkrst_1_0	; 26
 	movlw	0xaa
 	movwf	EECON2
 	bsf	EECON1, WR
-	banksel	PORTA
+	banksel	PORTA		; two cycles again
 	movlw	0x2
-	andwf	0x58, f
+	andwf	0x58, f		; cleanup forced mode
 	bcf	T1CON, 0	; stop the timer
 	clrf	PIR1		; reset overflow bit
 	clrf	TMR1L		; reset counter
@@ -878,14 +913,14 @@ checkrst_0_0	; 24
 	nop
 	; count some overflows, change region from detected to forced unless auto
 	btfsc	0x53, 4		; past delay?
-	goto	checkrst_0_0_setregion_plus5 ; 3
+	goto	checkrst_0_0_setregion_plus5
 	btfss	PIR1, 0
-	goto	checkrst_end_plus13 ; 5
+	goto	checkrst_end_plus13
 	clrf	PIR1
 	incf	0x53, f		; increment overflow counter
 	btfss	0x53, 4		; 0x10 reached?
-	goto	checkrst_end_plus9 ; 9
+	goto	checkrst_end_plus9
-checkrst_0_0_setregion ; 10
+checkrst_0_0_setregion
 	movlw	0x3
 	xorwf	0x55, w 	; mode=auto?
 	btfss	STATUS, Z
@@ -933,7 +968,7 @@ checkrst_end_plus9
 	nop
 	goto	checkrst_end
 
-checkrst_0_0_setregion_plus5	; 5
+checkrst_0_0_setregion_plus5
 	nop
 	nop
 	nop