diff --git a/src/Makefile b/src/Makefile
index 5e6c100..5d80539 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -73,7 +73,8 @@ else ifeq ($(MCU),atmega644)
BINARY_LENGTH = 0xf000
EFUSE = 0xfd
HFUSE = 0x91
- LFUSE = 0xef
+# LFUSE = 0xef
+ LFUSE = 0xaf
else ifeq ($(MCU),atmega644p)
BINARY_LENGTH = 0xf000
EFUSE = 0xfd
diff --git a/src/config.h b/src/config.h
index a5e6255..df06479 100644
--- a/src/config.h
+++ b/src/config.h
@@ -62,8 +62,10 @@
# error Unknown chip!
# endif
# define SD_CHANGE_VECT INT0_vect
-# define SDCARD_WP (PINB & _BV(PB1))
+# define SDCARD_WP (0)
# define SDCARD_WP_SETUP() do { DDRB &= ~ _BV(PB1); PORTB |= _BV(PB1); } while(0)
+// # define SDCARD_WP (PINB & _BV(PB1))
+// # define SDCARD_WP_SETUP() do { DDRB &= ~ _BV(PB1); PORTB |= _BV(PB1); } while(0)
# define SD_CHANGE_ICR MCUCR
# define SD_SUPPLY_VOLTAGE (1L<<21)
# define DEVICE_SELECT (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3)))
diff --git a/src/fpga.c b/src/fpga.c
index db2768f..08100c9 100644
--- a/src/fpga.c
+++ b/src/fpga.c
@@ -96,7 +96,7 @@ void fpga_pgm(uint8_t* filename) {
}
}
file_close();
- _delay_ms(10);
+ _delay_ms(100);
} while (!fpga_get_done() && retries--);
if(!fpga_get_done()) {
dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
diff --git a/src/main.c b/src/main.c
index 993c04d..d774293 100644
--- a/src/main.c
+++ b/src/main.c
@@ -282,7 +282,8 @@ restart:
led_std();
set_avr_ena(0);
snes_reset(1);
- if(romprops.ramsize_bytes) {
+ _delay_ms(100);
+ if(romprops.ramsize_bytes && fpga_test() == 0xa5) {
set_busy_led(1);
save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
set_busy_led(0);
diff --git a/src/spi.c b/src/spi.c
index 8cc6119..a492fbc 100644
--- a/src/spi.c
+++ b/src/spi.c
@@ -56,7 +56,7 @@
// access routines
void spiInit(void)
{
- uint8_t dummy;
+ volatile uint8_t dummy;
// setup SPI I/O pins
SPI_PORT = (SPI_PORT & ~SPI_MASK) | SPI_SCK | SPI_SS | SPI_MISO;
@@ -78,7 +78,7 @@ void spiInit(void)
}
-uint8_t spiTransferByte(uint8_t data)
+inline uint8_t spiTransferByte(uint8_t data)
{
// send the given data
SPDR = data;
@@ -94,7 +94,7 @@ uint8_t spiTransferByte(uint8_t data)
}
-uint32_t spiTransferLong(const uint32_t data)
+inline uint32_t spiTransferLong(const uint32_t data)
{
// It seems to be necessary to use the union in order to get efficient
// assembler code.
diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v
index 150cae8..7fbd89e 100644
--- a/verilog/sd2snes/dcm.v
+++ b/verilog/sd2snes/dcm.v
@@ -21,6 +21,7 @@
module my_dcm (
input CLKIN,
output CLKFX,
+ output CLK2X,
output LOCKED,
input CLKFB,
input RST,
@@ -37,18 +38,18 @@ module my_dcm (
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
- .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
+ .CLKFX_MULTIPLY(7), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(47.000), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
- .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
- .FACTORY_JF(16'hC080), // FACTORY JF values
-// .LOC("DCM_X0Y0"),
+ .FACTORY_JF(16'hFFFF), // FACTORY JF values
+// .LOC("X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 90e082a..f87e27a 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -1,5 +1,5 @@
NET "CLKIN" TNM_NET = CLKIN;
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.477 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 12.288 MHz HIGH 50 %;
NET "AVR_ENA" IOSTANDARD = LVCMOS33;
NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 4a9851c..699132f 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -109,7 +109,9 @@ avr_cmd snes_avr_cmd(
.rom_mask_out(ROM_MASK)
);
-wire [7:0] DCM_STATUS;
+//wire [7:0] DCM_STATUS;
+
+// dcm1: dfs 4x
my_dcm snes_dcm(.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
@@ -118,16 +120,20 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
.CLKFB(CLKFB),
.CLK0(CLK0)
);
-reg DCM_RSTr;
-assign DCM_RST = DCM_RSTr;
+
+dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
+ .Q(DCM_RST)
+ );
+
assign CLKFB = CLK0;
-wire DCM_FX_STOPPED = DCM_STATUS[2];
-always @(posedge CLKIN) begin
- if(DCM_FX_STOPPED)
- DCM_RSTr <= 1'b1;
- else
- DCM_RSTr <= 1'b0;
-end
+
+//wire DCM_FX_STOPPED = DCM_STATUS[2];
+//always @(posedge CLKIN) begin
+// if(DCM_FX_STOPPED)
+// DCM_RSTr <= 1'b1;
+// else
+// DCM_RSTr <= 1'b0;
+//end
/*reg DO_DCM_RESET, DCM_RESETTING;
reg DCM_RSTr;
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index f26bbe1..ec3d7c8 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -65,6 +65,10 @@
+
+
+
+
@@ -73,7 +77,9 @@
+
+
@@ -94,6 +100,7 @@
+