From 86576d2e48f97155ee7ed13970ee67a3db18aa0c Mon Sep 17 00:00:00 2001 From: Maximilian Rehkopf Date: Sun, 9 Oct 2011 13:59:38 +0200 Subject: [PATCH] FPGA: clean up (port size mismatches, unused regs/wires, ...) --- verilog/sd2snes/address.v | 22 ++--- verilog/sd2snes/bsx.v | 30 +++---- verilog/sd2snes/dac.v | 16 +--- verilog/sd2snes/main.ucf | 1 - verilog/sd2snes/main.v | 118 ++++----------------------- verilog/sd2snes/mcu_cmd.v | 70 ++++------------ verilog/sd2snes/msu.v | 10 +-- verilog/sd2snes/rtc.v | 36 ++++---- verilog/sd2snes/sd2snes.xise | 4 +- verilog/sd2snes/sd_dma.v | 19 ++--- verilog/sd2snes/spi.v | 57 +------------ verilog/sd2snes/srtc.v | 57 ++++++------- verilog/sd2snes/upd77c25.v | 65 ++++++--------- verilog/sd2sneslite/address.v | 5 -- verilog/sd2sneslite/main.v | 12 +-- verilog/sd2sneslite/sd2sneslite.xise | 2 +- verilog/sd2sneslite/spi.v | 63 +------------- 17 files changed, 151 insertions(+), 436 deletions(-) diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v index 7ddb76e..8b50fa1 100644 --- a/verilog/sd2snes/address.v +++ b/verilog/sd2snes/address.v @@ -19,20 +19,16 @@ ////////////////////////////////////////////////////////////////////////////////// module address( input CLK, - input [7:0] featurebits, // peripheral enable/disable + input [3:0] featurebits, // peripheral enable/disable input [2:0] MAPPER, // MCU detected mapper input [23:0] SNES_ADDR, // requested address from SNES - input SNES_CS, // "CART" pin from SNES (active low) output [23:0] ROM_ADDR, // Address to request from SRAM0 output ROM_SEL, // enable SRAM0 (active low) output IS_SAVERAM, // address/CS mapped as SRAM? output IS_ROM, // address mapped as ROM? output IS_WRITABLE, // address somehow mapped as writable area? - input [23:0] MCU_ADDR, // allow address to be set externally - input ADDR_WRITE, input [23:0] SAVERAM_MASK, input [23:0] ROM_MASK, - input use_msu, output msu_enable, output srtc_enable, output use_bsx, @@ -49,8 +45,6 @@ parameter [2:0] FEAT_MSU1 = 3 ; -wire [1:0] SRAM_BANK; - wire [23:0] SRAM_SNES_ADDR; /* currently supported mappers: @@ -187,12 +181,12 @@ assign SRAM_SNES_ADDR = ((MAPPER == 3'b000) assign ROM_ADDR = SRAM_SNES_ADDR; -assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK]; +assign ROM_SEL = 1'b0; assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000)); -reg [7:0] msu_enable_r; -initial msu_enable_r = 8'b00000000; -always @(posedge CLK) msu_enable_r <= {msu_enable_r[6:0], msu_enable_w}; +reg [5:0] msu_enable_r; +initial msu_enable_r = 6'b000000; +always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w}; assign msu_enable = &msu_enable_r[5:2]; assign use_bsx = (MAPPER == 3'b011); @@ -235,9 +229,9 @@ assign dspx_a0 = featurebits[FEAT_DSPX] //assign dspx_dp_enable = &dspx_dp_enable_r[5:2]; assign dspx_dp_enable = dspx_dp_enable_w; -reg [7:0] dspx_enable_r; -initial dspx_enable_r = 8'b00000000; -always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[6:0], dspx_enable_w}; +reg [5:0] dspx_enable_r; +initial dspx_enable_r = 6'b000000; +always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[4:0], dspx_enable_w}; assign dspx_enable = &dspx_enable_r[5:2]; diff --git a/verilog/sd2snes/bsx.v b/verilog/sd2snes/bsx.v index e411a1b..a776e0e 100644 --- a/verilog/sd2snes/bsx.v +++ b/verilog/sd2snes/bsx.v @@ -29,11 +29,10 @@ module bsx( input [7:0] reg_set_bits, output [14:0] regs_out, input pgm_we, - input [14:0] regs_in, input use_bsx, output data_ovr, output flash_writable, - input [59:0] rtc_data + input [55:0] rtc_data ); wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff @@ -42,8 +41,8 @@ wire [15:0] flash_addr = snes_addr[15:0]; reg flash_ovr_r; reg flash_we_r; -reg [16:0] flash_cmd0; -reg [24:0] flash_cmd5555; +reg [7:0] flash_cmd0; +reg [15:0] flash_cmd5555; wire cart_enable = (use_bsx) && ((snes_addr[23:12] & 12'hf0f) == 12'h005); @@ -70,10 +69,9 @@ assign flash_writable = (use_bsx) assign data_ovr = cart_enable | base_enable | flash_ovr; -reg [5:0] reg_oe_sreg; -always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; +reg [3:0] reg_oe_sreg; +always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe}; wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); -wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001); reg [1:0] reg_we_sreg; always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we}; @@ -83,7 +81,7 @@ reg [1:0] pgm_we_sreg; always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we}; wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01); -reg [15:0] regs_tmpr; +reg [14:0] regs_tmpr; reg [14:0] regs_outr; reg [7:0] reg_data_outr; @@ -98,12 +96,14 @@ wire [7:0] rtc_sec = rtc_data[3:0] + (rtc_data[7:4] << 3) + (rtc_data[7:4] << 1) wire [7:0] rtc_min = rtc_data[11:8] + (rtc_data[15:12] << 3) + (rtc_data[15:12] << 1); wire [7:0] rtc_hour = rtc_data[19:16] + (rtc_data[23:20] << 3) + (rtc_data[23:20] << 1); wire [7:0] rtc_day = rtc_data[27:24] + (rtc_data[31:28] << 3) + (rtc_data[31:28] << 1); +/* The following signals are currently unused. + They are kept in case more Satellaview date registers are discovered. */ wire [7:0] rtc_month = rtc_data[35:32] + (rtc_data[39:36] << 3) + (rtc_data[39:36] << 1); wire [7:0] rtc_year1 = rtc_data[43:40] + (rtc_data[47:44] << 3) + (rtc_data[47:44] << 1); wire [7:0] rtc_year100 = rtc_data[51:48] + (rtc_data[55:52] << 3) + (rtc_data[55:52] << 1); initial begin - regs_tmpr <= 16'b0_000000100000000; + regs_tmpr <= 15'b000000100000000; regs_outr <= 15'b000000100000000; bsx_counter <= 0; base_regs[8] <= 0; @@ -193,7 +193,7 @@ always @(posedge clkin) begin regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0]; end else if(reg_we_rising && cart_enable) begin if(reg_addr == 4'he && reg_data_in[7]) - regs_outr <= regs_tmpr | 16'b0100000000000000; + regs_outr <= regs_tmpr | 15'b100000000000000; else regs_tmpr[reg_addr] <= reg_data_in[7]; end else if(reg_we_rising && base_enable) begin @@ -215,13 +215,13 @@ always @(posedge clkin) begin end else if(reg_we_rising && flash_enable) begin case(flash_addr) 16'h0000: begin - flash_cmd0 <= {flash_cmd0[7:0], reg_data_in}; - if(flash_cmd0[7:0] == 8'h38 && reg_data_in == 8'hd0) + flash_cmd0 <= reg_data_in; + if(flash_cmd0 == 8'h38 && reg_data_in == 8'hd0) flash_ovr_r <= 1; end 16'h5555: begin - flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in}; - if(flash_cmd5555[15:0] == 16'haa55) begin + flash_cmd5555 <= {flash_cmd5555[7:0], reg_data_in}; + if(flash_cmd5555 == 16'haa55) begin case (reg_data_in) 8'hf0: begin flash_ovr_r <= 0; @@ -238,7 +238,7 @@ always @(posedge clkin) begin end end 16'h2aaa: begin - flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in}; + flash_cmd5555 <= {flash_cmd5555[7:0], reg_data_in}; end endcase end diff --git a/verilog/sd2snes/dac.v b/verilog/sd2snes/dac.v index 9dca091..6eca076 100644 --- a/verilog/sd2snes/dac.v +++ b/verilog/sd2snes/dac.v @@ -36,7 +36,6 @@ module dac( reg[8:0] dac_address_r; wire[8:0] dac_address = dac_address_r; -reg dac_nextaddr_r; wire[31:0] dac_data; assign DAC_STATUS = dac_address_r[8]; @@ -48,7 +47,6 @@ reg[2:0] sysclk_sreg; wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01); reg [25:0] interpol_count; -reg interpol_overflow; always @(posedge clkin) begin sysclk_sreg <= {sysclk_sreg[1:0], sysclk}; @@ -63,13 +61,10 @@ dac_buf snes_dac_buf ( .addrb(dac_address), // Bus [8 : 0] .doutb(dac_data)); // Bus [31 : 0] -reg [15:0] cnt; +reg [8:0] cnt; reg [15:0] smpcnt; -reg [15:0] samples; -wire [15:0] sample = {smpcnt[10] ? ~smpcnt[9:0] : smpcnt[9:0], 6'b0}; -wire [15:0] sample2 = {smpcnt[9] ? ~smpcnt[8:0] : smpcnt[8:0], 7'b0}; +reg [1:0] samples; reg [15:0] smpshift; -reg [15:0] smpdata; assign mclk = cnt[2]; // mclk = clk/8 assign lrck = cnt[8]; // lrck = mclk/128 @@ -92,7 +87,7 @@ wire reset_rising = (reset_sreg[1:0] == 2'b01); reg play_r; initial begin - cnt = 16'hff00; + cnt = 9'h100; smpcnt = 16'b0; lrck_sreg = 2'b11; sclk_sreg = 1'b0; @@ -101,22 +96,19 @@ initial begin vol_latch_reg = 1'b0; vol_reg = 8'h0; vol_target_reg = 8'hff; - samples <= 16'h0; + samples <= 2'b00; end always @(posedge clkin) begin if(reset_rising) begin dac_address_r <= 0; - interpol_overflow <= 0; interpol_count <= 0; end else if(sysclk_rising) begin if(interpol_count > 59378938) begin interpol_count <= interpol_count + 122500 - 59501439; dac_address_r <= dac_address_r + play_r; - interpol_overflow <= 1; end else begin interpol_count <= interpol_count + 122500; - interpol_overflow <= 0; end end end diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index 8ec5c4d..7ed7b66 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -5,7 +5,6 @@ TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24 MHz HIGH 50 %; NET "p113_out" IOSTANDARD = LVCMOS33; NET "p113_out" LOC = P113; - NET "SPI_SCK" LOC = P71; NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE; NET "SPI_SCK" TNM_NET = "SPI_SCK"; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 8ed8514..4199373 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -30,10 +30,9 @@ module main( inout [7:0] SNES_DATA, input SNES_CPU_CLK, input SNES_REFRESH, - inout SNES_IRQ, + output SNES_IRQ, output SNES_DATABUS_OE, output SNES_DATABUS_DIR, - output IRQ_DIR, input SNES_SYSCLK, /* SRAM signals */ @@ -81,9 +80,7 @@ wire [7:0] spi_input_data; wire [31:0] spi_byte_cnt; wire [2:0] spi_bit_cnt; wire [23:0] MCU_ADDR; -wire [7:0] mcu_data_in; -wire [7:0] mcu_data_out; -wire [3:0] MAPPER; +wire [2:0] MAPPER; wire [23:0] SAVERAM_MASK; wire [23:0] ROM_MASK; wire [7:0] SD_DMA_SRAM_DATA; @@ -105,16 +102,15 @@ wire [5:0] msu_status_reset_bits; wire [5:0] msu_status_set_bits; wire [14:0] bsx_regs; -wire [14:0] bsx_regs_in; wire [7:0] BSX_SNES_DATA_IN; wire [7:0] BSX_SNES_DATA_OUT; wire [7:0] bsx_regs_reset_bits; wire [7:0] bsx_regs_set_bits; wire [59:0] rtc_data; -wire [59:0] rtc_data_in; +wire [55:0] rtc_data_in; wire [59:0] srtc_rtc_data_out; -wire [7:0] SRTC_SNES_DATA_IN; +wire [3:0] SRTC_SNES_DATA_IN; wire [7:0] SRTC_SNES_DATA_OUT; wire [7:0] DSPX_SNES_DATA_IN; @@ -128,13 +124,10 @@ wire [15:0] dspx_dat_data; wire [10:0] dspx_dat_addr; wire dspx_dat_we; -wire [7:0] featurebits; +wire [3:0] featurebits; wire [23:0] MAPPED_SNES_ADDR; wire ROM_ADDR0; -wire [22:0] MAPPED_SNES_ADDR2 = MAPPED_SNES_ADDR[23:1]; - -//wire SD_DMA_EN; //SPI_DMA_CTRL; sd_dma snes_sd_dma( .CLK(CLK2), @@ -145,7 +138,6 @@ sd_dma snes_sd_dma( .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), - .SD_DMA_TGT(SD_DMA_TGT), .SD_DMA_PARTIAL(SD_DMA_PARTIAL), .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) @@ -171,7 +163,6 @@ dac snes_dac( srtc snes_srtc ( .clkin(CLK2), - /*XXX*/.reg_addr(srtc_reg_addr), .addr_in(SNES_ADDR[0]), .data_in(SRTC_SNES_DATA_IN), .data_out(SRTC_SNES_DATA_OUT), @@ -199,7 +190,7 @@ msu snes_msu ( .pgm_address(msu_write_addr), .pgm_data(SD_DMA_SRAM_DATA), .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1), - .reg_addr(SNES_ADDR), + .reg_addr(SNES_ADDR[2:0]), .reg_data_in(MSU_SNES_DATA_IN), .reg_data_out(MSU_SNES_DATA_OUT), .reg_oe(SNES_READ), @@ -230,7 +221,7 @@ bsx snes_bsx( .reg_set_bits(bsx_regs_set_bits), .data_ovr(bsx_data_ovr), .flash_writable(IS_FLASHWR), - .rtc_data(rtc_data) + .rtc_data(rtc_data[55:0]) ); spi snes_spi( @@ -280,8 +271,6 @@ mcu_cmd snes_mcu_cmd( .cmd_data(spi_cmd_data), .param_data(spi_param_data), .mcu_mapper(MAPPER), - .mcu_sram_size(SRAM_SIZE), -// .mcu_read(MCU_READ), .mcu_write(MCU_WRITE), .mcu_data_in(MCU_DINr), .mcu_data_out(MCU_DOUT), @@ -289,8 +278,6 @@ mcu_cmd snes_mcu_cmd( .spi_bit_cnt(spi_bit_cnt), .spi_data_out(spi_input_data), .addr_out(MCU_ADDR), - .endmessage(spi_endmessage), - .startmessage(spi_startmessage), .saveram_mask_out(SAVERAM_MASK), .rom_mask_out(ROM_MASK), .SD_DMA_EN(SD_DMA_EN), @@ -337,6 +324,7 @@ mcu_cmd snes_mcu_cmd( .mcu_rq_rdy(MCU_RDY) ); +wire [7:0] DCM_STATUS; // dcm1: dfs 4x my_dcm snes_dcm( .CLKIN(CLKIN), @@ -350,13 +338,8 @@ assign DCM_RST=0; reg [5:0] SNES_READr; reg [5:0] SNES_WRITEr; -reg [12:0] SNES_CPU_CLKr; -reg [5:0] SNES_RWr; -reg [23:0] SNES_ADDRr; +reg [5:0] SNES_CPU_CLKr; -wire SNES_RW = (SNES_READ & SNES_WRITE); - -wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle wire SNES_RD_start = (SNES_READr == 6'b111110); wire SNES_WR_start = (SNES_WRITEr == 6'b111110); wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); @@ -365,28 +348,22 @@ wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); always @(posedge CLK2) begin SNES_READr <= {SNES_READr[4:0], SNES_READ}; SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; - SNES_CPU_CLKr <= {SNES_CPU_CLKr[11:0], SNES_CPU_CLK}; - SNES_RWr <= {SNES_RWr[4:0], SNES_RW}; + SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK}; end -wire ROM_SEL; - address snes_addr( .CLK(CLK2), .MAPPER(MAPPER), .featurebits(featurebits), .SNES_ADDR(SNES_ADDR), // requested address from SNES - .SNES_CS(SNES_CS), // "CART" pin from SNES (active low) .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) .ROM_SEL(ROM_SEL), // which SRAM unit to access .IS_SAVERAM(IS_SAVERAM), .IS_ROM(IS_ROM), .IS_WRITABLE(IS_WRITABLE), - .MCU_ADDR(MCU_ADDR), .SAVERAM_MASK(SAVERAM_MASK), .ROM_MASK(ROM_MASK), //MSU-1 - .use_msu(use_msu), .msu_enable(msu_enable), //BS-X .use_bsx(use_bsx), @@ -399,11 +376,6 @@ address snes_addr( .dspx_a0(DSPX_A0) ); -wire SNES_READ_CYCLEw; -wire SNES_WRITE_CYCLEw; -wire MCU_READ_CYCLEw; -wire MCU_WRITE_CYCLEw; - parameter MODE_SNES = 1'b0; parameter MODE_MCU = 1'b1; @@ -426,53 +398,16 @@ parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000; parameter ST_MCU_WR_END = 18'b010000000000000000; parameter ROM_RD_WAIT = 4'h4; -parameter ROM_RD_WAIT_MCU = 4'h5; +parameter ROM_RD_WAIT_MCU = 4'h6; parameter ROM_WR_WAIT1 = 4'h2; parameter ROM_WR_WAIT2 = 4'h3; parameter ROM_WR_WAIT_MCU = 4'h6; reg [17:0] STATE; -reg [3:0] STATEIDX; - -reg [1:0] CYCLE_RESET; -reg ROM_WE_MASK; -reg ROM_OE_MASK; - -reg SNES_READ_CYCLE; -reg SNES_WRITE_CYCLE; -reg MCU_READ_CYCLE; -reg MCU_WRITE_CYCLE; -reg MCU_SPI_WRITEONCE; -reg MCU_SPI_READONCE; -reg MCU_SPI_WRITE; -reg MCU_SPI_READ; -reg MCU_SPI_ADDR_INCREMENT; -reg [7:0] MCU_DATA_IN; -reg [3:0] MAPPER_BUF; - -reg SNES_DATABUS_OE_BUF; -reg SNES_DATABUS_DIR_BUF; - -initial begin - CYCLE_RESET = 2'b0; - STATE = ST_IDLE; - STATEIDX = 13; - ROM_WE_MASK = 1'b1; - ROM_OE_MASK = 1'b1; - SNES_READ_CYCLE = 1'b1; - SNES_WRITE_CYCLE = 1'b1; - MCU_READ_CYCLE = 1'b1; - MCU_WRITE_CYCLE = 1'b1; -end - -// falling edge of SNES /RD or /WR marks the beginning of a new cycle -// SNES READ or WRITE always starts @posedge CLK !! -// CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy -// the minimum of 6 SNES cycles to get everything done. -// we have 24 internal cycles to work with. (CLKIN * 4) +initial STATE = ST_IDLE; assign DSPX_SNES_DATA_IN = SNES_DATA; -assign SRTC_SNES_DATA_IN = SNES_DATA; +assign SRTC_SNES_DATA_IN = SNES_DATA[3:0]; assign MSU_SNES_DATA_IN = SNES_DATA; assign BSX_SNES_DATA_IN = SNES_DATA; @@ -522,13 +457,6 @@ always @(posedge CLK2) begin end end -reg [23:0] SNES_ADDRsr[1:0]; -always @(posedge CLK2) begin - SNES_ADDRsr[0] <= SNES_ADDR; - SNES_ADDRsr[1] <= SNES_ADDRsr[0]; -end -wire SNES_ADDRchg = (SNES_ADDRsr[0] != SNES_ADDRsr[1]); - reg snes_wr_cycle; always @(posedge CLK2) begin @@ -640,9 +568,6 @@ always @(posedge CLK2) begin end end -// wire MCU_RRQ; -// wire MCU_WRQ; -// reg ROM_OEr; assign ROM_DATA[7:0] = ROM_ADDR0 ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) : (!ROM_WE ? ROM_DOUTr : 8'bZ) @@ -653,26 +578,19 @@ assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) : (!ROM_WE ? ROM_DOUTr : 8'bZ) ); - -// When in MCU mode, enable SRAM_WE according to MCU programming -// else enable SRAM_WE according to state&cycle + assign ROM_WE = SD_DMA_TO_ROM ?MCU_WRITE - :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); /* & !MODE) - | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX])*/ + :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); -// When in MCU mode, enable SRAM_OE whenever not writing -// else enable SRAM_OE according to state&cycle -assign ROM_OE = 1'b0; //!MCU_OVR - //?MCU_READ - //:ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]; +// OE always active. Overridden by WE when needed. +assign ROM_OE = 1'b0; -assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL; +assign ROM_CE = 1'b0; assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0; assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; -//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE); assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 : msu_enable ? 1'b0 : bsx_data_ovr ? (SNES_READ & SNES_WRITE) : diff --git a/verilog/sd2snes/mcu_cmd.v b/verilog/sd2snes/mcu_cmd.v index 192bb84..0c843eb 100644 --- a/verilog/sd2snes/mcu_cmd.v +++ b/verilog/sd2snes/mcu_cmd.v @@ -24,8 +24,7 @@ module mcu_cmd( input param_ready, input [7:0] cmd_data, input [7:0] param_data, - output [3:0] mcu_mapper, - output [3:0] mcu_sram_size, + output [2:0] mcu_mapper, output mcu_rrq, output mcu_write, output mcu_wrq, @@ -36,9 +35,6 @@ module mcu_cmd( input [31:0] spi_byte_cnt, input [2:0] spi_bit_cnt, output [23:0] addr_out, - output [3:0] mapper, - input endmessage, - input startmessage, output [23:0] saveram_mask_out, output [23:0] rom_mask_out, @@ -50,13 +46,11 @@ module mcu_cmd( input SD_DMA_SRAM_WE, output [1:0] SD_DMA_TGT, output SD_DMA_PARTIAL, - output [11:0] SD_DMA_PARTIAL_START, - output [11:0] SD_DMA_PARTIAL_END, + output [10:0] SD_DMA_PARTIAL_START, + output [10:0] SD_DMA_PARTIAL_END, // DAC output [10:0] dac_addr_out, -// output [7:0] dac_volume_out, -// output dac_volume_latch_out, input DAC_STATUS, output dac_play_out, output dac_reset_out, @@ -97,7 +91,7 @@ module mcu_cmd( output reg dspx_reset_out, // feature enable - output reg [7:0] featurebits_out, + output reg [3:0] featurebits_out, // SNES sync/clk input snes_sysclk @@ -118,10 +112,7 @@ clk_test snes_clk_test ( ); -reg [3:0] MAPPER_BUF; -reg [3:0] SRAM_SIZE_BUF; -reg MCU_READ_BUF; -reg MCU_WRITE_BUF; +reg [2:0] MAPPER_BUF; reg [23:0] ADDR_OUT_BUF; reg [10:0] DAC_ADDR_OUT_BUF; reg [7:0] DAC_VOL_OUT_BUF; @@ -149,9 +140,6 @@ reg [31:0] SNES_SYSCLK_FREQ_BUF; reg [7:0] MCU_DATA_OUT_BUF; reg [7:0] MCU_DATA_IN_BUF; reg [1:0] mcu_nextaddr_buf; -reg mcu_nextaddr_r; -reg SD_DMA_NEXTADDRr; -always @(posedge clk) SD_DMA_NEXTADDRr <= SD_DMA_NEXTADDR; wire mcu_nextaddr; @@ -173,14 +161,11 @@ assign SD_DMA_EN = SD_DMA_ENr; reg [1:0] SD_DMA_TGTr; assign SD_DMA_TGT = SD_DMA_TGTr; -reg [11:0] SD_DMA_PARTIAL_STARTr; -reg [11:0] SD_DMA_PARTIAL_ENDr; +reg [10:0] SD_DMA_PARTIAL_STARTr; +reg [10:0] SD_DMA_PARTIAL_ENDr; assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr; assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr; -reg [2:0] spi_dma_nextaddr_r; - -reg [1:0] SRAM_MASK_IDX; reg [23:0] SAVERAM_MASK; reg [23:0] ROM_MASK; @@ -190,9 +175,6 @@ initial begin ADDR_OUT_BUF = 0; DAC_ADDR_OUT_BUF = 0; MSU_ADDR_OUT_BUF = 0; - DAC_VOL_OUT_BUF = 0; - DAC_VOL_LATCH_BUF = 0; - spi_dma_nextaddr_r = 0; SD_DMA_ENr = 0; MAPPER_BUF = 1; end @@ -202,7 +184,7 @@ always @(posedge clk) begin if (cmd_ready) begin case (cmd_data[7:4]) 4'h3: // select mapper - MAPPER_BUF <= cmd_data[3:0]; + MAPPER_BUF <= cmd_data[2:0]; 4'h4: begin// SD DMA SD_DMA_ENr <= 1; SD_DMA_TGTr <= cmd_data[1:0]; @@ -235,15 +217,6 @@ always @(posedge clk) begin endcase 8'h4x: SD_DMA_ENr <= 1'b0; -// 8'h5x: -// case (spi_byte_cnt) -// 32'h2: -// DAC_VOL_OUT_BUF <= param_data; -// 32'h3: -// DAC_VOL_LATCH_BUF <= 1'b1; -// 32'h4: -// DAC_VOL_LATCH_BUF <= 1'b0; -// endcase 8'h6x: case (spi_byte_cnt) 32'h2: @@ -369,7 +342,7 @@ always @(posedge clk) begin 8'hec: // release DSPx reset dspx_reset_out <= 1'b0; 8'hed: - featurebits_out <= param_data[7:0]; + featurebits_out <= param_data[3:0]; endcase end end @@ -479,32 +452,27 @@ always @(posedge clk) begin mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy}; end -parameter ST_RRQ = 4'b0001; -parameter ST_WAIT = 4'b0010; -parameter ST_NEXT = 4'b0100; -parameter ST_IDLE = 4'b1000; +parameter ST_RQ = 2'b01; +parameter ST_IDLE = 2'b10; -reg [3:0] rrq_state; +reg [1:0] rrq_state; initial rrq_state = ST_IDLE; -reg [2:0] rrq_wait; reg mcu_rrq_r; -reg [3:0] wrq_state; +reg [1:0] wrq_state; initial wrq_state = ST_IDLE; -reg [2:0] wrq_wait; reg mcu_wrq_r; always @(posedge clk) begin case(rrq_state) ST_IDLE: begin - mcu_nextaddr_r <= 1'b0; if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin mcu_rrq_r <= 1'b1; - rrq_state <= ST_RRQ; + rrq_state <= ST_RQ; end else rrq_state <= ST_IDLE; end - ST_RRQ: begin + ST_RQ: begin mcu_rrq_r <= 1'b0; rrq_state <= ST_IDLE; end @@ -514,14 +482,13 @@ end always @(posedge clk) begin case(wrq_state) ST_IDLE: begin - mcu_nextaddr_r <= 1'b0; if(param_ready && cmd_data[7:4] == 4'h9) begin mcu_wrq_r <= 1'b1; - wrq_state <= ST_RRQ; + wrq_state <= ST_RQ; end else wrq_state <= ST_IDLE; end - ST_RRQ: begin + ST_RQ: begin mcu_wrq_r <= 1'b0; wrq_state <= ST_IDLE; end @@ -543,8 +510,6 @@ assign mcu_write = SD_DMA_STATUS assign addr_out = ADDR_OUT_BUF; assign dac_addr_out = DAC_ADDR_OUT_BUF; assign msu_addr_out = MSU_ADDR_OUT_BUF; -assign dac_volume_out = DAC_VOL_OUT_BUF; -assign dac_volume_latch_out = DAC_VOL_LATCH_BUF; assign dac_play_out = DAC_PLAY_OUT_BUF; assign dac_reset_out = DAC_RESET_OUT_BUF; assign msu_status_reset_we = msu_status_reset_we_buf; @@ -564,7 +529,6 @@ assign srtc_reset = srtc_reset_buf; assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF; assign mcu_mapper = MAPPER_BUF; -assign mcu_sram_size = SRAM_SIZE_BUF; assign rom_mask_out = ROM_MASK; assign saveram_mask_out = SAVERAM_MASK; diff --git a/verilog/sd2snes/msu.v b/verilog/sd2snes/msu.v index 4b93c65..32b106a 100644 --- a/verilog/sd2snes/msu.v +++ b/verilog/sd2snes/msu.v @@ -58,20 +58,18 @@ reg [13:0] msu_address_r; wire [13:0] msu_address = msu_address_r; wire [7:0] msu_data; -reg [7:0] msu_data_r; reg [1:0] msu_address_ext_write_sreg; always @(posedge clkin) msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write}; wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01); -reg [7:0] reg_enable_sreg; -initial reg_enable_sreg = 8'b11111111; -always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[6:0], enable}; +reg [4:0] reg_enable_sreg; +initial reg_enable_sreg = 5'b11111; +always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable}; reg [5:0] reg_oe_sreg; always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; -//wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001); reg [5:0] reg_we_sreg; @@ -122,10 +120,8 @@ msu_databuf snes_msu_databuf ( .doutb(msu_data) ); // Bus [7 : 0] -reg [7:0] data_in_r; reg [7:0] data_out_r; assign reg_data_out = data_out_r; -always @(posedge clkin) data_in_r <= reg_data_in; always @(posedge clkin) begin case(reg_addr_r[3]) diff --git a/verilog/sd2snes/rtc.v b/verilog/sd2snes/rtc.v index 9db752c..e643d65 100644 --- a/verilog/sd2snes/rtc.v +++ b/verilog/sd2snes/rtc.v @@ -21,7 +21,7 @@ module rtc ( input clkin, input pgm_we, - input [59:0] rtc_data_in, + input [55:0] rtc_data_in, input we1, input [59:0] rtc_data_in1, output [59:0] rtc_data @@ -48,7 +48,6 @@ end assign rtc_data = rtc_data_out_r; reg [21:0] rtc_state; -reg [21:0] next_state; reg carry; reg [3:0] dom1[11:0]; @@ -89,22 +88,21 @@ parameter [21:0] initial begin rtc_state = STATE_IDLE; - next_state = STATE_IDLE; - dom1[0] <= 1; dom10[0] <= 3; - dom1[1] <= 8; dom10[1] <= 2; - dom1[2] <= 1; dom10[2] <= 3; - dom1[3] <= 0; dom10[3] <= 3; - dom1[4] <= 1; dom10[4] <= 3; - dom1[5] <= 0; dom10[5] <= 3; - dom1[6] <= 1; dom10[6] <= 3; - dom1[7] <= 1; dom10[7] <= 3; - dom1[8] <= 0; dom10[8] <= 3; - dom1[9] <= 1; dom10[9] <= 3; - dom1[10] <= 0; dom10[10] <= 3; - dom1[11] <= 1; dom10[11] <= 3; - month <= 0; - rtc_data_r <= 60'h220110301000000; - tick_cnt <= 0; + dom1[0] = 1; dom10[0] = 3; + dom1[1] = 8; dom10[1] = 2; + dom1[2] = 1; dom10[2] = 3; + dom1[3] = 0; dom10[3] = 3; + dom1[4] = 1; dom10[4] = 3; + dom1[5] = 0; dom10[5] = 3; + dom1[6] = 1; dom10[6] = 3; + dom1[7] = 1; dom10[7] = 3; + dom1[8] = 0; dom10[8] = 3; + dom1[9] = 1; dom10[9] = 3; + dom1[10] = 0; dom10[10] = 3; + dom1[11] = 1; dom10[11] = 3; + month = 0; + rtc_data_r = 60'h220110301000000; + tick_cnt = 0; end wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00); @@ -167,7 +165,7 @@ end always @(posedge clkin) begin if(pgm_we_rising) begin - rtc_data_r <= rtc_data_in; + rtc_data_r[55:0] <= rtc_data_in; end else if (we1_rising) begin rtc_data_r <= rtc_data_in1; end else begin diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index 170cb39..c897c80 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -377,8 +377,8 @@ - - + + diff --git a/verilog/sd2snes/sd_dma.v b/verilog/sd2snes/sd_dma.v index f14ca1f..f3e9618 100644 --- a/verilog/sd2snes/sd_dma.v +++ b/verilog/sd2snes/sd_dma.v @@ -23,7 +23,6 @@ module sd_dma( inout SD_CLK, input CLK, input SD_DMA_EN, - input SD_DMA_TGT, output SD_DMA_STATUS, output SD_DMA_SRAM_WE, output SD_DMA_NEXTADDR, @@ -39,17 +38,17 @@ reg SD_DMA_PARTIALr; always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL; reg SD_DMA_DONEr; -reg[2:0] SD_DMA_DONEr2; +reg[1:0] SD_DMA_DONEr2; initial begin - SD_DMA_DONEr2 = 3'b000; + SD_DMA_DONEr2 = 2'b00; SD_DMA_DONEr = 1'b0; end -always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[1:0], SD_DMA_DONEr}; +always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr}; wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01); -reg [2:0] SD_DMA_ENr; -initial SD_DMA_ENr = 3'b000; -always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[1:0], SD_DMA_EN}; +reg [1:0] SD_DMA_ENr; +initial SD_DMA_ENr = 2'b00; +always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN}; wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01); reg SD_DMA_STATUSr; @@ -68,9 +67,9 @@ assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr reg[7:0] SD_DMA_SRAM_DATAr; assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; -// we have 4 internal cycles per SD clock -reg [12:0] clkcnt; -initial clkcnt = 13'd0; +// we have 4 internal cycles per SD clock, 8 per RAM byte write +reg [2:0] clkcnt; +initial clkcnt = 3'b000; reg SD_CLKr; always @(posedge CLK) SD_CLKr <= clkcnt[1]; assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; diff --git a/verilog/sd2snes/spi.v b/verilog/sd2snes/spi.v index f49f07c..cb6bf79 100644 --- a/verilog/sd2snes/spi.v +++ b/verilog/sd2snes/spi.v @@ -39,25 +39,13 @@ module spi( reg [7:0] cmd_data_r; reg [7:0] param_data_r; -// sync SCK to the FPGA clock using a 3-bits shift register -reg [2:0] SCKr; -always @(posedge clk) SCKr <= {SCKr[1:0], SCK}; - -wire SCK_risingedge = (SCKr[1:0]==2'b01); // now we can detect SCK rising edges -wire SCK_fallingedge = (SCKr[1:0]==2'b10); // and falling edges - -// same thing for SSEL -reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL}; +reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL}; wire SSEL_active = ~SSELr[1]; // SSEL is active low wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge assign endmessage = SSEL_endmessage; assign startmessage = SSEL_startmessage; -// and for MOSI -reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI}; -wire MOSI_data = MOSIr[0]; - // bit count for one SPI byte + byte count for the message reg [2:0] bitcnt; reg [31:0] byte_cnt_r; @@ -66,19 +54,6 @@ reg byte_received; // high when a byte has been received reg [7:0] byte_data_received; assign bit_cnt = bitcnt; -/* -always @(posedge clk) -begin - if(~SSEL_active) begin - bitcnt <= 3'b000; - end - else if(SCK_risingedge) begin - bitcnt <= bitcnt + 3'b001; - // shift received data into the register - byte_data_received <= {byte_data_received[6:0], MOSI_data}; - end -end -*/ always @(posedge SCK) begin if(SSEL) bitcnt <= 3'b000; @@ -90,9 +65,6 @@ always @(posedge SCK) begin else byte_received <= 1'b0; end -//always @(posedge clk) -// byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111); - reg [1:0] byte_received_r; always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received}; wire byte_received_sync = (byte_received_r == 2'b01); @@ -107,30 +79,7 @@ end reg [7:0] byte_data_sent; -/*always @(posedge clk) begin - if(SSEL_active) begin - if(SSEL_startmessage) - byte_data_sent <= 8'h5A; // dummy byte - else - if(SCK_fallingedge) begin - if(bitcnt==3'b000) - byte_data_sent <= input_data; // after that, we send whatever we get - else - byte_data_sent <= {byte_data_sent[6:0], 1'b0}; - end - end -end -*/ -always @(negedge SCK) begin - if(~SSEL) begin - if(bitcnt==3'b000) - byte_data_sent <= input_data; - else - byte_data_sent <= {byte_data_sent[6:0], 1'b0}; - end -end - -assign MISO = ~SSEL ? input_data[7-bitcnt] /*byte_data_sent[7]*/ : 1'bZ; // send MSB first +assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first reg cmd_ready_r; reg param_ready_r; @@ -155,7 +104,7 @@ always @(posedge clk) begin param_data_r <= byte_data_received; end -// delay ready signals by one clock (why did I do this again...) +// delay ready signals by one clock always @(posedge clk) begin cmd_ready_r <= cmd_ready_r2; param_ready_r <= param_ready_r2; diff --git a/verilog/sd2snes/srtc.v b/verilog/sd2snes/srtc.v index 1a5dd77..dd6e89d 100644 --- a/verilog/sd2snes/srtc.v +++ b/verilog/sd2snes/srtc.v @@ -20,9 +20,8 @@ ////////////////////////////////////////////////////////////////////////////////// module srtc( input clkin, - input [4:0] reg_addr, input addr_in, - input [7:0] data_in, + input [3:0] data_in, output [7:0] data_out, input [59:0] rtc_data_in, output [59:0] rtc_data_out, @@ -33,9 +32,6 @@ module srtc( input reset ); -reg rtc_dirty_r; -assign rtc_dirty = rtc_dirty_r; - reg [59:0] rtc_data_r; reg [59:0] rtc_data_out_r; assign rtc_data_out = rtc_data_out_r; @@ -43,17 +39,14 @@ assign rtc_data_out = rtc_data_out_r; reg [3:0] rtc_ptr; reg [7:0] data_out_r; -reg [7:0] data_in_r; reg [4:0] mode_r; -reg [3:0] command_r; reg rtc_we_r; assign rtc_we = rtc_we_r; assign data_out = data_out_r; -reg [5:0] reg_oe_sreg; -always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; -wire reg_oe_falling = (reg_oe_sreg[3:0] == 4'b1000); -wire reg_oe_rising = (reg_oe_sreg[3:0] == 4'b0001); +reg [3:0] reg_oe_sreg; +always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[2:0], reg_oe}; +wire reg_oe_falling = (reg_oe_sreg == 4'b1000); reg [1:0] reg_we_sreg; always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[0], reg_we}; @@ -91,7 +84,7 @@ always @(posedge clkin) begin case (addr_in) // 1'b0: // data register is read only 1'b1: // control register - case (data_in[3:0]) + case (data_in) 4'hd: begin mode_r <= SRTC_READ; rtc_ptr <= 4'hf; @@ -103,7 +96,7 @@ always @(posedge clkin) begin end default: begin if(mode_r == SRTC_COMMAND) begin - case (data_in[3:0]) + case (data_in) 4'h0: begin mode_r <= SRTC_WRITE; rtc_data_out_r <= rtc_data_in; @@ -119,30 +112,28 @@ always @(posedge clkin) begin end else if(mode_r == SRTC_WRITE) begin rtc_ptr <= rtc_ptr + 1; case(rtc_ptr) - 0: rtc_data_out_r[3:0] <= data_in[3:0]; - 1: rtc_data_out_r[7:4] <= data_in[3:0]; - 2: rtc_data_out_r[11:8] <= data_in[3:0]; - 3: rtc_data_out_r[15:12] <= data_in[3:0]; - 4: rtc_data_out_r[19:16] <= data_in[3:0]; - 5: rtc_data_out_r[23:20] <= data_in[3:0]; - 6: rtc_data_out_r[27:24] <= data_in[3:0]; - 7: rtc_data_out_r[31:28] <= data_in[3:0]; + 0: rtc_data_out_r[3:0] <= data_in; + 1: rtc_data_out_r[7:4] <= data_in; + 2: rtc_data_out_r[11:8] <= data_in; + 3: rtc_data_out_r[15:12] <= data_in; + 4: rtc_data_out_r[19:16] <= data_in; + 5: rtc_data_out_r[23:20] <= data_in; + 6: rtc_data_out_r[27:24] <= data_in; + 7: rtc_data_out_r[31:28] <= data_in; 8: begin - rtc_data_out_r[35:32] <= (data_in[3:0] < 10) - ? data_in[3:0] - : data_in[3:0] - 10; - rtc_data_out_r[39:36] <= data_in[3:0] < 10 ? 0 : 1; + rtc_data_out_r[35:32] <= (data_in < 10) + ? data_in + : data_in - 10; + rtc_data_out_r[39:36] <= data_in < 10 ? 0 : 1; end - 9: rtc_data_out_r[43:40] <= data_in[3:0]; - 10: rtc_data_out_r[47:44] <= data_in[3:0]; + 9: rtc_data_out_r[43:40] <= data_in; + 10: rtc_data_out_r[47:44] <= data_in; 11: begin - rtc_data_out_r[51:48] <= (data_in[3:0] < 10) - ? data_in[3:0] - : data_in[3:0] - 10; - rtc_data_out_r[55:52] <= data_in[3:0] < 10 ? 1 : 2; + rtc_data_out_r[51:48] <= (data_in < 10) + ? data_in + : data_in - 10; + rtc_data_out_r[55:52] <= data_in < 10 ? 1 : 2; end - default: - rtc_dirty_r <= 1; endcase mode_r <= SRTC_WRITE2; we_countdown_r <= 5; diff --git a/verilog/sd2snes/upd77c25.v b/verilog/sd2snes/upd77c25.v index 73d71aa..567483a 100644 --- a/verilog/sd2snes/upd77c25.v +++ b/verilog/sd2snes/upd77c25.v @@ -38,13 +38,13 @@ module upd77c25( input [10:0] DP_ADDR, // debug - output [15:0] DR, - output [15:0] SR, - output [10:0] PC, - output [15:0] A, - output [15:0] B, - output [5:0] FL_A, - output [5:0] FL_B + output [15:0] updDR, + output [15:0] updSR, + output [10:0] updPC, + output [15:0] updA, + output [15:0] updB, + output [5:0] updFL_A, + output [5:0] updFL_B ); parameter STATE_FETCH = 8'b00000001; @@ -86,8 +86,6 @@ wire [15:0] ram_dina; reg [15:0] ram_dina_r; assign ram_dina = ram_dina_r; -wire [10:0] pgm_addra; -wire [23:0] pgm_dina; wire [23:0] pgm_doutb; upd77c25_pgmrom pgmrom ( @@ -101,7 +99,6 @@ upd77c25_pgmrom pgmrom ( ); wire [23:0] opcode_w = pgm_doutb; -reg [23:0] opcode; reg [1:0] op; reg [1:0] op_pselect; reg [3:0] op_alu; @@ -112,8 +109,6 @@ reg op_rpdcr; reg [3:0] op_src; reg [3:0] op_dst; -wire [9:0] dat_addra; -wire [15:0] dat_dina; wire [15:0] dat_doutb; upd77c25_datrom datrom ( @@ -126,9 +121,9 @@ upd77c25_datrom datrom ( .doutb(dat_doutb) // output [15 : 0] doutb ); -reg [7:0] reg_nCS_sreg; -initial reg_nCS_sreg = 8'b11111111; -always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS}; +reg [4:0] reg_nCS_sreg; +initial reg_nCS_sreg = 5'b11111; +always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[3:0], nCS}; reg [5:0] reg_oe_sreg; initial reg_oe_sreg = 6'b111111; @@ -136,16 +131,14 @@ always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD}; wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001); wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000); -reg [7:0] reg_DP_nCS_sreg; -initial reg_DP_nCS_sreg = 8'b11111111; -always @(posedge CLK) reg_DP_nCS_sreg <= {reg_DP_nCS_sreg[6:0], DP_nCS}; +reg [4:0] reg_DP_nCS_sreg; +initial reg_DP_nCS_sreg = 5'b11111; +always @(posedge CLK) reg_DP_nCS_sreg <= {reg_DP_nCS_sreg[3:0], DP_nCS}; reg [5:0] reg_we_sreg; initial reg_we_sreg = 6'b111111; always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR}; wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001); -wire reg_dp_we_rising = !reg_DP_nCS_sreg[5] && (reg_we_sreg[1:0] == 2'b01); -wire reg_we_falling = (reg_we_sreg[1:0] == 2'b10); wire [15:0] ram_douta; wire [9:0] ram_addra; @@ -156,11 +149,6 @@ wire [7:0] UPD_DO; reg ram_web; reg [10:0] ram_addrb; -reg [65:0] DP_ADDRr; -always @(posedge CLK) begin - DP_ADDRr <= {DP_ADDRr[54:0], DP_ADDR}; -end - always @(posedge CLK) begin ram_addrb <= DP_ADDR; //r[10:0]; ram_web <= ~(nWR | reg_DP_nCS_sreg[0] | reg_DP_nCS_sreg[4]); @@ -191,7 +179,6 @@ reg [15:0] regs_trb; reg [15:0] regs_tr; reg [15:0] regs_dr; reg [15:0] regs_sr; -reg [15:0] regs_si; reg [3:0] regs_sp; reg cond_true; @@ -212,19 +199,19 @@ reg [15:0] alu_r; reg [1:0] alu_store; -reg [15:0] stack [15:0]; +reg [10:0] stack [15:0]; reg [15:0] idb; reg [15:0] regs_ab [1:0]; -assign DR = regs_dr; -assign SR = regs_sr; -assign PC = pc; -assign A = regs_ab[0]; -assign B = regs_ab[1]; -assign FL_A = {flags_s1[0],flags_s0[0],flags_c[0],flags_z[0],flags_ov1[0],flags_ov0[0]}; -assign FL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_ov0[1]}; +assign updDR = regs_dr; +assign updSR = regs_sr; +assign updPC = pc; +assign updA = regs_ab[0]; +assign updB = regs_ab[1]; +assign updFL_A = {flags_s1[0],flags_s0[0],flags_c[0],flags_z[0],flags_ov1[0],flags_ov0[0]}; +assign updFL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_ov0[1]}; initial begin @@ -252,12 +239,10 @@ initial begin regs_dr = 16'b0; end -reg [7:0] A0r; -initial A0r = 8'b11111111; -always @(posedge CLK) A0r <= {A0r[6:0], A0}; +reg [3:0] A0r; +initial A0r = 4'b1111; +always @(posedge CLK) A0r <= {A0r[2:0], A0}; -reg [7:0] last_op; -initial last_op = 8'h00; always @(posedge CLK) begin if(RST) begin if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == STATE_STORE) @@ -387,7 +372,6 @@ always @(posedge CLK) begin endcase end - opcode <= opcode_w; op <= opcode_w[23:22]; op_pselect <= opcode_w[21:20]; op_alu <= opcode_w[19:16]; @@ -658,7 +642,6 @@ always @(posedge CLK) begin flags_s1 <= 2'b0; regs_tr <= 16'b0; regs_trb <= 16'b0; - opcode <= 23'b0; op_pselect <= 2'b0; op_alu <= 4'b0; op_asl <= 1'b0; diff --git a/verilog/sd2sneslite/address.v b/verilog/sd2sneslite/address.v index ff9aa82..c05b722 100644 --- a/verilog/sd2sneslite/address.v +++ b/verilog/sd2sneslite/address.v @@ -22,11 +22,8 @@ module address( input [23:0] SNES_ADDR, // requested address from SNES input SNES_CS, // "CART" pin from SNES (active low) output [23:0] ROM_ADDR, // Address to request from SRAM0 - output ROM_SEL, // enable SRAM0 (active low) output IS_SAVERAM, // address/CS mapped as SRAM? output IS_ROM, // address mapped as ROM? - input [23:0] MCU_ADDR, // allow address to be set externally - input ADDR_WRITE, input [23:0] SAVERAM_MASK, input [23:0] ROM_MASK ); @@ -58,6 +55,4 @@ assign SRAM_SNES_ADDR = (IS_SAVERAM assign ROM_ADDR = SRAM_SNES_ADDR; -assign ROM_SEL = 1'b0; - endmodule diff --git a/verilog/sd2sneslite/main.v b/verilog/sd2sneslite/main.v index c06f43c..0e2dbf7 100644 --- a/verilog/sd2sneslite/main.v +++ b/verilog/sd2sneslite/main.v @@ -88,7 +88,6 @@ wire [2:0] spi_bit_cnt; wire [23:0] MCU_ADDR; wire [7:0] mcu_data_in; wire [7:0] mcu_data_out; -wire [3:0] MAPPER; wire [23:0] SAVERAM_MASK; wire [23:0] ROM_MASK; @@ -105,8 +104,6 @@ spi snes_spi( .param_ready(spi_param_ready), .cmd_data(spi_cmd_data), .param_data(spi_param_data), - .endmessage(spi_endmessage), - .startmessage(spi_startmessage), .input_data(spi_input_data), .byte_cnt(spi_byte_cnt), .bit_cnt(spi_bit_cnt) @@ -121,7 +118,6 @@ mcu_cmd snes_mcu_cmd( .param_ready(spi_param_ready), .cmd_data(spi_cmd_data), .param_data(spi_param_data), - .mcu_sram_size(SRAM_SIZE), .mcu_write(MCU_WRITE), .mcu_data_in(MCU_DINr), .mcu_data_out(MCU_DOUT), @@ -129,8 +125,6 @@ mcu_cmd snes_mcu_cmd( .spi_bit_cnt(spi_bit_cnt), .spi_data_out(spi_input_data), .addr_out(MCU_ADDR), - .endmessage(spi_endmessage), - .startmessage(spi_startmessage), .saveram_mask_out(SAVERAM_MASK), .rom_mask_out(ROM_MASK), .mcu_rrq(MCU_RRQ), @@ -138,6 +132,8 @@ mcu_cmd snes_mcu_cmd( .mcu_rq_rdy(MCU_RDY) ); +wire [7:0] DCM_STATUS; + // dcm1: dfs 4x my_dcm snes_dcm( .CLKIN(CLKIN), @@ -177,10 +173,8 @@ address snes_addr( .SNES_ADDR(SNES_ADDR), // requested address from SNES .SNES_CS(SNES_CS), // "CART" pin from SNES (active low) .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) - .ROM_SEL(ROM_SEL), // which SRAM unit to access .IS_SAVERAM(IS_SAVERAM), .IS_ROM(IS_ROM), - .MCU_ADDR(MCU_ADDR), .SAVERAM_MASK(SAVERAM_MASK), .ROM_MASK(ROM_MASK) ); @@ -212,7 +206,7 @@ parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000; parameter ST_MCU_WR_END = 18'b010000000000000000; parameter ROM_RD_WAIT = 4'h4; -parameter ROM_RD_WAIT_MCU = 4'h5; +parameter ROM_RD_WAIT_MCU = 4'h6; parameter ROM_WR_WAIT1 = 4'h2; parameter ROM_WR_WAIT2 = 4'h3; parameter ROM_WR_WAIT_MCU = 4'h6; diff --git a/verilog/sd2sneslite/sd2sneslite.xise b/verilog/sd2sneslite/sd2sneslite.xise index 1c5df33..1322c49 100644 --- a/verilog/sd2sneslite/sd2sneslite.xise +++ b/verilog/sd2sneslite/sd2sneslite.xise @@ -207,7 +207,7 @@ - + diff --git a/verilog/sd2sneslite/spi.v b/verilog/sd2sneslite/spi.v index f49f07c..f19abad 100644 --- a/verilog/sd2sneslite/spi.v +++ b/verilog/sd2sneslite/spi.v @@ -29,8 +29,6 @@ module spi( output param_ready, output [7:0] cmd_data, output [7:0] param_data, - output endmessage, - output startmessage, input [7:0] input_data, output [31:0] byte_cnt, output [2:0] bit_cnt @@ -39,25 +37,11 @@ module spi( reg [7:0] cmd_data_r; reg [7:0] param_data_r; -// sync SCK to the FPGA clock using a 3-bits shift register -reg [2:0] SCKr; -always @(posedge clk) SCKr <= {SCKr[1:0], SCK}; - -wire SCK_risingedge = (SCKr[1:0]==2'b01); // now we can detect SCK rising edges -wire SCK_fallingedge = (SCKr[1:0]==2'b10); // and falling edges - -// same thing for SSEL -reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL}; +reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL}; wire SSEL_active = ~SSELr[1]; // SSEL is active low wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge -wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge -assign endmessage = SSEL_endmessage; assign startmessage = SSEL_startmessage; -// and for MOSI -reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI}; -wire MOSI_data = MOSIr[0]; - // bit count for one SPI byte + byte count for the message reg [2:0] bitcnt; reg [31:0] byte_cnt_r; @@ -66,19 +50,6 @@ reg byte_received; // high when a byte has been received reg [7:0] byte_data_received; assign bit_cnt = bitcnt; -/* -always @(posedge clk) -begin - if(~SSEL_active) begin - bitcnt <= 3'b000; - end - else if(SCK_risingedge) begin - bitcnt <= bitcnt + 3'b001; - // shift received data into the register - byte_data_received <= {byte_data_received[6:0], MOSI_data}; - end -end -*/ always @(posedge SCK) begin if(SSEL) bitcnt <= 3'b000; @@ -90,9 +61,6 @@ always @(posedge SCK) begin else byte_received <= 1'b0; end -//always @(posedge clk) -// byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111); - reg [1:0] byte_received_r; always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received}; wire byte_received_sync = (byte_received_r == 2'b01); @@ -105,32 +73,7 @@ always @(posedge clk) begin end end -reg [7:0] byte_data_sent; - -/*always @(posedge clk) begin - if(SSEL_active) begin - if(SSEL_startmessage) - byte_data_sent <= 8'h5A; // dummy byte - else - if(SCK_fallingedge) begin - if(bitcnt==3'b000) - byte_data_sent <= input_data; // after that, we send whatever we get - else - byte_data_sent <= {byte_data_sent[6:0], 1'b0}; - end - end -end -*/ -always @(negedge SCK) begin - if(~SSEL) begin - if(bitcnt==3'b000) - byte_data_sent <= input_data; - else - byte_data_sent <= {byte_data_sent[6:0], 1'b0}; - end -end - -assign MISO = ~SSEL ? input_data[7-bitcnt] /*byte_data_sent[7]*/ : 1'bZ; // send MSB first +assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first reg cmd_ready_r; reg param_ready_r; @@ -155,7 +98,7 @@ always @(posedge clk) begin param_data_r <= byte_data_received; end -// delay ready signals by one clock (why did I do this again...) +// delay ready signals by one clock always @(posedge clk) begin cmd_ready_r <= cmd_ready_r2; param_ready_r <= param_ready_r2;