Firmware: tweak clock
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parent
986e37ee06
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8f67e742f7
@ -48,9 +48,10 @@ void clock_init() {
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*/
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enableMainOsc();
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setClkSrc(CLKSRC_MAINOSC);
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setPLL0MultPrediv(429, 19);
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// XXX setPLL0MultPrediv(429, 19);
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setPLL0MultPrediv(23, 2);
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enablePLL0();
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setCCLKDiv(6);
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setCCLKDiv(3);
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connectPLL0();
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}
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12
src/config.h
12
src/config.h
@ -3,12 +3,11 @@
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// #define DEBUG_SD
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// #define DEBUG_IRQ
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#define DEBUG_MSU1
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// #define DEBUG_MSU1
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#define VER "0.0.1(NSFW)"
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#define IN_AHBRAM __attribute__ ((section(".ahbram")))
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#define SD_DT_INT_SETUP() do {\
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BITBAND(LPC_GPIOINT->IO2IntEnR, SD_DT_BIT) = 1;\
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BITBAND(LPC_GPIOINT->IO2IntEnF, SD_DT_BIT) = 1;\
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@ -32,13 +31,14 @@
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// #define SD_CHANGE_VECT
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// #define CONFIG_SD_DATACRC 1
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#define CONFIG_UART_NUM 3
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#define CONFIG_CPU_FREQUENCY 90315789
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// #define CONFIG_CPU_FREQUENCY 90315789
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#define CONFIG_CPU_FREQUENCY 92000000
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//#define CONFIG_CPU_FREQUENCY 46000000
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#define CONFIG_UART_PCLKDIV 1
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#define CONFIG_UART_TX_BUF_SHIFT 5
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#define CONFIG_UART_TX_BUF_SHIFT 10
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#define CONFIG_UART_BAUDRATE 921600
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#define CONFIG_UART_DEADLOCKABLE
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//#define CONFIG_UART_DEADLOCKABLE
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#define SSP_CLK_DIVISOR_FAST 2
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#define SSP_CLK_DIVISOR_SLOW 250
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